From nobody Mon Sep 16 19:15:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+114548+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+114548+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1706250612; cv=none; d=zohomail.com; s=zohoarc; b=MYCQ0O+QMR9nNJm4GSTUXQFX8yR5OycpxMWPT6NapFVIbQWQZSSL8JRHG7Ttr0intRO5c4HUD5mmbfy94FsQWj7KX0LnFi/zgK8dohoSoO/zit3IdFt7wXXMIzheI/DVO4bmESo2UP0k39QHtLvtkDtP8OjpJ0Jbu/xeXNvWzuQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706250612; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=8e7azaRzEVZxCK+yMdUdQpeBRYHC86pau7G62oIDbLk=; b=LEO0zEY/tRHxQ38CBlPl7eys9sJVssDOOsg/1ZBq29NO994VmzZR8fW1RKFXMRSIDfEPlTdV8dofHfyxWTSYST7+qFZ05WT1Vp3S1PJX8ReeihWP2IcgkPOmIgu9fAEvsfEF3A3Rdo7aOnS8tjXTWHoRW6ZOfH2cHPl3mnDVyis= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+114548+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1706250612678908.6386721115831; Thu, 25 Jan 2024 22:30:12 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=PesVmmPFp7cDcdt6Q3m8OBN/9A5g2DDFcE9vV/gyhgM=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1706250612; v=1; b=Az2omRLEeZAYVdj/82IzQVQyrff0zgP0p1sPZMs4+H2MVA0ETM81JUc1BmOHjXAGcIESYMvy ZxwcRurD0P4W5PQ/qtcWM0MKru9RY2OAEhANgs9EFEtR3QYtvPukWL/+n+T5Ifp+GFmI1q1/Gqf JQDkjBzHotEBm3eJCF2c/h5o= X-Received: by 127.0.0.2 with SMTP id ZKqyYY1788612xm4NZox5xDi; Thu, 25 Jan 2024 22:30:12 -0800 X-Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by mx.groups.io with SMTP id smtpd.web10.10150.1706250611044203176 for ; Thu, 25 Jan 2024 22:30:11 -0800 X-Received: from loongson.cn (unknown [10.2.9.245]) by gateway (Coremail) with SMTP id _____8DxdfFvUbNlfB4GAA--.21914S3; Fri, 26 Jan 2024 14:30:07 +0800 (CST) X-Received: from code-server.gen (unknown [10.2.9.245]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Dxfs1tUbNl+3IbAA--.51151S2; Fri, 26 Jan 2024 14:30:05 +0800 (CST) From: "Chao Li" To: devel@edk2.groups.io Cc: Sunil V L , Andrei Warkentin Subject: [edk2-devel] [PATCH v8 22/37] OvmfPkg/RiscVVirt: Remove PciCpuIo2Dxe from RiscVVirt Date: Fri, 26 Jan 2024 14:30:04 +0800 Message-Id: <20240126063004.3102213-1-lichao@loongson.cn> In-Reply-To: <20240126062715.3099433-1-lichao@loongson.cn> References: <20240126062715.3099433-1-lichao@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Dxfs1tUbNl+3IbAA--.51151S2 X-CM-SenderInfo: xolfxt3r6o00pqjv00gofq/1tbiAQAICGWyG+ALOQBasF X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,lichao@loongson.cn List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: VrRsYhD5udQWNJVJFHv3dIhix1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1706250614408100003 Content-Type: text/plain; charset="utf-8" CpuIo2Dxe is already used by RiscVVirt, so remove it. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4584 Cc: Sunil V L Cc: Andrei Warkentin Signed-off-by: Chao Li Reviewed-by: Sunil V L --- OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 557 ------------------ .../RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 48 -- 2 files changed, 605 deletions(-) delete mode 100644 OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c delete mode 100644 OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf diff --git a/OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c b/OvmfPkg/RiscVV= irt/PciCpuIo2Dxe/PciCpuIo2Dxe.c deleted file mode 100644 index f3bf07e631..0000000000 --- a/OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c +++ /dev/null @@ -1,557 +0,0 @@ -/** @file - Produces the CPU I/O 2 Protocol. - -Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.
-Copyright (c) 2016, Linaro Ltd. All rights reserved.
-Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
- -SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include - -#include - -#include -#include -#include -#include -#include - -#define MAX_IO_PORT_ADDRESS 0xFFFF - -// -// Handle for the CPU I/O 2 Protocol -// -STATIC EFI_HANDLE mHandle =3D NULL; - -// -// Lookup table for increment values based on transfer widths -// -STATIC CONST UINT8 mInStride[] =3D { - 1, // EfiCpuIoWidthUint8 - 2, // EfiCpuIoWidthUint16 - 4, // EfiCpuIoWidthUint32 - 8, // EfiCpuIoWidthUint64 - 0, // EfiCpuIoWidthFifoUint8 - 0, // EfiCpuIoWidthFifoUint16 - 0, // EfiCpuIoWidthFifoUint32 - 0, // EfiCpuIoWidthFifoUint64 - 1, // EfiCpuIoWidthFillUint8 - 2, // EfiCpuIoWidthFillUint16 - 4, // EfiCpuIoWidthFillUint32 - 8 // EfiCpuIoWidthFillUint64 -}; - -// -// Lookup table for increment values based on transfer widths -// -STATIC CONST UINT8 mOutStride[] =3D { - 1, // EfiCpuIoWidthUint8 - 2, // EfiCpuIoWidthUint16 - 4, // EfiCpuIoWidthUint32 - 8, // EfiCpuIoWidthUint64 - 1, // EfiCpuIoWidthFifoUint8 - 2, // EfiCpuIoWidthFifoUint16 - 4, // EfiCpuIoWidthFifoUint32 - 8, // EfiCpuIoWidthFifoUint64 - 0, // EfiCpuIoWidthFillUint8 - 0, // EfiCpuIoWidthFillUint16 - 0, // EfiCpuIoWidthFillUint32 - 0 // EfiCpuIoWidthFillUint64 -}; - -/** - Check parameters to a CPU I/O 2 Protocol service request. - - The I/O operations are carried out exactly as requested. The caller is r= esponsible - for satisfying any alignment and I/O width restrictions that a PI System= on a - platform might require. For example on some platforms, width requests of - EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, = will - be handled by the driver. - - @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port= operation. - @param[in] Width Signifies the width of the I/O or Memory opera= tion. - @param[in] Address The base address of the I/O operation. - @param[in] Count The number of I/O operations to perform. The n= umber of - bytes moved is Width size * Count, starting at= Address. - @param[in] Buffer For read operations, the destination buffer to= store the results. - For write operations, the source buffer from w= hich to write data. - - @retval EFI_SUCCESS The parameters for this request pass the = checks. - @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. - @retval EFI_INVALID_PARAMETER Buffer is NULL. - @retval EFI_UNSUPPORTED The Buffer is not aligned for the given W= idth. - @retval EFI_UNSUPPORTED The address range specified by Address, W= idth, - and Count is not valid for this PI system. - -**/ -STATIC -EFI_STATUS -CpuIoCheckParameter ( - IN BOOLEAN MmioOperation, - IN EFI_CPU_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN VOID *Buffer - ) -{ - UINT64 MaxCount; - UINT64 Limit; - - // - // Check to see if Buffer is NULL - // - if (Buffer =3D=3D NULL) { - return EFI_INVALID_PARAMETER; - } - - // - // Check to see if Width is in the valid range - // - if ((UINT32)Width >=3D EfiCpuIoWidthMaximum) { - return EFI_INVALID_PARAMETER; - } - - // - // For FIFO type, the target address won't increase during the access, - // so treat Count as 1 - // - if ((Width >=3D EfiCpuIoWidthFifoUint8) && (Width <=3D EfiCpuIoWidthFifo= Uint64)) { - Count =3D 1; - } - - // - // Check to see if Width is in the valid range for I/O Port operations - // - Width =3D (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); - if (!MmioOperation && (Width =3D=3D EfiCpuIoWidthUint64)) { - return EFI_INVALID_PARAMETER; - } - - // - // Check to see if Address is aligned - // - if ((Address & (UINT64)(mInStride[Width] - 1)) !=3D 0) { - return EFI_UNSUPPORTED; - } - - // - // Check to see if any address associated with this transfer exceeds the= maximum - // allowed address. The maximum address implied by the parameters passe= d in is - // Address + Size * Count. If the following condition is met, then the = transfer - // is not supported. - // - // Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_POR= T_ADDRESS) + 1 - // - // Since MAX_ADDRESS can be the maximum integer value supported by the C= PU and Count - // can also be the maximum integer value supported by the CPU, this range - // check must be adjusted to avoid all overflow conditions. - // - // The following form of the range check is equivalent but assumes that - // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1). - // - Limit =3D (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS); - if (Count =3D=3D 0) { - if (Address > Limit) { - return EFI_UNSUPPORTED; - } - } else { - MaxCount =3D RShiftU64 (Limit, Width); - if (MaxCount < (Count - 1)) { - return EFI_UNSUPPORTED; - } - - if (Address > LShiftU64 (MaxCount - Count + 1, Width)) { - return EFI_UNSUPPORTED; - } - } - - // - // Check to see if Buffer is aligned - // - if (((UINTN)Buffer & ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != =3D 0) { - return EFI_UNSUPPORTED; - } - - return EFI_SUCCESS; -} - -/** - Reads memory-mapped registers. - - The I/O operations are carried out exactly as requested. The caller is r= esponsible - for satisfying any alignment and I/O width restrictions that a PI System= on a - platform might require. For example on some platforms, width requests of - EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, = will - be handled by the driver. - - If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, - or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for - each of the Count operations that is performed. - - If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, - EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is - incremented for each of the Count operations that is performed. The read= or - write operation is performed Count times on the same Address. - - If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, - EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is - incremented for each of the Count operations that is performed. The read= or - write operation is performed Count times from the first element of Buffe= r. - - @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. - @param[in] Width Signifies the width of the I/O or Memory operation. - @param[in] Address The base address of the I/O operation. - @param[in] Count The number of I/O operations to perform. The number= of - bytes moved is Width size * Count, starting at Addr= ess. - @param[out] Buffer For read operations, the destination buffer to stor= e the results. - For write operations, the source buffer from which = to write data. - - @retval EFI_SUCCESS The data was read from or written to the = PI system. - @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. - @retval EFI_INVALID_PARAMETER Buffer is NULL. - @retval EFI_UNSUPPORTED The Buffer is not aligned for the given W= idth. - @retval EFI_UNSUPPORTED The address range specified by Address, W= idth, - and Count is not valid for this PI system. - -**/ -STATIC -EFI_STATUS -EFIAPI -CpuMemoryServiceRead ( - IN EFI_CPU_IO2_PROTOCOL *This, - IN EFI_CPU_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - OUT VOID *Buffer - ) -{ - EFI_STATUS Status; - UINT8 InStride; - UINT8 OutStride; - EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; - UINT8 *Uint8Buffer; - - Status =3D CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer); - if (EFI_ERROR (Status)) { - return Status; - } - - // - // Select loop based on the width of the transfer - // - InStride =3D mInStride[Width]; - OutStride =3D mOutStride[Width]; - OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); - for (Uint8Buffer =3D Buffer; Count > 0; Address +=3D InStride, Uint8Buff= er +=3D OutStride, Count--) { - if (OperationWidth =3D=3D EfiCpuIoWidthUint8) { - *Uint8Buffer =3D MmioRead8 ((UINTN)Address); - } else if (OperationWidth =3D=3D EfiCpuIoWidthUint16) { - *((UINT16 *)Uint8Buffer) =3D MmioRead16 ((UINTN)Address); - } else if (OperationWidth =3D=3D EfiCpuIoWidthUint32) { - *((UINT32 *)Uint8Buffer) =3D MmioRead32 ((UINTN)Address); - } else if (OperationWidth =3D=3D EfiCpuIoWidthUint64) { - *((UINT64 *)Uint8Buffer) =3D MmioRead64 ((UINTN)Address); - } - } - - return EFI_SUCCESS; -} - -/** - Writes memory-mapped registers. - - The I/O operations are carried out exactly as requested. The caller is r= esponsible - for satisfying any alignment and I/O width restrictions that a PI System= on a - platform might require. For example on some platforms, width requests of - EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, = will - be handled by the driver. - - If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, - or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for - each of the Count operations that is performed. - - If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, - EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is - incremented for each of the Count operations that is performed. The read= or - write operation is performed Count times on the same Address. - - If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, - EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is - incremented for each of the Count operations that is performed. The read= or - write operation is performed Count times from the first element of Buffe= r. - - @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. - @param[in] Width Signifies the width of the I/O or Memory operation. - @param[in] Address The base address of the I/O operation. - @param[in] Count The number of I/O operations to perform. The number= of - bytes moved is Width size * Count, starting at Addr= ess. - @param[in] Buffer For read operations, the destination buffer to stor= e the results. - For write operations, the source buffer from which = to write data. - - @retval EFI_SUCCESS The data was read from or written to the = PI system. - @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. - @retval EFI_INVALID_PARAMETER Buffer is NULL. - @retval EFI_UNSUPPORTED The Buffer is not aligned for the given W= idth. - @retval EFI_UNSUPPORTED The address range specified by Address, W= idth, - and Count is not valid for this PI system. - -**/ -STATIC -EFI_STATUS -EFIAPI -CpuMemoryServiceWrite ( - IN EFI_CPU_IO2_PROTOCOL *This, - IN EFI_CPU_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN VOID *Buffer - ) -{ - EFI_STATUS Status; - UINT8 InStride; - UINT8 OutStride; - EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; - UINT8 *Uint8Buffer; - - Status =3D CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer); - if (EFI_ERROR (Status)) { - return Status; - } - - // - // Select loop based on the width of the transfer - // - InStride =3D mInStride[Width]; - OutStride =3D mOutStride[Width]; - OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); - for (Uint8Buffer =3D Buffer; Count > 0; Address +=3D InStride, Uint8Buff= er +=3D OutStride, Count--) { - if (OperationWidth =3D=3D EfiCpuIoWidthUint8) { - MmioWrite8 ((UINTN)Address, *Uint8Buffer); - } else if (OperationWidth =3D=3D EfiCpuIoWidthUint16) { - MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer)); - } else if (OperationWidth =3D=3D EfiCpuIoWidthUint32) { - MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer)); - } else if (OperationWidth =3D=3D EfiCpuIoWidthUint64) { - MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer)); - } - } - - return EFI_SUCCESS; -} - -/** - Reads I/O registers. - - The I/O operations are carried out exactly as requested. The caller is r= esponsible - for satisfying any alignment and I/O width restrictions that a PI System= on a - platform might require. For example on some platforms, width requests of - EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, = will - be handled by the driver. - - If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, - or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for - each of the Count operations that is performed. - - If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, - EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is - incremented for each of the Count operations that is performed. The read= or - write operation is performed Count times on the same Address. - - If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, - EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is - incremented for each of the Count operations that is performed. The read= or - write operation is performed Count times from the first element of Buffe= r. - - @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. - @param[in] Width Signifies the width of the I/O or Memory operation. - @param[in] Address The base address of the I/O operation. - @param[in] Count The number of I/O operations to perform. The number= of - bytes moved is Width size * Count, starting at Addr= ess. - @param[out] Buffer For read operations, the destination buffer to stor= e the results. - For write operations, the source buffer from which = to write data. - - @retval EFI_SUCCESS The data was read from or written to the = PI system. - @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. - @retval EFI_INVALID_PARAMETER Buffer is NULL. - @retval EFI_UNSUPPORTED The Buffer is not aligned for the given W= idth. - @retval EFI_UNSUPPORTED The address range specified by Address, W= idth, - and Count is not valid for this PI system. - -**/ -STATIC -EFI_STATUS -EFIAPI -CpuIoServiceRead ( - IN EFI_CPU_IO2_PROTOCOL *This, - IN EFI_CPU_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - OUT VOID *Buffer - ) -{ - EFI_STATUS Status; - UINT8 InStride; - UINT8 OutStride; - EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; - UINT8 *Uint8Buffer; - - Status =3D CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer); - if (EFI_ERROR (Status)) { - return Status; - } - - Address +=3D PcdGet64 (PcdPciIoTranslation); - - // - // Select loop based on the width of the transfer - // - InStride =3D mInStride[Width]; - OutStride =3D mOutStride[Width]; - OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); - - for (Uint8Buffer =3D Buffer; Count > 0; Address +=3D InStride, Uint8Buff= er +=3D OutStride, Count--) { - if (OperationWidth =3D=3D EfiCpuIoWidthUint8) { - *Uint8Buffer =3D MmioRead8 ((UINTN)Address); - } else if (OperationWidth =3D=3D EfiCpuIoWidthUint16) { - *((UINT16 *)Uint8Buffer) =3D MmioRead16 ((UINTN)Address); - } else if (OperationWidth =3D=3D EfiCpuIoWidthUint32) { - *((UINT32 *)Uint8Buffer) =3D MmioRead32 ((UINTN)Address); - } - } - - return EFI_SUCCESS; -} - -/** - Write I/O registers. - - The I/O operations are carried out exactly as requested. The caller is r= esponsible - for satisfying any alignment and I/O width restrictions that a PI System= on a - platform might require. For example on some platforms, width requests of - EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, = will - be handled by the driver. - - If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, - or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for - each of the Count operations that is performed. - - If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, - EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is - incremented for each of the Count operations that is performed. The read= or - write operation is performed Count times on the same Address. - - If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, - EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is - incremented for each of the Count operations that is performed. The read= or - write operation is performed Count times from the first element of Buffe= r. - - @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. - @param[in] Width Signifies the width of the I/O or Memory operation. - @param[in] Address The base address of the I/O operation. - @param[in] Count The number of I/O operations to perform. The number= of - bytes moved is Width size * Count, starting at Addr= ess. - @param[in] Buffer For read operations, the destination buffer to stor= e the results. - For write operations, the source buffer from which = to write data. - - @retval EFI_SUCCESS The data was read from or written to the = PI system. - @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. - @retval EFI_INVALID_PARAMETER Buffer is NULL. - @retval EFI_UNSUPPORTED The Buffer is not aligned for the given W= idth. - @retval EFI_UNSUPPORTED The address range specified by Address, W= idth, - and Count is not valid for this PI system. - -**/ -STATIC -EFI_STATUS -EFIAPI -CpuIoServiceWrite ( - IN EFI_CPU_IO2_PROTOCOL *This, - IN EFI_CPU_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN VOID *Buffer - ) -{ - EFI_STATUS Status; - UINT8 InStride; - UINT8 OutStride; - EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; - UINT8 *Uint8Buffer; - - // - // Make sure the parameters are valid - // - Status =3D CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer); - if (EFI_ERROR (Status)) { - return Status; - } - - Address +=3D PcdGet64 (PcdPciIoTranslation); - - // - // Select loop based on the width of the transfer - // - InStride =3D mInStride[Width]; - OutStride =3D mOutStride[Width]; - OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); - - for (Uint8Buffer =3D (UINT8 *)Buffer; Count > 0; Address +=3D InStride, = Uint8Buffer +=3D OutStride, Count--) { - if (OperationWidth =3D=3D EfiCpuIoWidthUint8) { - MmioWrite8 ((UINTN)Address, *Uint8Buffer); - } else if (OperationWidth =3D=3D EfiCpuIoWidthUint16) { - MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer)); - } else if (OperationWidth =3D=3D EfiCpuIoWidthUint32) { - MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer)); - } - } - - return EFI_SUCCESS; -} - -// -// CPU I/O 2 Protocol instance -// -STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 =3D { - { - CpuMemoryServiceRead, - CpuMemoryServiceWrite - }, - { - CpuIoServiceRead, - CpuIoServiceWrite - } -}; - -/** - The user Entry Point for module CpuIo2Dxe. The user code starts with thi= s function. - - @param[in] ImageHandle The firmware allocated handle for the EFI imag= e. - @param[in] SystemTable A pointer to the EFI System Table. - - @retval EFI_SUCCESS The entry point is executed successfully. - @retval other Some error occurs when executing this entry po= int. - -**/ -EFI_STATUS -EFIAPI -PciCpuIo2Initialize ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - - ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid); - Status =3D gBS->InstallMultipleProtocolInterfaces ( - &mHandle, - &gEfiCpuIo2ProtocolGuid, - &mCpuIo2, - NULL - ); - ASSERT_EFI_ERROR (Status); - - return Status; -} diff --git a/OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf b/OvmfPkg/Risc= VVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf deleted file mode 100644 index 4f78cfa406..0000000000 --- a/OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.inf +++ /dev/null @@ -1,48 +0,0 @@ -## @file -# Produces the CPU I/O 2 Protocol by using the services of the I/O Librar= y. -# -# Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.
-# Copyright (c) 2016, Linaro Ltd. All rights reserved.
-# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION =3D 0x0001001B - BASE_NAME =3D PciCpuIo2Dxe - FILE_GUID =3D 9BD3C765-2579-4CF0-9349-D77205565030 - MODULE_TYPE =3D DXE_DRIVER - VERSION_STRING =3D 1.0 - ENTRY_POINT =3D PciCpuIo2Initialize - -# -# The following information is for reference only and not required by the = build tools. -# -# VALID_ARCHITECTURES =3D RISCV64 -# - -[Sources] - PciCpuIo2Dxe.c - -[Packages] - OvmfPkg/OvmfPkg.dec - MdePkg/MdePkg.dec - -[LibraryClasses] - UefiDriverEntryPoint - BaseLib - DebugLib - IoLib - PcdLib - UefiBootServicesTableLib - -[Pcd] - gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation - -[Protocols] - gEfiCpuIo2ProtocolGuid ## PRODUCES - -[Depex] - TRUE --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114548): https://edk2.groups.io/g/devel/message/114548 Mute This Topic: https://groups.io/mt/103971666/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-