From nobody Fri Oct 18 05:16:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+114537+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+114537+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1706250550; cv=none; d=zohomail.com; s=zohoarc; b=D7U28n8xDNdCHFIGv9DJl8GiAEPchWEst8E1xfHxyUyip678E4V3xWYoQdY1drvY8dO1e6T5m1AIZQGT2/MR6QQ/mmncEirbutaxPG3rRzrumDCgUg7H8GiRMcLvT/Va9WYOI4CY7C7OqA9A9D6AZFWAdWM837oNkeNxfThMUgg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706250550; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=Z+B8LY2Xo2i58p100E0ZyfwNDd+YyF4fOS/tj6DpkX8=; b=FcRDi95KaOedZCCFUbDnmasSy1Upq4+rac8fiihdJxom8PbUbZ6cu09/FPTO8tbmLQF0wdjYEV9XX2xRz5ELsFCj2QJw4W4+wcSREQvLvPstCtIlkT3KSoMXCC/9Fmo57Yzu6CmfmBK4RsqJD2zw0QCUyrpXmp2/+o9GRdHY5d0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+114537+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1706250549991417.62838746827185; Thu, 25 Jan 2024 22:29:09 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=NhWpiiCHpc+jlIMZ30yNE6HUBcw0/Vue1Op9GMMdqRk=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1706250549; v=1; b=SV1rCpFwxSceM5xedMU2a42dcDPr8JuCtQG3hvOAle+sk7vP1AZrbsjo1E5KRu4cRXOoROeg 52SgE70nDfq400x6Arcm9LloTkp8u1VO0+XY5irFOL6uiKSQLowK4GukxM/9J1mzy9IHgF6Myft PVaEelx0MvkfkDnbEPcjO7fs= X-Received: by 127.0.0.2 with SMTP id oXEmYY1788612xDZGHTfFUjM; Thu, 25 Jan 2024 22:29:09 -0800 X-Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by mx.groups.io with SMTP id smtpd.web11.9996.1706250548387085067 for ; Thu, 25 Jan 2024 22:29:09 -0800 X-Received: from loongson.cn (unknown [10.2.9.245]) by gateway (Coremail) with SMTP id _____8CxmegwUbNl8B0GAA--.2185S3; Fri, 26 Jan 2024 14:29:04 +0800 (CST) X-Received: from code-server.gen (unknown [10.2.9.245]) by localhost.localdomain (Coremail) with SMTP id AQAAf8AxRMwtUbNlEHIbAA--.44272S2; Fri, 26 Jan 2024 14:29:01 +0800 (CST) From: "Chao Li" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [PATCH v8 11/37] UefiCpuPkg: Add LoongArch64 CPU Timer instance Date: Fri, 26 Jan 2024 14:29:00 +0800 Message-Id: <20240126062900.3101491-1-lichao@loongson.cn> In-Reply-To: <20240126062715.3099433-1-lichao@loongson.cn> References: <20240126062715.3099433-1-lichao@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8AxRMwtUbNlEHIbAA--.44272S2 X-CM-SenderInfo: xolfxt3r6o00pqjv00gofq/1tbiAQAICGWyG+ALOQBHsY X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,lichao@loongson.cn List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: gku8esKd87mxweDaTAQbadwox1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1706250550268100001 Content-Type: text/plain; charset="utf-8" Add the LoongArch64 CPU Timer instance to CpuTimerLib, using CPUCFG 0x4 and 0x5 for Stable Counter frequency. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4584 Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Signed-off-by: Chao Li --- .../Library/CpuTimerLib/BaseCpuTimerLib.inf | 9 +- .../CpuTimerLib/LoongArch64/CpuTimerLib.c | 251 ++++++++++++++++++ 2 files changed, 258 insertions(+), 2 deletions(-) create mode 100644 UefiCpuPkg/Library/CpuTimerLib/LoongArch64/CpuTimerLib.c diff --git a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf b/UefiCpuPk= g/Library/CpuTimerLib/BaseCpuTimerLib.inf index de0648de91..7e6152ef7e 100644 --- a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf +++ b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf @@ -5,6 +5,7 @@ # counter features are provided by the processors time stamp counter. # # Copyright (c) 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights= reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -18,18 +19,22 @@ LIBRARY_CLASS =3D TimerLib MODULE_UNI_FILE =3D BaseCpuTimerLib.uni =20 -[Sources] +[Sources.IA32, Sources.X64] CpuTimerLib.c BaseCpuTimerLib.c =20 +[Sources.LOONGARCH64] + LoongArch64/CpuTimerLib.c + [Packages] MdePkg/MdePkg.dec UefiCpuPkg/UefiCpuPkg.dec =20 [LibraryClasses] BaseLib - PcdLib DebugLib + PcdLib + SafeIntLib =20 [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ## CONSUMES diff --git a/UefiCpuPkg/Library/CpuTimerLib/LoongArch64/CpuTimerLib.c b/Uef= iCpuPkg/Library/CpuTimerLib/LoongArch64/CpuTimerLib.c new file mode 100644 index 0000000000..a5ae8d0185 --- /dev/null +++ b/UefiCpuPkg/Library/CpuTimerLib/LoongArch64/CpuTimerLib.c @@ -0,0 +1,251 @@ +/** @file + CPUCFG 0x4 and 0x5 for Stable Counter frequency instance of Timer Librar= y. + + Copyright (c) 2024, Loongson Technology Corporation Limited. All rights = reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include + +/** + Calculate clock frequency using CPUCFG 0x4 and 0x5 registers. + + @param VOID. + + @return The frequency in Hz. + +**/ +STATIC +UINT64 +CalcConstFreq ( + VOID + ) +{ + UINT32 BaseFreq; + UINT64 ClockMultiplier; + UINT32 ClockDivide; + CPUCFG_REG4_INFO_DATA CcFreq; + CPUCFG_REG5_INFO_DATA CpucfgReg5Data; + UINT64 StableTimerFreq; + + // + // Get the the crystal frequency corresponding to the constant + // frequency timer and the clock used by the timer. + // + AsmCpucfg (CPUCFG_REG4_INFO, &CcFreq.Uint32); + + // + // Get the multiplication factor and frequency division factor + // corresponding to the constant frequency timer and the clock + // used by the timer. + // + AsmCpucfg (CPUCFG_REG5_INFO, &CpucfgReg5Data.Uint32); + + BaseFreq =3D CcFreq.Bits.CC_FREQ; + ClockMultiplier =3D CpucfgReg5Data.Bits.CC_MUL & 0xFFFF; + ClockDivide =3D CpucfgReg5Data.Bits.CC_DIV & 0xFFFF; + + if ((BaseFreq =3D=3D 0x0) || (ClockMultiplier =3D=3D 0x0) || (ClockDivid= e =3D=3D 0x0)) { + DEBUG (( + DEBUG_ERROR, + "LoongArch Stable Timer is not available in the CPU, hence this libr= ary cannot be used.\n" + )); + ASSERT (FALSE); + CpuDeadLoop (); + } + + StableTimerFreq =3D ((ClockMultiplier * BaseFreq) / ClockDivide); + + if (StableTimerFreq =3D=3D 0x0) { + ASSERT (FALSE); + } + + return StableTimerFreq; +} + +/** + Stalls the CPU for at least the given number of microseconds. + + Stalls the CPU for the number of microseconds specified by MicroSeconds. + + @param MicroSeconds The minimum number of microseconds to delay. + + @return MicroSeconds + +**/ +UINTN +EFIAPI +MicroSecondDelay ( + IN UINTN MicroSeconds + ) +{ + UINT64 CurrentTicks, ExceptedTicks, Remaining; + RETURN_STATUS Status; + + Status =3D SafeUint64Mult (MicroSeconds, CalcConstFreq (), &Remaining); + ASSERT_RETURN_ERROR (Status); + + ExceptedTicks =3D DivU64x32 (Remaining, 1000000U); + CurrentTicks =3D AsmReadStableCounter (); + ExceptedTicks +=3D CurrentTicks; + + do { + CurrentTicks =3D AsmReadStableCounter (); + } while (CurrentTicks < ExceptedTicks); + + return MicroSeconds; +} + +/** + Stalls the CPU for at least the given number of nanoseconds. + + Stalls the CPU for the number of nanoseconds specified by NanoSeconds. + + @param NanoSeconds The minimum number of nanoseconds to delay. + + @return NanoSeconds + +**/ +UINTN +EFIAPI +NanoSecondDelay ( + IN UINTN NanoSeconds + ) +{ + UINTN MicroSeconds; + + // Round up to 1us Tick Number + MicroSeconds =3D NanoSeconds / 1000; + MicroSeconds +=3D ((NanoSeconds % 1000) =3D=3D 0) ? 0 : 1; + + MicroSecondDelay (MicroSeconds); + + return NanoSeconds; +} + +/** + Retrieves the current value of a 64-bit free running Stable Counter. + + The LoongArch defines a constant frequency timer, whose main body is a + 64-bit counter called StableCounter. StableCounter is set to 0 after + reset, and then increments by 1 every counting clock cycle. When the + count reaches all 1s, it automatically wraps around to 0 and continues + to increment. + The properties of the Stable Counter can be retrieved from + GetPerformanceCounterProperties(). + + @return The current value of the Stable Counter. + +**/ +UINT64 +EFIAPI +GetPerformanceCounter ( + VOID + ) +{ + // + // Just return the value of Stable Counter. + // + return AsmReadStableCounter (); +} + +/** + Retrieves the 64-bit frequency in Hz and the range of Stable Counter + values. + + If StartValue is not NULL, then the value that the stbale counter starts + with immediately after is it rolls over is returned in StartValue. If + EndValue is not NULL, then the value that the stable counter end with + immediately before it rolls over is returned in EndValue. The 64-bit + frequency of the system frequency in Hz is always returned. + + @param StartValue The value the stable counter starts with when it + rolls over. + @param EndValue The value that the stable counter ends with before + it rolls over. + + @return The frequency in Hz. + +**/ +UINT64 +EFIAPI +GetPerformanceCounterProperties ( + OUT UINT64 *StartValue OPTIONAL, + OUT UINT64 *EndValue OPTIONAL + ) +{ + if (StartValue !=3D NULL) { + *StartValue =3D 0; + } + + if (EndValue !=3D NULL) { + *EndValue =3D 0xFFFFFFFFFFFFFFFFULL; + } + + return CalcConstFreq (); +} + +/** + Converts elapsed ticks of performance counter to time in nanoseconds. + + This function converts the elapsed ticks of running performance counter = to + time value in unit of nanoseconds. + + @param Ticks The number of elapsed ticks of running performance cou= nter. + + @return The elapsed time in nanoseconds. + +**/ +UINT64 +EFIAPI +GetTimeInNanoSecond ( + IN UINT64 Ticks + ) +{ + UINT64 Frequency; + UINT64 NanoSeconds; + UINT64 Remainder; + INTN Shift; + RETURN_STATUS Status; + + Frequency =3D GetPerformanceCounterProperties (NULL, NULL); + + // + // Ticks + // Time =3D --------- x 1,000,000,000 + // Frequency + // + Status =3D SafeUint64Mult ( + DivU64x64Remainder (Ticks, Frequency, &Remainder), + 1000000000u, + &NanoSeconds + ); + + // + // Ensure (Remainder * 1,000,000,000) will not overflow 64-bit. + // Since 2^29 < 1,000,000,000 =3D 0x3B9ACA00 < 2^30, Remainder should < = 2^(64-30) =3D 2^34, + // i.e. highest bit set in Remainder should <=3D 33. + // + Shift =3D MAX (0, HighBitSet64 (Remainder) - 33); + Remainder =3D RShiftU64 (Remainder, (UINTN)Shift); + Frequency =3D RShiftU64 (Frequency, (UINTN)Shift); + + Status =3D SafeUint64Add ( + NanoSeconds, + DivU64x64Remainder ( + MultU64x32 (Remainder, 1000000000u), + Frequency, + NULL + ), + &NanoSeconds + ); + ASSERT_RETURN_ERROR (Status); + + return NanoSeconds; +} --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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