From nobody Mon Sep 16 19:40:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+114515+1787277+3901457@groups.io; arc=fail (BodyHash is different from the expected one) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 17062489721847.70705504960938; Thu, 25 Jan 2024 22:02:52 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=r//6tUOrViNK9JRiblHoHVHf4WCcYDQHQNzwxHKpNdg=; c=relaxed/simple; d=groups.io; h=ARC-Seal:ARC-Message-Signature:ARC-Authentication-Results:Received-SPF:From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding:Content-Type; s=20140610; t=1706248971; v=1; b=pdPopLPDaGc1F4V3jtIYOJosECJbfdYZDtZDoLeAwLbnwrmCmS7mbAUMsrojCFhLPLsQw4JK c5TcFIgXWYdvMFl7jKeIZDWMh0JZbd2RjZSWo0DH7Ksk9aF1P8UtOxKAAsEAejxZQWssggjq2bg oEwG8nb/lOZZBckgZRa/d5O4= X-Received: by 127.0.0.2 with SMTP id RkViYY1788612xkGOscKR4gt; Thu, 25 Jan 2024 22:02:51 -0800 X-Received: from NAM12-DM6-obe.outbound.protection.outlook.com (NAM12-DM6-obe.outbound.protection.outlook.com [40.107.243.50]) by mx.groups.io with SMTP id smtpd.web11.9702.1706248971071977576 for ; Thu, 25 Jan 2024 22:02:51 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=lEoPJtTUkDgjzfppzd7cYmpVglhN2QH3XtZmkyN9+344BsRJXHHLJWufev6PzhWX8v4lfO+FgNhy+Y9Reuc57fVi1fI1pt2OkPZUGsGFeAdk2LQU4MKFpTL/jIHpe2HTxe5RHcVX3KvqiywhiA2l4DaNre6VExINhLNHMwHgdmQQw8xaHoe9xmn9AtzjHBvCLmvxsc6yCoKQA+BxYTEo8YnBso10i0cj0jxxMBZW64LMI9W/mIMwUs0FqzQ3fELHdqAQDhp9Eti4sPdhSbPhBDlXKgVIfXwF6Wq0U3D/PJHAg7a8lQCWSmnW7rY1+U7WE9uRfwTgdxsROg745fspAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=B2uw+ecq/el1aPzvjaZvZSlbkT1Vcaj9EJyLVmDMUxY=; b=E+csv16zVvRWHXg8DQawH76TZ7aaOHrphfgnE54BSj2BN0KVz2W9rdSc/SXserXeWzopjAY3HNMi+bBdxwej5V+SG22I3DLbBoNSBijbbPiQ5/jWs9f826pgZjX2r2o6FuY3730s5VDg5INVkYX4zPjLV5trTwwvq2F6ptg+jh6bGpjippsLOQNXwGbBwHT/LeHTXmbfAOLdoTroCzKNRlTc5g251m3J0aDEqCaaR4hSMs2rlsYOVo0gzTmyP9r/TrkR9vysCnq459lqqcwCet3nWQ90ic29ZI4UNWQ/xMZKOUGB4xNkOYXHwY9EgIH7rZtkNe8zeY297xNoMj3/Sg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=edk2.groups.io smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) X-Received: from SJ0PR05CA0078.namprd05.prod.outlook.com (2603:10b6:a03:332::23) by CH3PR12MB8356.namprd12.prod.outlook.com (2603:10b6:610:130::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7228.26; Fri, 26 Jan 2024 06:02:46 +0000 X-Received: from DS2PEPF0000343B.namprd02.prod.outlook.com (2603:10b6:a03:332:cafe::37) by SJ0PR05CA0078.outlook.office365.com (2603:10b6:a03:332::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7249.12 via Frontend Transport; Fri, 26 Jan 2024 06:02:46 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+114515+1787277+3901457@groups.io; helo=mail02.groups.io; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C X-Received: from SATLEXMB04.amd.com (165.204.84.17) by DS2PEPF0000343B.mail.protection.outlook.com (10.167.18.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7228.16 via Frontend Transport; Fri, 26 Jan 2024 06:02:46 +0000 X-Received: from SHA-LX-MINGXZHA.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Fri, 26 Jan 2024 00:02:44 -0600 From: "Zhai, MingXin (Duke) via groups.io" To: CC: Ken Yao , Duke Zhai , Igniculus Fu , Abner Chang Subject: [edk2-devel] [PATCH V2 22/32] AMD/VanGoghBoard: Check in Vtf0 Date: Fri, 26 Jan 2024 14:00:40 +0800 Message-ID: <20240126060050.1725-23-duke.zhai@amd.com> In-Reply-To: <20240126060050.1725-1-duke.zhai@amd.com> References: <20240126060050.1725-1-duke.zhai@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343B:EE_|CH3PR12MB8356:EE_ X-MS-Office365-Filtering-Correlation-Id: e78a7a2e-d1ea-48c8-3f34-08dc1e346b0b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Message-Info: R33CepQWIfB01/uzDrgbhiL+OS5y6H96HunF9irTPtgP/mYw8LhwWJRs20z7TK8dtfuZ5WdM1/wLyaMVlLXU3+amrQvu7aCr5/dPf772//NPWnT+jKugWG25YfuKJZ9VjwXxwot0JTgN4BsYjTL+MW/uayIjxFvMTPXyrJHGgOQWjIfXzoly71qW6JDL34+676SXWaWFC9wXkfEleFNu69vLdP1rlpzB/+xmuV4y3Kh7GiaeSzHie55hInBhlTCfCxTtq25plbRZF+lbEPm+0T5wXyMULzcLnxd3vfMi9XkC/2dkUuNwYyNv5kp0a6k+oDQIaiDBMKR0ee46UzPkoPxoMw1Bqrt+H68BiIkvNSWkfoG5tUmhu9I2zIWTpv540r3fwxZmEbHIZkudkUiqKB3NJQodoV8ImTNc4Pw413r6+UGaFyt43n96r8gnZe6bn6df9QdbL5Me+/QRolF6nisL5b+BzkN38GkC3467a+iSOiKXVw+6VdhparUZvWOYnOc2lHlFt/qDUbDzqUgIwfOUWItvmkcLafcL6nMnpBfo1mCEruwaBcFuUlDGUYl4lOS3DQM/s7K/UnXmFOWG99Tqr0iaQw7AO15WfRnFnIc4m3Gfzo5bDJ4RE4i6PIOobZIC/qP38jMRepyxqLbfeANi29QyxyYA2Or+DffLcJXCTrr3UtO0u0Anrv1kVD3IBjFqPQGlUt3vnXAOTlcS7YHXEoNYUSSM7/m7xA+ngiEse1e5N5BIqVCDnzylS7r8Z/04KdiHMTMleOHYZbuDqw== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jan 2024 06:02:46.2018 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e78a7a2e-d1ea-48c8-3f34-08dc1e346b0b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8356 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,duke.zhai@amd.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: DVLltw2J0raTGnt88mt3Su8Yx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1706248973224100007 Content-Type: text/plain; charset="utf-8" From: Duke Zhai BZ #:4640 In V2: Improve coding style. 1.Remove the leading underscore and use double underscore at trailing in = C header files. 2.Remove old tianocore licenses and redundant license description. 3.Improve coding style. For example: remove space between @param. In V1: Initial Vtf0 module. This module includes all assembly code files of reset vector. Signed-off-by: Eric Xing Cc: Ken Yao Cc: Duke Zhai Cc: Igniculus Fu Cc: Abner Chang --- .../ResetVector/Vtf0/CommonMacros.inc | 27 +++ .../ResetVector/Vtf0/DebugDisabled.asm | 21 ++ .../ResetVector/Vtf0/Ia16/Init16.asm | 51 +++++ .../ResetVector/Vtf0/Ia16/Real16ToFlat32.asm | 138 +++++++++++++ .../ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm | 108 ++++++++++ .../ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm | 40 ++++ .../ResetVector/Vtf0/Ia32/PageTables64.asm | 25 +++ .../Vtf0/Ia32/SearchForBfvBase.asm | 84 ++++++++ .../Vtf0/Ia32/SearchForSecEntry.asm | 195 ++++++++++++++++++ .../edk2/UefiCpuPkg/ResetVector/Vtf0/Main.asm | 127 ++++++++++++ .../ResetVector/Vtf0/Port80Debug.asm | 23 +++ .../UefiCpuPkg/ResetVector/Vtf0/PostCodes.inc | 20 ++ .../ResetVector/Vtf0/ResetVector.uni | Bin 0 -> 780 bytes .../ResetVector/Vtf0/ResetVectorExtra.uni | Bin 0 -> 682 bytes .../ResetVector/Vtf0/SerialDebug.asm | 127 ++++++++++++ .../edk2/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf | 37 ++++ .../UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 67 ++++++ .../ResetVector/Vtf0/X64/PageTables.asm | 73 +++++++ 18 files changed, 1163 insertions(+) create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Rese= tVector/Vtf0/CommonMacros.inc create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Rese= tVector/Vtf0/DebugDisabled.asm create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Rese= tVector/Vtf0/Ia16/Init16.asm create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Rese= tVector/Vtf0/Ia16/Real16ToFlat32.asm create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Rese= tVector/Vtf0/Ia16/ResetVectorVtf0.asm create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Rese= tVector/Vtf0/Ia32/Flat32ToFlat64.asm create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Rese= tVector/Vtf0/Ia32/PageTables64.asm create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Rese= tVector/Vtf0/Ia32/SearchForBfvBase.asm create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Rese= tVector/Vtf0/Ia32/SearchForSecEntry.asm create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Rese= tVector/Vtf0/Main.asm create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Rese= tVector/Vtf0/Port80Debug.asm create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Rese= tVector/Vtf0/PostCodes.inc create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Rese= tVector/Vtf0/ResetVector.uni create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Rese= tVector/Vtf0/ResetVectorExtra.uni create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Rese= tVector/Vtf0/SerialDebug.asm create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Rese= tVector/Vtf0/Vtf0.inf create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Rese= tVector/Vtf0/Vtf0.nasmb create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Rese= tVector/Vtf0/X64/PageTables.asm diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector= /Vtf0/CommonMacros.inc b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg= /ResetVector/Vtf0/CommonMacros.inc new file mode 100644 index 0000000000..5da472faaa --- /dev/null +++ b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/C= ommonMacros.inc @@ -0,0 +1,27 @@ +;-------------------------------------------------------------------------= ----- +; @file +; Common macros used in the ResetVector VTF module. +; +; Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+; Copyright (c) 2008, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;-------------------------------------------------------------------------= ----- + +%define ADDR16_OF(x) (0x10000 - fourGigabytes + x) +%define ADDR_OF(x) (0x100000000 - fourGigabytes + x) +%define ADDR_OF_MEM(x) (VIRTUAL4G - fourGigabytes + x) +%define SMM_RESUME_SIGNATURE 0x55AABB66 +%macro OneTimeCall 1 + jmp %1 +%1 %+ OneTimerCallReturn: +%endmacro + +%macro OneTimeCallRet 1 + jmp %1 %+ OneTimerCallReturn +%endmacro + +StartOfResetVectorCode: + +%define ADDR_OF_START_OF_RESET_CODE ADDR_OF(StartOfResetVectorCode) + diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector= /Vtf0/DebugDisabled.asm b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPk= g/ResetVector/Vtf0/DebugDisabled.asm new file mode 100644 index 0000000000..540206a1d0 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/D= ebugDisabled.asm @@ -0,0 +1,21 @@ +;-------------------------------------------------------------------------= ----- +; @file +; Debug disabled +; +; Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+; Copyright (c) 2009, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;-------------------------------------------------------------------------= ----- + +BITS 16 + +%macro debugInitialize 0 + ; + ; No initialization is required + ; +%endmacro + +%macro debugShowPostCode 1 +%endmacro + diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector= /Vtf0/Ia16/Init16.asm b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/= ResetVector/Vtf0/Ia16/Init16.asm new file mode 100644 index 0000000000..36641c578b --- /dev/null +++ b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/I= a16/Init16.asm @@ -0,0 +1,51 @@ +;-------------------------------------------------------------------------= ----- +; @file +; 16-bit initialization code +; +; Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+; Copyright (c) 2008 - 2009, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;-------------------------------------------------------------------------= ----- + + +BITS 16 + +ALIGN 4 +SMMResumeInfo: ;; This offset can bie found as 0xFFFFFFF5 + word [0xFFFFFF= F3] - 0x10(16) + DD ADDR_OF_MEM(GDT_BASE) ; GDT base address + DW LINEAR_CODE_SEL ; code segment + DW LINEAR_SEL ; data segment + DD ADDR_OF_MEM(Main32) ; Offset of our 32 bit code + DD SMM_RESUME_SIGNATURE + +; +; @param[out] DI 'BP' to indicate boot-strap processor +; +EarlyBspInitReal16: + mov di, 'BP' + jmp short Main16 + +; +; @param[out] DI 'AP' to indicate application processor +; +EarlyApInitReal16: + mov di, 'AP' + jmp short Main16 + +; +; Modified: EAX +; +; @param[in] EAX Initial value of the EAX register (BIST: Built-in Self= Test) +; @param[out] ESP Initial value of the EAX register (BIST: Built-in Self= Test) +; +EarlyInit16: + ; + ; ESP - Initial value of the EAX register (BIST: Built-in Self Test) + ; + mov esp, eax + + debugInitialize + + OneTimeCallRet EarlyInit16 + diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector= /Vtf0/Ia16/Real16ToFlat32.asm b/Platform/AMD/VanGoghBoard/Override/edk2/Uef= iCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm new file mode 100644 index 0000000000..f986761488 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/I= a16/Real16ToFlat32.asm @@ -0,0 +1,138 @@ +;-------------------------------------------------------------------------= ----- +; @file +; Transition from 16 bit real mode into 32 bit flat protected mode +; +; Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+; Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;-------------------------------------------------------------------------= ----- + +%define SEC_DEFAULT_CR0 0x40000023 +%define SEC_DEFAULT_CR4 0x640 + +BITS 16 + +; +; Modified: EAX, EBX +; +; @param[out] DS Selector allowing flat access to all addresses +; @param[out] ES Selector allowing flat access to all addresses +; @param[out] FS Selector allowing flat access to all addresses +; @param[out] GS Selector allowing flat access to all addresses +; @param[out] SS Selector allowing flat access to all addresses +; +TransitionFromReal16To32BitFlat: + movd mm0, eax ; ( BIST ) + + debugShowPostCode POSTCODE_16BIT_MODE + + cli + + mov bx, ADDR16_OF(gdtrmem) + +o32 lgdt [cs:bx] + + mov eax, SEC_DEFAULT_CR0 + mov cr0, eax + + mov edx, VIRTUAL4G + jmp LINEAR_CODE_SEL:dword ADDR_OF_MEM(jumpTo32BitAndLandHere) + +BITS 32 +jumpTo32BitAndLandHere: + + mov eax, SEC_DEFAULT_CR4 + mov cr4, eax + + debugShowPostCode POSTCODE_32BIT_MODE + + mov ax, LINEAR_SEL + mov ds, ax + mov es, ax + mov fs, ax + mov gs, ax + mov ss, ax + + OneTimeCallRet TransitionFromReal16To32BitFlat + +ALIGN 2 + +gdtrmem: + dw GDT_END - GDT_BASE - 1 ; GDT limit + dd ADDR_OF_MEM(GDT_BASE) + +gdtr: + dw GDT_END - GDT_BASE - 1 ; GDT limit + dd ADDR_OF(GDT_BASE) + +ALIGN 16 + +; +; Macros for GDT entries +; + +%define PRESENT_FLAG(p) (p << 7) +%define DPL(dpl) (dpl << 5) +%define SYSTEM_FLAG(s) (s << 4) +%define DESC_TYPE(t) (t) + +; Type: data, expand-up, writable, accessed +%define DATA32_TYPE 3 + +; Type: execute, readable, expand-up, accessed +%define CODE32_TYPE 0xb + +; Type: execute, readable, expand-up, accessed +%define CODE64_TYPE 0xb + +%define GRANULARITY_FLAG(g) (g << 7) +%define DEFAULT_SIZE32(d) (d << 6) +%define CODE64_FLAG(l) (l << 5) +%define UPPER_LIMIT(l) (l) + +; +; The Global Descriptor Table (GDT) +; + +GDT_BASE: +; null descriptor +NULL_SEL equ $-GDT_BASE + DW 0 ; limit 15:0 + DW 0 ; base 15:0 + DB 0 ; base 23:16 + DB 0 ; sys flag, dpl, type + DB 0 ; limit 19:16, flags + DB 0 ; base 31:24 + +; linear data segment descriptor +LINEAR_SEL equ $-GDT_BASE + DW 0xffff ; limit 15:0 + DW 0 ; base 15:0 + DB 0 ; base 23:16 + DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(DATA32_TYPE) + DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(1)|CODE64_FLAG(0)|UPPER_LIM= IT(0xf) + DB 0 ; base 31:24 + +; linear code segment descriptor +LINEAR_CODE_SEL equ $-GDT_BASE + DW 0xffff ; limit 15:0 + DW 0 ; base 15:0 + DB 0 ; base 23:16 + DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(CODE32_TYPE) + DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(1)|CODE64_FLAG(0)|UPPER_LIM= IT(0xf) + DB 0 ; base 31:24 + +%ifdef ARCH_X64 +; linear code (64-bit) segment descriptor +LINEAR_CODE64_SEL equ $-GDT_BASE + DW 0xffff ; limit 15:0 + DW 0 ; base 15:0 + DB 0 ; base 23:16 + DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(CODE64_TYPE) + DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(0)|CODE64_FLAG(1)|UPPER_LIM= IT(0xf) + DB 0 ; base 31:24 +%endif + +GDT_END: + diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector= /Vtf0/Ia16/ResetVectorVtf0.asm b/Platform/AMD/VanGoghBoard/Override/edk2/Ue= fiCpuPkg/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm new file mode 100644 index 0000000000..8234366b2a --- /dev/null +++ b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/I= a16/ResetVectorVtf0.asm @@ -0,0 +1,108 @@ +;-------------------------------------------------------------------------= ----- +; @file +; First code executed by processor after resetting. +; +; Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;-------------------------------------------------------------------------= ----- + +BITS 16 + +ALIGN 16 + +; +; Pad the image size to 4k when page tables are in VTF0 +; +; If the VTF0 image has page tables built in, then we need to make +; sure the end of VTF0 is 4k above where the page tables end. +; +; This is required so the page tables will be 4k aligned when VTF0 is +; located just below 0x100000000 (4GB) in the firmware device. +; +%ifdef ALIGN_TOP_TO_4K_FOR_PAGING + TIMES (0x1000 - ($ - EndOfPageTables) - 0x50) DB 0 +%endif + +; 16 bytes reserved for Anti-rollback security level +; - 04 bytes: Security level +; - 12 bytes: Pad 0x00 + DD AntiRollback_SecurityLevel + TIMES 12 DB 0 + +; +; 32 bytes reserved for BIOS version string and build date and time +; Signature 4 bytes: BIVS +; Pad0 1 byte, 00 +; Version 8 bytes, such as UMD9B18C +; Pad1 1 byte, 00 +; Date 4 bytes, such as 20191118 +; Pad2 1 byte, 00 +; Time 3 bytes, such as 113028 +; Pad3 10 byte, 00 +; + +BiosVersionDateTimeSignature: + DB 'B', 'I', 'V', 'S' + +Pad0: + DB 0 + +Version: + TIMES 8 DB 0 + +Pad1: + DB 0 + +Date: + TIMES 4 DB 0 + +Pad2: + DB 0 + +DateTime: + TIMES 7 DB 0 + +Pad3: + TIMES 10 DB 0 + +applicationProcessorEntryPoint: +; +; Application Processors entry point +; +; GenFv generates code aligned on a 4k boundary which will jump to this +; location. (0xffffffe0) This allows the Local APIC Startup IPI to be +; used to wake up the application processors. +; + jmp EarlyApInitReal16 + +ALIGN 8 + + DD 0 + +; +; The VTF signature +; +; VTF-0 means that the VTF (Volume Top File) code does not require +; any fixups. +; +vtfSignature: + DB 'V', 'T', 'F', 0 + +ALIGN 16 + +resetVector: +; +; Reset Vector +; +; This is where the processor will begin execution +; + nop + nop + jmp near EarlyBspInitReal16 + +ALIGN 16 + +fourGigabytes: + diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector= /Vtf0/Ia32/Flat32ToFlat64.asm b/Platform/AMD/VanGoghBoard/Override/edk2/Uef= iCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm new file mode 100644 index 0000000000..121046fbaf --- /dev/null +++ b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/I= a32/Flat32ToFlat64.asm @@ -0,0 +1,40 @@ +;-------------------------------------------------------------------------= ----- +; @file +; Transition from 32 bit flat protected mode into 64 bit flat protected mo= de +; +; Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+; Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;-------------------------------------------------------------------------= ----- + +BITS 32 + +; +; Modified: EAX +; +Transition32FlatTo64Flat: + + OneTimeCall SetCr3ForPageTables64 + + mov eax, cr4 + bts eax, 5 ; enable PAE + mov cr4, eax + + mov ecx, 0xc0000080 + rdmsr + bts eax, 8 ; set LME + wrmsr + + mov eax, cr0 + bts eax, 31 ; set PG + mov cr0, eax ; enable paging + + jmp LINEAR_CODE64_SEL:ADDR_OF(jumpTo64BitAndLandHere) +BITS 64 +jumpTo64BitAndLandHere: + + debugShowPostCode POSTCODE_64BIT_MODE + + OneTimeCallRet Transition32FlatTo64Flat + diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector= /Vtf0/Ia32/PageTables64.asm b/Platform/AMD/VanGoghBoard/Override/edk2/UefiC= puPkg/ResetVector/Vtf0/Ia32/PageTables64.asm new file mode 100644 index 0000000000..14baa6e987 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/I= a32/PageTables64.asm @@ -0,0 +1,25 @@ +;-------------------------------------------------------------------------= ----- +; @file +; Sets the CR3 register for 64-bit paging +; +; Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;-------------------------------------------------------------------------= ----- + +BITS 32 + +; +; Modified: EAX +; +SetCr3ForPageTables64: + + ; + ; These pages are built into the ROM image in X64/PageTables.asm + ; + mov eax, ADDR_OF(TopLevelPageDirectory) + mov cr3, eax + + OneTimeCallRet SetCr3ForPageTables64 + diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector= /Vtf0/Ia32/SearchForBfvBase.asm b/Platform/AMD/VanGoghBoard/Override/edk2/U= efiCpuPkg/ResetVector/Vtf0/Ia32/SearchForBfvBase.asm new file mode 100644 index 0000000000..533004be7e --- /dev/null +++ b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/I= a32/SearchForBfvBase.asm @@ -0,0 +1,84 @@ +;-------------------------------------------------------------------------= ----- +; @file +; Search for the Boot Firmware Volume (BFV) base address +; +; Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+; Copyright (c) 2008 - 2022, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;-------------------------------------------------------------------------= ----- + +;#define EFI_FIRMWARE_FILE_SYSTEM2_GUID \ +; { 0x8c8ce578, 0x8a3d, 0x4f1c, { 0x99, 0x35, 0x89, 0x61, 0x85, 0xc3, 0x2= d, 0xd3 } } +%define FFS_GUID_DWORD0 0x8c8ce578 +%define FFS_GUID_DWORD1 0x4f1c8a3d +%define FFS_GUID_DWORD2 0x61893599 +%define FFS_GUID_DWORD3 0xd32dc385 + +BITS 32 + +; +; Modified: EAX, EBX +; Preserved: EDI, ESP +; +; @param[out] EBP Address of Boot Firmware Volume (BFV) +; +Flat32SearchForBfvBase: + + mov eax, edx ; edx maps 4G for SOC 15 or 0xA000000 for SOC 17 + mov esi, eax + sub esi, 0x1000000 +searchingForBfvHeaderLoop: + ; + ; We check for a firmware volume at every 4KB address in the top 16MB + ; just below 4GB. (Addresses at 0xffHHH000 where H is any hex digit.) + ; + sub eax, 0x1000 + cmp eax, esi + jb searchedForBfvHeaderButNotFound + + ; + ; Check FFS GUID + ; + cmp dword [eax + 0x10], FFS_GUID_DWORD0 + jne searchingForBfvHeaderLoop + cmp dword [eax + 0x14], FFS_GUID_DWORD1 + jne searchingForBfvHeaderLoop + cmp dword [eax + 0x18], FFS_GUID_DWORD2 + jne searchingForBfvHeaderLoop + cmp dword [eax + 0x1c], FFS_GUID_DWORD3 + jne searchingForBfvHeaderLoop + + ; + ; Check FV Length + ; + cmp dword [eax + 0x24], 0 + jne searchingForBfvHeaderLoop + mov ebx, eax + add ebx, dword [eax + 0x20] + cmp ebx, edx + jnz searchingForBfvHeaderLoop + + jmp searchedForBfvHeaderAndItWasFound + +searchedForBfvHeaderButNotFound: + ; + ; Hang if the SEC entry point was not found + ; + debugShowPostCode POSTCODE_BFV_NOT_FOUND + + ; + ; 0xbfbfbfbf in the EAX & EBP registers helps signal what failed + ; for debugging purposes. + ; + mov eax, 0xBFBFBFBF + mov ebp, eax + jmp $ + +searchedForBfvHeaderAndItWasFound: + mov ebp, eax + + debugShowPostCode POSTCODE_BFV_FOUND + + OneTimeCallRet Flat32SearchForBfvBase + diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector= /Vtf0/Ia32/SearchForSecEntry.asm b/Platform/AMD/VanGoghBoard/Override/edk2/= UefiCpuPkg/ResetVector/Vtf0/Ia32/SearchForSecEntry.asm new file mode 100644 index 0000000000..5bc83f39e5 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/I= a32/SearchForSecEntry.asm @@ -0,0 +1,195 @@ +;-------------------------------------------------------------------------= ----- +; @file +; Search for the SEC Core entry point +; +; Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+; Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;-------------------------------------------------------------------------= ----- + +BITS 32 + +%define EFI_FV_FILETYPE_SECURITY_CORE 0x03 + +; +; Modified: EAX, EBX, ECX, EDX +; Preserved: EDI, EBP, ESP +; +; @param[in] EBP Address of Boot Firmware Volume (BFV) +; @param[out] ESI SEC Core Entry Point Address +; +Flat32SearchForSecEntryPoint: + + ; + ; Initialize EBP and ESI to 0 + ; + xor ebx, ebx + mov esi, ebx + + ; + ; Pass over the BFV header + ; + mov eax, ebp + mov bx, [ebp + 0x30] + add eax, ebx + jc secEntryPointWasNotFound + + jmp searchingForFfsFileHeaderLoop + +moveForwardWhileSearchingForFfsFileHeaderLoop: + ; + ; Make forward progress in the search + ; + inc eax + jc secEntryPointWasNotFound + +searchingForFfsFileHeaderLoop: + test eax, eax + jz secEntryPointWasNotFound + + ; + ; Ensure 8 byte alignment + ; + add eax, 7 + jc secEntryPointWasNotFound + and al, 0xf8 + + ; + ; Look to see if there is an FFS file at eax + ; + mov bl, [eax + 0x17] + test bl, 0x20 + jz moveForwardWhileSearchingForFfsFileHeaderLoop + mov ecx, [eax + 0x14] + and ecx, 0x00ffffff + or ecx, ecx + jz moveForwardWhileSearchingForFfsFileHeaderLoop + add ecx, eax + jz jumpSinceWeFoundTheLastFfsFile + jc moveForwardWhileSearchingForFfsFileHeaderLoop +jumpSinceWeFoundTheLastFfsFile: + + ; + ; There seems to be a valid file at eax + ; + cmp byte [eax + 0x12], EFI_FV_FILETYPE_SECURITY_CORE ; Check File = Type + jne readyToTryFfsFileAtEcx + +fileTypeIsSecCore: + OneTimeCall GetEntryPointOfFfsFile + test eax, eax + jnz doneSeachingForSecEntryPoint + +readyToTryFfsFileAtEcx: + ; + ; Try the next FFS file at ECX + ; + mov eax, ecx + jmp searchingForFfsFileHeaderLoop + +secEntryPointWasNotFound: + xor eax, eax + +doneSeachingForSecEntryPoint: + mov esi, eax + + test esi, esi + jnz secCoreEntryPointWasFound + +secCoreEntryPointWasNotFound: + ; + ; Hang if the SEC entry point was not found + ; + debugShowPostCode POSTCODE_SEC_NOT_FOUND + jz $ + +secCoreEntryPointWasFound: + debugShowPostCode POSTCODE_SEC_FOUND + + OneTimeCallRet Flat32SearchForSecEntryPoint + +%define EFI_SECTION_PE32 0x10 +%define EFI_SECTION_TE 0x12 + +; +; Input: +; EAX - Start of FFS file +; ECX - End of FFS file +; +; Output: +; EAX - Entry point of PE32 (or 0 if not found) +; +; Modified: +; EBX +; +GetEntryPointOfFfsFile: + test eax, eax + jz getEntryPointOfFfsFileErrorReturn + add eax, 0x18 ; EAX =3D Start of section + +getEntryPointOfFfsFileLoopForSections: + cmp eax, ecx + jae getEntryPointOfFfsFileErrorReturn + + cmp byte [eax + 3], EFI_SECTION_PE32 + je getEntryPointOfFfsFileFoundPe32Section + + cmp byte [eax + 3], EFI_SECTION_TE + je getEntryPointOfFfsFileFoundTeSection + + ; + ; The section type was not PE32 or TE, so move to next section + ; + mov ebx, dword [eax] + and ebx, 0x00ffffff + add eax, ebx + jc getEntryPointOfFfsFileErrorReturn + + ; + ; Ensure that FFS section is 32-bit aligned + ; + add eax, 3 + jc getEntryPointOfFfsFileErrorReturn + and al, 0xfc + jmp getEntryPointOfFfsFileLoopForSections + +getEntryPointOfFfsFileFoundPe32Section: + add eax, 4 ; EAX =3D Start of PE32 image + + cmp word [eax], 'MZ' + jne getEntryPointOfFfsFileErrorReturn + movzx ebx, word [eax + 0x3c] + add ebx, eax + + ; if (Hdr.Pe32->Signature =3D=3D EFI_IMAGE_NT_SIGNATURE) + cmp dword [ebx], `PE\x00\x00` + jne getEntryPointOfFfsFileErrorReturn + + ; *EntryPoint =3D (VOID *)((UINTN)Pe32Data + + ; (UINTN)(Hdr.Pe32->OptionalHeader.AddressOfEntryPoint & 0x0ffffffff= )); + add eax, [ebx + 0x4 + 0x14 + 0x10] + jmp getEntryPointOfFfsFileReturn + +getEntryPointOfFfsFileFoundTeSection: + add eax, 4 ; EAX =3D Start of TE image + mov ebx, eax + + ; if (Hdr.Te->Signature =3D=3D EFI_TE_IMAGE_HEADER_SIGNATURE) + cmp word [ebx], 'VZ' + jne getEntryPointOfFfsFileErrorReturn + ; *EntryPoint =3D (VOID *)((UINTN)Pe32Data + + ; (UINTN)(Hdr.Te->AddressOfEntryPoint & 0x0ffffffff) + + ; sizeof(EFI_TE_IMAGE_HEADER) - Hdr.Te->StrippedSize); + add eax, [ebx + 0x8] + add eax, 0x28 + movzx ebx, word [ebx + 0x6] + sub eax, ebx + jmp getEntryPointOfFfsFileReturn + +getEntryPointOfFfsFileErrorReturn: + mov eax, 0 + +getEntryPointOfFfsFileReturn: + OneTimeCallRet GetEntryPointOfFfsFile + diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector= /Vtf0/Main.asm b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVe= ctor/Vtf0/Main.asm new file mode 100644 index 0000000000..08b6076bb8 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/M= ain.asm @@ -0,0 +1,127 @@ +;-------------------------------------------------------------------------= ----- +; @file +; Main routine of the pre-SEC code up through the jump into SEC +; +; Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+; Copyright (c) 2008 - 2009, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;-------------------------------------------------------------------------= ----- + + +BITS 16 + +; +; Modified: EBX, ECX, EDX, EBP +; +; @param[in,out] RAX/EAX Initial value of the EAX register +; (BIST: Built-in Self Test) +; @param[in,out] DI 'BP': boot-strap processor, or +; 'AP': application processor +; @param[out] RBP/EBP Address of Boot Firmware Volume (BFV) +; @param[out] DS Selector allowing flat access to all addresses +; @param[out] ES Selector allowing flat access to all addresses +; @param[out] FS Selector allowing flat access to all addresses +; @param[out] GS Selector allowing flat access to all addresses +; @param[out] SS Selector allowing flat access to all addresses +; +; @return None This routine jumps to SEC and does not return +; +Main16: + OneTimeCall EarlyInit16 + + ; + ; Transition the processor from 16-bit real mode to 32-bit flat mode + ; + OneTimeCall TransitionFromReal16To32BitFlat + +BITS 32 + jmp Not_S3Resume + +Main32: + cmp edx, SMM_RESUME_SIGNATURE + jne Not_S3Resume + + mov ebx, esp + push ebx + + push eax + push edx + + mov eax, esi + push eax + + mov eax, edi + push eax + + mov edi, SMM_RESUME_SIGNATURE + mov edx, VIRTUAL4G + +Not_S3Resume: + ; + ; Search for the Boot Firmware Volume (BFV) + ; + OneTimeCall Flat32SearchForBfvBase + + ; + ; EBP - Start of BFV + ; + + ; + ; Search for the SEC entry point + ; + OneTimeCall Flat32SearchForSecEntryPoint + + ; + ; ESI - SEC Core entry point + ; EBP - Start of BFV + ; + +%ifdef ARCH_IA32 + + ; + ; Restore initial EAX value into the EAX register + ; + mov eax, esp + + ; + ; Jump to the 32-bit SEC entry point + ; + jmp esi + +%else + + ; + ; Transition the processor from 32-bit flat mode to 64-bit flat mode + ; + OneTimeCall Transition32FlatTo64Flat + +BITS 64 + + ; + ; Some values were calculated in 32-bit mode. Make sure the upper + ; 32-bits of 64-bit registers are zero for these values. + ; + mov rax, 0x00000000ffffffff + and rsi, rax + and rbp, rax + and rsp, rax + + ; + ; RSI - SEC Core entry point + ; RBP - Start of BFV + ; + + ; + ; Restore initial EAX value into the RAX register + ; + mov rax, rsp + + ; + ; Jump to the 64-bit SEC entry point + ; + jmp rsi + +%endif + + diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector= /Vtf0/Port80Debug.asm b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/= ResetVector/Vtf0/Port80Debug.asm new file mode 100644 index 0000000000..7cb83244df --- /dev/null +++ b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/P= ort80Debug.asm @@ -0,0 +1,23 @@ +;-------------------------------------------------------------------------= ----- +; @file +; Port 0x80 debug support macros +; +; Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+; Copyright (c) 2009, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;-------------------------------------------------------------------------= ----- + +BITS 16 + +%macro debugInitialize 0 + ; + ; No initialization is required + ; +%endmacro + +%macro debugShowPostCode 1 + mov al, %1 + out 0x80, al +%endmacro + diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector= /Vtf0/PostCodes.inc b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Re= setVector/Vtf0/PostCodes.inc new file mode 100644 index 0000000000..326c8621d7 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/P= ostCodes.inc @@ -0,0 +1,20 @@ +;-------------------------------------------------------------------------= ----- +; @file +; Definitions of POST CODES for the reset vector module +; +; Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+; Copyright (c) 2009, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;-------------------------------------------------------------------------= ----- + +%define POSTCODE_16BIT_MODE 0x16 +%define POSTCODE_32BIT_MODE 0x32 +%define POSTCODE_64BIT_MODE 0x64 + +%define POSTCODE_BFV_NOT_FOUND 0xb0 +%define POSTCODE_BFV_FOUND 0xb1 + +%define POSTCODE_SEC_NOT_FOUND 0xf0 +%define POSTCODE_SEC_FOUND 0xf1 + diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector= /Vtf0/ResetVector.uni b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/= ResetVector/Vtf0/ResetVector.uni new file mode 100644 index 0000000000000000000000000000000000000000..b05945351150015ad85feecf680= a5dc2cb41f894 GIT binary patch literal 780 zcmbu7O-sW-5Qg8gzaq3371LBH9z?{n^-%C5G*!GwNn;I!RMHRd&#TXDlH#E~s4Uyg z&d$vH%xu0s0|oNf$1G3RdR3-esSfbj%@}*hUSU7+pI|Li*7r@+0N=3DYl@MoIq%|#z- zpd+%*)MfXuLd~?%R0UO1Y)^N@CuA+Khxj(`Y>Fp%MlQ1BGIOZBAN7~+RI!!hS-p-f z)ra_MOTU{d*>ZJtP92|Zl&4TOx+^N0qE#sA&3>o!m0=3DYqSvP-SY9OR78!zpw+b`zp9A#UGlI|i$@Mt=3D^c=3DeT`p#n`RA-%jfnJVU5rNXE=3D1f@cKn K{Z6L;@_YjtHFW_1 literal 0 HcmV?d00001 diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector= /Vtf0/ResetVectorExtra.uni b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCp= uPkg/ResetVector/Vtf0/ResetVectorExtra.uni new file mode 100644 index 0000000000000000000000000000000000000000..332232d2a2aa0cb9abd8e87dd12= 69917382e2af5 GIT binary patch literal 682 zcmbu7OH0E*6ot<^zhbBx71L;OB_i4;3&Ch3D=3D9((NW}XrH8~a@koCR{B2Kx=3DNP)_VjpLj}a8Qz9_t%@9n zxAyh{u{FM_Ki8GF_09LH51&`*nJA}y4RnC)>6m?rc14|)uUBk(rSvJtTHuYbt^D1v z9$~qrQ=3DzWUoP*K*sc*;{GK^J2o?-9mTz$A+?0C21Dt5R|z_smU%&dpyG_bKVhsg}B z{s)Tf8)X{8@lheKZmjJc4SfjD(%-C?P0kpdfuzqYV*EY!0BpIIn~b4H);0 +; Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;-------------------------------------------------------------------------= ----- + +;//--------------------------------------------- +;// UART Register Offsets +;//--------------------------------------------- +%define BAUD_LOW_OFFSET 0x00 +%define BAUD_HIGH_OFFSET 0x01 +%define IER_OFFSET 0x01 +%define LCR_SHADOW_OFFSET 0x01 +%define FCR_SHADOW_OFFSET 0x02 +%define IR_CONTROL_OFFSET 0x02 +%define FCR_OFFSET 0x02 +%define EIR_OFFSET 0x02 +%define BSR_OFFSET 0x03 +%define LCR_OFFSET 0x03 +%define MCR_OFFSET 0x04 +%define LSR_OFFSET 0x05 +%define MSR_OFFSET 0x06 + +;//--------------------------------------------- +;// UART Register Bit Defines +;//--------------------------------------------- +%define LSR_TXRDY 0x20 +%define LSR_RXDA 0x01 +%define DLAB 0x01 + +; UINT16 gComBase =3D 0x3f8; +; UINTN gBps =3D 115200; +; UINT8 gData =3D 8; +; UINT8 gStop =3D 1; +; UINT8 gParity =3D 0; +; UINT8 gBreakSet =3D 0; + +%define DEFAULT_COM_BASE 0x3f8 +%define DEFAULT_BPS 115200 +%define DEFAULT_DATA 8 +%define DEFAULT_STOP 1 +%define DEFAULT_PARITY 0 +%define DEFAULT_BREAK_SET 0 + +%define SERIAL_DEFAULT_LCR ( \ + (DEFAULT_BREAK_SET << 6) | \ + (DEFAULT_PARITY << 3) | \ + (DEFAULT_STOP << 2) | \ + (DEFAULT_DATA - 5) \ + ) + +%define SERIAL_PORT_IO_BASE_ADDRESS DEFAULT_COM_BASE + +%macro inFromSerialPort 1 + mov dx, (SERIAL_PORT_IO_BASE_ADDRESS + %1) + in al, dx +%endmacro + +%macro waitForSerialTxReady 0 + +%%waitingForTx: + inFromSerialPort LSR_OFFSET + test al, LSR_TXRDY + jz %%waitingForTx + +%endmacro + +%macro outToSerialPort 2 + mov dx, (SERIAL_PORT_IO_BASE_ADDRESS + %1) + mov al, %2 + out dx, al +%endmacro + +%macro debugShowCharacter 1 + waitForSerialTxReady + outToSerialPort 0, %1 +%endmacro + +%macro debugShowHexDigit 1 + %if (%1 < 0xa) + debugShowCharacter BYTE ('0' + (%1)) + %else + debugShowCharacter BYTE ('a' + ((%1) - 0xa)) + %endif +%endmacro + +%macro debugNewline 0 + debugShowCharacter `\r` + debugShowCharacter `\n` +%endmacro + +%macro debugShowPostCode 1 + debugShowHexDigit (((%1) >> 4) & 0xf) + debugShowHexDigit ((%1) & 0xf) + debugNewline +%endmacro + +BITS 16 + +%macro debugInitialize 0 + jmp real16InitDebug +real16InitDebugReturn: +%endmacro + +real16InitDebug: + ; + ; Set communications format + ; + outToSerialPort LCR_OFFSET, ((DLAB << 7) | SERIAL_DEFAULT_LCR) + + ; + ; Configure baud rate + ; + outToSerialPort BAUD_HIGH_OFFSET, ((115200 / DEFAULT_BPS) >> 8) + outToSerialPort BAUD_LOW_OFFSET, ((115200 / DEFAULT_BPS) & 0xff) + + ; + ; Switch back to bank 0 + ; + outToSerialPort LCR_OFFSET, SERIAL_DEFAULT_LCR + + jmp real16InitDebugReturn + diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector= /Vtf0/Vtf0.inf b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVe= ctor/Vtf0/Vtf0.inf new file mode 100644 index 0000000000..6271e7ac7f --- /dev/null +++ b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/V= tf0.inf @@ -0,0 +1,37 @@ +## @file +# Reset Vector +# +# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D ResetVector + FILE_GUID =3D 1BA0062E-C779-4582-8566-336AE8F78F09 + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.1 + MODULE_UNI_FILE =3D ResetVector.uni + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +[Sources] + Vtf0.nasmb + +[Packages] + MdePkg/MdePkg.dec + ChachaniBoardPkg/Project.dec + +[Pcd] + gPlatformPkgTokenSpaceGuid.PcdMemoryFvRecoveryBase + gPlatformPkgTokenSpaceGuid.PcdFlashFvRecoverySize + +[UserExtensions.TianoCore."ExtraFiles"] + ResetVectorExtra.uni diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector= /Vtf0/Vtf0.nasmb b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/Reset= Vector/Vtf0/Vtf0.nasmb new file mode 100644 index 0000000000..5eaa95148f --- /dev/null +++ b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/V= tf0.nasmb @@ -0,0 +1,67 @@ +;-------------------------------------------------------------------------= ----- +; @file +; This file includes all other code files to assemble the reset vector code +; +; Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;-------------------------------------------------------------------------= ----- + +; +; If neither ARCH_IA32 nor ARCH_X64 are defined, then try to include +; Base.h to use the C pre-processor to determine the architecture. +; +%ifndef ARCH_IA32 + %ifndef ARCH_X64 + #include + #if defined (MDE_CPU_IA32) + %define ARCH_IA32 + #elif defined (MDE_CPU_X64) + %define ARCH_X64 + #endif + %endif +%endif + #include + %define VIRTUAL4G (FixedPcdGet32 (PcdMemoryFvRecoveryBase)+FixedPcdGet32= (PcdFlashFvRecoverySize)) + %define AntiRollback_SecurityLevel (0) +%ifdef ARCH_IA32 + %ifdef ARCH_X64 + %error "Only one of ARCH_IA32 or ARCH_X64 can be defined." + %endif +%elifdef ARCH_X64 +%else + %error "Either ARCH_IA32 or ARCH_X64 must be defined." +%endif + +%include "CommonMacros.inc" + +%include "PostCodes.inc" + +%ifdef ARCH_X64 +%include "X64/PageTables.asm" +%endif + +%ifdef DEBUG_PORT80 + %include "Port80Debug.asm" +%elifdef DEBUG_SERIAL + %include "SerialDebug.asm" +%else + %include "DebugDisabled.asm" +%endif + +%include "Ia32/SearchForBfvBase.asm" +%include "Ia32/SearchForSecEntry.asm" + +%ifdef ARCH_X64 +%include "Ia32/Flat32ToFlat64.asm" +%include "Ia32/PageTables64.asm" +%endif + +%include "Ia16/Real16ToFlat32.asm" +%include "Ia16/Init16.asm" + +%include "Main.asm" + +%include "Ia16/ResetVectorVtf0.asm" + diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector= /Vtf0/X64/PageTables.asm b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuP= kg/ResetVector/Vtf0/X64/PageTables.asm new file mode 100644 index 0000000000..0f085cfa27 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/ResetVector/Vtf0/X= 64/PageTables.asm @@ -0,0 +1,73 @@ +;-------------------------------------------------------------------------= ----- +; @file +; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x100000000 (4GB) +; +; Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;-------------------------------------------------------------------------= ----- + +BITS 64 + +%define ALIGN_TOP_TO_4K_FOR_PAGING + +%define PAGE_PRESENT 0x01 +%define PAGE_READ_WRITE 0x02 +%define PAGE_USER_SUPERVISOR 0x04 +%define PAGE_WRITE_THROUGH 0x08 +%define PAGE_CACHE_DISABLE 0x010 +%define PAGE_ACCESSED 0x020 +%define PAGE_DIRTY 0x040 +%define PAGE_PAT 0x080 +%define PAGE_GLOBAL 0x0100 +%define PAGE_2M_MBO 0x080 +%define PAGE_2M_PAT 0x01000 + +%define PAGE_2M_PDE_ATTR (PAGE_2M_MBO + \ + PAGE_ACCESSED + \ + PAGE_DIRTY + \ + PAGE_READ_WRITE + \ + PAGE_PRESENT) + +%define PAGE_PDP_ATTR (PAGE_ACCESSED + \ + PAGE_READ_WRITE + \ + PAGE_PRESENT) + +%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) +%define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x)) + +%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ + PAGE_PDP_ATTR) +%define PTE_2MB(x) ((x << 21) + PAGE_2M_PDE_ATTR) + +TopLevelPageDirectory: + + ; + ; Top level Page Directory Pointers (1 * 512GB entry) + ; + DQ PDP(0x1000) + + + ; + ; Next level Page Directory Pointers (4 * 1GB entries =3D> 4GB) + ; + TIMES 0x1000-PGTBLS_OFFSET($) DB 0 + + DQ PDP(0x2000) + DQ PDP(0x3000) + DQ PDP(0x4000) + DQ PDP(0x5000) + + ; + ; Page Table Entries (2048 * 2MB entries =3D> 4GB) + ; + TIMES 0x2000-PGTBLS_OFFSET($) DB 0 + +%assign i 0 +%rep 0x800 + DQ PTE_2MB(i) + %assign i i+1 +%endrep + +EndOfPageTables: -- 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114515): https://edk2.groups.io/g/devel/message/114515 Mute This Topic: https://groups.io/mt/103971412/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-