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Date: Thu, 25 Jan 2024 09:23:08 +0100 Message-ID: <20240125082311.310203-2-kraxel@redhat.com> In-Reply-To: <20240125082311.310203-1-kraxel@redhat.com> References: <20240125082311.310203-1-kraxel@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.1 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,kraxel@redhat.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: hjnS4WA9Io6pLt7m2LDZT7hXx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1706170999591100006 Content-Type: text/plain; charset="utf-8"; x-default="true" Specifically before running lzma uncompress of the main firmware volume. This is needed to make sure caching is enabled, otherwise the uncompress can be extremely slow. Adapt the ASSERTs and MTRR setup in PlatformInitLib to the changes. Background: Depending on virtual machine configuration kvm may uses EPT memory types to apply guest MTRR settings. In case MTRRs are disabled kvm will use the uncachable memory type for all mappings. Here is the linux kernel function handling this: static u8 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) { /* We wanted to honor guest CD/MTRR/PAT, but doing so could result in * memory aliases with conflicting memory types and sometimes MCEs. * We have to be careful as to what are honored and when. * * For MMIO, guest CD/MTRR are ignored. The EPT memory type is set to * UC. The effective memory type is UC or WC depending on guest PAT. * This was historically the source of MCEs and we want to be * conservative. * * When there is no need to deal with noncoherent DMA (e.g., no VT-d * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored. The * EPT memory type is set to WB. The effective memory type is forced * WB. * * Otherwise, we trust guest. Guest CD/MTRR/PAT are all honored. The * EPT memory type is used to emulate guest CD/MTRR. */ if (is_mmio) return MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT; if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) return (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT) | VMX_EPT_IPAT_BIT; if (kvm_read_cr0_bits(vcpu, X86_CR0_CD)) { if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) return MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT; else return (MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT) | VMX_EPT_IPAT_BIT; } return kvm_mtrr_get_guest_memory_type(vcpu, gfn) << VMX_EPT_MT_EPTE_SHIFT; } In most VM configurations kvm_arch_has_noncoherent_dma() evaluate to false, so kvm uses MTRR_TYPE_WRBACK. In case the VM has a mdev device assigned that is not the case though. Before commit e8aa4c6546ad ("UefiCpuPkg/ResetVector: Cache Disable should not be set by default in CR0") the function also ended up using MTRR_TYPE_WRBACK thanks to KVM_X86_QUIRK_CD_NW_CLEARED. After that commit kvm actually evaluates mtrr settings via kvm_mtrr_get_guest_memory_type(). Signed-off-by: Gerd Hoffmann --- OvmfPkg/IntelTdx/Sec/SecMain.c | 32 +++++++++++++++++++++ OvmfPkg/Library/PlatformInitLib/MemDetect.c | 10 +++---- OvmfPkg/Sec/SecMain.c | 32 +++++++++++++++++++++ 3 files changed, 69 insertions(+), 5 deletions(-) diff --git a/OvmfPkg/IntelTdx/Sec/SecMain.c b/OvmfPkg/IntelTdx/Sec/SecMain.c index 42a587adfa57..e8ff0e9081d1 100644 --- a/OvmfPkg/IntelTdx/Sec/SecMain.c +++ b/OvmfPkg/IntelTdx/Sec/SecMain.c @@ -27,6 +27,8 @@ #include #include #include +#include +#include =20 #define SEC_IDT_ENTRY_COUNT 34 =20 @@ -48,6 +50,31 @@ IA32_IDT_GATE_DESCRIPTOR mIdtEntryTemplate =3D { } }; =20 +// +// Enable MTRR early, set default type to write back. +// Needed to make sure caching is enabled, +// without this lzma decompress can be very slow. +// +STATIC +VOID +SecMtrrSetup ( + VOID + ) +{ + CPUID_VERSION_INFO_EDX Edx; + MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType; + + AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &Edx.Uint32); + if (!Edx.Bits.MTRR) { + return; + } + + DefType.Uint64 =3D AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);; + DefType.Bits.Type =3D 6; /* write back */ + DefType.Bits.E =3D 1; /* enable */ + AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, DefType.Uint64); +} + VOID EFIAPI SecCoreStartupWithStack ( @@ -204,6 +231,11 @@ SecCoreStartupWithStack ( InitializeApicTimer (0, MAX_UINT32, TRUE, 5); DisableApicTimerInterrupt (); =20 + // + // Initialize MTRR + // + SecMtrrSetup (); + PeilessStartup (&SecCoreData); =20 ASSERT (FALSE); diff --git a/OvmfPkg/Library/PlatformInitLib/MemDetect.c b/OvmfPkg/Library/= PlatformInitLib/MemDetect.c index f042517bb64a..e89f63eee054 100644 --- a/OvmfPkg/Library/PlatformInitLib/MemDetect.c +++ b/OvmfPkg/Library/PlatformInitLib/MemDetect.c @@ -1082,18 +1082,18 @@ PlatformQemuInitializeRam ( MtrrGetAllMtrrs (&MtrrSettings); =20 // - // MTRRs disabled, fixed MTRRs disabled, default type is uncached + // See SecMtrrSetup(), default type should be write back // - ASSERT ((MtrrSettings.MtrrDefType & BIT11) =3D=3D 0); + ASSERT ((MtrrSettings.MtrrDefType & BIT11) !=3D 0); ASSERT ((MtrrSettings.MtrrDefType & BIT10) =3D=3D 0); - ASSERT ((MtrrSettings.MtrrDefType & 0xFF) =3D=3D 0); + ASSERT ((MtrrSettings.MtrrDefType & 0xFF) =3D=3D MTRR_CACHE_WRITE_BACK= ); =20 // // flip default type to writeback // - SetMem (&MtrrSettings.Fixed, sizeof MtrrSettings.Fixed, 0x06); + SetMem (&MtrrSettings.Fixed, sizeof MtrrSettings.Fixed, MTRR_CACHE_WRI= TE_BACK); ZeroMem (&MtrrSettings.Variables, sizeof MtrrSettings.Variables); - MtrrSettings.MtrrDefType |=3D BIT11 | BIT10 | 6; + MtrrSettings.MtrrDefType |=3D BIT10; MtrrSetAllMtrrs (&MtrrSettings); =20 // diff --git a/OvmfPkg/Sec/SecMain.c b/OvmfPkg/Sec/SecMain.c index 31da5d0ace51..a066db34997c 100644 --- a/OvmfPkg/Sec/SecMain.c +++ b/OvmfPkg/Sec/SecMain.c @@ -30,6 +30,8 @@ #include #include #include +#include +#include #include "AmdSev.h" =20 #define SEC_IDT_ENTRY_COUNT 34 @@ -744,6 +746,31 @@ FindAndReportEntryPoints ( return; } =20 +// +// Enable MTRR early, set default type to write back. +// Needed to make sure caching is enabled, +// without this lzma decompress can be very slow. +// +STATIC +VOID +SecMtrrSetup ( + VOID + ) +{ + CPUID_VERSION_INFO_EDX Edx; + MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType; + + AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &Edx.Uint32); + if (!Edx.Bits.MTRR) { + return; + } + + DefType.Uint64 =3D AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);; + DefType.Bits.Type =3D 6; /* write back */ + DefType.Bits.E =3D 1; /* enable */ + AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, DefType.Uint64); +} + VOID EFIAPI SecCoreStartupWithStack ( @@ -942,6 +969,11 @@ SecCoreStartupWithStack ( InitializeApicTimer (0, MAX_UINT32, TRUE, 5); DisableApicTimerInterrupt (); =20 + // + // Initialize MTRR + // + SecMtrrSetup (); + // // Initialize Debug Agent to support source level debug in SEC/PEI phase= s before memory ready. // --=20 2.43.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 25 Jan 2024 08:23:14 +0000 (UTC) X-Received: from sirius.home.kraxel.org (unknown [10.39.192.43]) by smtp.corp.redhat.com (Postfix) with ESMTPS id D84BF1C060B2; Thu, 25 Jan 2024 08:23:13 +0000 (UTC) X-Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id B26921801A90; Thu, 25 Jan 2024 09:23:11 +0100 (CET) From: "Gerd Hoffmann" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Laszlo Ersek , Erdem Aktas , Michael Roth , Min Xu , Gerd Hoffmann , Jiewen Yao , Tom Lendacky , Oliver Steffen Subject: [edk2-devel] [PATCH v2 2/4] MdePkg/ArchitecturalMsr.h: add #defines for MTRR cache types Date: Thu, 25 Jan 2024 09:23:09 +0100 Message-ID: <20240125082311.310203-3-kraxel@redhat.com> In-Reply-To: <20240125082311.310203-1-kraxel@redhat.com> References: <20240125082311.310203-1-kraxel@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.7 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,kraxel@redhat.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: vpnu3ZHvZFmujjGSwUHyGL29x1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1706171007591100001 Content-Type: text/plain; charset="utf-8"; x-default="true" Signed-off-by: Gerd Hoffmann --- MdePkg/Include/Register/Intel/ArchitecturalMsr.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h b/MdePkg/Incl= ude/Register/Intel/ArchitecturalMsr.h index 756e7c86ec31..2b2e34b08c8b 100644 --- a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h +++ b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h @@ -2103,6 +2103,13 @@ typedef union { #define MSR_IA32_MTRR_PHYSBASE9 0x00000212 /// @} =20 +#define MSR_IA32_MTRR_CACHE_UNCACHEABLE 0 +#define MSR_IA32_MTRR_CACHE_WRITE_COMBINING 1 +#define MSR_IA32_MTRR_CACHE_WRITE_THROUGH 4 +#define MSR_IA32_MTRR_CACHE_WRITE_PROTECTED 5 +#define MSR_IA32_MTRR_CACHE_WRITE_BACK 6 +#define MSR_IA32_MTRR_CACHE_INVALID_TYPE 7 + /** MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSBASE0 to #MSR_IA32_MTRR_PHYSBASE9 --=20 2.43.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,kraxel@redhat.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: l0D1UJBcmmG9FadbXfMFM89Dx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1706171001592100013 Content-Type: text/plain; charset="utf-8"; x-default="true" Signed-off-by: Gerd Hoffmann --- UefiCpuPkg/Include/Library/MtrrLib.h | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/UefiCpuPkg/Include/Library/MtrrLib.h b/UefiCpuPkg/Include/Libr= ary/MtrrLib.h index 86cc1aab3b8e..c7d505ac06ed 100644 --- a/UefiCpuPkg/Include/Library/MtrrLib.h +++ b/UefiCpuPkg/Include/Library/MtrrLib.h @@ -9,6 +9,8 @@ #ifndef _MTRR_LIB_H_ #define _MTRR_LIB_H_ =20 +#include + // // According to IA32 SDM, MTRRs number and MSR offset are always consistent // for IA32 processor family @@ -90,12 +92,12 @@ typedef enum { CacheInvalid =3D 7 } MTRR_MEMORY_CACHE_TYPE; =20 -#define MTRR_CACHE_UNCACHEABLE 0 -#define MTRR_CACHE_WRITE_COMBINING 1 -#define MTRR_CACHE_WRITE_THROUGH 4 -#define MTRR_CACHE_WRITE_PROTECTED 5 -#define MTRR_CACHE_WRITE_BACK 6 -#define MTRR_CACHE_INVALID_TYPE 7 +#define MTRR_CACHE_UNCACHEABLE MSR_IA32_MTRR_CACHE_UNCACHEABLE +#define MTRR_CACHE_WRITE_COMBINING MSR_IA32_MTRR_CACHE_WRITE_COMBINING +#define MTRR_CACHE_WRITE_THROUGH MSR_IA32_MTRR_CACHE_WRITE_THROUGH +#define MTRR_CACHE_WRITE_PROTECTED MSR_IA32_MTRR_CACHE_WRITE_PROTECTED +#define MTRR_CACHE_WRITE_BACK MSR_IA32_MTRR_CACHE_WRITE_BACK +#define MTRR_CACHE_INVALID_TYPE MSR_IA32_MTRR_CACHE_INVALID_TYPE =20 typedef struct { UINT64 BaseAddress; --=20 2.43.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,kraxel@redhat.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 0LBouFpIbGuNakZ9z4T7xaxix1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1706171003584100016 Content-Type: text/plain; charset="utf-8"; x-default="true" Signed-off-by: Gerd Hoffmann --- OvmfPkg/IntelTdx/Sec/SecMain.c | 2 +- OvmfPkg/Sec/SecMain.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/OvmfPkg/IntelTdx/Sec/SecMain.c b/OvmfPkg/IntelTdx/Sec/SecMain.c index e8ff0e9081d1..6ad2214293b2 100644 --- a/OvmfPkg/IntelTdx/Sec/SecMain.c +++ b/OvmfPkg/IntelTdx/Sec/SecMain.c @@ -70,7 +70,7 @@ SecMtrrSetup ( } =20 DefType.Uint64 =3D AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);; - DefType.Bits.Type =3D 6; /* write back */ + DefType.Bits.Type =3D MSR_IA32_MTRR_CACHE_WRITE_BACK; DefType.Bits.E =3D 1; /* enable */ AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, DefType.Uint64); } diff --git a/OvmfPkg/Sec/SecMain.c b/OvmfPkg/Sec/SecMain.c index a066db34997c..92cf510ea68f 100644 --- a/OvmfPkg/Sec/SecMain.c +++ b/OvmfPkg/Sec/SecMain.c @@ -766,7 +766,7 @@ SecMtrrSetup ( } =20 DefType.Uint64 =3D AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);; - DefType.Bits.Type =3D 6; /* write back */ + DefType.Bits.Type =3D MSR_IA32_MTRR_CACHE_WRITE_BACK; DefType.Bits.E =3D 1; /* enable */ AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, DefType.Uint64); } --=20 2.43.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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