From nobody Sun May 12 13:21:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+114294+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+114294+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706104424; cv=none; d=zohomail.com; s=zohoarc; b=TK6V0Z4KEEDgenwJNGJqQGei9N8z90nyx9lqfpzLxaBVDjy9ASGV80U0hW84s14k8z6NSVbxTNvX90QxY3c5AHKHPAe/KCJL2pdbcFAb0opjh+f+wq+1HtSeU8TZh6t4/4ROMl1lMmYVEKPd/MFR0zdHdC8bmccPHSbK1SMqBUM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706104424; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=p+CY/pys65EkajJRPMEuT31qMCncWgXZtC2f6sMW4HI=; b=Y2ot0Wf8v1bZcpVzO0Lp/UHtVKa4wgHgqXZnABK0KP2lrKkh+RbbM6KhAAq8TjYG5gPa1A5KYCGG8Hv/JLvUeak0QpK/rwXGYBUqONVftM4xvChtdt7CJhyHlP7bl/JIU4oDgwf79+EZmIeg2qXG+D/p1vQrHXX6AVHWR1HTLYE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+114294+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1706104424432222.28992793803843; Wed, 24 Jan 2024 05:53:44 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=9Ddcyul67icLeKG9r/u4U9AHh53Lavn2UIoLje3LTAs=; c=relaxed/simple; d=groups.io; h=From:Date:Subject:MIME-Version:Message-Id:References:In-Reply-To:To:Cc:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Transfer-Encoding; s=20140610; t=1706104424; v=1; b=Ssf2Xo5il9shLBwVWyP+2wGCPyeZTdHev2vq4Usn1Qjcdeb8R6NcVq5aRaJDv1BfIZA+uqo5 WGZMUc8DEelfqtbJjepo/W/cPyzajWnJbtf1xwSpz9+tgnG/bTNlKJZKIFWGjW3XGyY3RElnUkh IZHBcwMX0U/hfB6B6j4duu+o= X-Received: by 127.0.0.2 with SMTP id aTtmYY1788612xKViFLlIgO4; Wed, 24 Jan 2024 05:53:44 -0800 X-Received: from muminek.juszkiewicz.com.pl (muminek.juszkiewicz.com.pl [213.251.184.221]) by mx.groups.io with SMTP id smtpd.web10.22793.1706104422637686300 for ; Wed, 24 Jan 2024 05:53:43 -0800 X-Received: from localhost (localhost [127.0.0.1]) by muminek.juszkiewicz.com.pl (Postfix) with ESMTP id 39C8126009D; Wed, 24 Jan 2024 14:53:40 +0100 (CET) X-Virus-Scanned: Debian amavis at juszkiewicz.com.pl X-Received: from muminek.juszkiewicz.com.pl ([127.0.0.1]) by localhost (muminek.juszkiewicz.com.pl [127.0.0.1]) (amavis, port 10024) with ESMTP id BndZNHwUiBYM; Wed, 24 Jan 2024 14:53:38 +0100 (CET) X-Received: from [192.168.200.139] (83.11.3.72.ipv4.supernova.orange.pl [83.11.3.72]) by muminek.juszkiewicz.com.pl (Postfix) with ESMTPSA id D9FE026084B; Wed, 24 Jan 2024 14:53:37 +0100 (CET) From: "Marcin Juszkiewicz" Date: Wed, 24 Jan 2024 14:53:36 +0100 Subject: [edk2-devel] [PATCH edk2-platforms v3 1/5] Platform/SbsaQemu: add SbsaQemuHardwareInfoLib MIME-Version: 1.0 Message-Id: <20240124-no-dt-for-cpu-v3-1-5375fcf09037@linaro.org> References: <20240124-no-dt-for-cpu-v3-0-5375fcf09037@linaro.org> In-Reply-To: <20240124-no-dt-for-cpu-v3-0-5375fcf09037@linaro.org> To: devel@edk2.groups.io Cc: Leif Lindholm , Ard Biesheuvel , Graeme Gregory , Marcin Juszkiewicz Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,marcin.juszkiewicz@linaro.org List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: y4hcKGvA5SzOFa6kgXNYWn8sx1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1706104425605100002 This library provides functions to check for hardware information. For now it covers CPU ones: - amount of cpu cores - MPIDR value for cpu core - NUMA node id for cpu core Values are read from TF-A using platform specific SMC calls. Signed-off-by: Marcin Juszkiewicz --- Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 3 +- .../SbsaQemuHardwareInfoLib.inf | 32 +++++++ .../SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h | 15 ++- .../Include/Library/SbsaQemuHardwareInfoLib.h | 45 +++++++++ .../SbsaQemuHardwareInfoLib.c | 98 ++++++++++++++++= ++++ 5 files changed, 189 insertions(+), 4 deletions(-) diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/S= bsaQemu.dsc index 378600050df9..07cb3490f4cf 100644 --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc @@ -1,6 +1,6 @@ # # Copyright (c) 2021, NUVIA Inc. All rights reserved. -# Copyright (c) 2019, Linaro Limited. All rights reserved. +# Copyright (c) 2019-2024, Linaro Ltd. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -128,6 +128,7 @@ [LibraryClasses.common] =20 FdtHelperLib|Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.inf OemMiscLib|Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf + SbsaQemuHardwareInfoLib|Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareIn= foLib/SbsaQemuHardwareInfoLib.inf =20 # Debug Support PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCof= fExtraActionLib.inf diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemu= HardwareInfoLib.inf b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib= /SbsaQemuHardwareInfoLib.inf new file mode 100644 index 000000000000..8c2def1878e6 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwar= eInfoLib.inf @@ -0,0 +1,32 @@ +#/* @file +# +# Copyright (c) Linaro Ltd. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#*/ + +[Defines] + INF_VERSION =3D 0x0001001c + BASE_NAME =3D SbsaQemuHardwareInfoLib + FILE_GUID =3D 6454006f-6502-46e2-9be4-4bba8d4b29fb + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmPlatformLib + +[Sources] + SbsaQemuHardwareInfoLib.c + +[Packages] + ArmPkg/ArmPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + Silicon/Qemu/SbsaQemu/SbsaQemu.dec + +[LibraryClasses] + ArmSmcLib + BaseMemoryLib + DebugLib + + [Pcd] + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h b= /Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h index 7934875e4aba..d9faee7fa5b2 100644 --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h @@ -11,8 +11,17 @@ =20 #include =20 -#define SIP_SVC_VERSION SMC_SIP_FUNCTION_ID(1) -#define SIP_SVC_GET_GIC SMC_SIP_FUNCTION_ID(100) -#define SIP_SVC_GET_GIC_ITS SMC_SIP_FUNCTION_ID(101) +#define SIP_SVC_VERSION SMC_SIP_FUNCTION_ID(1) +#define SIP_SVC_GET_GIC SMC_SIP_FUNCTION_ID(100) +#define SIP_SVC_GET_GIC_ITS SMC_SIP_FUNCTION_ID(101) +#define SIP_SVC_GET_CPU_COUNT SMC_SIP_FUNCTION_ID(200) +#define SIP_SVC_GET_CPU_NODE SMC_SIP_FUNCTION_ID(201) + +/* + * SMCC does not define return codes for SiP functions. + * We use Architecture ones then. + */ + +#define SMC_SIP_CALL_SUCCESS SMC_ARCH_CALL_SUCCESS =20 #endif /* SBSA_QEMU_SMC_H_ */ diff --git a/Silicon/Qemu/SbsaQemu/Include/Library/SbsaQemuHardwareInfoLib.= h b/Silicon/Qemu/SbsaQemu/Include/Library/SbsaQemuHardwareInfoLib.h new file mode 100644 index 000000000000..ca52c6b27093 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/Include/Library/SbsaQemuHardwareInfoLib.h @@ -0,0 +1,45 @@ +/** @file +* +* Copyright (c) Linaro Ltd. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#ifndef SBSA_QEMU_HARDWARE_INFO_ +#define SBSA_QEMU_HARDWARE_INFO_ + +/** + Get CPU count from information passed by Qemu. + +**/ +VOID +SbsaQemuGetCpuCount ( + VOID + ); + +/** + Get MPIDR for a given cpu from device tree passed by Qemu. + + @param [in] CpuId Index of cpu to retrieve MPIDR value for. + + @retval MPIDR value of CPU at index +**/ +UINT64 +SbsaQemuGetMpidr ( + IN UINTN CpuId + ); + +/** + Get NUMA node id for a given cpu from device tree passed by Qemu. + + @param [in] CpuId Index of cpu to retrieve NUMA node id for. + + @retval NUMA node id for CPU at index +**/ +UINT64 +SbsaQemuGetCpuNumaNode ( + IN UINTN CpuId + ); + +#endif /* SBSA_QEMU_HARDWARE_INFO_ */ diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemu= HardwareInfoLib.c b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/S= bsaQemuHardwareInfoLib.c new file mode 100644 index 000000000000..134fe73a5284 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwar= eInfoLib.c @@ -0,0 +1,98 @@ +/** @file +* +* Copyright (c) 2021, NUVIA Inc. All rights reserved. +* Copyright (c) Linaro Ltd. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include +#include +#include + +/** + Get CPU count from information passed by Qemu. + +**/ +VOID +SbsaQemuGetCpuCount ( + VOID + ) +{ + UINTN Arg0; + UINTN SmcResult; + RETURN_STATUS Result; + + SmcResult =3D ArmCallSmc0 (SIP_SVC_GET_CPU_COUNT, &Arg0, NULL, NULL); + if (SmcResult !=3D SMC_SIP_CALL_SUCCESS) { + DEBUG ((DEBUG_INFO, "SIP_SVC_GET_CPU_COUNT call failed. We have to get= cpu info from DT.\n")); + Arg0 =3D FdtHelperCountCpus (); + } + + Result =3D PcdSet32S (PcdCoreCount, Arg0); + ASSERT_RETURN_ERROR (Result); + + DEBUG ((DEBUG_INFO, "We have %d cpus.\n", Arg0)); +} + +/** + Get MPIDR for a given cpu from device tree passed by Qemu. + + @param [in] CpuId Index of cpu to retrieve MPIDR value for. + + @retval MPIDR value of CPU at index +**/ +UINT64 +SbsaQemuGetMpidr ( + IN UINTN CpuId + ) +{ + UINTN SmcResult; + UINTN Arg0; + UINTN Arg1; + + Arg0 =3D CpuId; + + SmcResult =3D ArmCallSmc0 (SIP_SVC_GET_CPU_NODE, &Arg0, &Arg1, NULL); + if (SmcResult !=3D SMC_SIP_CALL_SUCCESS) { + DEBUG ((DEBUG_INFO, "SIP_SVC_GET_CPU_NODE call failed. We have to get = cpu info from DT.\n")); + Arg1 =3D FdtHelperGetMpidr (CpuId); + } + + DEBUG ((DEBUG_ERROR, "MPIDR for CPU:%d =3D %d\n", CpuId, Arg1)); + + return Arg1; +} + +/** + Get NUMA node id for a given cpu from device tree passed by Qemu. + + @param [in] CpuId Index of cpu to retrieve NUMA node id for. + + @retval NUMA node id for CPU at index +**/ +UINT64 +SbsaQemuGetCpuNumaNode ( + IN UINTN CpuId + ) +{ + UINTN SmcResult; + UINTN Arg0; + UINTN Arg1; + + Arg0 =3D CpuId; + + SmcResult =3D ArmCallSmc0 (SIP_SVC_GET_CPU_NODE, &Arg0, &Arg1, NULL); + if (SmcResult !=3D SMC_SIP_CALL_SUCCESS) { + /* No fallback to DeviceTree as we did not had that info earlier. */ + DEBUG ((DEBUG_ERROR, "SIP_SVC_GET_CPU_NODE call failed. Couldn't find = information for CPU:%d\n", CpuId)); + return 0; + } + + DEBUG ((DEBUG_ERROR, "NUMA node for CPU:%d =3D %d\n", CpuId, Arg0)); + + return Arg0; +} --=20 2.43.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Signed-off-by: Marcin Juszkiewicz --- .../SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf | 4 +++- .../SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c | 9 +++++= ---- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlat= formDxe.inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPla= tformDxe.inf index 19534b7a274a..9752694a432b 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe= .inf +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe= .inf @@ -1,7 +1,7 @@ ## @file # This driver effectuates SbsaQemu platform configuration settings # -# Copyright (c) 2019, Linaro Ltd. All rights reserved. +# Copyright (c) Linaro Ltd. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -32,6 +32,7 @@ [LibraryClasses] PcdLib DebugLib NonDiscoverableDeviceRegistrationLib + SbsaQemuHardwareInfoLib UefiDriverEntryPoint =20 [Pcd] @@ -46,6 +47,7 @@ [Pcd] gArmTokenSpaceGuid.PcdGicDistributorBase gArmTokenSpaceGuid.PcdGicRedistributorsBase gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdGicItsBase + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount =20 =20 [Depex] diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlat= formDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatf= ormDxe.c index 4ebbe7c93a19..14e1ec7eab29 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe= .c +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe= .c @@ -1,7 +1,7 @@ /** @file -* FDT client protocol driver for qemu,mach-virt-ahci DT node +* SbsaQemu Platform Initialization * -* Copyright (c) 2019, Linaro Ltd. All rights reserved. +* Copyright (c) Linaro Ltd. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -12,13 +12,12 @@ #include #include #include +#include #include #include #include #include =20 -#include - EFI_STATUS EFIAPI InitializeSbsaQemuPlatformDxe ( @@ -123,5 +122,7 @@ InitializeSbsaQemuPlatformDxe ( } } =20 + SbsaQemuGetCpuCount (); + return EFI_SUCCESS; } --=20 2.43.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Signed-off-by: Marcin Juszkiewicz --- Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf | 6 ++---- Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c | 10 ++++---= --- .../Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 11 ++-----= ---- 3 files changed, 8 insertions(+), 19 deletions(-) diff --git a/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf b/Platform/Qe= mu/SbsaQemu/OemMiscLib/OemMiscLib.inf index a34f54d431d4..8e2bf8c512f1 100644 --- a/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf +++ b/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf @@ -3,7 +3,7 @@ # # Copyright (c) 2021, NUVIA Inc. All rights reserved. # Copyright (c) 2018, Hisilicon Limited. All rights reserved. -# Copyright (c) 2018, Linaro Limited. All rights reserved. +# Copyright (c) 2023, Linaro Ltd. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -29,8 +29,6 @@ [Packages] =20 [LibraryClasses] BaseMemoryLib - FdtLib - FdtHelperLib IoLib PcdLib =20 @@ -40,7 +38,6 @@ [Guids] [Pcd] gArmTokenSpaceGuid.PcdEmbeddedControllerFirmwareRelease gArmTokenSpaceGuid.PcdSystemBiosRelease - gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress =20 gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdSystemManufacturer gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdSystemSerialNumber @@ -56,3 +53,4 @@ [Pcd] gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisManufacturer gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisAssetTag gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisSKU + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount diff --git a/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c b/Platform/Qemu= /SbsaQemu/OemMiscLib/OemMiscLib.c index c38f2851904f..ab97768b5ddc 100644 --- a/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c +++ b/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c @@ -2,7 +2,7 @@ * OemMiscLib.c * * Copyright (c) 2021, NUVIA Inc. All rights reserved. -* Copyright (c) 2020, Linaro Ltd. All rights reserved. +* Copyright (c) Linaro Ltd. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -12,14 +12,12 @@ #include #include #include -#include #include #include #include #include #include #include -#include =20 /** Returns whether the specified processor is present or not. =20 @@ -33,7 +31,7 @@ OemIsProcessorPresent ( UINTN ProcessorIndex ) { - if (ProcessorIndex < FdtHelperCountCpus ()) { + if (ProcessorIndex < PcdGet32 (PcdCoreCount)) { return TRUE; } =20 @@ -76,7 +74,7 @@ OemGetProcessorInformation ( { UINT16 ProcessorCount; =20 - ProcessorCount =3D FdtHelperCountCpus (); + ProcessorCount =3D PcdGet32 (PcdCoreCount); =20 if (ProcessorIndex < ProcessorCount) { ProcessorStatus->Bits.CpuStatus =3D 1; // CPU enabled @@ -121,7 +119,7 @@ OemGetMaxProcessors ( VOID ) { - return FdtHelperCountCpus (); + return PcdGet32 (PcdCoreCount); } =20 /** Gets information about the cache at the specified cache level. diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.= c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c index 9fb17151d7b8..59536ea9575e 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c @@ -1,7 +1,7 @@ /** @file * This file is an ACPI driver for the Qemu SBSA platform. * -* Copyright (c) 2020, Linaro Ltd. All rights reserved. +* Copyright (c) Linaro Ltd. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -255,7 +255,6 @@ AddMadtTable ( // Initialize GIC Redistributor Structure EFI_ACPI_6_0_GICR_STRUCTURE Gicr =3D SBSAQEMU_MADT_GICR_INIT(); =20 - // Get CoreCount which was determined eariler after parsing device tree NumCores =3D PcdGet32 (PcdCoreCount); =20 // Calculate the new table size based on the number of cores @@ -291,7 +290,7 @@ AddMadtTable ( New +=3D sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER); =20 // Add new GICC structures for the Cores - for (CoreIndex =3D 0; CoreIndex < PcdGet32 (PcdCoreCount); CoreIndex++) { + for (CoreIndex =3D 0; CoreIndex < NumCores; CoreIndex++) { EFI_ACPI_6_0_GIC_STRUCTURE *GiccPtr; =20 CopyMem (New, &Gicc, sizeof (EFI_ACPI_6_0_GIC_STRUCTURE)); @@ -758,12 +757,6 @@ InitializeSbsaQemuAcpiDxe ( { EFI_STATUS Status; EFI_ACPI_TABLE_PROTOCOL *AcpiTable; - UINT32 NumCores; - - // Parse the device tree and get the number of CPUs - NumCores =3D FdtHelperCountCpus (); - Status =3D PcdSet32S (PcdCoreCount, NumCores); - ASSERT_RETURN_ERROR (Status); =20 // Check if ACPI Table Protocol has been installed Status =3D gBS->LocateProtocol ( --=20 2.43.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114297): https://edk2.groups.io/g/devel/message/114297 Mute This Topic: https://groups.io/mt/103931819/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 12 13:21:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+114298+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+114298+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1706104427; cv=none; d=zohomail.com; s=zohoarc; b=ahAZCo6kHEQv3gX1abA3GDDcgwf6U3yr2kbIAuh556/LrCct6pXHLOOrNDe3oPImiXavLm5d2BcEyOSWEv+OQSGApKttcsN4Nq4tnxDkpSmuysycwxjmXD9DgOebN34gfHZNIAWyX5bSrS0GpeYXxZ2Ficj6sMC3mPvSi1AH3rE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706104427; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=SqxogtIqE52FolgLGyhJccb/xi6US3HM5zF5uLfaXIw=; b=D0rTJ4FJTKLKq4v3Hq/wHVtdhxDy/kcANriQxpKCwHa4HoBMWFA6fsLb6TyaH+xFVU+NTAxaUcqAqg/1jJjDFc6sbfFAfk6GQ4zzNanFEtQWEG7Ueb8FcKbUpQyD9S5lEgTVRcphmQDC+Dwd9d7uHdKvhvAYVg65Xo3kaYnHjY4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+114298+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1706104427211461.991646125967; Wed, 24 Jan 2024 05:53:47 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=rlB4LNbTGWwbaqo1EcPds5HEvd63AITegeXqAVz91Yc=; c=relaxed/simple; d=groups.io; h=From:Date:Subject:MIME-Version:Message-Id:References:In-Reply-To:To:Cc:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Transfer-Encoding; s=20140610; t=1706104426; v=1; b=BGwzvxMUaPyRmqEPByca3kCQ8U7q87R+wscoU20vMyqKzvJawZPpskTpUV9fYVu+DNsu6pGq 9rXtp27wbgQaip4OPvDGJEaNds5s/mCtT/TktY0/LwH7OLBfnDVpwNlX29hPiqcYl7kpn8W7LOZ ZqIftSRYa4yX1USCOVbSNj6w= X-Received: by 127.0.0.2 with SMTP id I6gYYY1788612xFwGU7BSETT; Wed, 24 Jan 2024 05:53:46 -0800 X-Received: from muminek.juszkiewicz.com.pl (muminek.juszkiewicz.com.pl [213.251.184.221]) by mx.groups.io with SMTP id smtpd.web10.22794.1706104425932023453 for ; Wed, 24 Jan 2024 05:53:46 -0800 X-Received: from localhost (localhost [127.0.0.1]) by muminek.juszkiewicz.com.pl (Postfix) with ESMTP id D0837260AB9; Wed, 24 Jan 2024 14:53:43 +0100 (CET) X-Virus-Scanned: Debian amavis at juszkiewicz.com.pl X-Received: from muminek.juszkiewicz.com.pl ([127.0.0.1]) by localhost (muminek.juszkiewicz.com.pl [127.0.0.1]) (amavis, port 10024) with ESMTP id oVuPLLlWaMlf; Wed, 24 Jan 2024 14:53:42 +0100 (CET) X-Received: from [192.168.200.139] (83.11.3.72.ipv4.supernova.orange.pl [83.11.3.72]) by muminek.juszkiewicz.com.pl (Postfix) with ESMTPSA id 0750326113E; Wed, 24 Jan 2024 14:53:39 +0100 (CET) From: "Marcin Juszkiewicz" Date: Wed, 24 Jan 2024 14:53:39 +0100 Subject: [edk2-devel] [PATCH edk2-platforms v3 4/5] Platform/SbsaQemu: move FdtHandlerLib to SbsaQemuHardwareInfoLib MIME-Version: 1.0 Message-Id: <20240124-no-dt-for-cpu-v3-4-5375fcf09037@linaro.org> References: <20240124-no-dt-for-cpu-v3-0-5375fcf09037@linaro.org> In-Reply-To: <20240124-no-dt-for-cpu-v3-0-5375fcf09037@linaro.org> To: devel@edk2.groups.io Cc: Leif Lindholm , Ard Biesheuvel , Graeme Gregory , Marcin Juszkiewicz Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,marcin.juszkiewicz@linaro.org List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 1kV7cbp0vpDRaiif1FrSJcaUx1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1706104427626100012 There is no need for EDK2 to know that there is DeviceTree around. All hardware information is read using functions from SbsaQemuHardwareInfoLib library. Library fallbacks to parsing DT if needed (used with too old TF-A). Signed-off-by: Marcin Juszkiewicz Reviewed-by: Leif Lindholm --- Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 1 - .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 4 +- .../SbsaQemu/Library/FdtHelperLib/FdtHelperLib.inf | 33 ------- .../SbsaQemuHardwareInfoLib.inf | 2 + .../Qemu/SbsaQemu/Include/Library/FdtHelperLib.h | 36 ------- .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 2 +- .../SbsaQemu/Library/FdtHelperLib/FdtHelperLib.c | 98 ----------------= -- .../SbsaQemuHardwareInfoLib.c | 104 ++++++++++++++++= ++++ 8 files changed, 109 insertions(+), 171 deletions(-) diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/S= bsaQemu.dsc index 07cb3490f4cf..bde61651da2e 100644 --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc @@ -126,7 +126,6 @@ [LibraryClasses.common] # ARM PL011 UART Driver PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf =20 - FdtHelperLib|Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.inf OemMiscLib|Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf SbsaQemuHardwareInfoLib|Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareIn= foLib/SbsaQemuHardwareInfoLib.inf =20 diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.= inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf index 291743b19115..9bf0a13de5d1 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf @@ -1,7 +1,7 @@ ## @file # This driver modifies ACPI tables for the Qemu SBSA platform # -# Copyright (c) 2020, Linaro Ltd. All rights reserved. +# Copyright (c) Linaro Ltd. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -35,9 +35,9 @@ [LibraryClasses] BaseLib DebugLib DxeServicesLib - FdtHelperLib PcdLib PrintLib + SbsaQemuHardwareInfoLib UefiDriverEntryPoint UefiLib UefiRuntimeServicesTableLib diff --git a/Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.inf b/= Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.inf deleted file mode 100644 index 9c059f3e5851..000000000000 --- a/Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.inf +++ /dev/null @@ -1,33 +0,0 @@ -#/** @file -# -# Component description file for FdtHelperLib module -# -# Copyright (c) 2021, NUVIA Inc. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#**/ - -[Defines] - INF_VERSION =3D 1.29 - BASE_NAME =3D FdtHelperLib - FILE_GUID =3D 34e4396f-c2fc-4f9e-ad58-0f98e99e3875 - MODULE_TYPE =3D BASE - VERSION_STRING =3D 1.0 - LIBRARY_CLASS =3D FdtHelperLib - -[Sources.common] - FdtHelperLib.c - -[Packages] - EmbeddedPkg/EmbeddedPkg.dec - MdePkg/MdePkg.dec - Silicon/Qemu/SbsaQemu/SbsaQemu.dec - -[LibraryClasses] - DebugLib - FdtLib - PcdLib - -[FixedPcd] - gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemu= HardwareInfoLib.inf b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib= /SbsaQemuHardwareInfoLib.inf index 8c2def1878e6..5358dd339eb3 100644 --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwar= eInfoLib.inf +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwar= eInfoLib.inf @@ -27,6 +27,8 @@ [LibraryClasses] ArmSmcLib BaseMemoryLib DebugLib + FdtLib =20 [Pcd] + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount diff --git a/Silicon/Qemu/SbsaQemu/Include/Library/FdtHelperLib.h b/Silicon= /Qemu/SbsaQemu/Include/Library/FdtHelperLib.h deleted file mode 100644 index ea9159857215..000000000000 --- a/Silicon/Qemu/SbsaQemu/Include/Library/FdtHelperLib.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @file -* FdtHelperLib.h -* -* Copyright (c) 2021, NUVIA Inc. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#ifndef FDT_HELPER_LIB_ -#define FDT_HELPER_LIB_ - -/** - Get MPIDR for a given cpu from device tree passed by Qemu. - - @param [in] CpuId Index of cpu to retrieve MPIDR value for. - - @retval MPIDR value of CPU at index -**/ -UINT64 -FdtHelperGetMpidr ( - IN UINTN CpuId - ); - -/** Walks through the Device Tree created by Qemu and counts the number - of CPUs present in it. - - @return The number of CPUs present. -**/ -EFIAPI -UINT32 -FdtHelperCountCpus ( - VOID - ); - -#endif /* FDT_HELPER_LIB_ */ diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.= c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c index 59536ea9575e..64bfb8139ce1 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c @@ -15,10 +15,10 @@ #include #include #include -#include #include #include #include +#include #include #include #include diff --git a/Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.c b/Si= licon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.c deleted file mode 100644 index 7fdfb055db76..000000000000 --- a/Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.c +++ /dev/null @@ -1,98 +0,0 @@ -/** @file -* FdtHelperLib.c -* -* Copyright (c) 2021, NUVIA Inc. All rights reserved. -* Copyright (c) 2020, Linaro Ltd. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -**/ - -#include -#include -#include -#include -#include - -STATIC INT32 mFdtFirstCpuOffset; -STATIC INT32 mFdtCpuNodeSize; - -/** - Get MPIDR for a given cpu from device tree passed by Qemu. - - @param [in] CpuId Index of cpu to retrieve MPIDR value for. - - @retval MPIDR value of CPU at index -**/ -UINT64 -FdtHelperGetMpidr ( - IN UINTN CpuId - ) -{ - VOID *DeviceTreeBase; - CONST UINT64 *RegVal; - INT32 Len; - - DeviceTreeBase =3D (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeBaseAddress); - ASSERT (DeviceTreeBase !=3D NULL); - - RegVal =3D fdt_getprop (DeviceTreeBase, - mFdtFirstCpuOffset + (CpuId * mFdtCpuNodeSize), - "reg", - &Len); - if (!RegVal) { - DEBUG ((DEBUG_ERROR, "Couldn't find reg property for CPU:%d\n", CpuId)= ); - return 0; - } - - return (fdt64_to_cpu (ReadUnaligned64 (RegVal))); -} - -/** Walks through the Device Tree created by Qemu and counts the number - of CPUs present in it. - - @return The number of CPUs present. -**/ -EFIAPI -UINT32 -FdtHelperCountCpus ( - VOID - ) -{ - VOID *DeviceTreeBase; - INT32 Node; - INT32 Prev; - INT32 CpuNode; - UINT32 CpuCount; - - DeviceTreeBase =3D (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeBaseAddress); - ASSERT (DeviceTreeBase !=3D NULL); - - // Make sure we have a valid device tree blob - ASSERT (fdt_check_header (DeviceTreeBase) =3D=3D 0); - - CpuNode =3D fdt_path_offset (DeviceTreeBase, "/cpus"); - if (CpuNode <=3D 0) { - DEBUG ((DEBUG_ERROR, "Unable to locate /cpus in device tree\n")); - return 0; - } - - CpuCount =3D 0; - - // Walk through /cpus node and count the number of subnodes. - // The count of these subnodes corresponds to the number of - // CPUs created by Qemu. - Prev =3D fdt_first_subnode (DeviceTreeBase, CpuNode); - mFdtFirstCpuOffset =3D Prev; - while (1) { - CpuCount++; - Node =3D fdt_next_subnode (DeviceTreeBase, Prev); - if (Node < 0) { - break; - } - mFdtCpuNodeSize =3D Node - Prev; - Prev =3D Node; - } - - return CpuCount; -} diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemu= HardwareInfoLib.c b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/S= bsaQemuHardwareInfoLib.c index 134fe73a5284..6315cce3fb7f 100644 --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwar= eInfoLib.c +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwar= eInfoLib.c @@ -11,8 +11,112 @@ #include #include #include +#include #include =20 +/** + Get MPIDR for a given cpu from device tree passed by Qemu. + + @param [in] CpuId Index of cpu to retrieve MPIDR value for. + + @retval MPIDR value of CPU at index +**/ +UINT64 +FdtHelperGetMpidr ( + IN UINTN CpuId + ) +{ + VOID *DeviceTreeBase; + INT32 Node; + INT32 Prev; + UINT32 CpuCount; + CONST UINT64 *RegVal; + + DeviceTreeBase =3D (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeBaseAddress); + ASSERT (DeviceTreeBase !=3D NULL); + + // Make sure we have a valid device tree blob + ASSERT (fdt_check_header (DeviceTreeBase) =3D=3D 0); + + Node =3D fdt_path_offset (DeviceTreeBase, "/cpus"); + if (Node <=3D 0) { + DEBUG ((DEBUG_ERROR, "Unable to locate /cpus in DeviceTree\n")); + return 0; + } + + CpuCount =3D 0; + + Prev =3D fdt_first_subnode (DeviceTreeBase, Node); + while (1) { + if (CpuCount =3D=3D CpuId) { + RegVal =3D fdt_getprop (DeviceTreeBase, Prev, "reg", NULL); + if (!RegVal) { + DEBUG ((DEBUG_ERROR, "Couldn't find reg property for CPU:%d\n", Cp= uId)); + return 0; + } + + return (fdt64_to_cpu (ReadUnaligned64 (RegVal))); + } + + Node =3D fdt_next_subnode (DeviceTreeBase, Prev); + if (Node < 0) { + break; + } + + Prev =3D Node; + CpuCount++; + } + + return 0; /* We did not found MPIDR */ +} + +/** Walks through the Device Tree created by Qemu and counts the number + of CPUs present in it. + + @return The number of CPUs present. +**/ +EFIAPI +UINT32 +FdtHelperCountCpus ( + VOID + ) +{ + VOID *DeviceTreeBase; + INT32 Node; + INT32 Prev; + UINT32 CpuCount; + + DeviceTreeBase =3D (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeBaseAddress); + ASSERT (DeviceTreeBase !=3D NULL); + + // Make sure we have a valid device tree blob + ASSERT (fdt_check_header (DeviceTreeBase) =3D=3D 0); + + Node =3D fdt_path_offset (DeviceTreeBase, "/cpus"); + if (Node <=3D 0) { + DEBUG ((DEBUG_ERROR, "Unable to locate /cpus in DeviceTree\n")); + return 0; + } + + CpuCount =3D 0; + + // Walk through /cpus node and count the number of subnodes. + // The count of these subnodes corresponds to the number of + // CPUs created by Qemu. + Prev =3D fdt_first_subnode (DeviceTreeBase, Node); + while (1) { + CpuCount++; + Node =3D fdt_next_subnode (DeviceTreeBase, Prev); + if (Node < 0) { + break; + } + + Prev =3D Node; + } + + return CpuCount; +} + /** Get CPU count from information passed by Qemu. =20 --=20 2.43.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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TODO: shutdown instead Signed-off-by: Marcin Juszkiewicz --- .../SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c | 3= +++ 1 file changed, 3 insertions(+) diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemu= HardwareInfoLib.c b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/S= bsaQemuHardwareInfoLib.c index 6315cce3fb7f..923997edb2f1 100644 --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwar= eInfoLib.c +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwar= eInfoLib.c @@ -95,6 +95,9 @@ FdtHelperCountCpus ( Node =3D fdt_path_offset (DeviceTreeBase, "/cpus"); if (Node <=3D 0) { DEBUG ((DEBUG_ERROR, "Unable to locate /cpus in DeviceTree\n")); + // as we do not have information about cpu count we panic here + // TODO: shutdown rather than hang + CpuDeadLoop(); return 0; } =20 --=20 2.43.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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