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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rebecca@os.amperecomputing.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: lk53xuNJHGn0FLASm61P9uqYx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1705679183161100005 Content-Type: text/plain; charset="utf-8" The generic watchdog offset register is 48 bits wide, and can be set by performing two 32-bit writes. Add support for writing the high 16 bits of the offset register and update the signature of the WatchdogWriteOffsetRegister function to take a UINT64 value. Signed-off-by: Rebecca Cran --- ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h | 11 +++++++++- ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c | 23 ++++++++++++++= +----- 2 files changed, 27 insertions(+), 7 deletions(-) diff --git a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h b/ArmPkg/D= rivers/GenericWatchdogDxe/GenericWatchdog.h index 9bc3bf47047c..fb117832683f 100644 --- a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h +++ b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h @@ -1,9 +1,13 @@ /** @file * +* Copyright (c) 2023, Ampere Computing LLC. All rights reserved.
* Copyright (c) 2013-2017, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * +* @par Reference(s): +* - Generic Watchdog specification in Arm Base System Architecture 1.0C: +* https://developer.arm.com/documentation/den0094/c/ **/ =20 #ifndef GENERIC_WATCHDOG_H_ @@ -14,12 +18,17 @@ =20 // Control Frame: #define GENERIC_WDOG_CONTROL_STATUS_REG ((UINTN)FixedPcdGet64 (PcdGen= ericWatchdogControlBase) + 0x000) -#define GENERIC_WDOG_OFFSET_REG ((UINTN)FixedPcdGet64 (PcdGen= ericWatchdogControlBase) + 0x008) +#define GENERIC_WDOG_OFFSET_REG_LOW ((UINTN)FixedPcdGet64 (PcdGen= ericWatchdogControlBase) + 0x008) +#define GENERIC_WDOG_OFFSET_REG_HIGH ((UINTN)FixedPcdGet64 (PcdGen= ericWatchdogControlBase) + 0x00C) #define GENERIC_WDOG_COMPARE_VALUE_REG_LOW ((UINTN)FixedPcdGet64 (PcdGen= ericWatchdogControlBase) + 0x010) #define GENERIC_WDOG_COMPARE_VALUE_REG_HIGH ((UINTN)FixedPcdGet64 (PcdGen= ericWatchdogControlBase) + 0x014) +#define GENERIC_WDOG_IID_REG ((UINTN)FixedPcdGet64 (PcdGen= ericWatchdogControlBase) + 0xFCC) =20 // Values of bit 0 of the Control/Status Register #define GENERIC_WDOG_ENABLED 1 #define GENERIC_WDOG_DISABLED 0 =20 +#define GENERIC_WDOG_IID_REV_SHIFT 16 +#define GENERIC_WDOG_IID_REV_MASK 0xF + #endif // GENERIC_WATCHDOG_H_ diff --git a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c b/ArmPk= g/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c index 66c6c37c08b0..20549aa91d94 100644 --- a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c +++ b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c @@ -1,5 +1,6 @@ /** @file * +* Copyright (c) 2023, Ampere Computing LLC. All rights reserved.
* Copyright (c) 2013-2018, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent @@ -35,16 +36,23 @@ STATIC UINTN mTimerFrequencyHz =3D 0; It is therefore stored here. 0 means the timer is not running. */ STATIC UINT64 mNumTimerTicks =3D 0; =20 +STATIC UINT8 WatchdogRevision; + +#define MAX_UINT48 0xFFFFFFFFFFFFULL + STATIC EFI_HARDWARE_INTERRUPT2_PROTOCOL *mInterruptProtocol; STATIC EFI_WATCHDOG_TIMER_NOTIFY mWatchdogNotify; =20 STATIC VOID WatchdogWriteOffsetRegister ( - UINT32 Value + UINT64 Value ) { - MmioWrite32 (GENERIC_WDOG_OFFSET_REG, Value); + MmioWrite32 (GENERIC_WDOG_OFFSET_REG_LOW, Value & MAX_UINT32); + if (WatchdogRevision =3D=3D 1) { + MmioWrite32 (GENERIC_WDOG_OFFSET_REG_HIGH, (Value >> 32) & MAX_UINT16); + } } =20 STATIC @@ -211,17 +219,17 @@ WatchdogSetTimerPeriod ( /* If the number of required ticks is greater than the max the watchdog's offset register (WOR) can hold, we need to manually compute and set the compare register (WCV) */ - if (mNumTimerTicks > MAX_UINT32) { + if (mNumTimerTicks > MAX_UINT48) { /* We need to enable the watchdog *before* writing to the compare regi= ster, because enabling the watchdog causes an "explicit refresh", which clobbers the compare register (WCV). In order to make sure this doe= sn't trigger an interrupt, set the offset to max. */ - WatchdogWriteOffsetRegister (MAX_UINT32); + WatchdogWriteOffsetRegister (MAX_UINT48); WatchdogEnable (); SystemCount =3D ArmGenericTimerGetSystemCount (); WatchdogWriteCompareRegister (SystemCount + mNumTimerTicks); } else { - WatchdogWriteOffsetRegister ((UINT32)mNumTimerTicks); + WatchdogWriteOffsetRegister (mNumTimerTicks); WatchdogEnable (); } =20 @@ -310,6 +318,7 @@ GenericWatchdogEntry ( { EFI_STATUS Status; EFI_HANDLE Handle; + UINT32 WatchdogIId; =20 Status =3D gBS->LocateProtocol ( &gHardwareInterrupt2ProtocolGuid, @@ -367,7 +376,9 @@ GenericWatchdogEntry ( ); ASSERT_EFI_ERROR (Status); =20 - mNumTimerTicks =3D 0; + mNumTimerTicks =3D 0; + WatchdogIId =3D MmioRead32 (GENERIC_WDOG_IID_REG); + WatchdogRevision =3D (WatchdogIId >> GENERIC_WDOG_IID_REV_SHIFT) & GENER= IC_WDOG_IID_REV_MASK; WatchdogDisable (); =20 return EFI_SUCCESS; --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114088): https://edk2.groups.io/g/devel/message/114088 Mute This Topic: https://groups.io/mt/103832319/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-