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Date: Thu, 18 Jan 2024 14:50:42 +0800 Message-ID: <20240118065046.961-30-duke.zhai@amd.com> In-Reply-To: <20240118065046.961-1-duke.zhai@amd.com> References: <20240118065046.961-1-duke.zhai@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F5:EE_|DS7PR12MB8232:EE_ X-MS-Office365-Filtering-Correlation-Id: 0e3e5d59-4e0a-4e48-cdda-08dc17f21506 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Message-Info: RnkA84uV3V5LW5jw9DFb6MuhyhobZ9b1CwiOMC6cNU4yH0vSZQXU/9E4MikiM1IOGEJa+WAUTO7E8gWD6jPtb/uetOZodERF8g++EtEBDnfJN1LrhtgBmarYXmwJii/+yPLWJ5gqmAPp3xPX8WRUZkQhlYlzZAw18a2kopFRmjAcsApoIXWrjPBghUYjROfcdJSPtm9xOzK39hDedst2zeNsrtcwjN8hq1PSt4uOF8rn6DTrohLHjUgxJFUlppzSnj5lJRbnBNFvoN/3OGHxJk7gYCf+TtDQ2/JMyRz3zjTHdVNu5SiPSDEcmhztJeGdXgVof7wGT76dyHSE18EGzzx6Su/fFbWR7MLBFWogtluA+ym99RRyIo/7WXHwhdJ5LpgqHbOabZzZ8O5Zw632ZDjOuihx0kmgWg4p6WK+I/xP4Kbug+b3v2XhBHthFXp7Jzz3iqHlIAGbEBjqTch6vLE1ofnDXoEwZoctrOs19ayEilMR+7Yi3JTqa+dzaGGT3mYcYqbULQtM21r4uZZTxqxc9AiyY5ddKQWmr1YD01OBnU19iQmtJjLbfKgvarvh3/X44JLiVNtxu3x9P9OuAq6mK7JFeNqbvz1VUxKf3fJM1HHJyfPSxYbs57CGGOYM6HM0KaetqoemLf3GSyyJLx/48v+CEWj0NRDpfeJa9kHrxeljBbpNZmrEqVJtCdZD5EUjR5NKXQ0OOYBpOZ33nduA3pIaxnygIUlLjs21gM5M/OVTT+VQZ8+08/INwgKnAxQpeJha02dqtAcbk9k2aA== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jan 2024 06:52:47.9403 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0e3e5d59-4e0a-4e48-cdda-08dc17f21506 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8232 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,duke.zhai@amd.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: c9z4xSvH5x2SRfUqFSjQxfBMx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1705676276915100031 Content-Type: text/plain; charset="utf-8" From: Duke Zhai BZ #:4640 Initial SmramSaveState module. This module provides services to access SMRAM Save State Map. Signed-off-by: Ken Yao Cc: Eric Xing Cc: Duke Zhai Cc: Igniculus Fu Cc: Abner Chang --- .../PiSmmCpuDxeSmm/SmramSaveState.c | 715 ++++++++++++++++++ 1 file changed, 715 insertions(+) create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/PiSm= mCpuDxeSmm/SmramSaveState.c diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/PiSmmCpuDxe= Smm/SmramSaveState.c b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/P= iSmmCpuDxeSmm/SmramSaveState.c new file mode 100644 index 0000000000..9e5a7d59fc --- /dev/null +++ b/Platform/AMD/VanGoghBoard/Override/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/Smr= amSaveState.c @@ -0,0 +1,715 @@ +/** @file + Implements SmramSaveState.c + + Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/* This file includes code originally published under the following licens= e. */ + +/** @file +Provides services to access SMRAM Save State Map + +Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include + +#include +#include +#include +#include + +#include "PiSmmCpuDxeSmm.h" + +typedef struct { + UINT64 Signature; // Offset 0x00 + UINT16 Reserved1; // Offset 0x08 + UINT16 Reserved2; // Offset 0x0A + UINT16 Reserved3; // Offset 0x0C + UINT16 SmmCs; // Offset 0x0E + UINT16 SmmDs; // Offset 0x10 + UINT16 SmmSs; // Offset 0x12 + UINT16 SmmOtherSegment; // Offset 0x14 + UINT16 Reserved4; // Offset 0x16 + UINT64 Reserved5; // Offset 0x18 + UINT64 Reserved6; // Offset 0x20 + UINT64 Reserved7; // Offset 0x28 + UINT64 SmmGdtPtr; // Offset 0x30 + UINT32 SmmGdtSize; // Offset 0x38 + UINT32 Reserved8; // Offset 0x3C + UINT64 Reserved9; // Offset 0x40 + UINT64 Reserved10; // Offset 0x48 + UINT16 Reserved11; // Offset 0x50 + UINT16 Reserved12; // Offset 0x52 + UINT32 Reserved13; // Offset 0x54 + UINT64 Reserved14; // Offset 0x58 +} PROCESSOR_SMM_DESCRIPTOR; + +extern CONST PROCESSOR_SMM_DESCRIPTOR gcPsd; + +// +// EFER register LMA bit +// +#define LMA BIT10 + +/// +/// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_S= TATE_LOOKUP_ENTRY +/// +#define SMM_CPU_OFFSET(Field) OFFSET_OF (SMRAM_SAVE_STATE_MAP, Field) + +/// +/// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_S= TATE_REGISTER_RANGE +/// +#define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 } + +/// +/// Structure used to describe a range of registers +/// +typedef struct { + EFI_SMM_SAVE_STATE_REGISTER Start; + EFI_SMM_SAVE_STATE_REGISTER End; + UINTN Length; +} CPU_SMM_SAVE_STATE_REGISTER_RANGE; + +/// +/// Structure used to build a lookup table to retrieve the widths and offs= ets +/// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value +/// + +#define SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX 1 +#define SMM_SAVE_STATE_REGISTER_IOMISC_INDEX 2 +#define SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX 3 +#define SMM_SAVE_STATE_REGISTER_MAX_INDEX 4 + +typedef struct { + UINT8 Width32; + UINT8 Width64; + UINT16 Offset32; + UINT16 Offset64Lo; + UINT16 Offset64Hi; + BOOLEAN Writeable; +} CPU_SMM_SAVE_STATE_LOOKUP_ENTRY; + +/// +/// Structure used to build a lookup table for the IOMisc width information +/// +typedef struct { + UINT8 Width; + EFI_SMM_SAVE_STATE_IO_WIDTH IoWidth; +} CPU_SMM_SAVE_STATE_IO_WIDTH; + +/// +/// Variables from SMI Handler +/// +X86_ASSEMBLY_PATCH_LABEL gPatchSmbase; +X86_ASSEMBLY_PATCH_LABEL gPatchSmiStack; +X86_ASSEMBLY_PATCH_LABEL gPatchSmiCr3; +extern volatile UINT8 gcSmiHandlerTemplate[]; +extern CONST UINT16 gcSmiHandlerSize; + +// +// Variables used by SMI Handler +// +IA32_DESCRIPTOR gSmiHandlerIdtr; + +/// +/// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGI= STER +/// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY +/// +CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] =3D { + SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, EFI_SMM_SAVE_ST= ATE_REGISTER_LDTINFO), + SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_ES, EFI_SMM_SAVE_ST= ATE_REGISTER_RIP), + SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_RFLAGS, EFI_SMM_SAVE_ST= ATE_REGISTER_CR4), + { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_S= TATE_REGISTER)0, 0} +}; + +/// +/// Lookup table used to retrieve the widths and offsets associated with e= ach +/// supported EFI_SMM_SAVE_STATE_REGISTER value +/// +CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] =3D { + { 0, 0, 0, 0, = 0, FALSE }, // Reserved + + // + // CPU Save State registers defined in PI SMM CPU Protocol. + // + { 0, 8, 0, SMM_CPU_OFFSET (x64.GdtrBaseLoDwor= d), SMM_CPU_OFFSET (x64.GdtrBaseHiDword), FALSE }, // EFI_SMM_SAVE_STATE_= REGISTER_GDTBASE =3D 4 + { 0, 8, 0, SMM_CPU_OFFSET (x64.IdtrBaseLoDwor= d), SMM_CPU_OFFSET (x64.IdtrBaseHiDword), FALSE }, // EFI_SMM_SAVE_STATE_= REGISTER_IDTBASE =3D 5 + { 0, 8, 0, SMM_CPU_OFFSET (x64.LdtrBaseLoDwor= d), SMM_CPU_OFFSET (x64.LdtrBaseHiDword), FALSE }, // EFI_SMM_SAVE_STATE_= REGISTER_LDTBASE =3D 6 + { 0, 0, 0, SMM_CPU_OFFSET (x64.GdtrLimit), = 0, FALSE }, // EFI_SMM_SAVE_STATE_= REGISTER_GDTLIMIT =3D 7 + { 0, 0, 0, SMM_CPU_OFFSET (x64.IdtrLimit), = 0, FALSE }, // EFI_SMM_SAVE_STATE_= REGISTER_IDTLIMIT =3D 8 + { 0, 0, 0, SMM_CPU_OFFSET (x64.LdtrLimit), = 0, FALSE }, // EFI_SMM_SAVE_STATE_= REGISTER_LDTLIMIT =3D 9 + { 0, 0, 0, 0, = 0, FALSE }, // EFI_SMM_SAVE_STATE_= REGISTER_LDTINFO =3D 10 + + { 4, 4, SMM_CPU_OFFSET (x86._ES), SMM_CPU_OFFSET (x64._ES), = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_ES =3D 20 + { 4, 4, SMM_CPU_OFFSET (x86._CS), SMM_CPU_OFFSET (x64._CS), = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_CS =3D 21 + { 4, 4, SMM_CPU_OFFSET (x86._SS), SMM_CPU_OFFSET (x64._SS), = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_SS =3D 22 + { 4, 4, SMM_CPU_OFFSET (x86._DS), SMM_CPU_OFFSET (x64._DS), = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_DS =3D 23 + { 4, 4, SMM_CPU_OFFSET (x86._FS), SMM_CPU_OFFSET (x64._FS), = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_FS =3D 24 + { 4, 4, SMM_CPU_OFFSET (x86._GS), SMM_CPU_OFFSET (x64._GS), = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_GS =3D 25 + { 0, 4, 0, SMM_CPU_OFFSET (x64.LdtrSelector),= 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_LDTR_SEL =3D 26 + { 4, 4, SMM_CPU_OFFSET (x86._TR), SMM_CPU_OFFSET (x64.TrSelector), = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_TR_SEL =3D 27 + { 4, 8, SMM_CPU_OFFSET (x86._DR7), SMM_CPU_OFFSET (x64._DR7), = SMM_CPU_OFFSET (x64._DR7) + 4, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_DR7 =3D 28 + { 4, 8, SMM_CPU_OFFSET (x86._DR6), SMM_CPU_OFFSET (x64._DR6), = SMM_CPU_OFFSET (x64._DR6) + 4, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_DR6 =3D 29 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R8), = SMM_CPU_OFFSET (x64._R8) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_R8 =3D 30 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R9), = SMM_CPU_OFFSET (x64._R9) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_R9 =3D 31 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R10), = SMM_CPU_OFFSET (x64._R10) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_R10 =3D 32 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R11), = SMM_CPU_OFFSET (x64._R11) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_R11 =3D 33 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R12), = SMM_CPU_OFFSET (x64._R12) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_R12 =3D 34 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R13), = SMM_CPU_OFFSET (x64._R13) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_R13 =3D 35 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R14), = SMM_CPU_OFFSET (x64._R14) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_R14 =3D 36 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R15), = SMM_CPU_OFFSET (x64._R15) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_R15 =3D 37 + { 4, 8, SMM_CPU_OFFSET (x86._EAX), SMM_CPU_OFFSET (x64._RAX), = SMM_CPU_OFFSET (x64._RAX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_RAX =3D 38 + { 4, 8, SMM_CPU_OFFSET (x86._EBX), SMM_CPU_OFFSET (x64._RBX), = SMM_CPU_OFFSET (x64._RBX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_RBX =3D 39 + { 4, 8, SMM_CPU_OFFSET (x86._ECX), SMM_CPU_OFFSET (x64._RCX), = SMM_CPU_OFFSET (x64._RCX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_RCX =3D 40 + { 4, 8, SMM_CPU_OFFSET (x86._EDX), SMM_CPU_OFFSET (x64._RDX), = SMM_CPU_OFFSET (x64._RDX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_RDX =3D 41 + { 4, 8, SMM_CPU_OFFSET (x86._ESP), SMM_CPU_OFFSET (x64._RSP), = SMM_CPU_OFFSET (x64._RSP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_RSP =3D 42 + { 4, 8, SMM_CPU_OFFSET (x86._EBP), SMM_CPU_OFFSET (x64._RBP), = SMM_CPU_OFFSET (x64._RBP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_RBP =3D 43 + { 4, 8, SMM_CPU_OFFSET (x86._ESI), SMM_CPU_OFFSET (x64._RSI), = SMM_CPU_OFFSET (x64._RSI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_RSI =3D 44 + { 4, 8, SMM_CPU_OFFSET (x86._EDI), SMM_CPU_OFFSET (x64._RDI), = SMM_CPU_OFFSET (x64._RDI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_RDI =3D 45 + { 4, 8, SMM_CPU_OFFSET (x86._EIP), SMM_CPU_OFFSET (x64._RIP), = SMM_CPU_OFFSET (x64._RIP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_RIP =3D 46 + + { 4, 8, SMM_CPU_OFFSET (x86._EFLAGS), SMM_CPU_OFFSET (x64._RFLAGS), = SMM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_RFLAGS =3D 51 + { 4, 8, SMM_CPU_OFFSET (x86._CR0), SMM_CPU_OFFSET (x64._CR0), = SMM_CPU_OFFSET (x64._CR0) + 4, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_CR0 =3D 52 + { 4, 8, SMM_CPU_OFFSET (x86._CR3), SMM_CPU_OFFSET (x64._CR3), = SMM_CPU_OFFSET (x64._CR3) + 4, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_CR3 =3D 53 + { 0, 4, 0, SMM_CPU_OFFSET (x64._CR4), = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_CR4 =3D 54 +}; + +/// +/// Lookup table for the IOMisc width information +/// +CONST CPU_SMM_SAVE_STATE_IO_WIDTH mSmmCpuIoWidth[] =3D { + { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined =3D 0 + { 1, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // SMM_IO_LENGTH_BYTE =3D 1 + { 2, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT16 }, // SMM_IO_LENGTH_WORD =3D 2 + { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined =3D 3 + { 4, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT32 }, // SMM_IO_LENGTH_DWORD =3D 4 + { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined =3D 5 + { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined =3D 6 + { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 } // Undefined =3D 7 +}; + +/// +/// Lookup table for the IOMisc type information +/// +CONST EFI_SMM_SAVE_STATE_IO_TYPE mSmmCpuIoType[] =3D { + EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT, // SMM_IO_TYPE_OUT_DX =3D 0 + EFI_SMM_SAVE_STATE_IO_TYPE_INPUT, // SMM_IO_TYPE_IN_DX =3D 1 + EFI_SMM_SAVE_STATE_IO_TYPE_STRING, // SMM_IO_TYPE_OUTS =3D 2 + EFI_SMM_SAVE_STATE_IO_TYPE_STRING, // SMM_IO_TYPE_INS =3D 3 + (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined =3D 4 + (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined =3D 5 + EFI_SMM_SAVE_STATE_IO_TYPE_REP_PREFIX, // SMM_IO_TYPE_REP_OUTS =3D 6 + EFI_SMM_SAVE_STATE_IO_TYPE_REP_PREFIX, // SMM_IO_TYPE_REP_INS =3D 7 + EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT, // SMM_IO_TYPE_OUT_IMMEDIATE =3D 8 + EFI_SMM_SAVE_STATE_IO_TYPE_INPUT, // SMM_IO_TYPE_OUT_IMMEDIATE =3D 9 + (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined =3D = 10 + (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined =3D = 11 + (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined =3D = 12 + (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined =3D = 13 + (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined =3D = 14 + (EFI_SMM_SAVE_STATE_IO_TYPE)0 // Undefined =3D = 15 +}; + +/// +/// The mode of the CPU at the time an SMI occurs +/// +UINT8 mSmmSaveStateRegisterLma; + +/** + Read information from the CPU save state. + + @param Register Specifies the CPU register to read form the save state. + + @retval 0 Register is not valid + @retval >0 Index into mSmmCpuWidthOffset[] associated with Register + +**/ +UINTN +GetRegisterIndex ( + IN EFI_SMM_SAVE_STATE_REGISTER Register + ) +{ + UINTN Index; + UINTN Offset; + + for (Index =3D 0, Offset =3D SMM_SAVE_STATE_REGISTER_MAX_INDEX; mSmmCpuR= egisterRanges[Index].Length !=3D 0; Index++) { + if ((Register >=3D mSmmCpuRegisterRanges[Index].Start) && (Register <= =3D mSmmCpuRegisterRanges[Index].End)) { + return Register - mSmmCpuRegisterRanges[Index].Start + Offset; + } + + Offset +=3D mSmmCpuRegisterRanges[Index].Length; + } + + return 0; +} + +/** + Read a CPU Save State register on the target processor. + + This function abstracts the differences that whether the CPU Save State = register is in the + IA32 CPU Save State Map or X64 CPU Save State Map. + + This function supports reading a CPU Save State register in SMBase reloc= ation handler. + + @param[in] CpuIndex Specifies the zero-based index of the CPU sav= e state. + @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table. + @param[in] Width The number of bytes to read from the CPU save= state. + @param[out] Buffer Upon return, this holds the CPU register valu= e read from the save state. + + @retval EFI_SUCCESS The register was read from Save State. + @retval EFI_NOT_FOUND The register is not defined for the Save S= tate of Processor. + @retval EFI_INVALID_PARAMETER This or Buffer is NULL. + +**/ +EFI_STATUS +ReadSaveStateRegisterByIndex ( + IN UINTN CpuIndex, + IN UINTN RegisterIndex, + IN UINTN Width, + OUT VOID *Buffer + ) +{ + SMRAM_SAVE_STATE_MAP *CpuSaveState; + + if (RegisterIndex =3D=3D 0) { + return EFI_NOT_FOUND; + } + + CpuSaveState =3D gSmst->CpuSaveState[CpuIndex]; + + if (mSmmSaveStateRegisterLma =3D=3D EFI_SMM_SAVE_STATE_REGISTER_LMA_32BI= T) { + // + // If 32-bit mode width is zero, then the specified register can not b= e accessed + // + if (mSmmCpuWidthOffset[RegisterIndex].Width32 =3D=3D 0) { + return EFI_NOT_FOUND; + } + + // + // If Width is bigger than the 32-bit mode width, then the specified r= egister can not be accessed + // + if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) { + return EFI_INVALID_PARAMETER; + } + + // + // Write return buffer + // + ASSERT (CpuSaveState !=3D NULL); + CopyMem (Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIn= dex].Offset32, Width); + } else { + // + // If 64-bit mode width is zero, then the specified register can not b= e accessed + // + if (mSmmCpuWidthOffset[RegisterIndex].Width64 =3D=3D 0) { + return EFI_NOT_FOUND; + } + + // + // If Width is bigger than the 64-bit mode width, then the specified r= egister can not be accessed + // + if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) { + return EFI_INVALID_PARAMETER; + } + + // + // Write at most 4 of the lower bytes of the return buffer + // + CopyMem (Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIn= dex].Offset64Lo, MIN (4, Width)); + if (Width > 4) { + // + // Write at most 4 of the upper bytes of the return buffer + // + CopyMem ((UINT8 *)Buffer + 4, (UINT8 *)CpuSaveState + mSmmCpuWidthOf= fset[RegisterIndex].Offset64Hi, Width - 4); + } + } + + return EFI_SUCCESS; +} + +/** + Read a CPU Save State register on the target processor. + + This function abstracts the differences that whether the CPU Save State = register is in the + IA32 CPU Save State Map or X64 CPU Save State Map. + + This function supports reading a CPU Save State register in SMBase reloc= ation handler. + + @param[in] CpuIndex Specifies the zero-based index of the CPU sav= e state. + @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table. + @param[in] Width The number of bytes to read from the CPU save= state. + @param[out] Buffer Upon return, this holds the CPU register valu= e read from the save state. + + @retval EFI_SUCCESS The register was read from Save State. + @retval EFI_NOT_FOUND The register is not defined for the Save S= tate of Processor. + @retval EFI_INVALID_PARAMETER Buffer is NULL, or Width does not meet req= uirement per Register type. + +**/ +EFI_STATUS +EFIAPI +ReadSaveStateRegister ( + IN UINTN CpuIndex, + IN EFI_SMM_SAVE_STATE_REGISTER Register, + IN UINTN Width, + OUT VOID *Buffer + ) +{ + SMRAM_SAVE_STATE_MAP *CpuSaveState; + EFI_SMM_SAVE_STATE_IO_INFO *IoInfo; + + CpuSaveState =3D gSmst->CpuSaveState[CpuIndex]; + // + // Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA + // + if (Register =3D=3D EFI_SMM_SAVE_STATE_REGISTER_LMA) { + // + // Only byte access is supported for this register + // + if (Width !=3D 1) { + return EFI_INVALID_PARAMETER; + } + + *(UINT8 *)Buffer =3D mSmmSaveStateRegisterLma; + + return EFI_SUCCESS; + } + + // + // Check for special EFI_SMM_SAVE_STATE_REGISTER_IO + // + if (Register =3D=3D EFI_SMM_SAVE_STATE_REGISTER_IO) { + // + // Check SMM IO Trap Offset valid bit + // + if (!(CpuSaveState->x64.SMM_IO_TRAP & 0x02)) { + return EFI_NOT_FOUND; + } + + // + // Zero the IoInfo structure that will be returned in Buffer + // + IoInfo =3D (EFI_SMM_SAVE_STATE_IO_INFO *)Buffer; + ZeroMem (IoInfo, sizeof (EFI_SMM_SAVE_STATE_IO_INFO)); + + // + // Use hard code to fill in all the fields of the IoInfo structure + // + IoInfo->IoPort =3D (UINT16)(CpuSaveState->x64.SMM_IO_TRAP >> 16); + IoInfo->IoWidth =3D EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8; + IoInfo->IoType =3D EFI_SMM_SAVE_STATE_IO_TYPE_INPUT; + IoInfo->IoData =3D (UINT64)IoRead8 ((CpuSaveState->x64.SMM_IO_TRAP >>= 16)); + + return EFI_SUCCESS; + } + + // + // Convert Register to a register lookup table index + // + return ReadSaveStateRegisterByIndex (CpuIndex, GetRegisterIndex (Registe= r), Width, Buffer); +} + +/** + Write value to a CPU Save State register on the target processor. + + This function abstracts the differences that whether the CPU Save State = register is in the + IA32 CPU Save State Map or X64 CPU Save State Map. + + This function supports writing a CPU Save State register in SMBase reloc= ation handler. + + @param[in] CpuIndex Specifies the zero-based index of the CPU save= state. + @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table. + @param[in] Width The number of bytes to read from the CPU save = state. + @param[in] Buffer Upon entry, this holds the new CPU register va= lue. + + @retval EFI_SUCCESS The register was written to Save State. + @retval EFI_NOT_FOUND The register is not defined for the Save S= tate of Processor. + @retval EFI_INVALID_PARAMETER ProcessorIndex or Width is not correct. + +**/ +EFI_STATUS +EFIAPI +WriteSaveStateRegister ( + IN UINTN CpuIndex, + IN EFI_SMM_SAVE_STATE_REGISTER Register, + IN UINTN Width, + IN CONST VOID *Buffer + ) +{ + UINTN RegisterIndex; + SMRAM_SAVE_STATE_MAP *CpuSaveState; + + // + // Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored + // + if (Register =3D=3D EFI_SMM_SAVE_STATE_REGISTER_LMA) { + return EFI_SUCCESS; + } + + // + // Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported + // + if (Register =3D=3D EFI_SMM_SAVE_STATE_REGISTER_IO) { + return EFI_NOT_FOUND; + } + + // + // Convert Register to a register lookup table index + // + RegisterIndex =3D GetRegisterIndex (Register); + if (RegisterIndex =3D=3D 0) { + return EFI_NOT_FOUND; + } + + CpuSaveState =3D gSmst->CpuSaveState[CpuIndex]; + + // + // Do not write non-writable SaveState, because it will cause exception. + // + if (!mSmmCpuWidthOffset[RegisterIndex].Writeable) { + return EFI_UNSUPPORTED; + } + + // + // Check CPU mode + // + if (mSmmSaveStateRegisterLma =3D=3D EFI_SMM_SAVE_STATE_REGISTER_LMA_32BI= T) { + // + // If 32-bit mode width is zero, then the specified register can not b= e accessed + // + if (mSmmCpuWidthOffset[RegisterIndex].Width32 =3D=3D 0) { + return EFI_NOT_FOUND; + } + + // + // If Width is bigger than the 32-bit mode width, then the specified r= egister can not be accessed + // + if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) { + return EFI_INVALID_PARAMETER; + } + + // + // Write SMM State register + // + ASSERT (CpuSaveState !=3D NULL); + CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Off= set32, Buffer, Width); + } else { + // + // If 64-bit mode width is zero, then the specified register can not b= e accessed + // + if (mSmmCpuWidthOffset[RegisterIndex].Width64 =3D=3D 0) { + return EFI_NOT_FOUND; + } + + // + // If Width is bigger than the 64-bit mode width, then the specified r= egister can not be accessed + // + if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) { + return EFI_INVALID_PARAMETER; + } + + // + // Write at most 4 of the lower bytes of SMM State register + // + CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Off= set64Lo, Buffer, MIN (4, Width)); + if (Width > 4) { + // + // Write at most 4 of the upper bytes of SMM State register + // + CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].O= ffset64Hi, (UINT8 *)Buffer + 4, Width - 4); + } + } + + return EFI_SUCCESS; +} + +/** + Hook the code executed immediately after an RSM instruction on the curre= ntly + executing CPU. The mode of code executed immediately after RSM must be + detected, and the appropriate hook must be selected. Always clear the a= uto + HALT restart flag if it is set. + + @param[in] CpuIndex The processor index for the currently + executing CPU. + @param[in] CpuState Pointer to SMRAM Save State Map for = the + currently executing CPU. + @param[in] NewInstructionPointer32 Instruction pointer to use if resumi= ng to + 32-bit mode from 64-bit SMM. + @param[in] NewInstructionPointer Instruction pointer to use if resumi= ng to + same mode as SMM. + + @retval The value of the original instruction pointer before it was hook= ed. + +**/ +UINT64 +EFIAPI +HookReturnFromSmm ( + IN UINTN CpuIndex, + SMRAM_SAVE_STATE_MAP *CpuState, + UINT64 NewInstructionPointer32, + UINT64 NewInstructionPointer + ) +{ + UINT64 OriginalInstructionPointer; + + OriginalInstructionPointer =3D SmmCpuFeaturesHookReturnFromSmm ( + CpuIndex, + CpuState, + NewInstructionPointer32, + NewInstructionPointer + ); + if (OriginalInstructionPointer !=3D 0) { + return OriginalInstructionPointer; + } + + if (mSmmSaveStateRegisterLma =3D=3D EFI_SMM_SAVE_STATE_REGISTER_LMA_32BI= T) { + OriginalInstructionPointer =3D (UINT64)CpuState->x86._EIP; + CpuState->x86._EIP =3D (UINT32)NewInstructionPointer; + // + // Clear the auto HALT restart flag so the RSM instruction returns + // program control to the instruction following the HLT instruction. + // + if ((CpuState->x86.AutoHALTRestart & BIT0) !=3D 0) { + CpuState->x86.AutoHALTRestart &=3D ~BIT0; + } + } else { + OriginalInstructionPointer =3D CpuState->x64._RIP; + if ((CpuState->x64.EFER & LMA) =3D=3D 0) { + CpuState->x64._RIP =3D (UINT32)NewInstructionPointer32; + } else { + CpuState->x64._RIP =3D (UINT32)NewInstructionPointer; + } + + // + // Clear the auto HALT restart flag so the RSM instruction returns + // program control to the instruction following the HLT instruction. + // + if ((CpuState->x64.AutoHALTRestart & BIT0) !=3D 0) { + CpuState->x64.AutoHALTRestart &=3D ~BIT0; + } + } + + return OriginalInstructionPointer; +} + +/** + Get the size of the SMI Handler in bytes. + + @retval The size, in bytes, of the SMI Handler. + +**/ +UINTN +EFIAPI +GetSmiHandlerSize ( + VOID + ) +{ + UINTN Size; + + Size =3D SmmCpuFeaturesGetSmiHandlerSize (); + if (Size !=3D 0) { + return Size; + } + + return gcSmiHandlerSize; +} + +/** + Install the SMI handler for the CPU specified by CpuIndex. This function + is called by the CPU that was elected as monarch during System Management + Mode initialization. + + @param[in] CpuIndex The index of the CPU to install the custom SMI han= dler. + The value must be between 0 and the NumberOfCpus f= ield + in the System Management System Table (SMST). + @param[in] SmBase The SMBASE address for the CPU specified by CpuInd= ex. + @param[in] SmiStack The stack to use when an SMI is processed by the + the CPU specified by CpuIndex. + @param[in] StackSize The size, in bytes, if the stack used when an SMI = is + processed by the CPU specified by CpuIndex. + @param[in] GdtBase The base address of the GDT to use when an SMI is + processed by the CPU specified by CpuIndex. + @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is + processed by the CPU specified by CpuIndex. + @param[in] IdtBase The base address of the IDT to use when an SMI is + processed by the CPU specified by CpuIndex. + @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is + processed by the CPU specified by CpuIndex. + @param[in] Cr3 The base address of the page tables to use when an= SMI + is processed by the CPU specified by CpuIndex. +**/ +VOID +EFIAPI +InstallSmiHandler ( + IN UINTN CpuIndex, + IN UINT32 SmBase, + IN VOID *SmiStack, + IN UINTN StackSize, + IN UINTN GdtBase, + IN UINTN GdtSize, + IN UINTN IdtBase, + IN UINTN IdtSize, + IN UINT32 Cr3 + ) +{ + PROCESSOR_SMM_DESCRIPTOR *Psd; + UINT32 CpuSmiStack; + + // + // Initialize PROCESSOR_SMM_DESCRIPTOR + // + Psd =3D (PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase + SMM_PSD_OFF= SET); + CopyMem (Psd, &gcPsd, sizeof (gcPsd)); + Psd->SmmGdtPtr =3D (UINT64)GdtBase; + Psd->SmmGdtSize =3D (UINT32)GdtSize; + + if (SmmCpuFeaturesGetSmiHandlerSize () !=3D 0) { + // + // Install SMI handler provided by library + // + SmmCpuFeaturesInstallSmiHandler ( + CpuIndex, + SmBase, + SmiStack, + StackSize, + GdtBase, + GdtSize, + IdtBase, + IdtSize, + Cr3 + ); + return; + } + + InitShadowStack (CpuIndex, (VOID *)((UINTN)SmiStack + StackSize)); + + // + // Initialize values in template before copy + // + CpuSmiStack =3D (UINT32)((UINTN)SmiStack + StackSize - sizeof (UINTN)); + PatchInstructionX86 (gPatchSmiStack, CpuSmiStack, 4); + PatchInstructionX86 (gPatchSmiCr3, Cr3, 4); + PatchInstructionX86 (gPatchSmbase, SmBase, 4); + gSmiHandlerIdtr.Base =3D IdtBase; + gSmiHandlerIdtr.Limit =3D (UINT16)(IdtSize - 1); + + // + // Set the value at the top of the CPU stack to the CPU Index + // + *(UINTN *)(UINTN)CpuSmiStack =3D CpuIndex; + + // + // Copy template to CPU specific SMI handler location + // + CopyMem ( + (VOID *)((UINTN)SmBase + SMM_HANDLER_OFFSET), + (VOID *)gcSmiHandlerTemplate, + gcSmiHandlerSize + ); +} -- 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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