From nobody Sat May 11 13:34:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+113743+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113743+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1705074506; cv=none; d=zohomail.com; s=zohoarc; b=Z64YWLilDBaXj6QZAx0gtgz5q/rDYPm1mNabu68i5PVjMMWnrMXw0SWycbJM9iVp4dQgpR4CU0biQ3GEIXGq0UdBXqNq1wrWPh8PX2m5CnhwvJlRKhpJPwbalsquBEF44cSyyRv06SnCaeJ74TCeqoqiimRMROX5M+0AwPSenjo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705074506; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=B2rl0HMEppuy4YQSeEWlxdLS2LZmjYx8cuTc3ZFusEY=; b=nSfRCz3gk4t3gVlxXsXRPEvujEBnpTjrOjSnodLhPUg9XBPMC9e8w8LGn2AN0raVB6f8Mp2XiDXiPVqfLqH2mSF6wD5ztdg1s1WaF2ak9okO9becgIAN+uZW3Uk0MgmPkmP0d4F/duCMK5ydolwsf8YiAR81GneO/AxMCpTleRw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113743+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1705074506237284.55078571382876; Fri, 12 Jan 2024 07:48:26 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=2GSflWKUz1FhxKQAW6j9Ht5qnzjmTTtbmSrxt6P8CLw=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1705074505; v=1; b=bwc8wn1hrxBrVuYDX7sXV+T42WxYI3BTgqO8VLytIzKZuBjHuEzgKJ0bmXXGejVISx8g8B8B NTixMaeB0jLiQypawwkkt8FMbHepT4Cek6hpWPLjkjiH14jUrtH6KbH7I14aApbSheJhRfNAPeL ynhEOZn3YE1ia4tA0b8kn2Co= X-Received: by 127.0.0.2 with SMTP id RBgnYY1788612xDN1aTvo0M8; Fri, 12 Jan 2024 07:48:25 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.10449.1705074505091626008 for ; Fri, 12 Jan 2024 07:48:25 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B7EFD2F4; Fri, 12 Jan 2024 07:49:10 -0800 (PST) X-Received: from usa.arm.com (a079755.arm.com [10.162.46.129]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E211D3F67D; Fri, 12 Jan 2024 07:48:22 -0800 (PST) From: "Prabin CA" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V2 1/8] Platform/Sgi: Update the datatype of PcdSmmuBase from u32 to u64 Date: Fri, 12 Jan 2024 21:17:52 +0530 Message-Id: <20240112154759.1222138-2-prabin.ca@arm.com> In-Reply-To: <20240112154759.1222138-1-prabin.ca@arm.com> References: <20240112154759.1222138-1-prabin.ca@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,prabin.ca@arm.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: aJuDApC6fL6NCeVamDVO6JXgx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1705074506798100001 Content-Type: text/plain; charset="utf-8" From: Vivek Gautam On RD-N2 and previous generation platforms, the base address was within 32-bit region. However, on upcoming platforms, the SMMUv3 base address is beyond 32-bit address region. So, update the datatype of SMMUv3 base PCD. Signed-off-by: Vivek Gautam Signed-off-by: Prabin CA Reviewed-by: Pierre Gondois --- Platform/ARM/SgiPkg/SgiPlatform.dec | 2 +- Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec b/Platform/ARM/SgiPkg/SgiP= latform.dec index 103dff8471a7..4087ff6cad2e 100644 --- a/Platform/ARM/SgiPkg/SgiPlatform.dec +++ b/Platform/ARM/SgiPkg/SgiPlatform.dec @@ -79,7 +79,7 @@ [PcdsFixedAtBuild] gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv|0|UINT32|0x00000014 =20 # SMMU - gArmSgiTokenSpaceGuid.PcdSmmuBase|0|UINT32|0x0000001D + gArmSgiTokenSpaceGuid.PcdSmmuBase|0|UINT64|0x0000001D gArmSgiTokenSpaceGuid.PcdSmmuSize|0|UINT32|0x0000001E =20 # GPIO Controller diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c b/Pla= tform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c index fa3cfbc730f6..62c212f3c5b0 100644 --- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c +++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2018-2023, ARM Limited. All rights reserved. +* Copyright (c) 2018-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -167,8 +167,8 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; =20 // Sub System Peripherals - SMMU - VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet32 (PcdSmmuBase= ); - VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet32 (PcdSmmuBase= ); + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdSmmuBase= ); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdSmmuBase= ); VirtualMemoryTable[Index].Length =3D FixedPcdGet32 (PcdSmmuSize= ); VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; =20 --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113743): https://edk2.groups.io/g/devel/message/113743 Mute This Topic: https://groups.io/mt/103685112/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 11 13:34:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+113744+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113744+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1705074507; cv=none; d=zohomail.com; s=zohoarc; b=V+h+UfpT0VIdI8n3uO+Cbm5S0UqMs+UFh+Od5GtjWPc5e8u5g6M8Skqn3IG98r26g6FcqkDGlIsW8+9exWvEJIeworC3As3f/nWvT7fJvl8ZfVsmDgfwxvgUCy+iqiE3lMipFSV4lxkDrpPZSHLhuuG4zWDXeTMyq5b6cdRUf2w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705074507; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=T9yzD1BemfaZjwSvMa71I5VAi4GL/I/RtFeWyj+qVfE=; b=NWKwMKMX/P4kGsZgNBPKM6s4UXRQcQ9BCV0ekXwVFoXDYe9aRIgGwPfnB0E/JEAlE0m3i4qTF4mnQT0kgZs8MFwRWPw8csFXQGSpoxAQb/mnYPtMvJPOsz5ZHWdyBwfawFuoh5RYg4r+PcIEZ+Nv1MrWqeTQjjOqlvpBgVaDy/c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113744+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1705074507647996.6855330623837; Fri, 12 Jan 2024 07:48:27 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=pHPL30uTMXU7JFFLqCKnhsLv/1Z2/RS+nTpJh3dBIkE=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1705074507; v=1; b=eQPLu5bALCgecJbJnvXnFwP5JQlxFSiQMG3bnuYxQ4pPkzzkme6HpUeylH7OO6pFrXHQnkHg cesCCqH8rAECgBH58W6p86h2JuhcM58Z94dchMj5YotgNMe8CgvgRdubzXLFHLogG8ivFarMGSu WpNgmPYXX5J4v6EKtEe8Tjmo= X-Received: by 127.0.0.2 with SMTP id Uk8JYY1788612xsku6dEBnSY; Fri, 12 Jan 2024 07:48:27 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.10450.1705074506658266458 for ; Fri, 12 Jan 2024 07:48:26 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AFC631FB; Fri, 12 Jan 2024 07:49:12 -0800 (PST) X-Received: from usa.arm.com (a079755.arm.com [10.162.46.129]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id DA4CE3F67D; Fri, 12 Jan 2024 07:48:24 -0800 (PST) From: "Prabin CA" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V2 2/8] Platform/Sgi: Refactor system memory base and size definitions Date: Fri, 12 Jan 2024 21:17:53 +0530 Message-Id: <20240112154759.1222138-3-prabin.ca@arm.com> In-Reply-To: <20240112154759.1222138-1-prabin.ca@arm.com> References: <20240112154759.1222138-1-prabin.ca@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,prabin.ca@arm.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: KLIwQlnfWTk4Xa4QNw1c2Nbhx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1705074508705100009 Content-Type: text/plain; charset="utf-8" In preparation of adding the next generation of reference design platform that have different memory map, refactor the PcdSystemMemoryBase and PcdSystemMemorySize PCD definitions from the common PCD definitions file into the various platform generation specific memory map PCD definitions file. Signed-off-by: Prabin CA Reviewed-by: Pierre Gondois --- Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc | 8 +++++++- Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc | 8 +++++++- Platform/ARM/SgiPkg/SgiPlatform.dsc.inc | 6 +----- 3 files changed, 15 insertions(+), 7 deletions(-) diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc b/Platform/ARM/SgiPkg= /SgiMemoryMap.dsc.inc index 0cffff577c42..eab43b23ec6d 100644 --- a/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc +++ b/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc @@ -1,5 +1,5 @@ # -# Copyright (c) 2020 - 2022, Arm Limited. All rights reserved. +# Copyright (c) 2020 - 2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -67,3 +67,9 @@ [PcdsFixedAtBuild.common] gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress|0x1C1D0000 gArmSgiTokenSpaceGuid.PcdGpioController0Size|0x00010000 gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt|136 + + # System Memory (1GB - 16MB of Trusted DRAM at the top of the + # 32bit address space) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000 + diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc b/Platform/ARM/SgiPk= g/SgiMemoryMap2.dsc.inc index de1d8ea24b89..35e27d42d5a2 100644 --- a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc +++ b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc @@ -1,5 +1,5 @@ # -# Copyright (c) 2020 - 2023, Arm Limited. All rights reserved. +# Copyright (c) 2020 - 2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -75,3 +75,9 @@ [PcdsFixedAtBuild.common] =20 # IO virtualization block gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlk0Base|0x1080000000 + + # System Memory (1GB - 16MB of Trusted DRAM at the top of the + # 32bit address space) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000 + diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc b/Platform/ARM/SgiPkg/= SgiPlatform.dsc.inc index 26ecd9ed59a7..1cfe07c7e4ed 100644 --- a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc +++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc @@ -1,5 +1,5 @@ # -# Copyright (c) 2018 - 2022, ARM Limited. All rights reserved. +# Copyright (c) 2018 - 2024, Arm Limited. All rights reserved. # (C) Copyright 2021 Hewlett Packard Enterprise Development LP
# # SPDX-License-Identifier: BSD-2-Clause-Patent @@ -131,10 +131,6 @@ [PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x40000 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x0 =20 - # System Memory (1GB - 16MB of Trusted DRAM at the top of the 32bit addr= ess space) - gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 - gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000 - # ACPI Table Version gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 =20 --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113744): https://edk2.groups.io/g/devel/message/113744 Mute This Topic: https://groups.io/mt/103685113/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 11 13:34:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+113745+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113745+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1705074509; cv=none; d=zohomail.com; s=zohoarc; b=KkzXxWr+KIVstdAVCUZAnUMNqAZLt2PF2BaFw8qOGfL3+WcIOfssuBkl9LGOLYwIkF2SiQjUVDFS9hkEeSG2o09zolyLizhJz/+s5cPS+U/AWUBE1OI89NAcLoieUjWj3rSgyUDPQGRXVad0RE0S+hn5HUEkwRP4oXgG2VVTvZY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705074509; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=umOYNZ+MFL5zXdfUE2MgfM/DpzSzrc1ytSNhg41Lre0=; b=NL/mULEbvNwZBHEiMW6lD0RCX51Mn/wGQ9/3rxa594wPAx83Hu+ZL+1qu6N30zo9NZfDXfx1UA01MN1NJKRspatqQsPkzJQGtbDztcdeDWrERFM83O+Ho05b6GWQAVtKa2OZTAeAevOryRTuDXFqtnlY3miC5u0BXbpDg6j+0jg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113745+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1705074509590340.81239149044995; Fri, 12 Jan 2024 07:48:29 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=dkClsrF7aYQH6xIYK0+VjCRxy8Sr+leJUqSfQjE1v/c=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1705074509; v=1; b=jl5DE8UvdUcxaCARO1GQHzSM2kmcfqAjR2HmqbnotWiq89ZPU+Jd5jgb2n+12i0O8tXeA4Bl g6eCpBIc3idGbKRNahcaflrmRA/gSww8Dp2r8dCCALxGO63ZZjg+n0kSejQOTkaeGd/3E1m81HZ a5/uh9F3a5d++ppmtEgroDW0= X-Received: by 127.0.0.2 with SMTP id bUyxYY1788612xXVYEjCWO8c; Fri, 12 Jan 2024 07:48:29 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.10453.1705074508627808241 for ; Fri, 12 Jan 2024 07:48:28 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A8B0C2F4; Fri, 12 Jan 2024 07:49:14 -0800 (PST) X-Received: from usa.arm.com (a079755.arm.com [10.162.46.129]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D23133F67D; Fri, 12 Jan 2024 07:48:26 -0800 (PST) From: "Prabin CA" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V2 3/8] Platform/Sgi: Introduce a flag to enable PCIe support for RD Platforms Date: Fri, 12 Jan 2024 21:17:54 +0530 Message-Id: <20240112154759.1222138-4-prabin.ca@arm.com> In-Reply-To: <20240112154759.1222138-1-prabin.ca@arm.com> References: <20240112154759.1222138-1-prabin.ca@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,prabin.ca@arm.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: hgXnIg863laTbIXvAkujSqVfx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1705074510744100013 Content-Type: text/plain; charset="utf-8" Introducing a flag called PCIE_ENABLE, which can be set to TRUE or FALSE from the respective .dsc files to enable or disable the PCIe support. As not all reference design platforms have PCIe support enabled, this flag is introduced. Signed-off-by: Prabin CA Reviewed-by: Pierre Gondois --- Platform/ARM/SgiPkg/SgiPlatform.dec | 1 + Platform/ARM/SgiPkg/SgiPlatform.dsc.inc | 6 ++++++ Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc | 4 +++- Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc | 4 +++- Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc | 4 +++- Platform/ARM/SgiPkg/RdV1/RdV1.dsc | 4 +++- Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.dsc | 4 +++- Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc | 4 +++- Platform/ARM/SgiPkg/SgiPlatform.fdf | 4 +++- Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf | 5 ++++- Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c | 19 +++++++++++-= ------- 11 files changed, 43 insertions(+), 16 deletions(-) diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec b/Platform/ARM/SgiPkg/SgiP= latform.dec index 4087ff6cad2e..af7887e54126 100644 --- a/Platform/ARM/SgiPkg/SgiPlatform.dec +++ b/Platform/ARM/SgiPkg/SgiPlatform.dec @@ -31,6 +31,7 @@ [Guids.common] [PcdsFeatureFlag.common] gArmSgiTokenSpaceGuid.PcdVirtioBlkSupported|FALSE|BOOLEAN|0x00000001 gArmSgiTokenSpaceGuid.PcdVirtioNetSupported|FALSE|BOOLEAN|0x00000010 + gArmSgiTokenSpaceGuid.PcdPcieEnable|FALSE|BOOLEAN|0x0000002E =20 [PcdsFixedAtBuild] gArmSgiTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x00000002 diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc b/Platform/ARM/SgiPkg/= SgiPlatform.dsc.inc index 1cfe07c7e4ed..1bf489ffeb39 100644 --- a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc +++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc @@ -103,6 +103,10 @@ [PcdsFeatureFlag.common] gArmSgiTokenSpaceGuid.PcdVirtioNetSupported|TRUE gEfiMdeModulePkgTokenSpaceGuid.PcdEnableVariableRuntimeCache|FALSE =20 +!if $(PCIE_ENABLE) =3D=3D TRUE + gArmSgiTokenSpaceGuid.PcdPcieEnable|TRUE +!endif + [PcdsFixedAtBuild.common] gArmTokenSpaceGuid.PcdVFPEnabled|1 gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 @@ -330,6 +334,7 @@ [Components.common] # Virtio Network OvmfPkg/VirtioNetDxe/VirtioNet.inf =20 +!if $(PCIE_ENABLE) =3D=3D TRUE # # Required by PCI # @@ -343,6 +348,7 @@ [Components.common] gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F } +!endif =20 # # AHCI Support diff --git a/Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc b/Platform/ARM/SgiPk= g/RdE1Edge/RdE1Edge.dsc index 32d67d380814..c7463da5203e 100644 --- a/Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc +++ b/Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc @@ -1,5 +1,5 @@ # -# Copyright (c) 2020-2022, ARM Limited. All rights reserved. +# Copyright (c) 2020-2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -22,6 +22,8 @@ [Defines] BOARD_DXE_FV_COMPONENTS =3D Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge= .fdf.inc BUILD_NUMBER =3D 1 =20 + DEFINE PCIE_ENABLE =3D TRUE + # include common definitions from SgiPlatform.dsc !include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc !include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc diff --git a/Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc b/Platform/ARM/SgiPk= g/RdN1Edge/RdN1Edge.dsc index 6c9a64df054f..77efec9d9533 100644 --- a/Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc +++ b/Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc @@ -1,5 +1,5 @@ # -# Copyright (c) 2020-2022, ARM Limited. All rights reserved. +# Copyright (c) 2020-2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -22,6 +22,8 @@ [Defines] BOARD_DXE_FV_COMPONENTS =3D Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge= .fdf.inc BUILD_NUMBER =3D 1 =20 + DEFINE PCIE_ENABLE =3D TRUE + # include common definitions from SgiPlatform.dsc !include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc !include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc diff --git a/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc b/Platform/ARM/S= giPkg/RdN1EdgeX2/RdN1EdgeX2.dsc index 10e5bfa29b46..521d88925059 100644 --- a/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc +++ b/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc @@ -1,5 +1,5 @@ # -# Copyright (c) 2020-2022, ARM Limited. All rights reserved. +# Copyright (c) 2020-2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -22,6 +22,8 @@ [Defines] BOARD_DXE_FV_COMPONENTS =3D Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1Ed= geX2.fdf.inc BUILD_NUMBER =3D 1 =20 + DEFINE PCIE_ENABLE =3D TRUE + # include common definitions from SgiPlatform.dsc !include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc !include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc diff --git a/Platform/ARM/SgiPkg/RdV1/RdV1.dsc b/Platform/ARM/SgiPkg/RdV1/R= dV1.dsc index e75f68fd8a40..2a4bb019fe7a 100644 --- a/Platform/ARM/SgiPkg/RdV1/RdV1.dsc +++ b/Platform/ARM/SgiPkg/RdV1/RdV1.dsc @@ -1,5 +1,5 @@ # -# Copyright (c) 2020-2022, ARM Limited. All rights reserved. +# Copyright (c) 2020-2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -22,6 +22,8 @@ [Defines] BOARD_DXE_FV_COMPONENTS =3D Platform/ARM/SgiPkg/RdV1/RdV1.fdf.inc BUILD_NUMBER =3D 1 =20 + DEFINE PCIE_ENABLE =3D TRUE + # include common definitions from SgiPlatform.dsc !include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc !include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc diff --git a/Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.dsc b/Platform/ARM/SgiPkg/Rd= V1Mc/RdV1Mc.dsc index ce014add4165..971e2ccca367 100644 --- a/Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.dsc +++ b/Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.dsc @@ -1,5 +1,5 @@ # -# Copyright (c) 2020-2022, ARM Limited. All rights reserved. +# Copyright (c) 2020-2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -22,6 +22,8 @@ [Defines] BOARD_DXE_FV_COMPONENTS =3D Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.fdf= .inc BUILD_NUMBER =3D 1 =20 + DEFINE PCIE_ENABLE =3D TRUE + # include common definitions from SgiPlatform.dsc !include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc !include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc diff --git a/Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc b/Platform/ARM/SgiPkg/Sg= i575/Sgi575.dsc index 4da4bc2c54a3..4ed64abecd31 100644 --- a/Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc +++ b/Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc @@ -1,5 +1,5 @@ # -# Copyright (c) 2020-2022, ARM Limited. All rights reserved. +# Copyright (c) 2020-2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -22,6 +22,8 @@ [Defines] BOARD_DXE_FV_COMPONENTS =3D Platform/ARM/SgiPkg/Sgi575/Sgi575.fdf= .inc BUILD_NUMBER =3D 1 =20 + DEFINE PCIE_ENABLE =3D TRUE + # include common definitions from SgiPlatform.dsc !include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc !include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc diff --git a/Platform/ARM/SgiPkg/SgiPlatform.fdf b/Platform/ARM/SgiPkg/SgiP= latform.fdf index 7e55214c2001..4558e886f863 100644 --- a/Platform/ARM/SgiPkg/SgiPlatform.fdf +++ b/Platform/ARM/SgiPkg/SgiPlatform.fdf @@ -1,5 +1,5 @@ # -# Copyright (c) 2018-2021, ARM Limited. All rights reserved. +# Copyright (c) 2018-2024, ARM Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -115,6 +115,7 @@ [FV.FvMain] INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf INF Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf =20 +!if $(PCIE_ENABLE) =3D=3D TRUE # Required by PCI INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf =20 @@ -123,6 +124,7 @@ [FV.FvMain] # INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf +!endif =20 # # AHCI Support diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf b/Plat= form/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf index 020bde0d1f56..9bb14eafc5ed 100644 --- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf +++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf @@ -1,5 +1,5 @@ # -# Copyright (c) 2018 - 2023, Arm Limited. All rights reserved. +# Copyright (c) 2018 - 2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -36,6 +36,9 @@ [Sources.common] [Sources.AARCH64] AArch64/Helper.S | GCC =20 +[FeaturePcd] + gArmSgiTokenSpaceGuid.PcdPcieEnable + [FixedPcd] gArmPlatformTokenSpaceGuid.PcdClusterCount gArmPlatformTokenSpaceGuid.PcdCoreCount diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c b/Pla= tform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c index 62c212f3c5b0..72fb0b13e48c 100644 --- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c +++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c @@ -18,7 +18,8 @@ =20 // Total number of descriptors, including the final "end-of-table" descrip= tor. #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS = \ - ((14 + (FixedPcdGet32 (PcdChipCount) * 2)) + = \ + ((13 + (FixedPcdGet32 (PcdChipCount) * 2)) + = \ + (FeaturePcdGet (PcdPcieEnable)) + = \ (FixedPcdGet32 (PcdIoVirtSocExpBlkUartEnable) * = \ FixedPcdGet32 (PcdChipCount) * 2)) =20 @@ -263,13 +264,15 @@ ArmPlatformGetVirtualMemoryMap ( #endif #endif =20 - // PCI Configuration Space - VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdPciExpressBas= eAddress); - VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdPciExpressBas= eAddress); - VirtualMemoryTable[Index].Length =3D (FixedPcdGet32 (PcdPciBusM= ax) - - FixedPcdGet32 (PcdPciBusMin= ) + 1) * - SIZE_1MB; - VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + if (FeaturePcdGet (PcdPcieEnable)) { + // PCI Configuration Space + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdPciExpressB= aseAddress); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdPciExpressB= aseAddress); + VirtualMemoryTable[Index].Length =3D (FixedPcdGet32 (PcdPciBu= sMax) - + FixedPcdGet32 (PcdPciBusM= in) + 1) * + SIZE_1MB; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_DEVICE; + } =20 // MM Memory Space VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdMmBufferBase); --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113745): https://edk2.groups.io/g/devel/message/113745 Mute This Topic: https://groups.io/mt/103685115/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 11 13:34:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+113746+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113746+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1705074511; cv=none; d=zohomail.com; s=zohoarc; b=LoWU5DzrpfUfVZjTRyWkTda4S5GL3kUtYEKr6VpYDLii/IYPY5uvlE8iLNF3fJtOmf4sMQJAFrwojncb7gqyJOb1fsf1XbWjSJG+DLe99VDasg83PeWRhJ49k+qe2sKpsg+PvVonviBwgokta0ingQa/nykQ42OybzItio8gtes= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705074511; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=A4caGaRzX4ZUdRvG176OBjSMYm0WftFvA8+KeZCzP8c=; b=cYMyqQQIHUMRq9BWDrWgQybfP/B1IqPvVv6NHvxLK/QlmGvirnh6CagFdoLgAxUsjZkbHWiZ4Z0zhMT2WKOrndvEnEEPefi7MsKnTQN5mXWHESvjnTz3DvsBeSewgzfd34sOdDy/pew5MrBQcSt0QCbK6VAIdFaIKc873yxe0MA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113746+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1705074511903665.9254116900709; Fri, 12 Jan 2024 07:48:31 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=tt/pVbKi7PYsO9XWME7TYNSpz1T2FvKyZ8PRDj5I2Yg=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1705074511; v=1; b=cSUH4GM6r+UJ0FrY8bAjMHHk4HUwPTs/vijIulmwH0ZnHAF/kmJwnoLoxssvb7YB4VcqhUVA uuP/oJ1MvvMVvTwUkaWCteS3kufix7reDz7yzAvMBKq94Hl6UQDLsNghaaiOQi1tHJnfCxHDzrw dFbWfT3uPv8j1bFz1W2HCOg8= X-Received: by 127.0.0.2 with SMTP id 9eV9YY1788612xexWbcPdxGZ; Fri, 12 Jan 2024 07:48:31 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.10454.1705074510893487286 for ; Fri, 12 Jan 2024 07:48:31 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DE2591FB; Fri, 12 Jan 2024 07:49:16 -0800 (PST) X-Received: from usa.arm.com (a079755.arm.com [10.162.46.129]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id CB5B83F67D; Fri, 12 Jan 2024 07:48:28 -0800 (PST) From: "Prabin CA" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V2 4/8] Platform/Sgi: Add ACPI tables for RD-Fremont platform Date: Fri, 12 Jan 2024 21:17:55 +0530 Message-Id: <20240112154759.1222138-5-prabin.ca@arm.com> In-Reply-To: <20240112154759.1222138-1-prabin.ca@arm.com> References: <20240112154759.1222138-1-prabin.ca@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,prabin.ca@arm.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: Itah7KewP7Lss7CY7k2MjlURx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1705074512741100017 Content-Type: text/plain; charset="utf-8" From: Shriram K RD-Fremont is the next platform in the Arm's reference design platform series. This platform includes 32 CPUs but the fixed virtual platform (FVP) simulates 16 CPUs of the platform. There is one CPU per cluster in the system and so the FVP simulates 16 clusters. In preparation for adding support for this platform, add the initial set of ACPI tables and reuse existing ACPI tables as applicable to boot a operating system on this platform. Signed-off-by: Shriram K Signed-off-by: Prabin CA Reviewed-by: Pierre Gondois --- Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf | 73 ++++++++ Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl | 196 +++++++++++++= +++++++ Platform/ARM/SgiPkg/AcpiTables/RdFremont/Madt.aslc | 138 ++++++++++++++ Platform/ARM/SgiPkg/AcpiTables/RdFremont/Pptt.aslc | 167 +++++++++++++= ++++ 4 files changed, 574 insertions(+) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf b/Platf= orm/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf new file mode 100644 index 000000000000..9d07001dec96 --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf @@ -0,0 +1,73 @@ +## @file +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2024, Arm Ltd. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D RdFremontAcpiTables + FILE_GUID =3D c712719a-0aaf-438c-9cdd-35ab4d60207d = # gArmSgiAcpiTablesGuid + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + Dbg2.aslc + Fadt.aslc + Gtdt.aslc + RdFremont/Dsdt.asl + RdFremont/Madt.aslc + RdFremont/Pptt.aslc + Spcr.aslc + SsdtEvents.asl + SsdtRos.asl + SsdtRosVirtioP9.asl + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/ARM/SgiPkg/SgiPlatform.dec + +[FixedPcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + + gArmPlatformTokenSpaceGuid.PcdSerialDbgInterrupt + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase + gArmPlatformTokenSpaceGuid.PL011UartInterrupt + gArmPlatformTokenSpaceGuid.PcdCoreCount + gArmPlatformTokenSpaceGuid.PcdClusterCount + + gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress + gArmSgiTokenSpaceGuid.PcdGpioController0Size + gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt + gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv + gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv + gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress + gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize + gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt + gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress + gArmSgiTokenSpaceGuid.PcdVirtioBlkSize + gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt + gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress + gArmSgiTokenSpaceGuid.PcdVirtioNetSize + gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt + gArmSgiTokenSpaceGuid.PcdVirtioP9BaseAddress + gArmSgiTokenSpaceGuid.PcdVirtioP9Size + gArmSgiTokenSpaceGuid.PcdVirtioP9Interrupt + gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv + gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv + + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl b/Platform/A= RM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl new file mode 100644 index 000000000000..8812ea877f7a --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl @@ -0,0 +1,196 @@ +/** @file +* Differentiated System Description Table Fields (DSDT) +* +* Copyright (c) 2024, Arm Limited. All rights reserved.
+* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +* @par Specification Reference: +* - ACPI 6.5, Chapter 5, Section 5.2.11.1, Differentiated System Descrip= tion +* Table (DSDT) +* +**/ + +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" + +DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", + EFI_ACPI_ARM_OEM_REVISION) { + Scope (_SB) { + Device (CL00) { // Cluster 0 + Name (_HID, "ACPI0010") + Name (_UID, 0) + + Device (CP00) { // Neoverse Poseidon core 0 + Name (_HID, "ACPI0007") + Name (_UID, 0) + Name (_STA, 0xF) + } + } + + Device (CL01) { // Cluster 1 + Name (_HID, "ACPI0010") + Name (_UID, 1) + + Device (CP01) { // Neoverse Poseidon core 1 + Name (_HID, "ACPI0007") + Name (_UID, 1) + Name (_STA, 0xF) + } + } + + Device (CL02) { // Cluster 2 + Name (_HID, "ACPI0010") + Name (_UID, 2) + + Device (CP02) { // Neoverse Poseidon core 2 + Name (_HID, "ACPI0007") + Name (_UID, 2) + Name (_STA, 0xF) + } + } + + Device (CL03) { // Cluster 3 + Name (_HID, "ACPI0010") + Name (_UID, 3) + + Device (CP03) { // Neoverse Poseidon core 3 + Name (_HID, "ACPI0007") + Name (_UID, 3) + Name (_STA, 0xF) + } + } + + Device (CL04) { // Cluster 4 + Name (_HID, "ACPI0010") + Name (_UID, 4) + + Device (CP04) { // Neoverse Poseidon core 4 + Name (_HID, "ACPI0007") + Name (_UID, 4) + Name (_STA, 0xF) + } + } + + Device (CL05) { // Cluster 5 + Name (_HID, "ACPI0010") + Name (_UID, 5) + + Device (CP05) { // Neoverse Poseidon core 5 + Name (_HID, "ACPI0007") + Name (_UID, 5) + Name (_STA, 0xF) + } + } + + Device (CL06) { // Cluster 6 + Name (_HID, "ACPI0010") + Name (_UID, 6) + + Device (CP06) { // Neoverse Poseidon core 6 + Name (_HID, "ACPI0007") + Name (_UID, 6) + Name (_STA, 0xF) + } + } + + Device (CL07) { // Cluster 7 + Name (_HID, "ACPI0010") + Name (_UID, 7) + + Device (CP07) { // Neoverse Poseidon core 7 + Name (_HID, "ACPI0007") + Name (_UID, 7) + Name (_STA, 0xF) + } + } + + Device (CL08) { // Cluster 8 + Name (_HID, "ACPI0010") + Name (_UID, 8) + + Device (CP08) { // Neoverse Poseidon core 8 + Name (_HID, "ACPI0007") + Name (_UID, 8) + Name (_STA, 0xF) + } + } + + Device (CL09) { // Cluster 9 + Name (_HID, "ACPI0010") + Name (_UID, 9) + + Device (CP09) { // Neoverse Poseidon core 9 + Name (_HID, "ACPI0007") + Name (_UID, 9) + Name (_STA, 0xF) + } + } + + Device (CL10) { // Cluster 10 + Name (_HID, "ACPI0010") + Name (_UID, 10) + + Device (CP10) { // Neoverse Poseidon core 10 + Name (_HID, "ACPI0007") + Name (_UID, 10) + Name (_STA, 0xF) + } + } + + Device (CL11) { // Cluster 11 + Name (_HID, "ACPI0010") + Name (_UID, 11) + + Device (CP11) { // Neoverse Poseidon core 11 + Name (_HID, "ACPI0007") + Name (_UID, 11) + Name (_STA, 0xF) + } + } + + Device (CL12) { // Cluster 12 + Name (_HID, "ACPI0010") + Name (_UID, 12) + + Device (CP12) { // Neoverse Poseidon core 12 + Name (_HID, "ACPI0007") + Name (_UID, 12) + Name (_STA, 0xF) + } + } + + Device (CL13) { // Cluster 13 + Name (_HID, "ACPI0010") + Name (_UID, 13) + + Device (CP13) { // Neoverse Poseidon core 13 + Name (_HID, "ACPI0007") + Name (_UID, 13) + Name (_STA, 0xF) + } + } + + Device (CL14) { // Cluster 14 + Name (_HID, "ACPI0010") + Name (_UID, 14) + + Device (CP14) { // Neoverse Poseidon core 14 + Name (_HID, "ACPI0007") + Name (_UID, 14) + Name (_STA, 0xF) + } + } + + Device (CL15) { // Cluster 15 + Name (_HID, "ACPI0010") + Name (_UID, 15) + + Device (CP15) { // Neoverse Poseidon core 15 + Name (_HID, "ACPI0007") + Name (_UID, 15) + Name (_STA, 0xF) + } + } + } // Scope(_SB) +} diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Madt.aslc b/Platform/= ARM/SgiPkg/AcpiTables/RdFremont/Madt.aslc new file mode 100644 index 000000000000..e81ce86ae8fd --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Madt.aslc @@ -0,0 +1,138 @@ +/** @file +* Multiple APIC Description Table (MADT) +* +* Copyright (c) 2024, Arm Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include + +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" + +#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \ + FixedPcdGet32 (PcdCoreCount)) + +// Multiple APIC Description Table +#pragma pack (1) + +typedef struct { + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_4_GIC_STRUCTURE GicInterfaces[CORE= _CNT]; + EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor; + EFI_ACPI_6_4_GIC_ITS_STRUCTURE GicIts[6]; +} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE; + +#pragma pack () + +STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + ), + // MADT specific fields + 0, // LocalApicAddress + 0 // Flags + }, + { + // Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, = Flags, + // PmuIrq, GicBase, GicVBase, + // GicHBase, GsivId, GicRBase, + // Efficiency, + // SpeOverflowInterrupt) + // Note: The GIC Structure of the primary CPU must be the first entry + // (see note in 5.2.12.14 GICC Structure of ACPI v6.4). + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core0 + 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core1 + 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core2 + 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core3 + 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core4 + 0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core5 + 0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core6 + 0, 6, GET_MPID(0x600, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core7 + 0, 7, GET_MPID(0x700, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core8 + 0, 8, GET_MPID(0x800, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core9 + 0, 9, GET_MPID(0x900, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core10 + 0, 10, GET_MPID(0xa00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core11 + 0, 11, GET_MPID(0xb00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core12 + 0, 12, GET_MPID(0xc00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core13 + 0, 13, GET_MPID(0xd00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core14 + 0, 14, GET_MPID(0xe00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core15 + 0, 15, GET_MPID(0xf00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + }, + // GIC Distributor Entry + EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBas= e), + 0, 3), + // GIC Redistributor + EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsB= ase), + SIZE_16MB), + // GIC ITS + { + EFI_ACPI_6_4_GIC_ITS_INIT(0, 0x30040000), + EFI_ACPI_6_4_GIC_ITS_INIT(1, 0x30080000), + EFI_ACPI_6_4_GIC_ITS_INIT(2, 0x300C0000), + EFI_ACPI_6_4_GIC_ITS_INIT(3, 0x30100000), + EFI_ACPI_6_4_GIC_ITS_INIT(4, 0x30140000), + EFI_ACPI_6_4_GIC_ITS_INIT(5, 0x30180000), + }, +}; + +// +// Reference the table being generated to prevent the optimizer from remov= ing +// the data structure from the executable +// +VOID* CONST ReferenceAcpiTable =3D &Madt; diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Pptt.aslc b/Platform/= ARM/SgiPkg/AcpiTables/RdFremont/Pptt.aslc new file mode 100644 index 000000000000..28cb6d452479 --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Pptt.aslc @@ -0,0 +1,167 @@ +/** @file +* Processor Properties Topology Table (PPTT) for RD-Fremont platform +* +* Copyright (c) 2024, Arm Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +* This file describes the topological structure of the processor block on = the +* RD-Fremont platform in the form as defined by ACPI PPTT table. The RD-Fr= emont +* platform includes sixteen single-thread CPUs. Each of the CPUs include 6= 4KB +* L1 Data cache, 64KB L1 Instruction cache and 2MB L2 cache. +* +* @par Specification Reference: +* - ACPI 6.4, Chapter 5, Section 5.2.29, Processor Properties Topology T= able +**/ + +#include +#include +#include +#include + +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" + +/** Define helper macro for populating processor core information. + + @param [in] PackageId Package instance number. + @param [in] ClusterId Cluster instance number. + @param [in] CpuId CPU instance number. +**/ +#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) = \ + { = \ + /* Parameters for CPU Core */ = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ = \ + PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[ClusterId]), /* Parent */ = \ + ((PackageId << 4) | ClusterId), /* ACPI Id */ = \ + 2 /* Num of private resource */ = \ + ), = \ + = \ + /* Offsets of the private resources */ = \ + { = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[ClusterId].Core[CpuId].DCache), = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[ClusterId].Core[CpuId].ICache) = \ + }, = \ + = \ + /* L1 data cache parameters */ = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[ClusterId].Core[CpuId].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ + 64, /* Line size */ = \ + RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1DataCache) = \ + /* Cache id */ = \ + ), = \ + = \ + /* L1 instruction cache parameters */ = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package.Cluster[ClusterId].Core[CpuId].L2Cache), = \ + /* Next level of cache */ = \ + SIZE_64KB, /* Size */ = \ + 256, /* Num of sets */ = \ + 4, /* Associativity */ = \ + PPTT_INST_CACHE_ATTR, /* Attributes */ = \ + 64, /* Line size */ = \ + RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1InstructionCache) = \ + /* Cache id */ = \ + ), = \ + = \ + /* L2 cache parameters */ = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ + 0, /* Next level of cache */ = \ + SIZE_2MB, /* Size */ = \ + 4096, /* Num of sets */ = \ + 8, /* Associativity */ = \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ + 64, /* Line size */ = \ + RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L2Cache) = \ + /* Cache id */ = \ + ), = \ + } + +/** Define helper macro for populating processor container information. + + @param [in] PackageId Package instance number. + @param [in] ClusterId Cluster instance number. +**/ +#define PPTT_CLUSTER_INIT(PackageId, ClusterId) = \ + { = \ + /* Parameters for Cluster */ = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ = \ + PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + Package), /* Parent */ = \ + ((PackageId << 4) | ClusterId), /* ACPI Id */ = \ + 0 /* Num of private resource */ = \ + ), = \ + = \ + /* Initialize child core */ = \ + { = \ + PPTT_CORE_INIT (PackageId, ClusterId, 0) = \ + } = \ + } + +#pragma pack(1) +/* + * Processor Properties Topology Table + */ +typedef struct { + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + RD_PPTT_PACKAGE Package; +} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +#pragma pack () + +STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + ) + }, + + { + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( + OFFSET_OF (RD_PPTT_PACKAGE, Cluster[0]), + PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0), + + { + PPTT_CLUSTER_INIT (0, 0), + PPTT_CLUSTER_INIT (0, 1), + PPTT_CLUSTER_INIT (0, 2), + PPTT_CLUSTER_INIT (0, 3), + PPTT_CLUSTER_INIT (0, 4), + PPTT_CLUSTER_INIT (0, 5), + PPTT_CLUSTER_INIT (0, 6), + PPTT_CLUSTER_INIT (0, 7), + PPTT_CLUSTER_INIT (0, 8), + PPTT_CLUSTER_INIT (0, 9), + PPTT_CLUSTER_INIT (0, 10), + PPTT_CLUSTER_INIT (0, 11), + PPTT_CLUSTER_INIT (0, 12), + PPTT_CLUSTER_INIT (0, 13), + PPTT_CLUSTER_INIT (0, 14), + PPTT_CLUSTER_INIT (0, 15) + } + } +}; + +/* + * Reference the table being generated to prevent the optimizer from remov= ing + * the data structure from the executable + */ +VOID* CONST ReferenceAcpiTable =3D &Pptt; --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113746): https://edk2.groups.io/g/devel/message/113746 Mute This Topic: https://groups.io/mt/103685116/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 11 13:34:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+113747+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113747+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1705074513; cv=none; d=zohomail.com; s=zohoarc; b=VUY7g84lCHW1S1teyIH+gMNbslPOZNjd4HxRskC+IAk2mVQyhArJPgqVHoJulhquPFqxhMzCxGvbsAcYruBjGl+yMmssKSME6ObzWKO61TSKmWchWlwe2X8KdaNlvGLOTmC5TLSALFiBEY1v8yP7MqHdBFiQ8wctmtjtdtxT9mQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705074513; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=77trppmj1OxjGUnl/7ugZ3YOyi0iXcQyp/puLzKa370=; b=eVEUtdF+mUqoar4X6sUf/8d4oPf9oL4RvVmL05Obh4yStiHQhT7He0HSfkg+Y2Qh7cAw2ysqOAuSElsZfDBYPGf3yCcPFfP3LWbnpgf7A+c7b7ZUe/iwe17jTgzbovUofF8ZRjpKPfv/1j7cWR4x6qUb+qT/kZRNgcs4HLQkRnA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113747+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1705074513666714.155268794944; Fri, 12 Jan 2024 07:48:33 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=B4rqAy8u2Ix4vcfVWNSXyl/PiUdFggmlrFEmZfrer28=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1705074513; v=1; b=KIptFd5dFyBUdtiKSb6W52AtZ+7W/4I6qIqzohd3ngh2snQ2tq8LEP7+gFF/1hYR9giZ8BWF R/G/EPXbkDbLAwZZ/piScGDIqZqfcEwGQ2448ZQw7Tci59dcOf4Hq5V6HKVDcxMjbiOSlDMuCYM k5WCAlf8AMtsvbzCXKO1EwIs= X-Received: by 127.0.0.2 with SMTP id TSg6YY1788612xt63Ahb6p24; Fri, 12 Jan 2024 07:48:33 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.10457.1705074512812689545 for ; Fri, 12 Jan 2024 07:48:32 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D60862F4; Fri, 12 Jan 2024 07:49:18 -0800 (PST) X-Received: from usa.arm.com (a079755.arm.com [10.162.46.129]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0C60D3F67D; Fri, 12 Jan 2024 07:48:30 -0800 (PST) From: "Prabin CA" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V2 5/8] Platform/Sgi: Add initial support for RD-Fremont platform Date: Fri, 12 Jan 2024 21:17:56 +0530 Message-Id: <20240112154759.1222138-6-prabin.ca@arm.com> In-Reply-To: <20240112154759.1222138-1-prabin.ca@arm.com> References: <20240112154759.1222138-1-prabin.ca@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,prabin.ca@arm.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: diyNheptLvDLcnjamC6pQMIDx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1705074514762100021 Content-Type: text/plain; charset="utf-8" The RD-Fremont fixed virtual platform simulates 16 CPUs and 8GB of RAM. Add initial support for this platform by adding the required platform build configuration files. This platform has considerable differences in its memory map compared to its predecessors. So add a corresponding memory map file as well to define the PCDs for its generation of platforms. Signed-off-by: Prabin CA Reviewed-by: Pierre Gondois --- Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc | 71 ++++++++++++++++++++ Platform/ARM/SgiPkg/RdFremont/RdFremont.dsc | 55 +++++++++++++++ Platform/ARM/SgiPkg/RdFremont/RdFremont.fdf.inc | 10 +++ 3 files changed, 136 insertions(+) diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc b/Platform/ARM/SgiPk= g/SgiMemoryMap3.dsc.inc new file mode 100644 index 000000000000..06c3b37388c1 --- /dev/null +++ b/Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc @@ -0,0 +1,71 @@ +# +# Copyright (c) 2024, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[PcdsFixedAtBuild.common] + # System Peripherals + gArmSgiTokenSpaceGuid.PcdSmcCs0Base|0x08000000 + gArmSgiTokenSpaceGuid.PcdSmcCs1Base|0x0600000000 + gArmSgiTokenSpaceGuid.PcdSysPeriphBase|0x0C000000 + gArmSgiTokenSpaceGuid.PcdSysPeriphSysRegBase|0x0C010000 + + # SP804 dual timer + gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress|0x0C110000 + gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize|0x00010000 + gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt|216 + + # Virtio Disk + gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress|0x0C130000 + gArmSgiTokenSpaceGuid.PcdVirtioBlkSize|0x10000 + gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt|184 + + # GPIO controller + gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress|0x0C1D0000 + gArmSgiTokenSpaceGuid.PcdGpioController0Size|0x00010000 + gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt|168 + + # Ethernet + gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress|0x0C150000 + gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt|186 + + # PL031 RealTimeClock + gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0C170000 + + # Virtio P9 + gArmSgiTokenSpaceGuid.PcdVirtioP9BaseAddress|0x0C190000 + gArmSgiTokenSpaceGuid.PcdVirtioP9Size|0x10000 + gArmSgiTokenSpaceGuid.PcdVirtioP9Interrupt|185 + + # PL370 - HDLCD1 + gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0EF60000 + + # PL011 - Serial Debug UART + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x0EF70000 + gArmPlatformTokenSpaceGuid.PcdSerialDbgInterrupt|179 + + # PL011 - Serial Terminal + gArmPlatformTokenSpaceGuid.PL011UartInterrupt|112 + + # System Memory (2GB - 128MB of Trusted DRAM at the top of the 32bit add= ress space) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x78000000 + + # SMMU + gArmSgiTokenSpaceGuid.PcdSmmuBase|0x280000000 + gArmSgiTokenSpaceGuid.PcdSmmuSize|0x4000000 + + # Non-Volatile variable storage + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x0600000= 000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x06014= 00000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x0602800= 000 + + # Address bus width - 64TB address space + gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip|46 + + # Timer & Watchdog interrupts + gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv|109 + gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv|108 + gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv|110 + gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv|111 diff --git a/Platform/ARM/SgiPkg/RdFremont/RdFremont.dsc b/Platform/ARM/Sgi= Pkg/RdFremont/RdFremont.dsc new file mode 100644 index 000000000000..b52d2f59e15d --- /dev/null +++ b/Platform/ARM/SgiPkg/RdFremont/RdFremont.dsc @@ -0,0 +1,55 @@ +# +# Copyright (c) 2024, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + PLATFORM_NAME =3D RdFremont + PLATFORM_GUID =3D fd140b0f-4467-4314-aa69-cd0bd712e08e + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x0001001B + OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES =3D AARCH64 + BUILD_TARGETS =3D NOOPT|DEBUG|RELEASE + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D Platform/ARM/SgiPkg/SgiPlatform.fdf + BOARD_DXE_FV_COMPONENTS =3D Platform/ARM/SgiPkg/RdFremont/RdFremo= nt.fdf.inc + BUILD_NUMBER =3D 1 + +# include common definitions from SgiPlatform.dsc +!include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc +!include Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc + +# include common/basic libraries from MdePkg. +!include MdePkg/MdeLibs.dsc.inc + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### + +[PcdsFixedAtBuild.common] + # GIC Base Addresses + gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x301C0000 + gArmSgiTokenSpaceGuid.PcdGicSize|0x200000 + + # ARM Cores and Clusters + gArmPlatformTokenSpaceGuid.PcdCoreCount|1 + gArmPlatformTokenSpaceGuid.PcdClusterCount|16 + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform +# +##########################################################################= ###### + +[Components.common] + Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf diff --git a/Platform/ARM/SgiPkg/RdFremont/RdFremont.fdf.inc b/Platform/ARM= /SgiPkg/RdFremont/RdFremont.fdf.inc new file mode 100644 index 000000000000..a465b7426653 --- /dev/null +++ b/Platform/ARM/SgiPkg/RdFremont/RdFremont.fdf.inc @@ -0,0 +1,10 @@ +# +# Copyright (c) 2024, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +# Per-platform additional content of the DXE phase firmware volume + + # ACPI support + INF RuleOverride=3DACPITABLE Platform/ARM/SgiPkg/AcpiTables/RdFremontAcp= iTables.inf --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113747): https://edk2.groups.io/g/devel/message/113747 Mute This Topic: https://groups.io/mt/103685117/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 11 13:34:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+113748+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113748+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1705074515; cv=none; d=zohomail.com; s=zohoarc; b=W12PdOMd/AU1DZsNuG6C/pK/9/UdsfEDmhv43tJEDYCTkdiOwC2VlmympXGW8qYQpDxO1xrMQ/GnV2PPIoV4g2s2vxrGDuQ4o1APuCQV971JXDi6+4AUh7P3NO71TYW4rwuFnXyj8HKMnaqEEb+zQ8xXvXX7InkqrS/pCh+/cW0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705074515; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=WlaZt6i0/sUE/lfxw6wlzoaJ5eD30b81UbDJx30C+fQ=; b=fSGZzatwTG801JWZFR9jxEr2WWdkaPLo15IRQJ2cR0I7+578lla7/gdlml4Ou+ZzG/tl2Em4yVvE+r2XiDHCRGjTW7odMSSztWMI8QEbjiSkVKZbmuhKkveZMIbWf8VZuS6HhoO2Oi1+OnmdNLdzQZ1bR62qMrRd6iYPUaWUr2g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113748+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1705074515782393.74586982676; Fri, 12 Jan 2024 07:48:35 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=hAQLXVMcCXRCCFMHipzPJ6L+p5pxBbsqk0CsqEnzSYw=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1705074515; v=1; b=Q5rtJenum+ArDp+b/UT3LFWY58koajxHaAILZKW8l1qKwGW8tvvTEBKJcDpojklxLiY86sXP IF46venkDyAk9T6gE9X0R63WfstAOfCtANKY5+gZ8p546P65BHySE/ILvG7vGSruJ3+5oEP+X29 Yn/db6PJhGFpFXQxF/kVCeVM= X-Received: by 127.0.0.2 with SMTP id SdMJYY1788612x3QEzXxeVhN; Fri, 12 Jan 2024 07:48:35 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.10461.1705074514815417098 for ; Fri, 12 Jan 2024 07:48:34 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CE40E1FB; Fri, 12 Jan 2024 07:49:20 -0800 (PST) X-Received: from usa.arm.com (a079755.arm.com [10.162.46.129]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 044A03F67D; Fri, 12 Jan 2024 07:48:32 -0800 (PST) From: "Prabin CA" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V2 6/8] Platform/Sgi: Extend SMBIOS support for RD-Fremont Date: Fri, 12 Jan 2024 21:17:57 +0530 Message-Id: <20240112154759.1222138-7-prabin.ca@arm.com> In-Reply-To: <20240112154759.1222138-1-prabin.ca@arm.com> References: <20240112154759.1222138-1-prabin.ca@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,prabin.ca@arm.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: oFxtrV12k2uLbWdPQQKcM4P6x1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1705074516735100025 Content-Type: text/plain; charset="utf-8" Extend the SMBIOS support for RD-Fremont platform. RD-Fremont is a 16 core platform with Poseidon CPU. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 2MB L2 cache. The platform also includes system level cache of 32MB and 8GB of RAM. Signed-off-by: Prabin CA Reviewed-by: Pierre Gondois --- Platform/ARM/SgiPkg/Include/SgiPlatform.h = | 5 +++++ Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c = | 5 ++++- Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c = | 5 ++++- Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c = | 1 + Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c = | 6 ++++++ 5 files changed, 20 insertions(+), 2 deletions(-) diff --git a/Platform/ARM/SgiPkg/Include/SgiPlatform.h b/Platform/ARM/SgiPk= g/Include/SgiPlatform.h index 6fa39d407bc9..acfa45910aed 100644 --- a/Platform/ARM/SgiPkg/Include/SgiPlatform.h +++ b/Platform/ARM/SgiPkg/Include/SgiPlatform.h @@ -51,6 +51,10 @@ #define RD_V2_PART_NUM 0x7F2 #define RD_V2_CONF_ID 0x1 =20 +// RD-Fremont Platform Identification values +#define RD_Fremont_PART_NUM 0x7EE +#define RD_Fremont_CONF_ID 0x1 + #define SGI_CONFIG_MASK 0x0F #define SGI_CONFIG_SHIFT 0x1C #define SGI_PART_NUM_MASK 0xFFF @@ -90,6 +94,7 @@ typedef enum { RdN2Cfg1, RdN2Cfg2, RdV2, + RdFremont, } ARM_RD_PRODUCT_ID; =20 // Arm ProductId look-up table diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInfor= mation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInforma= tion.c index edf2a5f63c63..9c28b051ebc2 100644 --- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c +++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c @@ -34,7 +34,8 @@ "RdN2\0" \ "RdN2Cfg1\0" \ "RdN2Cfg2\0" \ - "RdV2\0" + "RdV2\0" \ + "RdFremont\0" =20 typedef enum { ManufacturerName =3D 1, @@ -74,6 +75,8 @@ STATIC GUID mSmbiosUid[] =3D { {0xd2946d07, 0x8057, 0x4c26, {0xbf, 0x53, 0x78, 0xa6, 0x5b, 0xe1, 0xc1, = 0x60}}, /* Rd-V2 */ {0x3b1180a3, 0x0744, 0x4194, {0xae, 0x2e, 0xed, 0xa5, 0xbc, 0x2e, 0x43, = 0x45}}, + /* Rd-Fremont */ + {0x904b28d6, 0x0662, 0x11ed, {0xb9, 0x39, 0x02, 0x42, 0xac, 0x12, 0x00, = 0x02}}, }; =20 /* System information */ diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorIn= formation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorI= nformation.c index ee269f707714..c39c1553f6aa 100644 --- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformati= on.c +++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformati= on.c @@ -44,6 +44,7 @@ "Neoverse-N2\0" \ "Neoverse-N2\0" \ "Neoverse-V2\0" \ + "Neoverse-Poseidon\0" \ "000-0\0" /* Serial number */ \ "783-3\0" \ "786-1\0" \ @@ -54,7 +55,8 @@ "7B7-1\0" \ "7B6-1\0" \ "7B7-1\0" \ - "7F2-1\0" + "7F2-1\0" \ + "7EE-1\0" =20 typedef enum { PartNumber =3D 1, @@ -181,6 +183,7 @@ InstallType4ProcessorInformation ( case RdN2: case RdN2Cfg1: case RdV2: + case RdFremont: mArmRdSmbiosType4.Base.CoreCount =3D CoreCount; mArmRdSmbiosType4.Base.EnabledCoreCount =3D CoreCount; mArmRdSmbiosType4.Base.ThreadCount =3D CoreCount; diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInform= ation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformati= on.c index 4af72919a3f1..4cdea5b3b763 100644 --- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c +++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c @@ -335,6 +335,7 @@ InstallType7CacheInformation ( mArmRdSmbiosType7[4].Base.Associativity =3D CacheAssociativity16Way; break; case RdV2: + case RdFremont: /* L1 instruction cache */ mArmRdSmbiosType7[0].Base.MaximumCacheSize2 =3D 64; // 64KB mArmRdSmbiosType7[0].Base.InstalledSize2 =3D 64; // 64KB diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c b/Platfo= rm/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c index 14b06796ae9c..ae31be142d12 100644 --- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c +++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c @@ -85,6 +85,12 @@ STATIC CONST SGI_PRODUCT_ID_LOOKUP SgiProductIdLookup[] = =3D { RD_V2_CONF_ID, 0 }, + { + RdFremont, + RD_Fremont_PART_NUM, + RD_Fremont_CONF_ID, + 0 + }, }; =20 EFI_BOOT_MODE --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113748): https://edk2.groups.io/g/devel/message/113748 Mute This Topic: https://groups.io/mt/103685120/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 11 13:34:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+113749+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113749+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1705074517; cv=none; d=zohomail.com; s=zohoarc; b=LwJt8K0AyvMhqkymIfF3V1Y7Tvalco7cB0sc3h+XVr/FWug8aDcBCUOhhTA9GERSlNFf0FIjLg0lQ3gjpV1x3kV7/5GTC47QK9J9GElg8DBhkfNJgdLGmV8ZJwjIw69LvcFpEKw/O/Ozb2u+W0g1M05E7Kr7+cn6XcQgYpTRKRE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705074517; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=iop7PMgQKbB0qOSDZSZHmjn2S+PDNeVfRssvpGG0kyI=; b=NV6mCCjPYSnJEbXXqCdKFAOUJm6YtE6HgB/mLpGQqjRRA4zlg7abLJv6qtiCZmIxsBEIsVkBoDLQ1aLqWtTqrxsbQNYD++PQUc/3Rt1llHg3zdUfNzh4kQW391dUXSsmfif0Xn1JPln4lRxYL/t8Tld1Xxp48RX2Q/N0CX00acU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113749+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1705074517683469.49805770233854; Fri, 12 Jan 2024 07:48:37 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=OexaanEY20Prx+e1Xlk5+2DKqD3OwsAx3AYu2Vvi21Q=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1705074517; v=1; b=jW6qY5FXQ36UNLRaOqPSwmXg5xoXA8mOwKh/ovG4dgD8aX6CVWfz3Z+GXhatl3dJyFgO33Qq p0iW7FZfSzc8muxqIc3O0o2cS33R0IrrVzk682jAJ/0yHV0HqaDFVdj4h2mksGaaJLJxPkvH8GM bS/BMKk+A5L1OLhr6l2sJuOc= X-Received: by 127.0.0.2 with SMTP id HvkQYY1788612xhm3hfJzrwy; Fri, 12 Jan 2024 07:48:37 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.10464.1705074516744921096 for ; Fri, 12 Jan 2024 07:48:36 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C62521FB; Fri, 12 Jan 2024 07:49:22 -0800 (PST) X-Received: from usa.arm.com (a079755.arm.com [10.162.46.129]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id F0A123F67D; Fri, 12 Jan 2024 07:48:34 -0800 (PST) From: "Prabin CA" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V2 7/8] Platform/Sgi: Low Power Idle States for RD-Fremont Date: Fri, 12 Jan 2024 21:17:58 +0530 Message-Id: <20240112154759.1222138-8-prabin.ca@arm.com> In-Reply-To: <20240112154759.1222138-1-prabin.ca@arm.com> References: <20240112154759.1222138-1-prabin.ca@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,prabin.ca@arm.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: X9D7eIsP3RCO225LGFjQcERix1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1705074518769100029 Content-Type: text/plain; charset="utf-8" RD-Fremont platform supports two LPI states, LPI1 (Standby WFI) and LPI3 (Power-down). The cluster supports LPI2 (Power-down) state. The LPI implementation also supports combined power state for core and cluster. Signed-off-by: Prabin CA Reviewed-by: Pierre Gondois --- Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf | 1 + Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl | 154 +++++++++++++= +++++++ 2 files changed, 155 insertions(+) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf b/Platf= orm/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf index 9d07001dec96..7556c1239116 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf @@ -48,6 +48,7 @@ [FixedPcd] gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv + gArmSgiTokenSpaceGuid.PcdOscLpiEnable gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl b/Platform/A= RM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl index 8812ea877f7a..f921eeb2d99e 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl +++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl @@ -8,6 +8,9 @@ * @par Specification Reference: * - ACPI 6.5, Chapter 5, Section 5.2.11.1, Differentiated System Descrip= tion * Table (DSDT) +* - ACPI 6.5, Chapter 8, Section 8.4.3, Lower Power Idle States +* - Arm Functional Fixed Hardware Specification v1.2, Chapter 3, Section= 3.1, +* Idle management and Low Power Idle states * **/ =20 @@ -17,6 +20,93 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", EFI_ACPI_ARM_OEM_REVISION) { Scope (_SB) { + /* _OSC: Operating System Capabilities */ + Method (_OSC, 4, Serialized) { + CreateDWordField (Arg3, 0x00, STS0) + CreateDWordField (Arg3, 0x04, CAP0) + + /* Platform-wide Capabilities */ + If (LEqual (Arg0, ToUUID("0811b06e-4a27-44f9-8d60-3cbbc22e7b48"))) { + /* OSC rev 1 supported, for other version, return failure */ + If (LEqual (Arg1, One)) { + And (STS0, Not (OSC_STS_MASK), STS0) + + If (And (CAP0, OSC_CAP_OS_INITIATED_LPI)) { + /* OS initiated LPI not supported */ + And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0) + Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0) + } + + If (And (CAP0, OSC_CAP_PLAT_COORDINATED_LPI)) { + if (LEqual (FixedPcdGet32 (PcdOscLpiEnable), Zero)) { + And (CAP0, Not (OSC_CAP_PLAT_COORDINATED_LPI), CAP0) + Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0) + } + } + } Else { + And (STS0, Not (OSC_STS_MASK), STS0) + Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0) + } + } Else { + And (STS0, Not (OSC_STS_MASK), STS0) + Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_UUID), STS0) + } + + Return (Arg3) + } + + Name (PLPI, Package () { /* LPI for Processor, support 2 LPI states */ + 0, // Version + 0, // Level Index + 2, // Count + Package () { // WFI for CPU + 1, // Min residency (uS) + 1, // Wake latency (uS) + 1, // Flags + 0, // Arch Context lost Flags (no loss) + 0, // Residency Counter Frequency + 0, // No parent state + ResourceTemplate () { // Register Entry method + Register (FFixedHW, + 32, // Bit Width + 0, // Bit Offset + 0xFFFFFFFF, // Address + 3, // Access Size + ) + }, + ResourceTemplate () { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate () { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "LPI1-Core" + }, + Package () { // Power Gating state for CPU + 150, // Min residency (uS) + 350, // Wake latency (uS) + 1, // Flags + 1, // Arch Context lost Flags (Core context los= t) + 0, // Residency Counter Frequency + 0, // No parent state + ResourceTemplate () { // Register Entry method + Register (FFixedHW, + 32, // Bit Width + 0, // Bit Offset + 0x40000002, // Address (PwrLvl:core, StateTyp:PwrDn) + 3, // Access Size + ) + }, + ResourceTemplate () { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate () { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "LPI3-Core" + }, + }) + Device (CL00) { // Cluster 0 Name (_HID, "ACPI0010") Name (_UID, 0) @@ -25,6 +115,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", = "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 0) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } =20 @@ -36,6 +130,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", = "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 1) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } =20 @@ -47,6 +145,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", = "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 2) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } =20 @@ -58,6 +160,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", = "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 3) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } =20 @@ -69,6 +175,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", = "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 4) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } =20 @@ -80,6 +190,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", = "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 5) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } =20 @@ -91,6 +205,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", = "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 6) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } =20 @@ -102,6 +220,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",= "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 7) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } =20 @@ -113,6 +235,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",= "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 8) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } =20 @@ -124,6 +250,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",= "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 9) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } =20 @@ -135,6 +265,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",= "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 10) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } =20 @@ -146,6 +280,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",= "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 11) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } =20 @@ -157,6 +295,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",= "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 12) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } =20 @@ -168,6 +310,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",= "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 13) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } =20 @@ -179,6 +325,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",= "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 14) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } =20 @@ -190,6 +340,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",= "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 15) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } } // Scope(_SB) --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113749): https://edk2.groups.io/g/devel/message/113749 Mute This Topic: https://groups.io/mt/103685122/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 11 13:34:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+113750+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113750+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1705074519; cv=none; d=zohomail.com; s=zohoarc; b=kwSXFr5U8Ew2lg1rVwANdC+mVTu2du0MeFaXLeZp6gv49krMpzN6QYbsCD9a+6VYFsX0tKmR2jSYx4j4nCfXZ1kSpFU98FAPiitvTOtNSTHdZpUZG08481cjL/XCLo5VqN07iPcqpJZr/tD1+5sbhZgXoU5d72MV9lkSgYwrfXs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705074519; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=MjNu2q056onqhJmfiMUGbPv9FRyYbfXkzJ3icF3VncM=; b=LvMOrZpwyrNbimpJJTLRViQRk0vwJxXbfSUnk+nLVJlg80dHjRfntyqIVvSB41z0Um1qJddQmyMScxaVOfkh5ezZOADcrrv1Krf1h/8/uuQsRNDLRYir8jlR+N6v5Ue4O4mHWaL9RhBEG3BOId19M26ImeqlNzAAGwlqoXeWSQY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113750+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1705074519614797.0178085254443; Fri, 12 Jan 2024 07:48:39 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=mIdjqIswn47nr8jfpbWhRWF2wGgexUtuyJWVaQqbBeg=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1705074519; v=1; b=KTSd28nDt3pEBCusKZHmNGXx6GYxPFz7vlFzGqsqHwk/i0Jy7TsGCj47Y4OjiiIQ7rhbGJva OKZHUMCywOuActaZv44WxlJoS0lAksptuzi+jvh+tvvkbUiBJfzSqrZNqT9aou81MixhNKZOXjt DgOPMIcJvIdDZJSsiqcM4qOc= X-Received: by 127.0.0.2 with SMTP id iK0rYY1788612xsPi5znCnX4; Fri, 12 Jan 2024 07:48:39 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.10467.1705074518716211820 for ; Fri, 12 Jan 2024 07:48:38 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BE6DA2F4; Fri, 12 Jan 2024 07:49:24 -0800 (PST) X-Received: from usa.arm.com (a079755.arm.com [10.162.46.129]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E88643F67D; Fri, 12 Jan 2024 07:48:36 -0800 (PST) From: "Prabin CA" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V2 8/8] Platform/Sgi: Add CPPC support for RD-Fremont platform Date: Fri, 12 Jan 2024 21:17:59 +0530 Message-Id: <20240112154759.1222138-9-prabin.ca@arm.com> In-Reply-To: <20240112154759.1222138-1-prabin.ca@arm.com> References: <20240112154759.1222138-1-prabin.ca@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,prabin.ca@arm.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: xJGiupI1YvxfoubbFXo4d2gjx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1705074520788100033 Content-Type: text/plain; charset="utf-8" Enable ACPI CPPC mechanism for RD-Fremont as defined by the ACPI specification. The implementation uses AMU registers accessible as Fixed-feature Hardware (FFixedHW) for monitoring the performance. Non-secure SCMI fastchannels are used to communicate with LCP to set the desired performance. RD-Fremont platform does not support CPPC revision 1 and below. So update the _OSC method to let OSPM know about this fact. Signed-off-by: Prabin CA Reviewed-by: Pierre Gondois --- Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf | 1 + Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl | 162 +++++++++++++= +++++++ 2 files changed, 163 insertions(+) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf b/Platf= orm/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf index 7556c1239116..fcaa3299c4ea 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf @@ -48,6 +48,7 @@ [FixedPcd] gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv + gArmSgiTokenSpaceGuid.PcdOscCppcEnable gArmSgiTokenSpaceGuid.PcdOscLpiEnable gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl b/Platform/A= RM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl index f921eeb2d99e..b9aca8477ca4 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl +++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl @@ -11,6 +11,10 @@ * - ACPI 6.5, Chapter 8, Section 8.4.3, Lower Power Idle States * - Arm Functional Fixed Hardware Specification v1.2, Chapter 3, Section= 3.1, * Idle management and Low Power Idle states +* - ACPI 6.5, Chapter 8, Section 8.4.6, Collaborative Processor Performa= nce +* Control +* - Arm Functional Fixed Hardware Specification v1.2, Chapter 3, Section= 3.2, +* Performance management and Collaborative Processor Performance Contr= ol * **/ =20 @@ -43,6 +47,20 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "= ARMSGI", Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0) } } + + If (And (CAP0, OSC_CAP_CPPC_SUPPORT)) { + /* CPPC revision 1 and below not supported */ + And (CAP0, Not (OSC_CAP_CPPC_SUPPORT), CAP0) + Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0) + } + + If (And (CAP0, OSC_CAP_CPPC2_SUPPORT)) { + if (LEqual (FixedPcdGet32 (PcdOscCppcEnable), Zero)) { + And (CAP0, Not (OSC_CAP_CPPC2_SUPPORT), CAP0) + Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0) + } + } + } Else { And (STS0, Not (OSC_STS_MASK), STS0) Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0) @@ -116,6 +134,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",= "ARMSGI", Name (_UID, 0) Name (_STA, 0xF) =20 + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x200093000, 0x200093004, 20, 160, 160, 85, 8= 5, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (0) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -131,6 +158,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",= "ARMSGI", Name (_UID, 1) Name (_STA, 0xF) =20 + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x200293000, 0x200293004, 20, 160, 160, 85, 8= 5, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (1) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -146,6 +182,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",= "ARMSGI", Name (_UID, 2) Name (_STA, 0xF) =20 + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x200493000, 0x200493004, 20, 160, 160, 85, 8= 5, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (2) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -161,6 +206,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",= "ARMSGI", Name (_UID, 3) Name (_STA, 0xF) =20 + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x200693000, 0x200693004, 20, 160, 160, 85, 8= 5, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (3) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -176,6 +230,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",= "ARMSGI", Name (_UID, 4) Name (_STA, 0xF) =20 + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x200893000, 0x200893004, 20, 160, 160, 85, 8= 5, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (4) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -191,6 +254,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",= "ARMSGI", Name (_UID, 5) Name (_STA, 0xF) =20 + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x200A93000, 0x200A93004, 20, 160, 160, 85, 8= 5, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (5) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -206,6 +278,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",= "ARMSGI", Name (_UID, 6) Name (_STA, 0xF) =20 + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x200C93000, 0x200C93004, 20, 160, 160, 85, 8= 5, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (6) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -221,6 +302,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",= "ARMSGI", Name (_UID, 7) Name (_STA, 0xF) =20 + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x200E93000, 0x200E93004, 20, 160, 160, 85, 8= 5, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (7) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -236,6 +326,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",= "ARMSGI", Name (_UID, 8) Name (_STA, 0xF) =20 + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x201093000, 0x201093004, 20, 160, 160, 85, 8= 5, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (8) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -251,6 +350,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",= "ARMSGI", Name (_UID, 9) Name (_STA, 0xF) =20 + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x201293000, 0x201293004, 20, 160, 160, 85, 8= 5, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (9) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -266,6 +374,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",= "ARMSGI", Name (_UID, 10) Name (_STA, 0xF) =20 + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x201493000, 0x201493004, 20, 160, 160, 85, 8= 5, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (10) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -281,6 +398,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",= "ARMSGI", Name (_UID, 11) Name (_STA, 0xF) =20 + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x201693000, 0x201693004, 20, 160, 160, 85, 8= 5, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (11) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -296,6 +422,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",= "ARMSGI", Name (_UID, 12) Name (_STA, 0xF) =20 + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x201893000, 0x201893004, 20, 160, 160, 85, 8= 5, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (12) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -311,6 +446,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",= "ARMSGI", Name (_UID, 13) Name (_STA, 0xF) =20 + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x201A93000, 0x201A93004, 20, 160, 160, 85, 8= 5, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (13) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -326,6 +470,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",= "ARMSGI", Name (_UID, 14) Name (_STA, 0xF) =20 + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x201C93000, 0x201C93004, 20, 160, 160, 85, 8= 5, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (14) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -341,6 +494,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",= "ARMSGI", Name (_UID, 15) Name (_STA, 0xF) =20 + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x201E93000, 0x201E93004, 20, 160, 160, 85, 8= 5, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (15) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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