From nobody Fri May 17 03:12:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+113692+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113692+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1705048316; cv=none; d=zohomail.com; s=zohoarc; b=ZutqWnWIj3Zc04fX/5o24l7gFtZXzq40GBXAqUMxNfmQDHqUAgihzeO6mnsH0Xj/Yp10R9oKMmyoq6klVrI5ARUE4OkEi42qt4n7hZOA+tTJNbLdWRyM/v0tJ+laM/JVu2+c06BtE3M4V+x5GvwGLnB7jrGPNe9lspo5mnCGrSc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705048316; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:Sender:Subject:Subject:To:To:Message-Id; bh=GbySN/+tQBIXQSXDNjfysMcrKtCEigsIRgdpH2tQ4K8=; b=nERJuF3MQbHeAI9pbvgn2Jw0O18WLTphyvaV+e+Iz3AlNwEgURaHfzXXXqSrxS25cOwsSbYQbcB5TGSUIJNcbhSiLNUdRfg0E+kBnDhjwHsNQunB6ey88+QRJVomIv2Q25MxvjehYY3BfeJaExPY5K9xb3+vjmt7dMrXTqN1BwM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113692+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1705048316371884.8711551357976; Fri, 12 Jan 2024 00:31:56 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=gSbtLGRfGyVAHLhnthgbdwq8DT0T+x0YWc9o+k5q5Yc=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1705048316; v=1; b=r1RUEIzlNg/jgY5FyKLz898lZgkMi973uCHdibuWrIVn4MqhKTTYPDjp8VlkkzkQM+2B0Llf 6z3C1PlOt5b7rk5eL0YeuXHs+x+z/xj4MC6rD4UsGlF7pgXivjbKV7iCQHCtbnMW24C9glzWa/2 shF+TbBXHeKlLIBv8OvEzWs8= X-Received: by 127.0.0.2 with SMTP id 7NdEYY1788612x0ES4ByUwy5; Fri, 12 Jan 2024 00:31:56 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) by mx.groups.io with SMTP id smtpd.web10.3183.1705048315090948230 for ; Fri, 12 Jan 2024 00:31:55 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10950"; a="5878632" X-IronPort-AV: E=Sophos;i="6.04,188,1695711600"; d="scan'208";a="5878632" X-Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2024 00:31:55 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.04,188,1695711600"; d="scan'208";a="24933978" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.43]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2024 00:31:53 -0800 From: "duntan" To: devel@edk2.groups.io Cc: Ray Ni , Laszlo Ersek , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V4] UefiCpuPkg:Limit PhysicalAddressBits in special case Date: Fri, 12 Jan 2024 16:31:42 +0800 Message-Id: <20240112083142.230-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: IJ9HXaXupaZMZQ5TJ99oF1LUx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1705048316543100001 Content-Type: text/plain; charset="utf-8" When creating smm page table, limit maximum supported physical addresses bits returned by CalculateMaximumSupportAddress() to 47 if 5-Level Paging is disabled. This commit is to avoid issue that more than 47-bit physical addresses are requested in smm page table when 5-level paging is disabled. 4-level paging supports translating 48-bit linear addresses to 52-bit physical addresses. Since linear addresses are sign-extended, linear-address space of 4-level paging is: [0, 2^47-1] and [0xffff8000_00000000, 0xffffffff_ffffffff]. So only [0, 2^47-1] linear-address range maps to the identical physical-address range when 5-Level paging is disabled. Signed-off-by: Dun Tan Reviewed-by: Ray Ni Cc: Laszlo Ersek Cc: Rahul Kumar Cc: Gerd Hoffmann Reviewed-by: Gerd Hoffmann --- UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuD= xeSmm/X64/PageTbl.c index ddd9be66b5..5964884762 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -137,11 +137,13 @@ GetSubEntriesNum ( /** Calculate the maximum support address. =20 + @param[in] Is5LevelPagingNeeded If 5-level paging enabling is needed. + @return the maximum support address. **/ UINT8 CalculateMaximumSupportAddress ( - VOID + BOOLEAN Is5LevelPagingNeeded ) { UINT32 RegEax; @@ -164,6 +166,18 @@ CalculateMaximumSupportAddress ( } } =20 + // + // 4-level paging supports translating 48-bit linear addresses to 52-bit= physical addresses. + // Since linear addresses are sign-extended, the linear-address space of= 4-level paging is: + // [0, 2^47-1] and [0xffff8000_00000000, 0xffffffff_ffffffff]. + // So only [0, 2^47-1] linear-address range maps to the identical physic= al-address range when + // 5-Level paging is disabled. + // + ASSERT (PhysicalAddressBits <=3D 52); + if (!Is5LevelPagingNeeded && (PhysicalAddressBits > 47)) { + PhysicalAddressBits =3D 47; + } + return PhysicalAddressBits; } =20 @@ -197,7 +211,7 @@ SmmInitPageTable ( mCpuSmmRestrictedMemoryAccess =3D PcdGetBool (PcdCpuSmmRestrictedMemoryA= ccess); m1GPageTableSupport =3D Is1GPageSupport (); m5LevelPagingNeeded =3D Is5LevelPagingNeeded (); - mPhysicalAddressBits =3D CalculateMaximumSupportAddress (); + mPhysicalAddressBits =3D CalculateMaximumSupportAddress (m5Leve= lPagingNeeded); PatchInstructionX86 (gPatch5LevelPagingNeeded, m5LevelPagingNeeded, 1); if (m5LevelPagingNeeded) { mPagingMode =3D m1GPageTableSupport ? Paging5Level1GB : Paging5Level; --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113692): https://edk2.groups.io/g/devel/message/113692 Mute This Topic: https://groups.io/mt/103679520/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-