From nobody Tue Feb 10 11:15:46 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+113664+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113664+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1705047843; cv=none; d=zohomail.com; s=zohoarc; b=YelazSTam8ibf0eZ4GPn6VAKagbWkvYWOg9ox8PbQ+5sUdVDx4oGcRVYLFeXKVbRAW9ndryz4ThwduCR/RQhbHljNs5OVFG/MW5uMh3/wXEXEu55TMfB6kjfLkgen0UFIkbxUfGYG0HGwHGx/GM1vrbWFCyW0D6VMOH5iSFVMl0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705047843; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=ab/CBw3hRzT8vrWlQWgxuqXaukvJuXWk2mMvSTTxzis=; b=VnQfVDHFE20lm5B5uilck3iKyNTJlWUuakIc9t4Sz5h4wC/PhnGS2S2JJre0UObgm0YANnCpK0QKI+tkvVunt+9B+ZD15lW/8gW9zMiqyCKsQzEP8j6qN1VOFdCkvQBwlBbyDgL6omqI77VjIbldfmemAz6afmnD53DVA+R64AQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113664+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 17050478432586.488486948888067; Fri, 12 Jan 2024 00:24:03 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=zM2XRPd0QRXOJNEDAGzIP0ucewu7mJc+xoUouGQeVk8=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1705047842; v=1; b=VQDN+MarttjdR30E54ZomL7f3/p6Ia6wDpZDjjCEJJUJ+IKt1WNbe5uDICYR/jDj1ihztyFN tJ2h4PgCa+Pe1FJ1rey30/nz+cXZgzh5fKkeopkNXBqt+THa9HRl1tckFlc0+K+QHCPGFN3k9qE GS41Z7knagfD5yZuU8lE1qHE= X-Received: by 127.0.0.2 with SMTP id 2nBUYY1788612x1MaoSrSmba; Fri, 12 Jan 2024 00:24:02 -0800 X-Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by mx.groups.io with SMTP id smtpd.web11.3016.1705047841537427934 for ; Fri, 12 Jan 2024 00:24:02 -0800 X-Received: from loongson.cn (unknown [10.2.9.245]) by gateway (Coremail) with SMTP id _____8CxLukY96Bl+n0EAA--.4916S3; Fri, 12 Jan 2024 16:23:52 +0800 (CST) X-Received: from code-server.gen (unknown [10.2.9.245]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxK9wV96BlgogTAA--.51368S2; Fri, 12 Jan 2024 16:23:49 +0800 (CST) From: "Chao Li" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [PATCH v7 11/37] UefiCpuPkg: Add LoongArch64 CPU Timer library Date: Fri, 12 Jan 2024 16:23:48 +0800 Message-Id: <20240112082348.3288089-1-lichao@loongson.cn> In-Reply-To: <20240112082153.3284189-1-lichao@loongson.cn> References: <20240112082153.3284189-1-lichao@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8BxK9wV96BlgogTAA--.51368S2 X-CM-SenderInfo: xolfxt3r6o00pqjv00gofq/1tbiAQAOCGWgj6kGSgAXs- X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,lichao@loongson.cn List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: nb5LC2XfcY9mfWpAPvIhU15bx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1705047844574100001 Content-Type: text/plain; charset="utf-8" Add the LoongArch64 CPU Timer library, using CPUCFG 0x4 and 0x5 for Stable Counter frequency. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4584 Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Signed-off-by: Chao Li Acked-by: Ray Ni Acked-by: Ray Ni --- .../BaseLoongArch64CpuTimerLib.inf | 29 ++ .../BaseLoongArch64CpuTimerLib.uni | 15 ++ .../BaseLoongArch64CpuTimerLib/CpuTimerLib.c | 251 ++++++++++++++++++ UefiCpuPkg/UefiCpuPkg.dsc | 3 + 4 files changed, 298 insertions(+) create mode 100644 UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoong= Arch64CpuTimerLib.inf create mode 100644 UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoong= Arch64CpuTimerLib.uni create mode 100644 UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/CpuTimerL= ib.c diff --git a/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64C= puTimerLib.inf b/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArc= h64CpuTimerLib.inf new file mode 100644 index 0000000000..8648cc2a57 --- /dev/null +++ b/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64CpuTimer= Lib.inf @@ -0,0 +1,29 @@ +## @file +# Base CPU Timer Library +# +# Provides base timer support using CPUCFG 0x4 and 0x5 stable counter fre= quency. +# +# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights= reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010029 + BASE_NAME =3D BaseLoongArch64CpuTimerLib + FILE_GUID =3D 740389C7-CC44-4A2F-88DC-89D97D312E= 7C + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D TimerLib + MODULE_UNI_FILE =3D BaseLoongArch64CpuTimerLib.uni + +[Sources] + CpuTimerLib.c + +[Packages] + MdePkg/MdePkg.dec + +[LibraryClasses] + BaseLib + DebugLib + SafeIntLib diff --git a/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64C= puTimerLib.uni b/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArc= h64CpuTimerLib.uni new file mode 100644 index 0000000000..f66e96e972 --- /dev/null +++ b/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64CpuTimer= Lib.uni @@ -0,0 +1,15 @@ +// /** @file +// Base CPU Timer Library +// +// Provides base timer support using CPUCFG 0x4 and 0x5 stable counter fre= quency. +// +// Copyright (c) 2024, Loongson Technology Corporation Limited. All rights= reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "LOONGARCH CPU Tim= er Library" + +#string STR_MODULE_DESCRIPTION #language en-US "Provides basic ti= mer support using CPUCFG 0x4 and 0x5 stable counter frequency." diff --git a/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/CpuTimerLib.c b/= UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/CpuTimerLib.c new file mode 100644 index 0000000000..a5ae8d0185 --- /dev/null +++ b/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/CpuTimerLib.c @@ -0,0 +1,251 @@ +/** @file + CPUCFG 0x4 and 0x5 for Stable Counter frequency instance of Timer Librar= y. + + Copyright (c) 2024, Loongson Technology Corporation Limited. All rights = reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include + +/** + Calculate clock frequency using CPUCFG 0x4 and 0x5 registers. + + @param VOID. + + @return The frequency in Hz. + +**/ +STATIC +UINT64 +CalcConstFreq ( + VOID + ) +{ + UINT32 BaseFreq; + UINT64 ClockMultiplier; + UINT32 ClockDivide; + CPUCFG_REG4_INFO_DATA CcFreq; + CPUCFG_REG5_INFO_DATA CpucfgReg5Data; + UINT64 StableTimerFreq; + + // + // Get the the crystal frequency corresponding to the constant + // frequency timer and the clock used by the timer. + // + AsmCpucfg (CPUCFG_REG4_INFO, &CcFreq.Uint32); + + // + // Get the multiplication factor and frequency division factor + // corresponding to the constant frequency timer and the clock + // used by the timer. + // + AsmCpucfg (CPUCFG_REG5_INFO, &CpucfgReg5Data.Uint32); + + BaseFreq =3D CcFreq.Bits.CC_FREQ; + ClockMultiplier =3D CpucfgReg5Data.Bits.CC_MUL & 0xFFFF; + ClockDivide =3D CpucfgReg5Data.Bits.CC_DIV & 0xFFFF; + + if ((BaseFreq =3D=3D 0x0) || (ClockMultiplier =3D=3D 0x0) || (ClockDivid= e =3D=3D 0x0)) { + DEBUG (( + DEBUG_ERROR, + "LoongArch Stable Timer is not available in the CPU, hence this libr= ary cannot be used.\n" + )); + ASSERT (FALSE); + CpuDeadLoop (); + } + + StableTimerFreq =3D ((ClockMultiplier * BaseFreq) / ClockDivide); + + if (StableTimerFreq =3D=3D 0x0) { + ASSERT (FALSE); + } + + return StableTimerFreq; +} + +/** + Stalls the CPU for at least the given number of microseconds. + + Stalls the CPU for the number of microseconds specified by MicroSeconds. + + @param MicroSeconds The minimum number of microseconds to delay. + + @return MicroSeconds + +**/ +UINTN +EFIAPI +MicroSecondDelay ( + IN UINTN MicroSeconds + ) +{ + UINT64 CurrentTicks, ExceptedTicks, Remaining; + RETURN_STATUS Status; + + Status =3D SafeUint64Mult (MicroSeconds, CalcConstFreq (), &Remaining); + ASSERT_RETURN_ERROR (Status); + + ExceptedTicks =3D DivU64x32 (Remaining, 1000000U); + CurrentTicks =3D AsmReadStableCounter (); + ExceptedTicks +=3D CurrentTicks; + + do { + CurrentTicks =3D AsmReadStableCounter (); + } while (CurrentTicks < ExceptedTicks); + + return MicroSeconds; +} + +/** + Stalls the CPU for at least the given number of nanoseconds. + + Stalls the CPU for the number of nanoseconds specified by NanoSeconds. + + @param NanoSeconds The minimum number of nanoseconds to delay. + + @return NanoSeconds + +**/ +UINTN +EFIAPI +NanoSecondDelay ( + IN UINTN NanoSeconds + ) +{ + UINTN MicroSeconds; + + // Round up to 1us Tick Number + MicroSeconds =3D NanoSeconds / 1000; + MicroSeconds +=3D ((NanoSeconds % 1000) =3D=3D 0) ? 0 : 1; + + MicroSecondDelay (MicroSeconds); + + return NanoSeconds; +} + +/** + Retrieves the current value of a 64-bit free running Stable Counter. + + The LoongArch defines a constant frequency timer, whose main body is a + 64-bit counter called StableCounter. StableCounter is set to 0 after + reset, and then increments by 1 every counting clock cycle. When the + count reaches all 1s, it automatically wraps around to 0 and continues + to increment. + The properties of the Stable Counter can be retrieved from + GetPerformanceCounterProperties(). + + @return The current value of the Stable Counter. + +**/ +UINT64 +EFIAPI +GetPerformanceCounter ( + VOID + ) +{ + // + // Just return the value of Stable Counter. + // + return AsmReadStableCounter (); +} + +/** + Retrieves the 64-bit frequency in Hz and the range of Stable Counter + values. + + If StartValue is not NULL, then the value that the stbale counter starts + with immediately after is it rolls over is returned in StartValue. If + EndValue is not NULL, then the value that the stable counter end with + immediately before it rolls over is returned in EndValue. The 64-bit + frequency of the system frequency in Hz is always returned. + + @param StartValue The value the stable counter starts with when it + rolls over. + @param EndValue The value that the stable counter ends with before + it rolls over. + + @return The frequency in Hz. + +**/ +UINT64 +EFIAPI +GetPerformanceCounterProperties ( + OUT UINT64 *StartValue OPTIONAL, + OUT UINT64 *EndValue OPTIONAL + ) +{ + if (StartValue !=3D NULL) { + *StartValue =3D 0; + } + + if (EndValue !=3D NULL) { + *EndValue =3D 0xFFFFFFFFFFFFFFFFULL; + } + + return CalcConstFreq (); +} + +/** + Converts elapsed ticks of performance counter to time in nanoseconds. + + This function converts the elapsed ticks of running performance counter = to + time value in unit of nanoseconds. + + @param Ticks The number of elapsed ticks of running performance cou= nter. + + @return The elapsed time in nanoseconds. + +**/ +UINT64 +EFIAPI +GetTimeInNanoSecond ( + IN UINT64 Ticks + ) +{ + UINT64 Frequency; + UINT64 NanoSeconds; + UINT64 Remainder; + INTN Shift; + RETURN_STATUS Status; + + Frequency =3D GetPerformanceCounterProperties (NULL, NULL); + + // + // Ticks + // Time =3D --------- x 1,000,000,000 + // Frequency + // + Status =3D SafeUint64Mult ( + DivU64x64Remainder (Ticks, Frequency, &Remainder), + 1000000000u, + &NanoSeconds + ); + + // + // Ensure (Remainder * 1,000,000,000) will not overflow 64-bit. + // Since 2^29 < 1,000,000,000 =3D 0x3B9ACA00 < 2^30, Remainder should < = 2^(64-30) =3D 2^34, + // i.e. highest bit set in Remainder should <=3D 33. + // + Shift =3D MAX (0, HighBitSet64 (Remainder) - 33); + Remainder =3D RShiftU64 (Remainder, (UINTN)Shift); + Frequency =3D RShiftU64 (Frequency, (UINTN)Shift); + + Status =3D SafeUint64Add ( + NanoSeconds, + DivU64x64Remainder ( + MultU64x32 (Remainder, 1000000000u), + Frequency, + NULL + ), + &NanoSeconds + ); + ASSERT_RETURN_ERROR (Status); + + return NanoSeconds; +} diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index 28eed85bce..a977884c3d 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -207,5 +207,8 @@ UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf =20 +[Components.LOONGARCH64] + UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64CpuTimerLib= .inf + [BuildOptions] *_*_*_CC_FLAGS =3D -D DISABLE_NEW_DEPRECATED_INTERFACES --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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