This patch series introduce support for RD-Fremont reference design platform. This platform includes 32 CPUs, but the fixed virtual platform (FVP) simulates 16 CPUs of the platform. There is one CPU per cluster in the system and so the FVP simulates 16 clusters. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 2MB L2 cache. The platform also includes system level cache of 32MB and 8GB of RAM. Also, this patch series adding the extended SMBIO support for RD-Fremont platform. In addition to patches that introduce RD-Fremont platform, there are three patches that update support for existing platforms. The first patch in this series changes the data type of PcdSmmuBase from u32 to u64. The second patch refactor the system memory map base and size values. The third patch add a flag to enable PCIE support for existing and future platforms. Link to github branch with the patches in this series - https://gitlab.arm.com/infra-solutions/reference-design/platsw/edk2-platforms/-/commits/topics/rdfremont/ Prabin CA (6): Platform/Sgi: Refactor system memory base and size definitions Platform/Sgi: Introduce a flag to enable PCIe support for RD Platforms Platform/Sgi: Add initial support for RD-Fremont platform Platform/Sgi: Extend SMBIOS support for RD-Fremont Platform/Sgi: Low Power Idle States for RD-Fremont Platform/Sgi: Add CPPC support for RD-Fremont platform Shriram K (1): Platform/Sgi: Add ACPI tables for RD-Fremont platform Vivek Gautam (1): Platform/Sgi: Update the datatype of PcdSmmuBase from u32 to u64 Platform/ARM/SgiPkg/SgiPlatform.dec | 3 +- Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc | 7 +- Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc | 7 +- ...moryMap2.dsc.inc => SgiMemoryMap3.dsc.inc} | 88 ++- Platform/ARM/SgiPkg/SgiPlatform.dsc.inc | 12 +- Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc | 4 +- .../RdN2.dsc => RdFremont/RdFremont.dsc} | 14 +- Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc | 4 +- Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc | 4 +- Platform/ARM/SgiPkg/RdN2/RdN2.dsc | 4 +- Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.dsc | 4 +- Platform/ARM/SgiPkg/RdN2Cfg2/RdN2Cfg2.dsc | 4 +- Platform/ARM/SgiPkg/RdV1/RdV1.dsc | 4 +- Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.dsc | 4 +- Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc | 4 +- Platform/ARM/SgiPkg/SgiPlatform.fdf | 4 +- .../SgiPkg/AcpiTables/RdFremontAcpiTables.inf | 75 +++ .../Library/PlatformLib/PlatformLib.inf | 5 +- Platform/ARM/SgiPkg/Include/SgiPlatform.h | 5 + .../Type1SystemInformation.c | 5 +- .../Type4ProcessorInformation.c | 5 +- .../SmbiosPlatformDxe/Type7CacheInformation.c | 1 + .../SgiPkg/Library/PlatformLib/PlatformLib.c | 6 + .../Library/PlatformLib/PlatformLibMem.c | 25 +- .../ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl | 512 ++++++++++++++++++ .../ARM/SgiPkg/AcpiTables/RdFremont/Madt.aslc | 138 +++++ .../ARM/SgiPkg/AcpiTables/RdFremont/Pptt.aslc | 167 ++++++ .../ARM/SgiPkg/RdFremont/RdFremont.fdf.inc | 10 + 28 files changed, 1040 insertions(+), 85 deletions(-) copy Platform/ARM/SgiPkg/{SgiMemoryMap2.dsc.inc => SgiMemoryMap3.dsc.inc} (62%) copy Platform/ARM/SgiPkg/{RdN2/RdN2.dsc => RdFremont/RdFremont.dsc} (78%) create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdFremont/Madt.aslc create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdFremont/Pptt.aslc create mode 100644 Platform/ARM/SgiPkg/RdFremont/RdFremont.fdf.inc -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113300): https://edk2.groups.io/g/devel/message/113300 Mute This Topic: https://groups.io/mt/103546562/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- From: Vivek Gautam <vivek.gautam@arm.com> On RD-N2 and previous generation platforms, the base address was within 32-bit region. However, on upcoming platforms, the SMMUv3 base address is beyond 32-bit address region. So, update the datatype of SMMUv3 base PCD. Signed-off-by: Vivek Gautam <vivek.gautam@arm.com> Signed-off-by: Prabin CA <prabin.ca@arm.com> --- Platform/ARM/SgiPkg/SgiPlatform.dec | 2 +- Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec b/Platform/ARM/SgiPkg/SgiPlatform.dec index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/SgiPlatform.dec +++ b/Platform/ARM/SgiPkg/SgiPlatform.dec @@ -XXX,XX +XXX,XX @@ [PcdsFixedAtBuild] gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv|0|UINT32|0x00000014 # SMMU - gArmSgiTokenSpaceGuid.PcdSmmuBase|0|UINT32|0x0000001D + gArmSgiTokenSpaceGuid.PcdSmmuBase|0|UINT64|0x0000001D gArmSgiTokenSpaceGuid.PcdSmmuSize|0|UINT32|0x0000001E # GPIO Controller diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c +++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c @@ -XXX,XX +XXX,XX @@ /** @file * -* Copyright (c) 2018-2023, ARM Limited. All rights reserved. +* Copyright (c) 2018-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -XXX,XX +XXX,XX @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; // Sub System Peripherals - SMMU - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet32 (PcdSmmuBase); - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet32 (PcdSmmuBase); + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdSmmuBase); + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdSmmuBase); VirtualMemoryTable[Index].Length = FixedPcdGet32 (PcdSmmuSize); VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113301): https://edk2.groups.io/g/devel/message/113301 Mute This Topic: https://groups.io/mt/103546564/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- In preparation of adding the next generation of reference design platform that have different memory map, refactor the PcdSystemMemoryBase and PcdSystemMemorySize PCD definitions from the common PCD definitions file into the various platform generation specific memory map PCD definitions file. Signed-off-by: Prabin CA <prabin.ca@arm.com> --- Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc | 8 +++++++- Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc | 8 +++++++- Platform/ARM/SgiPkg/SgiPlatform.dsc.inc | 6 +----- 3 files changed, 15 insertions(+), 7 deletions(-) diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc b/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc +++ b/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc @@ -XXX,XX +XXX,XX @@ # -# Copyright (c) 2020 - 2022, Arm Limited. All rights reserved. +# Copyright (c) 2020 - 2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -XXX,XX +XXX,XX @@ [PcdsFixedAtBuild.common] gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress|0x1C1D0000 gArmSgiTokenSpaceGuid.PcdGpioController0Size|0x00010000 gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt|136 + + # System Memory (1GB - 16MB of Trusted DRAM at the top of the + # 32bit address space) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000 + diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc +++ b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc @@ -XXX,XX +XXX,XX @@ # -# Copyright (c) 2020 - 2023, Arm Limited. All rights reserved. +# Copyright (c) 2020 - 2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -XXX,XX +XXX,XX @@ [PcdsFixedAtBuild.common] # IO virtualization block gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlk0Base|0x1080000000 + + # System Memory (1GB - 16MB of Trusted DRAM at the top of the + # 32bit address space) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000 + diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc +++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc @@ -XXX,XX +XXX,XX @@ # -# Copyright (c) 2018 - 2022, ARM Limited. All rights reserved. +# Copyright (c) 2018 - 2024, Arm Limited. All rights reserved. # (C) Copyright 2021 Hewlett Packard Enterprise Development LP<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent @@ -XXX,XX +XXX,XX @@ [PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x40000 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x0 - # System Memory (1GB - 16MB of Trusted DRAM at the top of the 32bit address space) - gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 - gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000 - # ACPI Table Version gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113302): https://edk2.groups.io/g/devel/message/113302 Mute This Topic: https://groups.io/mt/103546566/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- Introducing a flag called PCIE_ENABLE, which can be set to TRUE or FALSE from the respective <platform>.dsc files to enable or disable the PCIe support. As not all reference design platforms have PCIe support enabled, this flag is introduced. Signed-off-by: Prabin CA <prabin.ca@arm.com> --- Platform/ARM/SgiPkg/SgiPlatform.dec | 1 + Platform/ARM/SgiPkg/SgiPlatform.dsc.inc | 6 ++++++ Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc | 4 +++- Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc | 4 +++- Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc | 4 +++- Platform/ARM/SgiPkg/RdV1/RdV1.dsc | 4 +++- Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.dsc | 4 +++- Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc | 4 +++- Platform/ARM/SgiPkg/SgiPlatform.fdf | 4 +++- Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf | 5 ++++- Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c | 19 +++++++++++-------- 11 files changed, 43 insertions(+), 16 deletions(-) diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec b/Platform/ARM/SgiPkg/SgiPlatform.dec index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/SgiPlatform.dec +++ b/Platform/ARM/SgiPkg/SgiPlatform.dec @@ -XXX,XX +XXX,XX @@ [Guids.common] [PcdsFeatureFlag.common] gArmSgiTokenSpaceGuid.PcdVirtioBlkSupported|FALSE|BOOLEAN|0x00000001 gArmSgiTokenSpaceGuid.PcdVirtioNetSupported|FALSE|BOOLEAN|0x00000010 + gArmSgiTokenSpaceGuid.PcdPcieEnable|FALSE|BOOLEAN|0x0000002E [PcdsFixedAtBuild] gArmSgiTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x00000002 diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc +++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc @@ -XXX,XX +XXX,XX @@ [PcdsFeatureFlag.common] gArmSgiTokenSpaceGuid.PcdVirtioNetSupported|TRUE gEfiMdeModulePkgTokenSpaceGuid.PcdEnableVariableRuntimeCache|FALSE +!if $(PCIE_ENABLE) == TRUE + gArmSgiTokenSpaceGuid.PcdPcieEnable|TRUE +!endif + [PcdsFixedAtBuild.common] gArmTokenSpaceGuid.PcdVFPEnabled|1 gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 @@ -XXX,XX +XXX,XX @@ [Components.common] # Virtio Network OvmfPkg/VirtioNetDxe/VirtioNet.inf +!if $(PCIE_ENABLE) == TRUE # # Required by PCI # @@ -XXX,XX +XXX,XX @@ [Components.common] <PcdsFixedAtBuild> gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F } +!endif # # AHCI Support diff --git a/Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc b/Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc +++ b/Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc @@ -XXX,XX +XXX,XX @@ # -# Copyright (c) 2020-2022, ARM Limited. All rights reserved. +# Copyright (c) 2020-2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -XXX,XX +XXX,XX @@ [Defines] BOARD_DXE_FV_COMPONENTS = Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.fdf.inc BUILD_NUMBER = 1 + DEFINE PCIE_ENABLE = TRUE + # include common definitions from SgiPlatform.dsc !include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc !include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc diff --git a/Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc b/Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc +++ b/Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc @@ -XXX,XX +XXX,XX @@ # -# Copyright (c) 2020-2022, ARM Limited. All rights reserved. +# Copyright (c) 2020-2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -XXX,XX +XXX,XX @@ [Defines] BOARD_DXE_FV_COMPONENTS = Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.fdf.inc BUILD_NUMBER = 1 + DEFINE PCIE_ENABLE = TRUE + # include common definitions from SgiPlatform.dsc !include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc !include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc diff --git a/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc b/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc +++ b/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc @@ -XXX,XX +XXX,XX @@ # -# Copyright (c) 2020-2022, ARM Limited. All rights reserved. +# Copyright (c) 2020-2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -XXX,XX +XXX,XX @@ [Defines] BOARD_DXE_FV_COMPONENTS = Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.fdf.inc BUILD_NUMBER = 1 + DEFINE PCIE_ENABLE = TRUE + # include common definitions from SgiPlatform.dsc !include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc !include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc diff --git a/Platform/ARM/SgiPkg/RdV1/RdV1.dsc b/Platform/ARM/SgiPkg/RdV1/RdV1.dsc index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/RdV1/RdV1.dsc +++ b/Platform/ARM/SgiPkg/RdV1/RdV1.dsc @@ -XXX,XX +XXX,XX @@ # -# Copyright (c) 2020-2022, ARM Limited. All rights reserved. +# Copyright (c) 2020-2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -XXX,XX +XXX,XX @@ [Defines] BOARD_DXE_FV_COMPONENTS = Platform/ARM/SgiPkg/RdV1/RdV1.fdf.inc BUILD_NUMBER = 1 + DEFINE PCIE_ENABLE = TRUE + # include common definitions from SgiPlatform.dsc !include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc !include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc diff --git a/Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.dsc b/Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.dsc index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.dsc +++ b/Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.dsc @@ -XXX,XX +XXX,XX @@ # -# Copyright (c) 2020-2022, ARM Limited. All rights reserved. +# Copyright (c) 2020-2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -XXX,XX +XXX,XX @@ [Defines] BOARD_DXE_FV_COMPONENTS = Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.fdf.inc BUILD_NUMBER = 1 + DEFINE PCIE_ENABLE = TRUE + # include common definitions from SgiPlatform.dsc !include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc !include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc diff --git a/Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc b/Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc +++ b/Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc @@ -XXX,XX +XXX,XX @@ # -# Copyright (c) 2020-2022, ARM Limited. All rights reserved. +# Copyright (c) 2020-2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -XXX,XX +XXX,XX @@ [Defines] BOARD_DXE_FV_COMPONENTS = Platform/ARM/SgiPkg/Sgi575/Sgi575.fdf.inc BUILD_NUMBER = 1 + DEFINE PCIE_ENABLE = TRUE + # include common definitions from SgiPlatform.dsc !include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc !include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc diff --git a/Platform/ARM/SgiPkg/SgiPlatform.fdf b/Platform/ARM/SgiPkg/SgiPlatform.fdf index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/SgiPlatform.fdf +++ b/Platform/ARM/SgiPkg/SgiPlatform.fdf @@ -XXX,XX +XXX,XX @@ # -# Copyright (c) 2018-2021, ARM Limited. All rights reserved. +# Copyright (c) 2018-2024, ARM Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -XXX,XX +XXX,XX @@ [FV.FvMain] INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf INF Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf +!if $(PCIE_ENABLE) == TRUE # Required by PCI INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf @@ -XXX,XX +XXX,XX @@ [FV.FvMain] # INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf +!endif # # AHCI Support diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf +++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf @@ -XXX,XX +XXX,XX @@ # -# Copyright (c) 2018 - 2023, Arm Limited. All rights reserved. +# Copyright (c) 2018 - 2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -XXX,XX +XXX,XX @@ [Sources.common] [Sources.AARCH64] AArch64/Helper.S | GCC +[FeaturePcd] + gArmSgiTokenSpaceGuid.PcdPcieEnable + [FixedPcd] gArmPlatformTokenSpaceGuid.PcdClusterCount gArmPlatformTokenSpaceGuid.PcdCoreCount diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c +++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c @@ -XXX,XX +XXX,XX @@ // Total number of descriptors, including the final "end-of-table" descriptor. #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS \ - ((14 + (FixedPcdGet32 (PcdChipCount) * 2)) + \ + ((13 + (FixedPcdGet32 (PcdChipCount) * 2)) + \ + (FeaturePcdGet (PcdPcieEnable)) + \ (FixedPcdGet32 (PcdIoVirtSocExpBlkUartEnable) * \ FixedPcdGet32 (PcdChipCount) * 2)) @@ -XXX,XX +XXX,XX @@ ArmPlatformGetVirtualMemoryMap ( #endif #endif - // PCI Configuration Space - VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciExpressBaseAddress); - VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciExpressBaseAddress); - VirtualMemoryTable[Index].Length = (FixedPcdGet32 (PcdPciBusMax) - - FixedPcdGet32 (PcdPciBusMin) + 1) * - SIZE_1MB; - VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + if (FeaturePcdGet (PcdPcieEnable)) { + // PCI Configuration Space + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciExpressBaseAddress); + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciExpressBaseAddress); + VirtualMemoryTable[Index].Length = (FixedPcdGet32 (PcdPciBusMax) - + FixedPcdGet32 (PcdPciBusMin) + 1) * + SIZE_1MB; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + } // MM Memory Space VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdMmBufferBase); -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113303): https://edk2.groups.io/g/devel/message/113303 Mute This Topic: https://groups.io/mt/103546569/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- From: Shriram K <shriram.k@arm.com> RD-Fremont is the next platform in the Arm's reference design platform series. This platform includes 32 CPUs but the fixed virtual platform (FVP) simulates 16 CPUs of the platform. There is one CPU per cluster in the system and so the FVP simulates 16 clusters. In preparation for adding support for this platform, add the initial set of ACPI tables and reuse existing ACPI tables as applicable to boot a operating system on this platform. Signed-off-by: Shriram K <shriram.k@arm.com> Signed-off-by: Prabin CA <prabin.ca@arm.com> --- Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf | 73 ++++++++ Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl | 196 ++++++++++++++++++++ Platform/ARM/SgiPkg/AcpiTables/RdFremont/Madt.aslc | 138 ++++++++++++++ Platform/ARM/SgiPkg/AcpiTables/RdFremont/Pptt.aslc | 167 +++++++++++++++++ 4 files changed, 574 insertions(+) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf @@ -XXX,XX +XXX,XX @@ +## @file +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2024, Arm Ltd. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = RdFremontAcpiTables + FILE_GUID = c712719a-0aaf-438c-9cdd-35ab4d60207d # gArmSgiAcpiTablesGuid + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + +[Sources] + Dbg2.aslc + Fadt.aslc + Gtdt.aslc + RdFremont/Dsdt.asl + RdFremont/Madt.aslc + RdFremont/Pptt.aslc + Spcr.aslc + SsdtEvents.asl + SsdtRos.asl + SsdtRosVirtioP9.asl + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/ARM/SgiPkg/SgiPlatform.dec + +[FixedPcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + + gArmPlatformTokenSpaceGuid.PcdSerialDbgInterrupt + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase + gArmPlatformTokenSpaceGuid.PL011UartInterrupt + gArmPlatformTokenSpaceGuid.PcdCoreCount + gArmPlatformTokenSpaceGuid.PcdClusterCount + + gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress + gArmSgiTokenSpaceGuid.PcdGpioController0Size + gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt + gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv + gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv + gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress + gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize + gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt + gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress + gArmSgiTokenSpaceGuid.PcdVirtioBlkSize + gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt + gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress + gArmSgiTokenSpaceGuid.PcdVirtioNetSize + gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt + gArmSgiTokenSpaceGuid.PcdVirtioP9BaseAddress + gArmSgiTokenSpaceGuid.PcdVirtioP9Size + gArmSgiTokenSpaceGuid.PcdVirtioP9Interrupt + gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv + gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv + + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl @@ -XXX,XX +XXX,XX @@ +/** @file +* Differentiated System Description Table Fields (DSDT) +* +* Copyright (c) 2024, Arm Limited. All rights reserved.<BR> +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +* @par Specification Reference: +* - ACPI 6.5, Chapter 5, Section 5.2.11.1, Differentiated System Description +* Table (DSDT) +* +**/ + +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" + +DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", + EFI_ACPI_ARM_OEM_REVISION) { + Scope (_SB) { + Device (CL00) { // Cluster 0 + Name (_HID, "ACPI0010") + Name (_UID, 0) + + Device (CP00) { // Neoverse Poseidon core 0 + Name (_HID, "ACPI0007") + Name (_UID, 0) + Name (_STA, 0xF) + } + } + + Device (CL01) { // Cluster 1 + Name (_HID, "ACPI0010") + Name (_UID, 1) + + Device (CP01) { // Neoverse Poseidon core 1 + Name (_HID, "ACPI0007") + Name (_UID, 1) + Name (_STA, 0xF) + } + } + + Device (CL02) { // Cluster 2 + Name (_HID, "ACPI0010") + Name (_UID, 2) + + Device (CP02) { // Neoverse Poseidon core 2 + Name (_HID, "ACPI0007") + Name (_UID, 2) + Name (_STA, 0xF) + } + } + + Device (CL03) { // Cluster 3 + Name (_HID, "ACPI0010") + Name (_UID, 3) + + Device (CP03) { // Neoverse Poseidon core 3 + Name (_HID, "ACPI0007") + Name (_UID, 3) + Name (_STA, 0xF) + } + } + + Device (CL04) { // Cluster 4 + Name (_HID, "ACPI0010") + Name (_UID, 4) + + Device (CP04) { // Neoverse Poseidon core 4 + Name (_HID, "ACPI0007") + Name (_UID, 4) + Name (_STA, 0xF) + } + } + + Device (CL05) { // Cluster 5 + Name (_HID, "ACPI0010") + Name (_UID, 5) + + Device (CP05) { // Neoverse Poseidon core 5 + Name (_HID, "ACPI0007") + Name (_UID, 5) + Name (_STA, 0xF) + } + } + + Device (CL06) { // Cluster 6 + Name (_HID, "ACPI0010") + Name (_UID, 6) + + Device (CP06) { // Neoverse Poseidon core 6 + Name (_HID, "ACPI0007") + Name (_UID, 6) + Name (_STA, 0xF) + } + } + + Device (CL07) { // Cluster 7 + Name (_HID, "ACPI0010") + Name (_UID, 7) + + Device (CP07) { // Neoverse Poseidon core 7 + Name (_HID, "ACPI0007") + Name (_UID, 7) + Name (_STA, 0xF) + } + } + + Device (CL08) { // Cluster 8 + Name (_HID, "ACPI0010") + Name (_UID, 8) + + Device (CP08) { // Neoverse Poseidon core 8 + Name (_HID, "ACPI0007") + Name (_UID, 8) + Name (_STA, 0xF) + } + } + + Device (CL09) { // Cluster 9 + Name (_HID, "ACPI0010") + Name (_UID, 9) + + Device (CP09) { // Neoverse Poseidon core 9 + Name (_HID, "ACPI0007") + Name (_UID, 9) + Name (_STA, 0xF) + } + } + + Device (CL10) { // Cluster 10 + Name (_HID, "ACPI0010") + Name (_UID, 10) + + Device (CP10) { // Neoverse Poseidon core 10 + Name (_HID, "ACPI0007") + Name (_UID, 10) + Name (_STA, 0xF) + } + } + + Device (CL11) { // Cluster 11 + Name (_HID, "ACPI0010") + Name (_UID, 11) + + Device (CP11) { // Neoverse Poseidon core 11 + Name (_HID, "ACPI0007") + Name (_UID, 11) + Name (_STA, 0xF) + } + } + + Device (CL12) { // Cluster 12 + Name (_HID, "ACPI0010") + Name (_UID, 12) + + Device (CP12) { // Neoverse Poseidon core 12 + Name (_HID, "ACPI0007") + Name (_UID, 12) + Name (_STA, 0xF) + } + } + + Device (CL13) { // Cluster 13 + Name (_HID, "ACPI0010") + Name (_UID, 13) + + Device (CP13) { // Neoverse Poseidon core 13 + Name (_HID, "ACPI0007") + Name (_UID, 13) + Name (_STA, 0xF) + } + } + + Device (CL14) { // Cluster 14 + Name (_HID, "ACPI0010") + Name (_UID, 14) + + Device (CP14) { // Neoverse Poseidon core 14 + Name (_HID, "ACPI0007") + Name (_UID, 14) + Name (_STA, 0xF) + } + } + + Device (CL15) { // Cluster 15 + Name (_HID, "ACPI0010") + Name (_UID, 15) + + Device (CP15) { // Neoverse Poseidon core 15 + Name (_HID, "ACPI0007") + Name (_UID, 15) + Name (_STA, 0xF) + } + } + } // Scope(_SB) +} diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Madt.aslc new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Madt.aslc @@ -XXX,XX +XXX,XX @@ +/** @file +* Multiple APIC Description Table (MADT) +* +* Copyright (c) 2024, Arm Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include <Library/AcpiLib.h> +#include <Library/ArmLib.h> +#include <Library/PcdLib.h> + +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" + +#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \ + FixedPcdGet32 (PcdCoreCount)) + +// Multiple APIC Description Table +#pragma pack (1) + +typedef struct { + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_4_GIC_STRUCTURE GicInterfaces[CORE_CNT]; + EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor; + EFI_ACPI_6_4_GIC_ITS_STRUCTURE GicIts[6]; +} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE; + +#pragma pack () + +STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + ), + // MADT specific fields + 0, // LocalApicAddress + 0 // Flags + }, + { + // Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, + // PmuIrq, GicBase, GicVBase, + // GicHBase, GsivId, GicRBase, + // Efficiency, + // SpeOverflowInterrupt) + // Note: The GIC Structure of the primary CPU must be the first entry + // (see note in 5.2.12.14 GICC Structure of ACPI v6.4). + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core0 + 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core1 + 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core2 + 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core3 + 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core4 + 0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core5 + 0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core6 + 0, 6, GET_MPID(0x600, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core7 + 0, 7, GET_MPID(0x700, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core8 + 0, 8, GET_MPID(0x800, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core9 + 0, 9, GET_MPID(0x900, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core10 + 0, 10, GET_MPID(0xa00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core11 + 0, 11, GET_MPID(0xb00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core12 + 0, 12, GET_MPID(0xc00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core13 + 0, 13, GET_MPID(0xd00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core14 + 0, 14, GET_MPID(0xe00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core15 + 0, 15, GET_MPID(0xf00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + }, + // GIC Distributor Entry + EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), + 0, 3), + // GIC Redistributor + EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase), + SIZE_16MB), + // GIC ITS + { + EFI_ACPI_6_4_GIC_ITS_INIT(0, 0x30040000), + EFI_ACPI_6_4_GIC_ITS_INIT(1, 0x30080000), + EFI_ACPI_6_4_GIC_ITS_INIT(2, 0x300C0000), + EFI_ACPI_6_4_GIC_ITS_INIT(3, 0x30100000), + EFI_ACPI_6_4_GIC_ITS_INIT(4, 0x30140000), + EFI_ACPI_6_4_GIC_ITS_INIT(5, 0x30180000), + }, +}; + +// +// Reference the table being generated to prevent the optimizer from removing +// the data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Madt; diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Pptt.aslc new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Pptt.aslc @@ -XXX,XX +XXX,XX @@ +/** @file +* Processor Properties Topology Table (PPTT) for RD-Fremont platform +* +* Copyright (c) 2024, Arm Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +* This file describes the topological structure of the processor block on the +* RD-Fremont platform in the form as defined by ACPI PPTT table. The RD-Fremont +* platform includes sixteen single-thread CPUs. Each of the CPUs include 64KB +* L1 Data cache, 64KB L1 Instruction cache and 2MB L2 cache. +* +* @par Specification Reference: +* - ACPI 6.4, Chapter 5, Section 5.2.29, Processor Properties Topology Table +**/ + +#include <IndustryStandard/Acpi.h> +#include <Library/AcpiLib.h> +#include <Library/ArmLib.h> +#include <Library/PcdLib.h> + +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" + +/** Define helper macro for populating processor core information. + + @param [in] PackageId Package instance number. + @param [in] ClusterId Cluster instance number. + @param [in] CpuId CPU instance number. +**/ +#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) \ + { \ + /* Parameters for CPU Core */ \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \ + OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ \ + PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \ + Package.Cluster[ClusterId]), /* Parent */ \ + ((PackageId << 4) | ClusterId), /* ACPI Id */ \ + 2 /* Num of private resource */ \ + ), \ + \ + /* Offsets of the private resources */ \ + { \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \ + Package.Cluster[ClusterId].Core[CpuId].DCache), \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \ + Package.Cluster[ClusterId].Core[CpuId].ICache) \ + }, \ + \ + /* L1 data cache parameters */ \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \ + Package.Cluster[ClusterId].Core[CpuId].L2Cache), \ + /* Next level of cache */ \ + SIZE_64KB, /* Size */ \ + 256, /* Num of sets */ \ + 4, /* Associativity */ \ + PPTT_DATA_CACHE_ATTR, /* Attributes */ \ + 64, /* Line size */ \ + RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1DataCache) \ + /* Cache id */ \ + ), \ + \ + /* L1 instruction cache parameters */ \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \ + Package.Cluster[ClusterId].Core[CpuId].L2Cache), \ + /* Next level of cache */ \ + SIZE_64KB, /* Size */ \ + 256, /* Num of sets */ \ + 4, /* Associativity */ \ + PPTT_INST_CACHE_ATTR, /* Attributes */ \ + 64, /* Line size */ \ + RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1InstructionCache) \ + /* Cache id */ \ + ), \ + \ + /* L2 cache parameters */ \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \ + 0, /* Next level of cache */ \ + SIZE_2MB, /* Size */ \ + 4096, /* Num of sets */ \ + 8, /* Associativity */ \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \ + 64, /* Line size */ \ + RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L2Cache) \ + /* Cache id */ \ + ), \ + } + +/** Define helper macro for populating processor container information. + + @param [in] PackageId Package instance number. + @param [in] ClusterId Cluster instance number. +**/ +#define PPTT_CLUSTER_INIT(PackageId, ClusterId) \ + { \ + /* Parameters for Cluster */ \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \ + OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ \ + PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \ + Package), /* Parent */ \ + ((PackageId << 4) | ClusterId), /* ACPI Id */ \ + 0 /* Num of private resource */ \ + ), \ + \ + /* Initialize child core */ \ + { \ + PPTT_CORE_INIT (PackageId, ClusterId, 0) \ + } \ + } + +#pragma pack(1) +/* + * Processor Properties Topology Table + */ +typedef struct { + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + RD_PPTT_PACKAGE Package; +} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +#pragma pack () + +STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + ) + }, + + { + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( + OFFSET_OF (RD_PPTT_PACKAGE, Cluster[0]), + PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0), + + { + PPTT_CLUSTER_INIT (0, 0), + PPTT_CLUSTER_INIT (0, 1), + PPTT_CLUSTER_INIT (0, 2), + PPTT_CLUSTER_INIT (0, 3), + PPTT_CLUSTER_INIT (0, 4), + PPTT_CLUSTER_INIT (0, 5), + PPTT_CLUSTER_INIT (0, 6), + PPTT_CLUSTER_INIT (0, 7), + PPTT_CLUSTER_INIT (0, 8), + PPTT_CLUSTER_INIT (0, 9), + PPTT_CLUSTER_INIT (0, 10), + PPTT_CLUSTER_INIT (0, 11), + PPTT_CLUSTER_INIT (0, 12), + PPTT_CLUSTER_INIT (0, 13), + PPTT_CLUSTER_INIT (0, 14), + PPTT_CLUSTER_INIT (0, 15) + } + } +}; + +/* + * Reference the table being generated to prevent the optimizer from removing + * the data structure from the executable + */ +VOID* CONST ReferenceAcpiTable = &Pptt; -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113304): https://edk2.groups.io/g/devel/message/113304 Mute This Topic: https://groups.io/mt/103546571/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- The RD-Fremont fixed virtual platform simulates 16 CPUs and 8GB of RAM. Add initial support for this platform by adding the required platform build configuration files. This platform has considerable differences in its memory map compared to its predecessors. So add a corresponding memory map file as well to define the PCDs for its generation of platforms. Signed-off-by: Prabin CA <prabin.ca@arm.com> --- Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc | 71 ++++++++++++++++++++ Platform/ARM/SgiPkg/RdFremont/RdFremont.dsc | 55 +++++++++++++++ Platform/ARM/SgiPkg/RdFremont/RdFremont.fdf.inc | 10 +++ 3 files changed, 136 insertions(+) diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc b/Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc @@ -XXX,XX +XXX,XX @@ +# +# Copyright (c) 2024, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[PcdsFixedAtBuild.common] + # System Peripherals + gArmSgiTokenSpaceGuid.PcdSmcCs0Base|0x08000000 + gArmSgiTokenSpaceGuid.PcdSmcCs1Base|0x0600000000 + gArmSgiTokenSpaceGuid.PcdSysPeriphBase|0x0C000000 + gArmSgiTokenSpaceGuid.PcdSysPeriphSysRegBase|0x0C010000 + + # SP804 dual timer + gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress|0x0C110000 + gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize|0x00010000 + gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt|216 + + # Virtio Disk + gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress|0x0C130000 + gArmSgiTokenSpaceGuid.PcdVirtioBlkSize|0x10000 + gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt|184 + + # GPIO controller + gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress|0x0C1D0000 + gArmSgiTokenSpaceGuid.PcdGpioController0Size|0x00010000 + gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt|168 + + # Ethernet + gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress|0x0C150000 + gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt|186 + + # PL031 RealTimeClock + gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0C170000 + + # Virtio P9 + gArmSgiTokenSpaceGuid.PcdVirtioP9BaseAddress|0x0C190000 + gArmSgiTokenSpaceGuid.PcdVirtioP9Size|0x10000 + gArmSgiTokenSpaceGuid.PcdVirtioP9Interrupt|185 + + # PL370 - HDLCD1 + gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0EF60000 + + # PL011 - Serial Debug UART + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x0EF70000 + gArmPlatformTokenSpaceGuid.PcdSerialDbgInterrupt|179 + + # PL011 - Serial Terminal + gArmPlatformTokenSpaceGuid.PL011UartInterrupt|112 + + # System Memory (2GB - 128MB of Trusted DRAM at the top of the 32bit address space) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x78000000 + + # SMMU + gArmSgiTokenSpaceGuid.PcdSmmuBase|0x280000000 + gArmSgiTokenSpaceGuid.PcdSmmuSize|0x4000000 + + # Non-Volatile variable storage + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x0600000000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x0601400000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x0602800000 + + # Address bus width - 64TB address space + gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip|46 + + # Timer & Watchdog interrupts + gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv|109 + gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv|108 + gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv|110 + gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv|111 diff --git a/Platform/ARM/SgiPkg/RdFremont/RdFremont.dsc b/Platform/ARM/SgiPkg/RdFremont/RdFremont.dsc new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/ARM/SgiPkg/RdFremont/RdFremont.dsc @@ -XXX,XX +XXX,XX @@ +# +# Copyright (c) 2024, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = RdFremont + PLATFORM_GUID = fd140b0f-4467-4314-aa69-cd0bd712e08e + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x0001001B + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = NOOPT|DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/ARM/SgiPkg/SgiPlatform.fdf + BOARD_DXE_FV_COMPONENTS = Platform/ARM/SgiPkg/RdFremont/RdFremont.fdf.inc + BUILD_NUMBER = 1 + +# include common definitions from SgiPlatform.dsc +!include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc +!include Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc + +# include common/basic libraries from MdePkg. +!include MdePkg/MdeLibs.dsc.inc + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + +[PcdsFixedAtBuild.common] + # GIC Base Addresses + gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x301C0000 + gArmSgiTokenSpaceGuid.PcdGicSize|0x200000 + + # ARM Cores and Clusters + gArmPlatformTokenSpaceGuid.PcdCoreCount|1 + gArmPlatformTokenSpaceGuid.PcdClusterCount|16 + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ + +[Components.common] + Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf diff --git a/Platform/ARM/SgiPkg/RdFremont/RdFremont.fdf.inc b/Platform/ARM/SgiPkg/RdFremont/RdFremont.fdf.inc new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/ARM/SgiPkg/RdFremont/RdFremont.fdf.inc @@ -XXX,XX +XXX,XX @@ +# +# Copyright (c) 2024, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +# Per-platform additional content of the DXE phase firmware volume + + # ACPI support + INF RuleOverride=ACPITABLE Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113305): https://edk2.groups.io/g/devel/message/113305 Mute This Topic: https://groups.io/mt/103546573/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- Extend the SMBIOS support for RD-Fremont platform. RD-Fremont is a 16 core platform with Poseidon CPU. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 2MB L2 cache. The platform also includes system level cache of 32MB and 8GB of RAM. Signed-off-by: Prabin CA <prabin.ca@arm.com> --- Platform/ARM/SgiPkg/Include/SgiPlatform.h | 5 +++++ Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c | 5 ++++- Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c | 5 ++++- Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c | 1 + Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c | 6 ++++++ 5 files changed, 20 insertions(+), 2 deletions(-) diff --git a/Platform/ARM/SgiPkg/Include/SgiPlatform.h b/Platform/ARM/SgiPkg/Include/SgiPlatform.h index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/Include/SgiPlatform.h +++ b/Platform/ARM/SgiPkg/Include/SgiPlatform.h @@ -XXX,XX +XXX,XX @@ #define RD_V2_PART_NUM 0x7F2 #define RD_V2_CONF_ID 0x1 +// RD-Fremont Platform Identification values +#define RD_Fremont_PART_NUM 0x7EE +#define RD_Fremont_CONF_ID 0x1 + #define SGI_CONFIG_MASK 0x0F #define SGI_CONFIG_SHIFT 0x1C #define SGI_PART_NUM_MASK 0xFFF @@ -XXX,XX +XXX,XX @@ typedef enum { RdN2Cfg1, RdN2Cfg2, RdV2, + RdFremont, } ARM_RD_PRODUCT_ID; // Arm ProductId look-up table diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c +++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c @@ -XXX,XX +XXX,XX @@ "RdN2\0" \ "RdN2Cfg1\0" \ "RdN2Cfg2\0" \ - "RdV2\0" + "RdV2\0" \ + "RdFremont\0" typedef enum { ManufacturerName = 1, @@ -XXX,XX +XXX,XX @@ STATIC GUID mSmbiosUid[] = { {0xd2946d07, 0x8057, 0x4c26, {0xbf, 0x53, 0x78, 0xa6, 0x5b, 0xe1, 0xc1, 0x60}}, /* Rd-V2 */ {0x3b1180a3, 0x0744, 0x4194, {0xae, 0x2e, 0xed, 0xa5, 0xbc, 0x2e, 0x43, 0x45}}, + /* Rd-Fremont */ + {0x904b28d6, 0x0662, 0x11ed, {0xb9, 0x39, 0x02, 0x42, 0xac, 0x12, 0x00, 0x02}}, }; /* System information */ diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c +++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c @@ -XXX,XX +XXX,XX @@ "Neoverse-N2\0" \ "Neoverse-N2\0" \ "Neoverse-V2\0" \ + "Neoverse-Poseidon\0" \ "000-0\0" /* Serial number */ \ "783-3\0" \ "786-1\0" \ @@ -XXX,XX +XXX,XX @@ "7B7-1\0" \ "7B6-1\0" \ "7B7-1\0" \ - "7F2-1\0" + "7F2-1\0" \ + "7EE-1\0" typedef enum { PartNumber = 1, @@ -XXX,XX +XXX,XX @@ InstallType4ProcessorInformation ( case RdN2: case RdN2Cfg1: case RdV2: + case RdFremont: mArmRdSmbiosType4.Base.CoreCount = CoreCount; mArmRdSmbiosType4.Base.EnabledCoreCount = CoreCount; mArmRdSmbiosType4.Base.ThreadCount = CoreCount; diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c +++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c @@ -XXX,XX +XXX,XX @@ InstallType7CacheInformation ( mArmRdSmbiosType7[4].Base.Associativity = CacheAssociativity16Way; break; case RdV2: + case RdFremont: /* L1 instruction cache */ mArmRdSmbiosType7[0].Base.MaximumCacheSize2 = 64; // 64KB mArmRdSmbiosType7[0].Base.InstalledSize2 = 64; // 64KB diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c +++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c @@ -XXX,XX +XXX,XX @@ STATIC CONST SGI_PRODUCT_ID_LOOKUP SgiProductIdLookup[] = { RD_V2_CONF_ID, 0 }, + { + RdFremont, + RD_Fremont_PART_NUM, + RD_Fremont_CONF_ID, + 0 + }, }; EFI_BOOT_MODE -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113306): https://edk2.groups.io/g/devel/message/113306 Mute This Topic: https://groups.io/mt/103546576/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- RD-Fremont platform supports two LPI states, LPI1 (Standby WFI) and LPI3 (Power-down). The cluster supports LPI2 (Power-down) state. The LPI implementation also supports combined power state for core and cluster. Signed-off-by: Prabin CA <prabin.ca@arm.com> --- Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf | 1 + Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl | 154 ++++++++++++++++++++ 2 files changed, 155 insertions(+) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf @@ -XXX,XX +XXX,XX @@ [FixedPcd] gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv + gArmSgiTokenSpaceGuid.PcdOscLpiEnable gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl +++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl @@ -XXX,XX +XXX,XX @@ * @par Specification Reference: * - ACPI 6.5, Chapter 5, Section 5.2.11.1, Differentiated System Description * Table (DSDT) +* - ACPI 6.5, Chapter 8, Section 8.4.3, Lower Power Idle States +* - Arm Functional Fixed Hardware Specification v1.2, Chapter 3, Section 3.1, +* Idle management and Low Power Idle states * **/ @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", EFI_ACPI_ARM_OEM_REVISION) { Scope (_SB) { + /* _OSC: Operating System Capabilities */ + Method (_OSC, 4, Serialized) { + CreateDWordField (Arg3, 0x00, STS0) + CreateDWordField (Arg3, 0x04, CAP0) + + /* Platform-wide Capabilities */ + If (LEqual (Arg0, ToUUID("0811b06e-4a27-44f9-8d60-3cbbc22e7b48"))) { + /* OSC rev 1 supported, for other version, return failure */ + If (LEqual (Arg1, One)) { + And (STS0, Not (OSC_STS_MASK), STS0) + + If (And (CAP0, OSC_CAP_OS_INITIATED_LPI)) { + /* OS initiated LPI not supported */ + And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0) + Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0) + } + + If (And (CAP0, OSC_CAP_PLAT_COORDINATED_LPI)) { + if (LEqual (FixedPcdGet32 (PcdOscLpiEnable), Zero)) { + And (CAP0, Not (OSC_CAP_PLAT_COORDINATED_LPI), CAP0) + Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0) + } + } + } Else { + And (STS0, Not (OSC_STS_MASK), STS0) + Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0) + } + } Else { + And (STS0, Not (OSC_STS_MASK), STS0) + Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_UUID), STS0) + } + + Return (Arg3) + } + + Name (PLPI, Package () { /* LPI for Processor, support 2 LPI states */ + 0, // Version + 0, // Level Index + 2, // Count + Package () { // WFI for CPU + 1, // Min residency (uS) + 1, // Wake latency (uS) + 1, // Flags + 0, // Arch Context lost Flags (no loss) + 0, // Residency Counter Frequency + 0, // No parent state + ResourceTemplate () { // Register Entry method + Register (FFixedHW, + 32, // Bit Width + 0, // Bit Offset + 0xFFFFFFFF, // Address + 3, // Access Size + ) + }, + ResourceTemplate () { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate () { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "LPI1-Core" + }, + Package () { // Power Gating state for CPU + 150, // Min residency (uS) + 350, // Wake latency (uS) + 1, // Flags + 1, // Arch Context lost Flags (Core context lost) + 0, // Residency Counter Frequency + 0, // No parent state + ResourceTemplate () { // Register Entry method + Register (FFixedHW, + 32, // Bit Width + 0, // Bit Offset + 0x40000002, // Address (PwrLvl:core, StateTyp:PwrDn) + 3, // Access Size + ) + }, + ResourceTemplate () { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate () { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "LPI3-Core" + }, + }) + Device (CL00) { // Cluster 0 Name (_HID, "ACPI0010") Name (_UID, 0) @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 0) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 1) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 2) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 3) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 4) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 5) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 6) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 7) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 8) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 9) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 10) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 11) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 12) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 13) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 14) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 15) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } } // Scope(_SB) -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113307): https://edk2.groups.io/g/devel/message/113307 Mute This Topic: https://groups.io/mt/103546578/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- Enable ACPI CPPC mechanism for RD-Fremont as defined by the ACPI specification. The implementation uses AMU registers accessible as Fixed-feature Hardware (FFixedHW) for monitoring the performance. Non-secure SCMI fastchannels are used to communicate with LCP to set the desired performance. RD-Fremont platform does not support CPPC revision 1 and below. So update the _OSC method to let OSPM know about this fact. Signed-off-by: Prabin CA <prabin.ca@arm.com> --- Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf | 1 + Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl | 162 ++++++++++++++++++++ 2 files changed, 163 insertions(+) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf @@ -XXX,XX +XXX,XX @@ [FixedPcd] gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv + gArmSgiTokenSpaceGuid.PcdOscCppcEnable gArmSgiTokenSpaceGuid.PcdOscLpiEnable gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl +++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl @@ -XXX,XX +XXX,XX @@ * - ACPI 6.5, Chapter 8, Section 8.4.3, Lower Power Idle States * - Arm Functional Fixed Hardware Specification v1.2, Chapter 3, Section 3.1, * Idle management and Low Power Idle states +* - ACPI 6.5, Chapter 8, Section 8.4.6, Collaborative Processor Performance +* Control +* - Arm Functional Fixed Hardware Specification v1.2, Chapter 3, Section 3.2, +* Performance management and Collaborative Processor Performance Control * **/ @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0) } } + + If (And (CAP0, OSC_CAP_CPPC_SUPPORT)) { + /* CPPC revision 1 and below not supported */ + And (CAP0, Not (OSC_CAP_CPPC_SUPPORT), CAP0) + Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0) + } + + If (And (CAP0, OSC_CAP_CPPC2_SUPPORT)) { + if (LEqual (FixedPcdGet32 (PcdOscCppcEnable), Zero)) { + And (CAP0, Not (OSC_CAP_CPPC2_SUPPORT), CAP0) + Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0) + } + } + } Else { And (STS0, Not (OSC_STS_MASK), STS0) Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0) @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 0) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x200093000, 0x200093004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (0) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 1) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x200293000, 0x200293004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (1) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 2) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x200493000, 0x200493004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (2) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 3) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x200693000, 0x200063004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (3) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 4) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x200893000, 0x200893004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (4) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 5) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x200A93000, 0x200A93004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (5) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 6) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x200C93000, 0x200C93004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (6) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 7) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x200E93000, 0x200E93004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (7) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 8) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x201093000, 0x201093004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (8) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 9) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x201293000, 0x201293004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (9) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 10) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x201493000, 0x201493004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (10) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 11) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x201693000, 0x201693004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (11) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 12) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x201893000, 0x201893004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (12) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 13) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x201A93000, 0x201A93004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (13) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 14) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x201C93000, 0x201C93004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (14) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 15) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x201E93000, 0x201E93004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (15) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113308): https://edk2.groups.io/g/devel/message/113308 Mute This Topic: https://groups.io/mt/103546580/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- Changes since V2: - Removed author's signed-off on the patches, which is owned by another author. Changes since V1: - Corrected memory map in the DSDT file. This patch series introduce support for RD-Fremont reference design platform. This platform includes 32 CPUs, but the fixed virtual platform (FVP) simulates 16 CPUs of the platform. There is one CPU per cluster in the system and so the FVP simulates 16 clusters. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 2MB L2 cache. The platform also includes system level cache of 32MB and 8GB of RAM. Also, this patch series adding the extended SMBIO support for RD-Fremont platform. In addition to patches that introduce RD-Fremont platform, there are three patches that update support for existing platforms. The first patch in this series changes the data type of PcdSmmuBase from u32 to u64. The second patch refactor the system memory map base and size values. The third patch add a flag to enable PCIE support for existing and future platforms. This patch series should be applied on top of the patch series https://edk2.groups.io/g/devel/message/113732 Link to gitlab branch with the patches in this series - https://gitlab.arm.com/infra-solutions/reference-design/platsw/edk2-platforms/-/tree/topics/rdfremont Prabin CA (6): Platform/Sgi: Refactor system memory base and size definitions Platform/Sgi: Introduce a flag to enable PCIe support for RD Platforms Platform/Sgi: Add initial support for RD-Fremont platform Platform/Sgi: Extend SMBIOS support for RD-Fremont Platform/Sgi: Low Power Idle States for RD-Fremont Platform/Sgi: Add CPPC support for RD-Fremont platform Shriram K (1): Platform/Sgi: Add ACPI tables for RD-Fremont platform Vivek Gautam (1): Platform/Sgi: Update the datatype of PcdSmmuBase from u32 to u64 Platform/ARM/SgiPkg/SgiPlatform.dec | 3 +- Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc | 8 +- Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc | 8 +- Platform/ARM/SgiPkg/{SgiMemoryMap2.dsc.inc => SgiMemoryMap3.dsc.inc} | 88 ++-- Platform/ARM/SgiPkg/SgiPlatform.dsc.inc | 12 +- Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc | 4 +- Platform/ARM/SgiPkg/{RdV1/RdV1.dsc => RdFremont/RdFremont.dsc} | 14 +- Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc | 4 +- Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc | 4 +- Platform/ARM/SgiPkg/RdV1/RdV1.dsc | 4 +- Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.dsc | 4 +- Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc | 4 +- Platform/ARM/SgiPkg/SgiPlatform.fdf | 4 +- Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf | 75 +++ Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf | 5 +- Platform/ARM/SgiPkg/Include/SgiPlatform.h | 5 + Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c | 5 +- Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c | 5 +- Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c | 1 + Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c | 6 + Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c | 25 +- Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl | 512 ++++++++++++++++++++ Platform/ARM/SgiPkg/AcpiTables/RdFremont/Madt.aslc | 138 ++++++ Platform/ARM/SgiPkg/AcpiTables/RdFremont/Pptt.aslc | 167 +++++++ Platform/ARM/SgiPkg/RdFremont/RdFremont.fdf.inc | 10 + 25 files changed, 1032 insertions(+), 83 deletions(-) copy Platform/ARM/SgiPkg/{SgiMemoryMap2.dsc.inc => SgiMemoryMap3.dsc.inc} (62%) copy Platform/ARM/SgiPkg/{RdV1/RdV1.dsc => RdFremont/RdFremont.dsc} (77%) create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdFremont/Madt.aslc create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdFremont/Pptt.aslc create mode 100644 Platform/ARM/SgiPkg/RdFremont/RdFremont.fdf.inc -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114445): https://edk2.groups.io/g/devel/message/114445 Mute This Topic: https://groups.io/mt/103959491/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- From: Vivek Gautam <vivek.gautam@arm.com> On RD-N2 and previous generation platforms, the base address was within 32-bit region. However, on upcoming platforms, the SMMUv3 base address is beyond 32-bit address region. So, update the datatype of SMMUv3 base PCD. Signed-off-by: Prabin CA <prabin.ca@arm.com> --- Platform/ARM/SgiPkg/SgiPlatform.dec | 2 +- Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec b/Platform/ARM/SgiPkg/SgiPlatform.dec index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/SgiPlatform.dec +++ b/Platform/ARM/SgiPkg/SgiPlatform.dec @@ -XXX,XX +XXX,XX @@ [PcdsFixedAtBuild] gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv|0|UINT32|0x00000014 # SMMU - gArmSgiTokenSpaceGuid.PcdSmmuBase|0|UINT32|0x0000001D + gArmSgiTokenSpaceGuid.PcdSmmuBase|0|UINT64|0x0000001D gArmSgiTokenSpaceGuid.PcdSmmuSize|0|UINT32|0x0000001E # GPIO Controller diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c +++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c @@ -XXX,XX +XXX,XX @@ /** @file * -* Copyright (c) 2018-2023, ARM Limited. All rights reserved. +* Copyright (c) 2018-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -XXX,XX +XXX,XX @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; // Sub System Peripherals - SMMU - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet32 (PcdSmmuBase); - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet32 (PcdSmmuBase); + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdSmmuBase); + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdSmmuBase); VirtualMemoryTable[Index].Length = FixedPcdGet32 (PcdSmmuSize); VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114446): https://edk2.groups.io/g/devel/message/114446 Mute This Topic: https://groups.io/mt/103959493/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- In preparation of adding the next generation of reference design platform that have different memory map, refactor the PcdSystemMemoryBase and PcdSystemMemorySize PCD definitions from the common PCD definitions file into the various platform generation specific memory map PCD definitions file. Signed-off-by: Prabin CA <prabin.ca@arm.com> --- Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc | 8 +++++++- Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc | 8 +++++++- Platform/ARM/SgiPkg/SgiPlatform.dsc.inc | 6 +----- 3 files changed, 15 insertions(+), 7 deletions(-) diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc b/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc +++ b/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc @@ -XXX,XX +XXX,XX @@ # -# Copyright (c) 2020 - 2022, Arm Limited. All rights reserved. +# Copyright (c) 2020 - 2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -XXX,XX +XXX,XX @@ [PcdsFixedAtBuild.common] gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress|0x1C1D0000 gArmSgiTokenSpaceGuid.PcdGpioController0Size|0x00010000 gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt|136 + + # System Memory (1GB - 16MB of Trusted DRAM at the top of the + # 32bit address space) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000 + diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc +++ b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc @@ -XXX,XX +XXX,XX @@ # -# Copyright (c) 2020 - 2023, Arm Limited. All rights reserved. +# Copyright (c) 2020 - 2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -XXX,XX +XXX,XX @@ [PcdsFixedAtBuild.common] # IO virtualization block gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlk0Base|0x1080000000 + + # System Memory (1GB - 16MB of Trusted DRAM at the top of the + # 32bit address space) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000 + diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc +++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc @@ -XXX,XX +XXX,XX @@ # -# Copyright (c) 2018 - 2022, ARM Limited. All rights reserved. +# Copyright (c) 2018 - 2024, Arm Limited. All rights reserved. # (C) Copyright 2021 Hewlett Packard Enterprise Development LP<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent @@ -XXX,XX +XXX,XX @@ [PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x40000 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x0 - # System Memory (1GB - 16MB of Trusted DRAM at the top of the 32bit address space) - gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 - gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000 - # ACPI Table Version gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114447): https://edk2.groups.io/g/devel/message/114447 Mute This Topic: https://groups.io/mt/103959494/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- Introducing a flag called PCIE_ENABLE, which can be set to TRUE or FALSE from the respective <platform>.dsc files to enable or disable the PCIe support. As not all reference design platforms have PCIe support enabled, this flag is introduced. Signed-off-by: Prabin CA <prabin.ca@arm.com> --- Platform/ARM/SgiPkg/SgiPlatform.dec | 1 + Platform/ARM/SgiPkg/SgiPlatform.dsc.inc | 6 ++++++ Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc | 4 +++- Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc | 4 +++- Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc | 4 +++- Platform/ARM/SgiPkg/RdV1/RdV1.dsc | 4 +++- Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.dsc | 4 +++- Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc | 4 +++- Platform/ARM/SgiPkg/SgiPlatform.fdf | 4 +++- Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf | 5 ++++- Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c | 19 +++++++++++-------- 11 files changed, 43 insertions(+), 16 deletions(-) diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec b/Platform/ARM/SgiPkg/SgiPlatform.dec index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/SgiPlatform.dec +++ b/Platform/ARM/SgiPkg/SgiPlatform.dec @@ -XXX,XX +XXX,XX @@ [Guids.common] [PcdsFeatureFlag.common] gArmSgiTokenSpaceGuid.PcdVirtioBlkSupported|FALSE|BOOLEAN|0x00000001 gArmSgiTokenSpaceGuid.PcdVirtioNetSupported|FALSE|BOOLEAN|0x00000010 + gArmSgiTokenSpaceGuid.PcdPcieEnable|FALSE|BOOLEAN|0x0000002E [PcdsFixedAtBuild] gArmSgiTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x00000002 diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc +++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc @@ -XXX,XX +XXX,XX @@ [PcdsFeatureFlag.common] gArmSgiTokenSpaceGuid.PcdVirtioNetSupported|TRUE gEfiMdeModulePkgTokenSpaceGuid.PcdEnableVariableRuntimeCache|FALSE +!if $(PCIE_ENABLE) == TRUE + gArmSgiTokenSpaceGuid.PcdPcieEnable|TRUE +!endif + [PcdsFixedAtBuild.common] gArmTokenSpaceGuid.PcdVFPEnabled|1 gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 @@ -XXX,XX +XXX,XX @@ [Components.common] # Virtio Network OvmfPkg/VirtioNetDxe/VirtioNet.inf +!if $(PCIE_ENABLE) == TRUE # # Required by PCI # @@ -XXX,XX +XXX,XX @@ [Components.common] <PcdsFixedAtBuild> gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F } +!endif # # AHCI Support diff --git a/Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc b/Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc +++ b/Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc @@ -XXX,XX +XXX,XX @@ # -# Copyright (c) 2020-2022, ARM Limited. All rights reserved. +# Copyright (c) 2020-2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -XXX,XX +XXX,XX @@ [Defines] BOARD_DXE_FV_COMPONENTS = Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.fdf.inc BUILD_NUMBER = 1 + DEFINE PCIE_ENABLE = TRUE + # include common definitions from SgiPlatform.dsc !include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc !include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc diff --git a/Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc b/Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc +++ b/Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc @@ -XXX,XX +XXX,XX @@ # -# Copyright (c) 2020-2022, ARM Limited. All rights reserved. +# Copyright (c) 2020-2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -XXX,XX +XXX,XX @@ [Defines] BOARD_DXE_FV_COMPONENTS = Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.fdf.inc BUILD_NUMBER = 1 + DEFINE PCIE_ENABLE = TRUE + # include common definitions from SgiPlatform.dsc !include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc !include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc diff --git a/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc b/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc +++ b/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc @@ -XXX,XX +XXX,XX @@ # -# Copyright (c) 2020-2022, ARM Limited. All rights reserved. +# Copyright (c) 2020-2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -XXX,XX +XXX,XX @@ [Defines] BOARD_DXE_FV_COMPONENTS = Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.fdf.inc BUILD_NUMBER = 1 + DEFINE PCIE_ENABLE = TRUE + # include common definitions from SgiPlatform.dsc !include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc !include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc diff --git a/Platform/ARM/SgiPkg/RdV1/RdV1.dsc b/Platform/ARM/SgiPkg/RdV1/RdV1.dsc index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/RdV1/RdV1.dsc +++ b/Platform/ARM/SgiPkg/RdV1/RdV1.dsc @@ -XXX,XX +XXX,XX @@ # -# Copyright (c) 2020-2022, ARM Limited. All rights reserved. +# Copyright (c) 2020-2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -XXX,XX +XXX,XX @@ [Defines] BOARD_DXE_FV_COMPONENTS = Platform/ARM/SgiPkg/RdV1/RdV1.fdf.inc BUILD_NUMBER = 1 + DEFINE PCIE_ENABLE = TRUE + # include common definitions from SgiPlatform.dsc !include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc !include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc diff --git a/Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.dsc b/Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.dsc index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.dsc +++ b/Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.dsc @@ -XXX,XX +XXX,XX @@ # -# Copyright (c) 2020-2022, ARM Limited. All rights reserved. +# Copyright (c) 2020-2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -XXX,XX +XXX,XX @@ [Defines] BOARD_DXE_FV_COMPONENTS = Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.fdf.inc BUILD_NUMBER = 1 + DEFINE PCIE_ENABLE = TRUE + # include common definitions from SgiPlatform.dsc !include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc !include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc diff --git a/Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc b/Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc +++ b/Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc @@ -XXX,XX +XXX,XX @@ # -# Copyright (c) 2020-2022, ARM Limited. All rights reserved. +# Copyright (c) 2020-2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -XXX,XX +XXX,XX @@ [Defines] BOARD_DXE_FV_COMPONENTS = Platform/ARM/SgiPkg/Sgi575/Sgi575.fdf.inc BUILD_NUMBER = 1 + DEFINE PCIE_ENABLE = TRUE + # include common definitions from SgiPlatform.dsc !include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc !include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc diff --git a/Platform/ARM/SgiPkg/SgiPlatform.fdf b/Platform/ARM/SgiPkg/SgiPlatform.fdf index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/SgiPlatform.fdf +++ b/Platform/ARM/SgiPkg/SgiPlatform.fdf @@ -XXX,XX +XXX,XX @@ # -# Copyright (c) 2018-2021, ARM Limited. All rights reserved. +# Copyright (c) 2018-2024, ARM Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -XXX,XX +XXX,XX @@ [FV.FvMain] INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf INF Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf +!if $(PCIE_ENABLE) == TRUE # Required by PCI INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf @@ -XXX,XX +XXX,XX @@ [FV.FvMain] # INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf +!endif # # AHCI Support diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf +++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf @@ -XXX,XX +XXX,XX @@ # -# Copyright (c) 2018 - 2023, Arm Limited. All rights reserved. +# Copyright (c) 2018 - 2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -XXX,XX +XXX,XX @@ [Sources.common] [Sources.AARCH64] AArch64/Helper.S | GCC +[FeaturePcd] + gArmSgiTokenSpaceGuid.PcdPcieEnable + [FixedPcd] gArmPlatformTokenSpaceGuid.PcdClusterCount gArmPlatformTokenSpaceGuid.PcdCoreCount diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c +++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c @@ -XXX,XX +XXX,XX @@ // Total number of descriptors, including the final "end-of-table" descriptor. #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS \ - ((14 + (FixedPcdGet32 (PcdChipCount) * 2)) + \ + ((13 + (FixedPcdGet32 (PcdChipCount) * 2)) + \ + (FeaturePcdGet (PcdPcieEnable)) + \ (FixedPcdGet32 (PcdIoVirtSocExpBlkUartEnable) * \ FixedPcdGet32 (PcdChipCount) * 2)) @@ -XXX,XX +XXX,XX @@ ArmPlatformGetVirtualMemoryMap ( #endif #endif - // PCI Configuration Space - VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciExpressBaseAddress); - VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciExpressBaseAddress); - VirtualMemoryTable[Index].Length = (FixedPcdGet32 (PcdPciBusMax) - - FixedPcdGet32 (PcdPciBusMin) + 1) * - SIZE_1MB; - VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + if (FeaturePcdGet (PcdPcieEnable)) { + // PCI Configuration Space + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciExpressBaseAddress); + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciExpressBaseAddress); + VirtualMemoryTable[Index].Length = (FixedPcdGet32 (PcdPciBusMax) - + FixedPcdGet32 (PcdPciBusMin) + 1) * + SIZE_1MB; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + } // MM Memory Space VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdMmBufferBase); -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114448): https://edk2.groups.io/g/devel/message/114448 Mute This Topic: https://groups.io/mt/103959495/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- From: Shriram K <shriram.k@arm.com> RD-Fremont is the next platform in the Arm's reference design platform series. This platform includes 32 CPUs but the fixed virtual platform (FVP) simulates 16 CPUs of the platform. There is one CPU per cluster in the system and so the FVP simulates 16 clusters. In preparation for adding support for this platform, add the initial set of ACPI tables and reuse existing ACPI tables as applicable to boot a operating system on this platform. Signed-off-by: Prabin CA <prabin.ca@arm.com> --- Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf | 73 ++++++++ Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl | 196 ++++++++++++++++++++ Platform/ARM/SgiPkg/AcpiTables/RdFremont/Madt.aslc | 138 ++++++++++++++ Platform/ARM/SgiPkg/AcpiTables/RdFremont/Pptt.aslc | 167 +++++++++++++++++ 4 files changed, 574 insertions(+) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf @@ -XXX,XX +XXX,XX @@ +## @file +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2024, Arm Ltd. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = RdFremontAcpiTables + FILE_GUID = c712719a-0aaf-438c-9cdd-35ab4d60207d # gArmSgiAcpiTablesGuid + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + +[Sources] + Dbg2.aslc + Fadt.aslc + Gtdt.aslc + RdFremont/Dsdt.asl + RdFremont/Madt.aslc + RdFremont/Pptt.aslc + Spcr.aslc + SsdtEvents.asl + SsdtRos.asl + SsdtRosVirtioP9.asl + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/ARM/SgiPkg/SgiPlatform.dec + +[FixedPcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + + gArmPlatformTokenSpaceGuid.PcdSerialDbgInterrupt + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase + gArmPlatformTokenSpaceGuid.PL011UartInterrupt + gArmPlatformTokenSpaceGuid.PcdCoreCount + gArmPlatformTokenSpaceGuid.PcdClusterCount + + gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress + gArmSgiTokenSpaceGuid.PcdGpioController0Size + gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt + gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv + gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv + gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress + gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize + gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt + gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress + gArmSgiTokenSpaceGuid.PcdVirtioBlkSize + gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt + gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress + gArmSgiTokenSpaceGuid.PcdVirtioNetSize + gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt + gArmSgiTokenSpaceGuid.PcdVirtioP9BaseAddress + gArmSgiTokenSpaceGuid.PcdVirtioP9Size + gArmSgiTokenSpaceGuid.PcdVirtioP9Interrupt + gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv + gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv + + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl @@ -XXX,XX +XXX,XX @@ +/** @file +* Differentiated System Description Table Fields (DSDT) +* +* Copyright (c) 2024, Arm Limited. All rights reserved.<BR> +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +* @par Specification Reference: +* - ACPI 6.5, Chapter 5, Section 5.2.11.1, Differentiated System Description +* Table (DSDT) +* +**/ + +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" + +DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", + EFI_ACPI_ARM_OEM_REVISION) { + Scope (_SB) { + Device (CL00) { // Cluster 0 + Name (_HID, "ACPI0010") + Name (_UID, 0) + + Device (CP00) { // Neoverse Poseidon core 0 + Name (_HID, "ACPI0007") + Name (_UID, 0) + Name (_STA, 0xF) + } + } + + Device (CL01) { // Cluster 1 + Name (_HID, "ACPI0010") + Name (_UID, 1) + + Device (CP01) { // Neoverse Poseidon core 1 + Name (_HID, "ACPI0007") + Name (_UID, 1) + Name (_STA, 0xF) + } + } + + Device (CL02) { // Cluster 2 + Name (_HID, "ACPI0010") + Name (_UID, 2) + + Device (CP02) { // Neoverse Poseidon core 2 + Name (_HID, "ACPI0007") + Name (_UID, 2) + Name (_STA, 0xF) + } + } + + Device (CL03) { // Cluster 3 + Name (_HID, "ACPI0010") + Name (_UID, 3) + + Device (CP03) { // Neoverse Poseidon core 3 + Name (_HID, "ACPI0007") + Name (_UID, 3) + Name (_STA, 0xF) + } + } + + Device (CL04) { // Cluster 4 + Name (_HID, "ACPI0010") + Name (_UID, 4) + + Device (CP04) { // Neoverse Poseidon core 4 + Name (_HID, "ACPI0007") + Name (_UID, 4) + Name (_STA, 0xF) + } + } + + Device (CL05) { // Cluster 5 + Name (_HID, "ACPI0010") + Name (_UID, 5) + + Device (CP05) { // Neoverse Poseidon core 5 + Name (_HID, "ACPI0007") + Name (_UID, 5) + Name (_STA, 0xF) + } + } + + Device (CL06) { // Cluster 6 + Name (_HID, "ACPI0010") + Name (_UID, 6) + + Device (CP06) { // Neoverse Poseidon core 6 + Name (_HID, "ACPI0007") + Name (_UID, 6) + Name (_STA, 0xF) + } + } + + Device (CL07) { // Cluster 7 + Name (_HID, "ACPI0010") + Name (_UID, 7) + + Device (CP07) { // Neoverse Poseidon core 7 + Name (_HID, "ACPI0007") + Name (_UID, 7) + Name (_STA, 0xF) + } + } + + Device (CL08) { // Cluster 8 + Name (_HID, "ACPI0010") + Name (_UID, 8) + + Device (CP08) { // Neoverse Poseidon core 8 + Name (_HID, "ACPI0007") + Name (_UID, 8) + Name (_STA, 0xF) + } + } + + Device (CL09) { // Cluster 9 + Name (_HID, "ACPI0010") + Name (_UID, 9) + + Device (CP09) { // Neoverse Poseidon core 9 + Name (_HID, "ACPI0007") + Name (_UID, 9) + Name (_STA, 0xF) + } + } + + Device (CL10) { // Cluster 10 + Name (_HID, "ACPI0010") + Name (_UID, 10) + + Device (CP10) { // Neoverse Poseidon core 10 + Name (_HID, "ACPI0007") + Name (_UID, 10) + Name (_STA, 0xF) + } + } + + Device (CL11) { // Cluster 11 + Name (_HID, "ACPI0010") + Name (_UID, 11) + + Device (CP11) { // Neoverse Poseidon core 11 + Name (_HID, "ACPI0007") + Name (_UID, 11) + Name (_STA, 0xF) + } + } + + Device (CL12) { // Cluster 12 + Name (_HID, "ACPI0010") + Name (_UID, 12) + + Device (CP12) { // Neoverse Poseidon core 12 + Name (_HID, "ACPI0007") + Name (_UID, 12) + Name (_STA, 0xF) + } + } + + Device (CL13) { // Cluster 13 + Name (_HID, "ACPI0010") + Name (_UID, 13) + + Device (CP13) { // Neoverse Poseidon core 13 + Name (_HID, "ACPI0007") + Name (_UID, 13) + Name (_STA, 0xF) + } + } + + Device (CL14) { // Cluster 14 + Name (_HID, "ACPI0010") + Name (_UID, 14) + + Device (CP14) { // Neoverse Poseidon core 14 + Name (_HID, "ACPI0007") + Name (_UID, 14) + Name (_STA, 0xF) + } + } + + Device (CL15) { // Cluster 15 + Name (_HID, "ACPI0010") + Name (_UID, 15) + + Device (CP15) { // Neoverse Poseidon core 15 + Name (_HID, "ACPI0007") + Name (_UID, 15) + Name (_STA, 0xF) + } + } + } // Scope(_SB) +} diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Madt.aslc new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Madt.aslc @@ -XXX,XX +XXX,XX @@ +/** @file +* Multiple APIC Description Table (MADT) +* +* Copyright (c) 2024, Arm Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include <Library/AcpiLib.h> +#include <Library/ArmLib.h> +#include <Library/PcdLib.h> + +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" + +#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \ + FixedPcdGet32 (PcdCoreCount)) + +// Multiple APIC Description Table +#pragma pack (1) + +typedef struct { + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_4_GIC_STRUCTURE GicInterfaces[CORE_CNT]; + EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor; + EFI_ACPI_6_4_GIC_ITS_STRUCTURE GicIts[6]; +} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE; + +#pragma pack () + +STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + ), + // MADT specific fields + 0, // LocalApicAddress + 0 // Flags + }, + { + // Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, + // PmuIrq, GicBase, GicVBase, + // GicHBase, GsivId, GicRBase, + // Efficiency, + // SpeOverflowInterrupt) + // Note: The GIC Structure of the primary CPU must be the first entry + // (see note in 5.2.12.14 GICC Structure of ACPI v6.4). + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core0 + 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core1 + 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core2 + 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core3 + 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core4 + 0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core5 + 0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core6 + 0, 6, GET_MPID(0x600, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core7 + 0, 7, GET_MPID(0x700, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core8 + 0, 8, GET_MPID(0x800, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core9 + 0, 9, GET_MPID(0x900, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core10 + 0, 10, GET_MPID(0xa00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core11 + 0, 11, GET_MPID(0xb00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core12 + 0, 12, GET_MPID(0xc00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core13 + 0, 13, GET_MPID(0xd00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core14 + 0, 14, GET_MPID(0xe00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core15 + 0, 15, GET_MPID(0xf00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + }, + // GIC Distributor Entry + EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), + 0, 3), + // GIC Redistributor + EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase), + SIZE_16MB), + // GIC ITS + { + EFI_ACPI_6_4_GIC_ITS_INIT(0, 0x30040000), + EFI_ACPI_6_4_GIC_ITS_INIT(1, 0x30080000), + EFI_ACPI_6_4_GIC_ITS_INIT(2, 0x300C0000), + EFI_ACPI_6_4_GIC_ITS_INIT(3, 0x30100000), + EFI_ACPI_6_4_GIC_ITS_INIT(4, 0x30140000), + EFI_ACPI_6_4_GIC_ITS_INIT(5, 0x30180000), + }, +}; + +// +// Reference the table being generated to prevent the optimizer from removing +// the data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Madt; diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Pptt.aslc new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Pptt.aslc @@ -XXX,XX +XXX,XX @@ +/** @file +* Processor Properties Topology Table (PPTT) for RD-Fremont platform +* +* Copyright (c) 2024, Arm Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +* This file describes the topological structure of the processor block on the +* RD-Fremont platform in the form as defined by ACPI PPTT table. The RD-Fremont +* platform includes sixteen single-thread CPUs. Each of the CPUs include 64KB +* L1 Data cache, 64KB L1 Instruction cache and 2MB L2 cache. +* +* @par Specification Reference: +* - ACPI 6.4, Chapter 5, Section 5.2.29, Processor Properties Topology Table +**/ + +#include <IndustryStandard/Acpi.h> +#include <Library/AcpiLib.h> +#include <Library/ArmLib.h> +#include <Library/PcdLib.h> + +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" + +/** Define helper macro for populating processor core information. + + @param [in] PackageId Package instance number. + @param [in] ClusterId Cluster instance number. + @param [in] CpuId CPU instance number. +**/ +#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) \ + { \ + /* Parameters for CPU Core */ \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \ + OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ \ + PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \ + Package.Cluster[ClusterId]), /* Parent */ \ + ((PackageId << 4) | ClusterId), /* ACPI Id */ \ + 2 /* Num of private resource */ \ + ), \ + \ + /* Offsets of the private resources */ \ + { \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \ + Package.Cluster[ClusterId].Core[CpuId].DCache), \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \ + Package.Cluster[ClusterId].Core[CpuId].ICache) \ + }, \ + \ + /* L1 data cache parameters */ \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \ + Package.Cluster[ClusterId].Core[CpuId].L2Cache), \ + /* Next level of cache */ \ + SIZE_64KB, /* Size */ \ + 256, /* Num of sets */ \ + 4, /* Associativity */ \ + PPTT_DATA_CACHE_ATTR, /* Attributes */ \ + 64, /* Line size */ \ + RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1DataCache) \ + /* Cache id */ \ + ), \ + \ + /* L1 instruction cache parameters */ \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \ + Package.Cluster[ClusterId].Core[CpuId].L2Cache), \ + /* Next level of cache */ \ + SIZE_64KB, /* Size */ \ + 256, /* Num of sets */ \ + 4, /* Associativity */ \ + PPTT_INST_CACHE_ATTR, /* Attributes */ \ + 64, /* Line size */ \ + RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1InstructionCache) \ + /* Cache id */ \ + ), \ + \ + /* L2 cache parameters */ \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \ + 0, /* Next level of cache */ \ + SIZE_2MB, /* Size */ \ + 4096, /* Num of sets */ \ + 8, /* Associativity */ \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \ + 64, /* Line size */ \ + RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L2Cache) \ + /* Cache id */ \ + ), \ + } + +/** Define helper macro for populating processor container information. + + @param [in] PackageId Package instance number. + @param [in] ClusterId Cluster instance number. +**/ +#define PPTT_CLUSTER_INIT(PackageId, ClusterId) \ + { \ + /* Parameters for Cluster */ \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( \ + OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ \ + PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \ + Package), /* Parent */ \ + ((PackageId << 4) | ClusterId), /* ACPI Id */ \ + 0 /* Num of private resource */ \ + ), \ + \ + /* Initialize child core */ \ + { \ + PPTT_CORE_INIT (PackageId, ClusterId, 0) \ + } \ + } + +#pragma pack(1) +/* + * Processor Properties Topology Table + */ +typedef struct { + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + RD_PPTT_PACKAGE Package; +} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +#pragma pack () + +STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + ) + }, + + { + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( + OFFSET_OF (RD_PPTT_PACKAGE, Cluster[0]), + PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0), + + { + PPTT_CLUSTER_INIT (0, 0), + PPTT_CLUSTER_INIT (0, 1), + PPTT_CLUSTER_INIT (0, 2), + PPTT_CLUSTER_INIT (0, 3), + PPTT_CLUSTER_INIT (0, 4), + PPTT_CLUSTER_INIT (0, 5), + PPTT_CLUSTER_INIT (0, 6), + PPTT_CLUSTER_INIT (0, 7), + PPTT_CLUSTER_INIT (0, 8), + PPTT_CLUSTER_INIT (0, 9), + PPTT_CLUSTER_INIT (0, 10), + PPTT_CLUSTER_INIT (0, 11), + PPTT_CLUSTER_INIT (0, 12), + PPTT_CLUSTER_INIT (0, 13), + PPTT_CLUSTER_INIT (0, 14), + PPTT_CLUSTER_INIT (0, 15) + } + } +}; + +/* + * Reference the table being generated to prevent the optimizer from removing + * the data structure from the executable + */ +VOID* CONST ReferenceAcpiTable = &Pptt; -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114449): https://edk2.groups.io/g/devel/message/114449 Mute This Topic: https://groups.io/mt/103959497/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- The RD-Fremont fixed virtual platform simulates 16 CPUs and 8GB of RAM. Add initial support for this platform by adding the required platform build configuration files. This platform has considerable differences in its memory map compared to its predecessors. So add a corresponding memory map file as well to define the PCDs for its generation of platforms. Signed-off-by: Prabin CA <prabin.ca@arm.com> --- Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc | 71 ++++++++++++++++++++ Platform/ARM/SgiPkg/RdFremont/RdFremont.dsc | 55 +++++++++++++++ Platform/ARM/SgiPkg/RdFremont/RdFremont.fdf.inc | 10 +++ 3 files changed, 136 insertions(+) diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc b/Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc @@ -XXX,XX +XXX,XX @@ +# +# Copyright (c) 2024, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[PcdsFixedAtBuild.common] + # System Peripherals + gArmSgiTokenSpaceGuid.PcdSmcCs0Base|0x08000000 + gArmSgiTokenSpaceGuid.PcdSmcCs1Base|0x0600000000 + gArmSgiTokenSpaceGuid.PcdSysPeriphBase|0x0C000000 + gArmSgiTokenSpaceGuid.PcdSysPeriphSysRegBase|0x0C010000 + + # SP804 dual timer + gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress|0x0C110000 + gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize|0x00010000 + gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt|216 + + # Virtio Disk + gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress|0x0C130000 + gArmSgiTokenSpaceGuid.PcdVirtioBlkSize|0x10000 + gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt|184 + + # GPIO controller + gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress|0x0C1D0000 + gArmSgiTokenSpaceGuid.PcdGpioController0Size|0x00010000 + gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt|168 + + # Ethernet + gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress|0x0C150000 + gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt|186 + + # PL031 RealTimeClock + gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0C170000 + + # Virtio P9 + gArmSgiTokenSpaceGuid.PcdVirtioP9BaseAddress|0x0C190000 + gArmSgiTokenSpaceGuid.PcdVirtioP9Size|0x10000 + gArmSgiTokenSpaceGuid.PcdVirtioP9Interrupt|185 + + # PL370 - HDLCD1 + gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0EF60000 + + # PL011 - Serial Debug UART + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x0EF70000 + gArmPlatformTokenSpaceGuid.PcdSerialDbgInterrupt|179 + + # PL011 - Serial Terminal + gArmPlatformTokenSpaceGuid.PL011UartInterrupt|112 + + # System Memory (2GB - 128MB of Trusted DRAM at the top of the 32bit address space) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x78000000 + + # SMMU + gArmSgiTokenSpaceGuid.PcdSmmuBase|0x280000000 + gArmSgiTokenSpaceGuid.PcdSmmuSize|0x4000000 + + # Non-Volatile variable storage + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x0600000000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x0601400000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x0602800000 + + # Address bus width - 64TB address space + gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip|46 + + # Timer & Watchdog interrupts + gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv|109 + gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv|108 + gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv|110 + gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv|111 diff --git a/Platform/ARM/SgiPkg/RdFremont/RdFremont.dsc b/Platform/ARM/SgiPkg/RdFremont/RdFremont.dsc new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/ARM/SgiPkg/RdFremont/RdFremont.dsc @@ -XXX,XX +XXX,XX @@ +# +# Copyright (c) 2024, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = RdFremont + PLATFORM_GUID = fd140b0f-4467-4314-aa69-cd0bd712e08e + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x0001001B + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = NOOPT|DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/ARM/SgiPkg/SgiPlatform.fdf + BOARD_DXE_FV_COMPONENTS = Platform/ARM/SgiPkg/RdFremont/RdFremont.fdf.inc + BUILD_NUMBER = 1 + +# include common definitions from SgiPlatform.dsc +!include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc +!include Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc + +# include common/basic libraries from MdePkg. +!include MdePkg/MdeLibs.dsc.inc + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + +[PcdsFixedAtBuild.common] + # GIC Base Addresses + gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x301C0000 + gArmSgiTokenSpaceGuid.PcdGicSize|0x200000 + + # ARM Cores and Clusters + gArmPlatformTokenSpaceGuid.PcdCoreCount|1 + gArmPlatformTokenSpaceGuid.PcdClusterCount|16 + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ + +[Components.common] + Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf diff --git a/Platform/ARM/SgiPkg/RdFremont/RdFremont.fdf.inc b/Platform/ARM/SgiPkg/RdFremont/RdFremont.fdf.inc new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/ARM/SgiPkg/RdFremont/RdFremont.fdf.inc @@ -XXX,XX +XXX,XX @@ +# +# Copyright (c) 2024, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +# Per-platform additional content of the DXE phase firmware volume + + # ACPI support + INF RuleOverride=ACPITABLE Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114450): https://edk2.groups.io/g/devel/message/114450 Mute This Topic: https://groups.io/mt/103959498/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- Extend the SMBIOS support for RD-Fremont platform. RD-Fremont is a 16 core platform with Poseidon CPU. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 2MB L2 cache. The platform also includes system level cache of 32MB and 8GB of RAM. Signed-off-by: Prabin CA <prabin.ca@arm.com> --- Platform/ARM/SgiPkg/Include/SgiPlatform.h | 5 +++++ Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c | 5 ++++- Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c | 5 ++++- Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c | 1 + Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c | 6 ++++++ 5 files changed, 20 insertions(+), 2 deletions(-) diff --git a/Platform/ARM/SgiPkg/Include/SgiPlatform.h b/Platform/ARM/SgiPkg/Include/SgiPlatform.h index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/Include/SgiPlatform.h +++ b/Platform/ARM/SgiPkg/Include/SgiPlatform.h @@ -XXX,XX +XXX,XX @@ #define RD_V2_PART_NUM 0x7F2 #define RD_V2_CONF_ID 0x1 +// RD-Fremont Platform Identification values +#define RD_Fremont_PART_NUM 0x7EE +#define RD_Fremont_CONF_ID 0x1 + #define SGI_CONFIG_MASK 0x0F #define SGI_CONFIG_SHIFT 0x1C #define SGI_PART_NUM_MASK 0xFFF @@ -XXX,XX +XXX,XX @@ typedef enum { RdN2Cfg1, RdN2Cfg2, RdV2, + RdFremont, } ARM_RD_PRODUCT_ID; // Arm ProductId look-up table diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c +++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c @@ -XXX,XX +XXX,XX @@ "RdN2\0" \ "RdN2Cfg1\0" \ "RdN2Cfg2\0" \ - "RdV2\0" + "RdV2\0" \ + "RdFremont\0" typedef enum { ManufacturerName = 1, @@ -XXX,XX +XXX,XX @@ STATIC GUID mSmbiosUid[] = { {0xd2946d07, 0x8057, 0x4c26, {0xbf, 0x53, 0x78, 0xa6, 0x5b, 0xe1, 0xc1, 0x60}}, /* Rd-V2 */ {0x3b1180a3, 0x0744, 0x4194, {0xae, 0x2e, 0xed, 0xa5, 0xbc, 0x2e, 0x43, 0x45}}, + /* Rd-Fremont */ + {0x904b28d6, 0x0662, 0x11ed, {0xb9, 0x39, 0x02, 0x42, 0xac, 0x12, 0x00, 0x02}}, }; /* System information */ diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c +++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c @@ -XXX,XX +XXX,XX @@ "Neoverse-N2\0" \ "Neoverse-N2\0" \ "Neoverse-V2\0" \ + "Neoverse-Poseidon\0" \ "000-0\0" /* Serial number */ \ "783-3\0" \ "786-1\0" \ @@ -XXX,XX +XXX,XX @@ "7B7-1\0" \ "7B6-1\0" \ "7B7-1\0" \ - "7F2-1\0" + "7F2-1\0" \ + "7EE-1\0" typedef enum { PartNumber = 1, @@ -XXX,XX +XXX,XX @@ InstallType4ProcessorInformation ( case RdN2: case RdN2Cfg1: case RdV2: + case RdFremont: mArmRdSmbiosType4.Base.CoreCount = CoreCount; mArmRdSmbiosType4.Base.EnabledCoreCount = CoreCount; mArmRdSmbiosType4.Base.ThreadCount = CoreCount; diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c +++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c @@ -XXX,XX +XXX,XX @@ InstallType7CacheInformation ( mArmRdSmbiosType7[4].Base.Associativity = CacheAssociativity16Way; break; case RdV2: + case RdFremont: /* L1 instruction cache */ mArmRdSmbiosType7[0].Base.MaximumCacheSize2 = 64; // 64KB mArmRdSmbiosType7[0].Base.InstalledSize2 = 64; // 64KB diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c +++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c @@ -XXX,XX +XXX,XX @@ STATIC CONST SGI_PRODUCT_ID_LOOKUP SgiProductIdLookup[] = { RD_V2_CONF_ID, 0 }, + { + RdFremont, + RD_Fremont_PART_NUM, + RD_Fremont_CONF_ID, + 0 + }, }; EFI_BOOT_MODE -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114451): https://edk2.groups.io/g/devel/message/114451 Mute This Topic: https://groups.io/mt/103959499/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- RD-Fremont platform supports two LPI states, LPI1 (Standby WFI) and LPI3 (Power-down). The cluster supports LPI2 (Power-down) state. The LPI implementation also supports combined power state for core and cluster. Signed-off-by: Prabin CA <prabin.ca@arm.com> --- Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf | 1 + Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl | 154 ++++++++++++++++++++ 2 files changed, 155 insertions(+) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf @@ -XXX,XX +XXX,XX @@ [FixedPcd] gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv + gArmSgiTokenSpaceGuid.PcdOscLpiEnable gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl +++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl @@ -XXX,XX +XXX,XX @@ * @par Specification Reference: * - ACPI 6.5, Chapter 5, Section 5.2.11.1, Differentiated System Description * Table (DSDT) +* - ACPI 6.5, Chapter 8, Section 8.4.3, Lower Power Idle States +* - Arm Functional Fixed Hardware Specification v1.2, Chapter 3, Section 3.1, +* Idle management and Low Power Idle states * **/ @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", EFI_ACPI_ARM_OEM_REVISION) { Scope (_SB) { + /* _OSC: Operating System Capabilities */ + Method (_OSC, 4, Serialized) { + CreateDWordField (Arg3, 0x00, STS0) + CreateDWordField (Arg3, 0x04, CAP0) + + /* Platform-wide Capabilities */ + If (LEqual (Arg0, ToUUID("0811b06e-4a27-44f9-8d60-3cbbc22e7b48"))) { + /* OSC rev 1 supported, for other version, return failure */ + If (LEqual (Arg1, One)) { + And (STS0, Not (OSC_STS_MASK), STS0) + + If (And (CAP0, OSC_CAP_OS_INITIATED_LPI)) { + /* OS initiated LPI not supported */ + And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0) + Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0) + } + + If (And (CAP0, OSC_CAP_PLAT_COORDINATED_LPI)) { + if (LEqual (FixedPcdGet32 (PcdOscLpiEnable), Zero)) { + And (CAP0, Not (OSC_CAP_PLAT_COORDINATED_LPI), CAP0) + Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0) + } + } + } Else { + And (STS0, Not (OSC_STS_MASK), STS0) + Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0) + } + } Else { + And (STS0, Not (OSC_STS_MASK), STS0) + Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_UUID), STS0) + } + + Return (Arg3) + } + + Name (PLPI, Package () { /* LPI for Processor, support 2 LPI states */ + 0, // Version + 0, // Level Index + 2, // Count + Package () { // WFI for CPU + 1, // Min residency (uS) + 1, // Wake latency (uS) + 1, // Flags + 0, // Arch Context lost Flags (no loss) + 0, // Residency Counter Frequency + 0, // No parent state + ResourceTemplate () { // Register Entry method + Register (FFixedHW, + 32, // Bit Width + 0, // Bit Offset + 0xFFFFFFFF, // Address + 3, // Access Size + ) + }, + ResourceTemplate () { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate () { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "LPI1-Core" + }, + Package () { // Power Gating state for CPU + 150, // Min residency (uS) + 350, // Wake latency (uS) + 1, // Flags + 1, // Arch Context lost Flags (Core context lost) + 0, // Residency Counter Frequency + 0, // No parent state + ResourceTemplate () { // Register Entry method + Register (FFixedHW, + 32, // Bit Width + 0, // Bit Offset + 0x40000002, // Address (PwrLvl:core, StateTyp:PwrDn) + 3, // Access Size + ) + }, + ResourceTemplate () { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate () { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "LPI3-Core" + }, + }) + Device (CL00) { // Cluster 0 Name (_HID, "ACPI0010") Name (_UID, 0) @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 0) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 1) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 2) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 3) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 4) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 5) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 6) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 7) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 8) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 9) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 10) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 11) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 12) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 13) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 14) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_HID, "ACPI0007") Name (_UID, 15) Name (_STA, 0xF) + + Method (_LPI, 0, NotSerialized) { + Return (\_SB.PLPI) + } } } } // Scope(_SB) -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114452): https://edk2.groups.io/g/devel/message/114452 Mute This Topic: https://groups.io/mt/103959501/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- Enable ACPI CPPC mechanism for RD-Fremont as defined by the ACPI specification. The implementation uses AMU registers accessible as Fixed-feature Hardware (FFixedHW) for monitoring the performance. Non-secure SCMI fastchannels are used to communicate with LCP to set the desired performance. RD-Fremont platform does not support CPPC revision 1 and below. So update the _OSC method to let OSPM know about this fact. Signed-off-by: Prabin CA <prabin.ca@arm.com> --- Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf | 1 + Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl | 162 ++++++++++++++++++++ 2 files changed, 163 insertions(+) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf @@ -XXX,XX +XXX,XX @@ [FixedPcd] gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv + gArmSgiTokenSpaceGuid.PcdOscCppcEnable gArmSgiTokenSpaceGuid.PcdOscLpiEnable gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl index XXXXXXX..XXXXXXX 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl +++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl @@ -XXX,XX +XXX,XX @@ * - ACPI 6.5, Chapter 8, Section 8.4.3, Lower Power Idle States * - Arm Functional Fixed Hardware Specification v1.2, Chapter 3, Section 3.1, * Idle management and Low Power Idle states +* - ACPI 6.5, Chapter 8, Section 8.4.6, Collaborative Processor Performance +* Control +* - Arm Functional Fixed Hardware Specification v1.2, Chapter 3, Section 3.2, +* Performance management and Collaborative Processor Performance Control * **/ @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0) } } + + If (And (CAP0, OSC_CAP_CPPC_SUPPORT)) { + /* CPPC revision 1 and below not supported */ + And (CAP0, Not (OSC_CAP_CPPC_SUPPORT), CAP0) + Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0) + } + + If (And (CAP0, OSC_CAP_CPPC2_SUPPORT)) { + if (LEqual (FixedPcdGet32 (PcdOscCppcEnable), Zero)) { + And (CAP0, Not (OSC_CAP_CPPC2_SUPPORT), CAP0) + Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0) + } + } + } Else { And (STS0, Not (OSC_STS_MASK), STS0) Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0) @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 0) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x200093000, 0x200093004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (0) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 1) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x200293000, 0x200293004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (1) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 2) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x200493000, 0x200493004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (2) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 3) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x200693000, 0x200693004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (3) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 4) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x200893000, 0x200893004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (4) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 5) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x200A93000, 0x200A93004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (5) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 6) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x200C93000, 0x200C93004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (6) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 7) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x200E93000, 0x200E93004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (7) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 8) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x201093000, 0x201093004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (8) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 9) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x201293000, 0x201293004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (9) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 10) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x201493000, 0x201493004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (10) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 11) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x201693000, 0x201693004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (11) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 12) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x201893000, 0x201893004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (12) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 13) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x201A93000, 0x201A93004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (13) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 14) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x201C93000, 0x201C93004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (14) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", Name (_UID, 15) Name (_STA, 0xF) + Name (_CPC, Package() + CPPC_PACKAGE_INIT (0x201E93000, 0x201E93004, 20, 160, 160, 85, 85, 5) + ) + + Name (_PSD, Package () { + Package () + PSD_INIT (15) + }) + Method (_LPI, 0, NotSerialized) { Return (\_SB.PLPI) } -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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