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([171.76.83.136]) by smtp.gmail.com with ESMTPSA id s16-20020a62e710000000b006ce3bf7acc7sm9985388pfh.113.2023.12.13.06.59.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 06:59:40 -0800 (PST) From: "Dhaval Sharma" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Laszlo Ersek , Pedro Falcato Subject: [edk2-devel] [PATCH v10 1/5] MdePkg: Move RISC-V Cache Management Declarations Into BaseLib Date: Wed, 13 Dec 2023 20:29:27 +0530 Message-Id: <20231213145931.28307-2-dhaval@rivosinc.com> In-Reply-To: <20231213145931.28307-1-dhaval@rivosinc.com> References: <20231213145931.28307-1-dhaval@rivosinc.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dhaval@rivosinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1702479584220100005 Content-Type: text/plain; charset="utf-8" The declarations for cache Management functions belong to BaseLib instead of instance source file. This helps with further restructuring of cache management code for RISC-V. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Laszlo Ersek Cc: Pedro Falcato Signed-off-by: Dhaval Sharma Reviewed-by: Laszlo Ersek --- Notes: V7: - Added RB tag V6: - Move cache management function declaration in baselib where it belongs MdePkg/Include/Library/BaseLib.h | 20 +++++++++++++++++= +++ MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 20 -----------------= --- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index 728e89d2bf44..2c69c5f52877 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -206,6 +206,26 @@ RiscVClearPendingTimerInterrupt ( VOID ); =20 +/** + RISC-V invalidate instruction cache. + +**/ +VOID +EFIAPI +RiscVInvalidateInstCacheAsm ( + VOID + ); + +/** + RISC-V invalidate data cache. + +**/ +VOID +EFIAPI +RiscVInvalidateDataCacheAsm ( + VOID + ); + #endif // defined (MDE_CPU_RISCV64) =20 #if defined (MDE_CPU_LOONGARCH64) diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/L= ibrary/BaseCacheMaintenanceLib/RiscVCache.c index d08fb9f193ca..d5efcf49a4bf 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c @@ -10,26 +10,6 @@ #include #include =20 -/** - RISC-V invalidate instruction cache. - -**/ -VOID -EFIAPI -RiscVInvalidateInstCacheAsm ( - VOID - ); - -/** - RISC-V invalidate data cache. - -**/ -VOID -EFIAPI -RiscVInvalidateDataCacheAsm ( - VOID - ); - /** Invalidates the entire instruction cache in cache coherency domain of the calling CPU. --=20 2.39.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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([171.76.83.136]) by smtp.gmail.com with ESMTPSA id s16-20020a62e710000000b006ce3bf7acc7sm9985388pfh.113.2023.12.13.06.59.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 06:59:43 -0800 (PST) From: "Dhaval Sharma" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Sunil V L , Daniel Schaefer , Laszlo Ersek , Pedro Falcato Subject: [edk2-devel] [PATCH v10 2/5] MdePkg: Rename Cache Management Function To Clarify Fence Based Op Date: Wed, 13 Dec 2023 20:29:28 +0530 Message-Id: <20231213145931.28307-3-dhaval@rivosinc.com> In-Reply-To: <20231213145931.28307-1-dhaval@rivosinc.com> References: <20231213145931.28307-1-dhaval@rivosinc.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dhaval@rivosinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1702479586210100009 Content-Type: text/plain; charset="utf-8" There are different ways to manage cache on RISC-V Processors. One way is to use fence instruction. Another way is to use CPU specific cache management operation instructions ratified as per RISC-V ISA specifications to be introduced in future patches. Current method is fence instruction based, rename the function accordingly to add that clarity. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Sunil V L Cc: Daniel Schaefer Cc: Laszlo Ersek Cc: Pedro Falcato Signed-off-by: Dhaval Sharma Reviewed-by: Laszlo Ersek --- Notes: V8: - Update function name to udpate *asm* in the end V7: - Add RB tag V6: - As part of restructuring, adding cache instruction differentiation in function naming MdePkg/Include/Library/BaseLib.h | 4 ++-- MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 4 ++-- MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 8 ++++---- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index 2c69c5f52877..c5e7f6dff0bc 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -212,7 +212,7 @@ RiscVClearPendingTimerInterrupt ( **/ VOID EFIAPI -RiscVInvalidateInstCacheAsm ( +RiscVInvalidateInstCacheFenceAsm ( VOID ); =20 @@ -222,7 +222,7 @@ RiscVInvalidateInstCacheAsm ( **/ VOID EFIAPI -RiscVInvalidateDataCacheAsm ( +RiscVInvalidateDataCacheFenceAsm ( VOID ); =20 diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/L= ibrary/BaseCacheMaintenanceLib/RiscVCache.c index d5efcf49a4bf..ac2a3c23a249 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c @@ -21,7 +21,7 @@ InvalidateInstructionCache ( VOID ) { - RiscVInvalidateInstCacheAsm (); + RiscVInvalidateInstCacheFenceAsm (); } =20 /** @@ -193,7 +193,7 @@ InvalidateDataCache ( VOID ) { - RiscVInvalidateDataCacheAsm (); + RiscVInvalidateDataCacheFenceAsm (); } =20 /** diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S b/MdePkg/Library/B= aseLib/RiscV64/FlushCache.S index 7c10fdd268af..8cfb85097996 100644 --- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S +++ b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S @@ -9,13 +9,13 @@ //------------------------------------------------------------------------= ------ =20 .align 3 -ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm) -ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm) +ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheFenceAsm) +ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheFenceAsm) =20 -ASM_PFX(RiscVInvalidateInstCacheAsm): +ASM_PFX(RiscVInvalidateInstCacheFenceAsm): fence.i ret =20 -ASM_PFX(RiscVInvalidateDataCacheAsm): +ASM_PFX(RiscVInvalidateDataCacheFenceAsm): fence ret --=20 2.39.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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([171.76.83.136]) by smtp.gmail.com with ESMTPSA id s16-20020a62e710000000b006ce3bf7acc7sm9985388pfh.113.2023.12.13.07.00.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 07:00:50 -0800 (PST) From: "Dhaval Sharma" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Sunil V L , Daniel Schaefer , Laszlo Ersek , Pedro Falcato , jingyulee98@gmail.com Subject: [edk2-devel] [PATCH v10 3/5] MdePkg: Implement RISC-V Cache Management Operations Date: Wed, 13 Dec 2023 20:29:29 +0530 Message-Id: <20231213145931.28307-4-dhaval@rivosinc.com> In-Reply-To: <20231213145931.28307-1-dhaval@rivosinc.com> References: <20231213145931.28307-1-dhaval@rivosinc.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dhaval@rivosinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1702479654617100003 Content-Type: text/plain; charset="utf-8" Implement Cache Management Operations (CMO) defined by RISC-V spec https://github.com/riscv/riscv-CMOs. Notes: 1. CMO only supports block based Operations. Meaning cache flush/invd/clean Operations are not available for the entire range. In that case we fallback on fence.i instructions. 2. Operations are implemented using Opcodes to make them compiler independent. binutils 2.39+ compilers support CMO instructions. Test: 1. Ensured correct instructions are refelecting in asm 2. Qemu implements basic support for CMO operations in that it allwos instructions without exceptions. Verified it works properly in that sense. 3. SG2042Pkg implements CMO-like instructions. It was verified that CpuFlushCpuDataCache works fine. This more of less confirms that framework is alright. 4. TODO: Once Silicon is available with exact instructions, we will further verify this. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Sunil V L Cc: Daniel Schaefer Cc: Laszlo Ersek Cc: Pedro Falcato Signed-off-by: Dhaval Sharma Reviewed-by: Laszlo Ersek Reviewed-by: Sunil V L Reviewed-by: Jingyu Li --- Notes: v8: - Add *asm* postfix to cmo functions - Add reviewed by tags V7: - Modify instruction names as per feedback from V6 - Added RB V6: - Implement Cache management instructions in Baselib MdePkg/Library/BaseLib/BaseLib.inf | 2 +- MdePkg/Include/Library/BaseLib.h | 33 +++= +++++++++++++++++ MdePkg/Include/RiscV64/RiscVasm.inc | 19 +++= ++++++++ MdePkg/Library/BaseLib/RiscV64/{FlushCache.S =3D> RiscVCacheMgmt.S} | 17 += +++++++++ 4 files changed, 70 insertions(+), 1 deletion(-) diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 03c7b02e828b..53389389448c 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -400,7 +400,7 @@ [Sources.RISCV64] RiscV64/RiscVCpuBreakpoint.S | GCC RiscV64/RiscVCpuPause.S | GCC RiscV64/RiscVInterrupt.S | GCC - RiscV64/FlushCache.S | GCC + RiscV64/RiscVCacheMgmt.S | GCC RiscV64/CpuScratch.S | GCC RiscV64/ReadTimer.S | GCC RiscV64/RiscVMmu.S | GCC diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index c5e7f6dff0bc..b71e47f41b7f 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -226,6 +226,39 @@ RiscVInvalidateDataCacheFenceAsm ( VOID ); =20 +/** + RISC-V flush cache block. Atomically perform a clean operation + followed by an invalidate operation + +**/ +VOID +EFIAPI +RiscVCpuCacheFlushCmoAsm ( + IN UINTN + ); + +/** +Perform a write transfer to another cache or to memory if the +data in the copy of the cache block have been modified by a store +operation + +**/ +VOID +EFIAPI +RiscVCpuCacheCleanCmoAsm ( + IN UINTN + ); + +/** +Deallocate the copy of the cache block + +**/ +VOID +EFIAPI +RiscVCpuCacheInvalCmoAsm ( + IN UINTN + ); + #endif // defined (MDE_CPU_RISCV64) =20 #if defined (MDE_CPU_LOONGARCH64) diff --git a/MdePkg/Include/RiscV64/RiscVasm.inc b/MdePkg/Include/RiscV64/R= iscVasm.inc new file mode 100644 index 000000000000..29de7358855c --- /dev/null +++ b/MdePkg/Include/RiscV64/RiscVasm.inc @@ -0,0 +1,19 @@ +/* + * + * RISC-V cache operation encoding. + * Copyright (c) 2023, Rivos Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-2-Clause-Patent + * + */ + +.macro RISCVCMOFLUSH + .word 0x25200f +.endm + +.macro RISCVCMOINVALIDATE + .word 0x05200f +.endm + +.macro RISCVCMOCLEAN + .word 0x15200f +.endm diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S b/MdePkg/Library/B= aseLib/RiscV64/RiscVCacheMgmt.S similarity index 56% rename from MdePkg/Library/BaseLib/RiscV64/FlushCache.S rename to MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S index 8cfb85097996..4752aa72d95e 100644 --- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S @@ -3,10 +3,12 @@ // RISC-V cache operation. // // Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// Copyright (c) 2023, Rivos Inc. All rights reserved.
// // SPDX-License-Identifier: BSD-2-Clause-Patent // //------------------------------------------------------------------------= ------ +.include "RiscVasm.inc" =20 .align 3 ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheFenceAsm) @@ -19,3 +21,18 @@ ASM_PFX(RiscVInvalidateInstCacheFenceAsm): ASM_PFX(RiscVInvalidateDataCacheFenceAsm): fence ret + +ASM_GLOBAL ASM_PFX (RiscVCpuCacheFlushCmoAsm) +ASM_PFX (RiscVCpuCacheFlushCmoAsm): + RISCVCMOFLUSH + ret + +ASM_GLOBAL ASM_PFX (RiscVCpuCacheCleanCmoAsm) +ASM_PFX (RiscVCpuCacheCleanCmoAsm): + RISCVCMOCLEAN + ret + +ASM_GLOBAL ASM_PFX (RiscVCpuCacheInvalCmoAsm) +ASM_PFX (RiscVCpuCacheInvalCmoAsm): + RISCVCMOINVALIDATE + ret --=20 2.39.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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([171.76.83.136]) by smtp.gmail.com with ESMTPSA id s16-20020a62e710000000b006ce3bf7acc7sm9985388pfh.113.2023.12.13.07.00.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 07:00:53 -0800 (PST) From: "Dhaval Sharma" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Laszlo Ersek , Pedro Falcato Subject: [edk2-devel] [PATCH v10 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V Date: Wed, 13 Dec 2023 20:29:30 +0530 Message-Id: <20231213145931.28307-5-dhaval@rivosinc.com> In-Reply-To: <20231213145931.28307-1-dhaval@rivosinc.com> References: <20231213145931.28307-1-dhaval@rivosinc.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dhaval@rivosinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1702479658663100002 Content-Type: text/plain; charset="utf-8" Use newly defined cache management operations for RISC-V where possible It builds up on the support added for RISC-V cache management instructions in BaseLib. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Laszlo Ersek Cc: Pedro Falcato Signed-off-by: Dhaval Sharma Acked-by: Laszlo Ersek Reviewed-by: Pedro Falcato Reviewed-by: Sunil V L --- Notes: V10: - Fix formatting to keep comments within 80 - Replace RV with RISC-V - Fix an issue with multi line comments - Added assert to an unsupported function - Minor case modification in str in .uni V9: - Fixed an issue with Instruction cache invalidation. Use fence.i instruction as CMO does not support i-cache operations. V8: - Added note to convert PCD into RISC-V feature bitmap pointer - Modified function names to be more explicit about cache ops - Added RB tag V7: - Added PcdLib - Restructure DEBUG message based on feedback on V6 - Make naming consistent to CMO, remove all CBO references - Add ASSERT for not supported functions instead of plain debug message - Added RB tag V6: - Utilize cache management instructions if HW supports it This patch is part of restructuring on top of v5 MdePkg/MdePkg.dec | 8 + MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf | 5 + MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 177 += +++++++++++++++---- MdePkg/MdePkg.uni | 4 + 4 files changed, 166 insertions(+), 28 deletions(-) diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index ac54338089e8..fa92673ff633 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -2399,6 +2399,14 @@ [PcdsFixedAtBuild.AARCH64, PcdsPatchableInModule.AAR= CH64] # @Prompt CPU Rng algorithm's GUID. gEfiMdePkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x00,0x0= 0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID*|0x0000= 0037 =20 +[PcdsFixedAtBuild.RISCV64, PcdsPatchableInModule.RISCV64] + # + # Configurability to override RISC-V CPU Features + # BIT 0 =3D Cache Management Operations. This bit is relevant only if + # previous stage has feature enabled and user wants to disable it. + # + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFF|UINT= 64|0x69 + [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] ## This value is used to set the base address of PCI express hierarchy. # @Prompt PCI Express Base Address. diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib= .inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf index 6fd9cbe5f6c9..601a38d6c109 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf @@ -56,3 +56,8 @@ [LibraryClasses] BaseLib DebugLib =20 +[LibraryClasses.RISCV64] + PcdLib + +[Pcd.RISCV64] + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride ## CONSUMES diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/L= ibrary/BaseCacheMaintenanceLib/RiscVCache.c index ac2a3c23a249..7c53a17abbb5 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c @@ -2,6 +2,7 @@ RISC-V specific functionality for cache. =20 Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2023, Rivos Inc. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -9,10 +10,116 @@ #include #include #include +#include + +// +// TODO: Grab cache block size and make Cache Management Operation +// enabling decision based on RISC-V CPU HOB in +// future when it is available and convert PcdRiscVFeatureOverride +// PCD to a pointer that contains pointer to bitmap structure +// which can be operated more elegantly. +// +#define RISCV_CACHE_BLOCK_SIZE 64 +#define RISCV_CPU_FEATURE_CMO_BITMASK 0x1 + +typedef enum { + CacheOpClean, + CacheOpFlush, + CacheOpInvld, +} CACHE_OP; + +/** +Verify CBOs are supported by this HW +TODO: Use RISC-V CPU HOB once available. + +**/ +STATIC +BOOLEAN +RiscVIsCMOEnabled ( + VOID + ) +{ + // If CMO is disabled in HW, skip Override check + // Otherwise this PCD can override settings + return ((PcdGet64 (PcdRiscVFeatureOverride) & RISCV_CPU_FEATURE_CMO_BITM= ASK) !=3D 0); +} + +/** + Performs required opeartion on cache lines in the cache coherency domain + of the calling CPU. If Address is not aligned on a cache line boundary, + then entire cache line containing Address is operated. If Address + Leng= th + is not aligned on a cache line boundary, then the entire cache line + containing Address + Length -1 is operated. + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + @param Address The base address of the cache lines to + invalidate. + @param Length The number of bytes to invalidate from the instruction + cache. + @param Op Type of CMO operation to be performed + @return Address. + +**/ +STATIC +VOID +CacheOpCacheRange ( + IN VOID *Address, + IN UINTN Length, + IN CACHE_OP Op + ) +{ + UINTN CacheLineSize; + UINTN Start; + UINTN End; + + if (Length =3D=3D 0) { + return; + } + + if ((Op !=3D CacheOpInvld) && (Op !=3D CacheOpFlush) && (Op !=3D CacheOp= Clean)) { + return; + } + + ASSERT ((Length - 1) <=3D (MAX_ADDRESS - (UINTN)Address)); + + CacheLineSize =3D RISCV_CACHE_BLOCK_SIZE; + + Start =3D (UINTN)Address; + // + // Calculate the cache line alignment + // + End =3D (Start + Length + (CacheLineSize - 1)) & ~(CacheLineSize - 1); + Start &=3D ~((UINTN)CacheLineSize - 1); + + DEBUG ( + (DEBUG_VERBOSE, + "CacheOpCacheRange: Performing Cache Management Operation %d \n", Op) + ); + + do { + switch (Op) { + case CacheOpInvld: + RiscVCpuCacheInvalCmoAsm (Start); + break; + case CacheOpFlush: + RiscVCpuCacheFlushCmoAsm (Start); + break; + case CacheOpClean: + RiscVCpuCacheCleanCmoAsm (Start); + break; + default: + break; + } + + Start =3D Start + CacheLineSize; + } while (Start !=3D End); +} =20 /** Invalidates the entire instruction cache in cache coherency domain of the - calling CPU. + calling CPU. Risc-V does not have currently an CBO implementation which = can + invalidate the entire I-cache. Hence using Fence instruction for now. P.= S. + Fence instruction may or may not implement full I-cache invd functionali= ty + on all implementations. =20 **/ VOID @@ -28,17 +135,11 @@ InvalidateInstructionCache ( Invalidates a range of instruction cache lines in the cache coherency do= main of the calling CPU. =20 - Invalidates the instruction cache lines specified by Address and Length.= If - Address is not aligned on a cache line boundary, then entire instruction - cache line containing Address is invalidated. If Address + Length is not - aligned on a cache line boundary, then the entire instruction cache line - containing Address + Length -1 is invalidated. This function may choose = to - invalidate the entire instruction cache if that is more efficient than - invalidating the specified range. If Length is 0, then no instruction ca= che - lines are invalidated. Address is returned. - - If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). - + An operation from a CMO instruction is defined to operate only on the co= pies + of a cache block that are cached in the caches accessible by the explicit + memory accesses performed by the set of coherent agents.In other words C= MO + operations are not applicable to instruction cache. Use fence.i instruct= ion + instead to achieve the same purpose. @param Address The base address of the instruction cache lines to invalidate. If the CPU is in a physical addressing mode,= then Address is a physical address. If the CPU is in a virtual @@ -57,9 +158,10 @@ InvalidateInstructionCacheRange ( ) { DEBUG ( - (DEBUG_WARN, - "%a:RISC-V unsupported function.\n" - "Invalidating the whole instruction cache instead.\n", __func__) + (DEBUG_VERBOSE, + "InvalidateInstructionCacheRange: RISC-V unsupported function.\n" + "Invalidating the whole instruction cache instead.\n" + ) ); InvalidateInstructionCache (); return Address; @@ -81,7 +183,12 @@ WriteBackInvalidateDataCache ( VOID ) { - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__)); + ASSERT (FALSE); + DEBUG (( + DEBUG_ERROR, + "WriteBackInvalidateDataCache:" \ + "RISC-V unsupported function.\n" + )); } =20 /** @@ -117,7 +224,12 @@ WriteBackInvalidateDataCacheRange ( IN UINTN Length ) { - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__)); + if (RiscVIsCMOEnabled ()) { + CacheOpCacheRange (Address, Length, CacheOpFlush); + } else { + ASSERT (FALSE); + } + return Address; } =20 @@ -137,7 +249,7 @@ WriteBackDataCache ( VOID ) { - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__)); + ASSERT (FALSE); } =20 /** @@ -156,10 +268,7 @@ WriteBackDataCache ( =20 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). =20 - @param Address The base address of the data cache lines to write back. = If - the CPU is in a physical addressing mode, then Address i= s a - physical address. If the CPU is in a virtual addressing - mode, then Address is a virtual address. + @param Address The base address of the data cache lines to write back. @param Length The number of bytes to write back from the data cache. =20 @return Address of cache written in main memory. @@ -172,7 +281,12 @@ WriteBackDataCacheRange ( IN UINTN Length ) { - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__)); + if (RiscVIsCMOEnabled ()) { + CacheOpCacheRange (Address, Length, CacheOpClean); + } else { + ASSERT (FALSE); + } + return Address; } =20 @@ -214,10 +328,7 @@ InvalidateDataCache ( =20 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). =20 - @param Address The base address of the data cache lines to invalidate. = If - the CPU is in a physical addressing mode, then Address i= s a - physical address. If the CPU is in a virtual addressing = mode, - then Address is a virtual address. + @param Address The base address of the data cache lines to invalidate. @param Length The number of bytes to invalidate from the data cache. =20 @return Address. @@ -230,6 +341,16 @@ InvalidateDataCacheRange ( IN UINTN Length ) { - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__)); + if (RiscVIsCMOEnabled ()) { + CacheOpCacheRange (Address, Length, CacheOpInvld); + } else { + DEBUG ( + (DEBUG_VERBOSE, + "InvalidateDataCacheRange: Zicbom not supported.\n" \ + "Invalidating the whole Data cache instead.\n") \ + ); + InvalidateDataCache (); + } + return Address; } diff --git a/MdePkg/MdePkg.uni b/MdePkg/MdePkg.uni index 5c1fa24065c7..73b5dd8f32cc 100644 --- a/MdePkg/MdePkg.uni +++ b/MdePkg/MdePkg.uni @@ -287,6 +287,10 @@ =20 #string STR_gEfiMdePkgTokenSpaceGuid_PcdGuidedExtractHandlerTableAddress_H= ELP #language en-US "This value is used to set the available memory addres= s to store Guided Extract Handlers. The required memory space is decided by= the value of PcdMaximumGuidedExtractHandler." =20 +#string STR_gEfiMdePkgTokenSpaceGuid_PcdRiscVFeatureOverride_PROMPT #lang= uage en-US "RISC-V Feature Override" + +#string STR_gEfiMdePkgTokenSpaceGuid_PcdRiscVFeatureOverride_HELP #langua= ge en-US "This value is used to override any RISC-V specific features suppo= rted by this PCD" + #string STR_gEfiMdePkgTokenSpaceGuid_PcdPciExpressBaseAddress_PROMPT #lan= guage en-US "PCI Express Base Address" =20 #string STR_gEfiMdePkgTokenSpaceGuid_PcdPciExpressBaseAddress_HELP #langu= age en-US "This value is used to set the base address of PCI express hierar= chy." --=20 2.39.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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([171.76.83.136]) by smtp.gmail.com with ESMTPSA id s16-20020a62e710000000b006ce3bf7acc7sm9985388pfh.113.2023.12.13.07.01.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 07:01:14 -0800 (PST) From: "Dhaval Sharma" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Sunil V L , Andrei Warkentin , Laszlo Ersek , Pedro Falcato Subject: [edk2-devel] [PATCH v10 5/5] OvmfPkg/RiscVVirt: Override for RISC-V CPU Features Date: Wed, 13 Dec 2023 20:29:31 +0530 Message-Id: <20231213145931.28307-6-dhaval@rivosinc.com> In-Reply-To: <20231213145931.28307-1-dhaval@rivosinc.com> References: <20231213145931.28307-1-dhaval@rivosinc.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dhaval@rivosinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1702479678882100001 Content-Type: text/plain; charset="utf-8" This PCD provides a way for platform to override any HW features that are default enabled by previous stages of FW (like OpenSBI). For the case where previous/prev stage has disabled the feature, this override is not useful and its usage should be avoided. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Sunil V L Cc: Andrei Warkentin Cc: Laszlo Ersek Cc: Pedro Falcato Signed-off-by: Dhaval Sharma Acked-by: Laszlo Ersek Reviewed-by: Andrei Warkentin Reviewed-by: Sunil V L --- Notes: V10: - Only keep CMO feature bitmask bit to disabled. Unimplemented bits remain 1. V8: - Added RV tag V7: - Added RB tag v6: - Modify PCD name according to changes made in Baselib implementation V5: - Introduce PCD for platform OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc b/OvmfPkg/RiscVVirt/RiscVV= irt.dsc.inc index fe320525153f..a050f1ffc1d4 100644 --- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc +++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc @@ -203,6 +203,7 @@ [PcdsFeatureFlag] gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE =20 [PcdsFixedAtBuild.common] + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFE gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000 gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0 --=20 2.39.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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