From nobody Mon Feb 9 00:42:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+112224+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112224+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1702029319; cv=none; d=zohomail.com; s=zohoarc; b=buoDmIk6gWKjL0jxY9oeC/Zol5WqiQOK4jGQTHKeF+Yv38JKdahHI7+c2ikitrUe/iXTDbToeNg5GL8Qc8jE8zErdUVYuVRsPYH+SKMGvQQ8ydgwHA6Fd/+xZaPzsTJxSY29sqB1+bbWgvgSXm6b6P4NJEVh5pbYsXTry7Y9vFo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1702029319; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=afs9g6rtjZiGNWHWqCZ+sNd4BeGrE4MJYYW49w5aXYo=; b=ORICXlay5HWP/AYNuUi1YAddUEmoFDz3ugmIEGMIK6JeoAyOFXrvmdCibMx/FyYQkYbSMk/QurKq6FFRHg4dYnDE2pTtHmNEGvmkD03e+xO1K5+TXb7Arrow5MWrQIOpUOKwqwQTewp3w9UpkG8DPufWv9haR2mXyTuxp9ZO2aM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112224+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1702029319429859.9708351469344; Fri, 8 Dec 2023 01:55:19 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=/Fk5J820QSvzLuT/Hh8t1lWnDxItGRBXFfxn6GrX72k=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1702029318; v=1; b=B9cGsyc5/ixgeMYETWkD8USQ98zOnadBXNgkisdiGZpX7+jvtlZ3B4u/xmUInzpHP96Z6TPL K4JZAyvImgQmISSbcru311vVxfOzFL0gM8SEL1ZCugTpONvna5Jhu3725qoYrzAhwWU7pq8BK6c w+oqC2UBY02rtFmr0Ok0aPqg= X-Received: by 127.0.0.2 with SMTP id s0iZYY1788612xirO6WmcxQM; Fri, 08 Dec 2023 01:55:18 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web11.16817.1702029313223455448 for ; Fri, 08 Dec 2023 01:55:18 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10917"; a="397176406" X-IronPort-AV: E=Sophos;i="6.04,260,1695711600"; d="scan'208";a="397176406" X-Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Dec 2023 01:55:17 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.04,260,1695711600"; d="scan'208";a="20028211" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.43]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Dec 2023 01:55:16 -0800 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V3 6/6] UefiCpuPkg: Avoid assuming only one smmbasehob Date: Fri, 8 Dec 2023 17:54:43 +0800 Message-Id: <20231208095443.1328-4-dun.tan@intel.com> In-Reply-To: <20231208095443.1328-1-dun.tan@intel.com> References: <20231208095443.1328-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: w5FHmhHBk4YqDZn0juBs8HYcx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1702029320471100015 Content-Type: text/plain; charset="utf-8" Modify the gSmmBaseHobGuid consumption code to remove the asuumption that there is only one gSmmBaseHobGuid. If the CPU number is big enough, there will be more than one SmmBaseHob in the HOB list. Signed-off-by: Dun Tan Cc: Eric Dong Reviewed-by: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 181 +++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++--------------------------= ------ 1 file changed, 149 insertions(+), 32 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.c index 53f67d544d..209a2e4810 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -586,6 +586,132 @@ SmmReadyToLockEventNotify ( return EFI_SUCCESS; } =20 +/** + Function to compare 2 SMM_BASE_HOB_DATA pointer based on ProcessorIndex. + + @param[in] Buffer1 pointer to SMM_BASE_HOB_DATA poiner to com= pare + @param[in] Buffer2 pointer to second SMM_BASE_HOB_DATA pointe= r to compare + + @retval 0 Buffer1 equal to Buffer2 + @retval <0 Buffer1 is less than Buffer2 + @retval >0 Buffer1 is greater than Buffer2 +**/ +INTN +EFIAPI +SmBaseHobCompare ( + IN CONST VOID *Buffer1, + IN CONST VOID *Buffer2 + ) +{ + if ((*(SMM_BASE_HOB_DATA **)Buffer1)->ProcessorIndex > (*(SMM_BASE_HOB_D= ATA **)Buffer2)->ProcessorIndex) { + return 1; + } else if ((*(SMM_BASE_HOB_DATA **)Buffer1)->ProcessorIndex < (*(SMM_BAS= E_HOB_DATA **)Buffer2)->ProcessorIndex) { + return -1; + } + + return 0; +} + +/** + Extract SmBase for all CPU from SmmBase HOB. + + @param[in] MaxNumberOfCpus Max NumberOfCpus. + + @retval SmBaseBuffer Pointer to SmBase Buffer. + @retval NULL gSmmBaseHobGuid was not been created. +**/ +UINTN * +GetSmBase ( + IN UINTN MaxNumberOfCpus + ) +{ + UINTN HobCount; + EFI_HOB_GUID_TYPE *GuidHob; + SMM_BASE_HOB_DATA *SmmBaseHobData; + UINTN NumberOfProcessors; + SMM_BASE_HOB_DATA **SmBaseHobs; + UINTN *SmBaseBuffer; + UINTN HobIndex; + UINTN SortBuffer; + UINTN ProcessorIndex; + UINT64 PrevProcessorIndex; + EFI_HOB_GUID_TYPE *FirstSmmBaseGuidHob; + + SmmBaseHobData =3D NULL; + HobIndex =3D 0; + ProcessorIndex =3D 0; + HobCount =3D 0; + NumberOfProcessors =3D 0; + + FirstSmmBaseGuidHob =3D GetFirstGuidHob (&gSmmBaseHobGuid); + if (FirstSmmBaseGuidHob =3D=3D NULL) { + return NULL; + } + + GuidHob =3D FirstSmmBaseGuidHob; + while (GuidHob !=3D NULL) { + HobCount++; + SmmBaseHobData =3D GET_GUID_HOB_DATA (GuidHob); + NumberOfProcessors +=3D SmmBaseHobData->NumberOfProcessors; + + if (NumberOfProcessors >=3D MaxNumberOfCpus) { + break; + } + + GuidHob =3D GetNextGuidHob (&gSmmBaseHobGuid, GET_NEXT_HOB (GuidHob)); + } + + ASSERT (NumberOfProcessors =3D=3D MaxNumberOfCpus); + if (NumberOfProcessors !=3D MaxNumberOfCpus) { + CpuDeadLoop (); + } + + SmBaseHobs =3D AllocatePool (sizeof (SMM_BASE_HOB_DATA *) * HobCount); + ASSERT (SmBaseHobs !=3D NULL); + if (SmBaseHobs =3D=3D NULL) { + return NULL; + } + + // + // Record each SmmBaseHob pointer in the SmBaseHobs. + // The FirstSmmBaseGuidHob is to speed up this while-loop + // without needing to look for SmBaseHob from beginning. + // + GuidHob =3D FirstSmmBaseGuidHob; + while (HobIndex < HobCount) { + SmBaseHobs[HobIndex++] =3D GET_GUID_HOB_DATA (GuidHob); + GuidHob =3D GetNextGuidHob (&gSmmBaseHobGuid, GET_NEXT_= HOB (GuidHob)); + } + + SmBaseBuffer =3D (UINTN *)AllocatePool (sizeof (UINTN) * (MaxNumberOfCpu= s)); + ASSERT (SmBaseBuffer !=3D NULL); + if (SmBaseBuffer =3D=3D NULL) { + FreePool (SmBaseHobs); + return NULL; + } + + QuickSort (SmBaseHobs, HobCount, sizeof (SMM_BASE_HOB_DATA *), (BASE_SOR= T_COMPARE)SmBaseHobCompare, &SortBuffer); + PrevProcessorIndex =3D 0; + for (HobIndex =3D 0; HobIndex < HobCount; HobIndex++) { + // + // Make sure no overlap and no gap in the CPU range covered by each HOB + // + ASSERT (SmBaseHobs[HobIndex]->ProcessorIndex =3D=3D PrevProcessorIndex= ); + + // + // Cache each SmBase in order. + // + for (ProcessorIndex =3D 0; ProcessorIndex < SmBaseHobs[HobIndex]->Numb= erOfProcessors; ProcessorIndex++) { + SmBaseBuffer[PrevProcessorIndex + ProcessorIndex] =3D (UINTN)SmBaseH= obs[HobIndex]->SmBase[ProcessorIndex]; + } + + PrevProcessorIndex +=3D SmBaseHobs[HobIndex]->NumberOfProcessors; + } + + FreePool (SmBaseHobs); + return SmBaseBuffer; +} + /** Function to compare 2 MP_INFORMATION2_HOB_DATA pointer based on Processo= rIndex. =20 @@ -743,27 +869,22 @@ PiCpuSmmEntry ( IN EFI_SYSTEM_TABLE *SystemTable ) { - EFI_STATUS Status; - UINTN Index; - VOID *Buffer; - UINTN BufferPages; - UINTN TileCodeSize; - UINTN TileDataSize; - UINTN TileSize; - UINT8 *Stacks; - VOID *Registration; - UINT32 RegEax; - UINT32 RegEbx; - UINT32 RegEcx; - UINT32 RegEdx; - UINTN FamilyId; - UINTN ModelId; - UINT32 Cr3; - EFI_HOB_GUID_TYPE *GuidHob; - SMM_BASE_HOB_DATA *SmmBaseHobData; - - GuidHob =3D NULL; - SmmBaseHobData =3D NULL; + EFI_STATUS Status; + UINTN Index; + VOID *Buffer; + UINTN BufferPages; + UINTN TileCodeSize; + UINTN TileDataSize; + UINTN TileSize; + UINT8 *Stacks; + VOID *Registration; + UINT32 RegEax; + UINT32 RegEbx; + UINT32 RegEcx; + UINT32 RegEdx; + UINTN FamilyId; + UINTN ModelId; + UINT32 Cr3; =20 PERF_FUNCTION_BEGIN (); =20 @@ -985,23 +1106,19 @@ PiCpuSmmEntry ( // Retrive the allocated SmmBase from gSmmBaseHobGuid. If found, // means the SmBase relocation has been done. // - GuidHob =3D GetFirstGuidHob (&gSmmBaseHobGuid); - if (GuidHob !=3D NULL) { + mCpuHotPlugData.SmBase =3D GetSmBase (mMaxNumberOfCpus); + if (mCpuHotPlugData.SmBase !=3D NULL) { // // Check whether the Required TileSize is enough. // if (TileSize > SIZE_8KB) { DEBUG ((DEBUG_ERROR, "The Range of Smbase in SMRAM is not enough -- = Required TileSize =3D 0x%08x, Actual TileSize =3D 0x%08x\n", TileSize, SIZE= _8KB)); + FreePool (mCpuHotPlugData.SmBase); + FreePool (gSmmCpuPrivate->ProcessorInfo); CpuDeadLoop (); return RETURN_BUFFER_TOO_SMALL; } =20 - SmmBaseHobData =3D GET_GUID_HOB_DATA (GuidHob); - - // - // Assume single instance of HOB produced, expect the HOB.NumberOfProc= essors equals to the mMaxNumberOfCpus. - // - ASSERT (SmmBaseHobData->NumberOfProcessors =3D=3D (UINT32)mMaxNumberOf= Cpus && SmmBaseHobData->ProcessorIndex =3D=3D 0); mSmmRelocated =3D TRUE; } else { // @@ -1047,8 +1164,6 @@ PiCpuSmmEntry ( // mCpuHotPlugData.ApicId =3D (UINT64 *)AllocatePool (sizeof (UINT64) * mMa= xNumberOfCpus); ASSERT (mCpuHotPlugData.ApicId !=3D NULL); - mCpuHotPlugData.SmBase =3D (UINTN *)AllocatePool (sizeof (UINTN) * mMaxN= umberOfCpus); - ASSERT (mCpuHotPlugData.SmBase !=3D NULL); mCpuHotPlugData.ArrayLength =3D (UINT32)mMaxNumberOfCpus; =20 // @@ -1057,7 +1172,9 @@ PiCpuSmmEntry ( // size for each CPU in the platform // for (Index =3D 0; Index < mMaxNumberOfCpus; Index++) { - mCpuHotPlugData.SmBase[Index] =3D mSmmRelocated ? (UINTN)SmmBaseHobDat= a->SmBase[Index] : (UINTN)Buffer + Index * TileSize - SMM_HANDLER_OFFSET; + if (!mSmmRelocated) { + mCpuHotPlugData.SmBase[Index] =3D (UINTN)Buffer + Index * TileSize -= SMM_HANDLER_OFFSET; + } =20 gSmmCpuPrivate->CpuSaveStateSize[Index] =3D sizeof (SMRAM_SAVE_STATE_M= AP); gSmmCpuPrivate->CpuSaveState[Index] =3D (VOID *)(mCpuHotPlugData.S= mBase[Index] + SMRAM_SAVE_STATE_MAP_OFFSET); --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112224): https://edk2.groups.io/g/devel/message/112224 Mute This Topic: https://groups.io/mt/103052271/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-