From nobody Mon Feb 9 16:18:29 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+112110+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112110+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1701856894; cv=none; d=zohomail.com; s=zohoarc; b=Luu2/cTef0BJsSIvBELEvVNjYRJE6wRrvcB8oSA+C7Jjh/pEvkuEGEuCo7W8p4JfP5Eyq6Dw6V32CceRKUuFq8GBZfmj1MzFggL04AmWq6hNEyqSdNyn0S2qhXkpngz/rPHNNG6ub24tUYCzbOaNbV1NnNb8ZCXyU9V7m4zmxLU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1701856894; h=Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=t89qXVnKQ0js7IwR53MZcKYtDiprclL1JzVnQOHPr4Y=; b=Ls49Aea46IoF7WK9sxArx+8WrbYntI6+wXCx4mND3T6prEOYoH4AZMrMyocvDFoPdN8ki+JDXQnDwEWU8wpC0jRBoh79Jyu+JQauDw2prYXIIe3S6eQx8XQO/ghs7mso46QR2h19atnfb/Vz/OKexFlnZMO3dIMK533BL6V5YX8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112110+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1701856894111125.69246560753663; Wed, 6 Dec 2023 02:01:34 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=GgqP0Jqgax8iEKhBAnl8pJwEN7XSDfC5Bb8wezZfCF4=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe; s=20140610; t=1701856893; v=1; b=aJmvk3d0UsSV0XexD8MLGhUeeiOYfgCnHZwPuFOswpNNICisNriuZoDvdbSihs9fRjt6fSU8 dKFgop8JKUaUnI/owp1ph/JL+M0g6EvYqRT3UZ6z1jBxiWgeKkfW6BNRoHgd8HDzG2srI6lsgfD 5z3L/I2B1kyxIVAAnqDWUp/U= X-Received: by 127.0.0.2 with SMTP id 7V18YY1788612xJQbAeBIh7X; Wed, 06 Dec 2023 02:01:33 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by mx.groups.io with SMTP id smtpd.web11.28132.1701856892226271583 for ; Wed, 06 Dec 2023 02:01:32 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10915"; a="1130564" X-IronPort-AV: E=Sophos;i="6.04,254,1695711600"; d="scan'208";a="1130564" X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Dec 2023 02:01:33 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10915"; a="841775349" X-IronPort-AV: E=Sophos;i="6.04,254,1695711600"; d="scan'208";a="841775349" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by fmsmga004.fm.intel.com with ESMTP; 06 Dec 2023 02:01:29 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Laszlo Ersek , Eric Dong , Ray Ni , Zeng Star , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v3 2/6] UefiCpuPkg: Adds SmmCpuSyncLib library class Date: Wed, 6 Dec 2023 18:01:18 +0800 Message-Id: <20231206100122.8028-3-jiaxin.wu@intel.com> In-Reply-To: <20231206100122.8028-1-jiaxin.wu@intel.com> References: <20231206100122.8028-1-jiaxin.wu@intel.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: z0BRAO42hfddOSKc1SzFIvH6x1787277AA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1701856896313100011 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Intel is planning to provide different SMM CPU Sync implementation along with some specific registers to improve the SMI performance, hence need SmmCpuSyncLib Library for Intel. This patch is to: 1.Adds SmmCpuSyncLib Library class in UefiCpuPkg.dec. 2.Adds SmmCpuSyncLib.h function declaration header file. For the new SmmCpuSyncLib, it provides 3 sets of APIs: 1. ContextInit/ContextDeinit/ContextReset: ContextInit() is called in driver's entrypoint to allocate and initialize the SMM CPU Sync context. ContextDeinit() is called in driver's unload function to deinitialize SMM CPU Sync context. ContextReset() is called before CPU exist SMI, which allows CPU to check into the next SMI from this point. 2. GetArrivedCpuCount/CheckInCpu/CheckOutCpu/LockDoor: When SMI happens, all processors including BSP enter to SMM mode by calling CheckInCpu(). The elected BSP calls LockDoor() so that CheckInCpu() will return the error code after that. CheckOutCpu() can be called in error handling flow for the CPU who calls CheckInCpu() earlier. GetArrivedCpuCount() returns the number of checked-in CPUs. 3. WaitForAPs/ReleaseOneAp/WaitForBsp/ReleaseBsp WaitForAPs() & ReleaseOneAp() are called from BSP to wait the number of APs and release one specific AP. WaitForBsp() & ReleaseBsp() are called from APs to wait and release BSP. The 4 APIs are used to synchronize the running flow among BSP and APs. BSP and AP Sync flow can be easy understand as below: BSP: ReleaseOneAp --> AP: WaitForBsp BSP: WaitForAPs <-- AP: ReleaseBsp Cc: Laszlo Ersek Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- UefiCpuPkg/Include/Library/SmmCpuSyncLib.h | 275 +++++++++++++++++++++++++= ++++ UefiCpuPkg/UefiCpuPkg.dec | 3 + 2 files changed, 278 insertions(+) create mode 100644 UefiCpuPkg/Include/Library/SmmCpuSyncLib.h diff --git a/UefiCpuPkg/Include/Library/SmmCpuSyncLib.h b/UefiCpuPkg/Includ= e/Library/SmmCpuSyncLib.h new file mode 100644 index 0000000000..0f9eb3414a --- /dev/null +++ b/UefiCpuPkg/Include/Library/SmmCpuSyncLib.h @@ -0,0 +1,275 @@ +/** @file + Library that provides SMM CPU Sync related operations. + The lib provides 3 sets of APIs: + 1. ContextInit/ContextDeinit/ContextReset: + ContextInit() is called in driver's entrypoint to allocate and initializ= e the SMM CPU Sync context. + ContextDeinit() is called in driver's unload function to deinitialize th= e SMM CPU Sync context. + ContextReset() is called before CPU exist SMI, which allows CPU to check= into the next SMI from this point. + + 2. GetArrivedCpuCount/CheckInCpu/CheckOutCpu/LockDoor: + When SMI happens, all processors including BSP enter to SMM mode by call= ing CheckInCpu(). + The elected BSP calls LockDoor() so that CheckInCpu() will return the er= ror code after that. + CheckOutCpu() can be called in error handling flow for the CPU who calls= CheckInCpu() earlier. + GetArrivedCpuCount() returns the number of checked-in CPUs. + + 3. WaitForAPs/ReleaseOneAp/WaitForBsp/ReleaseBsp + WaitForAPs() & ReleaseOneAp() are called from BSP to wait the number of = APs and release one specific AP. + WaitForBsp() & ReleaseBsp() are called from APs to wait and release BSP. + The 4 APIs are used to synchronize the running flow among BSP and APs. B= SP and AP Sync flow can be + easy understand as below: + BSP: ReleaseOneAp --> AP: WaitForBsp + BSP: WaitForAPs <-- AP: ReleaseBsp + + Copyright (c) 2023, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SMM_CPU_SYNC_LIB_H_ +#define SMM_CPU_SYNC_LIB_H_ + +#include + +// +// Opaque structure for SMM CPU Sync context. +// +typedef struct SMM_CPU_SYNC_CONTEXT SMM_CPU_SYNC_CONTEXT; + +/** + Create and initialize the SMM CPU Sync context. + + SmmCpuSyncContextInit() function is to allocate and initialize the SMM C= PU Sync context. + + @param[in] NumberOfCpus The number of Logical Processors in th= e system. + @param[out] SmmCpuSyncCtx Pointer to the new created and initial= ized SMM CPU Sync context object. + NULL will be returned if any error hap= pen during init. + + @retval RETURN_SUCCESS The SMM CPU Sync context was successfu= l created and initialized. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL. + @retval RETURN_BUFFER_TOO_SMALL Overflow happen + @retval RETURN_OUT_OF_RESOURCES There are not enough resources availab= le to create and initialize SMM CPU Sync context. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncContextInit ( + IN UINTN NumberOfCpus, + OUT SMM_CPU_SYNC_CONTEXT **SmmCpuSyncCtx + ); + +/** + Deinit an allocated SMM CPU Sync context. + + SmmCpuSyncContextDeinit() function is to deinitialize SMM CPU Sync conte= xt, the resources allocated in + SmmCpuSyncContextInit() will be freed. + + Note: This function only can be called after SmmCpuSyncContextInit() ret= urn success. + + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync context ob= ject to be deinitialized. + + @retval RETURN_SUCCESS The SMM CPU Sync context was successfu= l deinitialized. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL. + @retval RETURN_UNSUPPORTED Unsupported operation. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncContextDeinit ( + IN OUT SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx + ); + +/** + Reset SMM CPU Sync context. + + SmmCpuSyncContextReset() function is to reset SMM CPU Sync context to th= e initialized state. + + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync context ob= ject to be reset. + + @retval RETURN_SUCCESS The SMM CPU Sync context was successfu= l reset. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncContextReset ( + IN OUT SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx + ); + +/** + Get current number of arrived CPU in SMI. + + For traditional CPU synchronization method, BSP might need to know the c= urrent number of arrived CPU in + SMI to make sure all APs in SMI. This API can be for that purpose. + + @param[in] SmmCpuSyncCtx Pointer to the SMM CPU Sync context ob= ject. + @param[in,out] CpuCount Current count of arrived CPU in SMI. + + @retval RETURN_SUCCESS Get current number of arrived CPU in S= MI successfully. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx or CpuCount is NULL. + @retval RETURN_UNSUPPORTED Unsupported operation. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncGetArrivedCpuCount ( + IN SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx, + IN OUT UINTN *CpuCount + ); + +/** + Performs an atomic operation to check in CPU. + + When SMI happens, all processors including BSP enter to SMM mode by call= ing SmmCpuSyncCheckInCpu(). + + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync context ob= ject. + @param[in] CpuIndex Check in CPU index. + + @retval RETURN_SUCCESS Check in CPU (CpuIndex) successfully. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL. + @retval RETURN_ABORTED Check in CPU failed due to SmmCpuSyncL= ockDoor() has been called by one elected CPU. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncCheckInCpu ( + IN OUT SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx, + IN UINTN CpuIndex + ); + +/** + Performs an atomic operation to check out CPU. + + CheckOutCpu() can be called in error handling flow for the CPU who calls= CheckInCpu() earlier. + + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync context ob= ject. + @param[in] CpuIndex Check out CPU index. + + @retval RETURN_SUCCESS Check out CPU (CpuIndex) successfully. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL. + @retval RETURN_NOT_READY The CPU is not checked-in. + @retval RETURN_UNSUPPORTED Unsupported operation. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncCheckOutCpu ( + IN OUT SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx, + IN UINTN CpuIndex + ); + +/** + Performs an atomic operation lock door for CPU checkin or checkout. + + After this function, CPU can not check in via SmmCpuSyncCheckInCpu(). + + The CPU specified by CpuIndex is elected to lock door. + + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync context ob= ject. + @param[in] CpuIndex Indicate which CPU to lock door. + @param[in,out] CpuCount Number of arrived CPU in SMI after loo= k door. + + @retval RETURN_SUCCESS Lock door for CPU successfully. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx or CpuCount is NULL. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncLockDoor ( + IN OUT SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx, + IN UINTN CpuIndex, + IN OUT UINTN *CpuCount + ); + +/** + Used by the BSP to wait for APs. + + The number of APs need to be waited is specified by NumberOfAPs. The BSP= is specified by BspIndex. + + Note: This function is blocking mode, and it will return only after the = number of APs released by + calling SmmCpuSyncReleaseBsp(): + BSP: WaitForAPs <-- AP: ReleaseBsp + + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync context ob= ject. + @param[in] NumberOfAPs Number of APs need to be waited by BSP. + @param[in] BspIndex The BSP Index to wait for APs. + + @retval RETURN_SUCCESS BSP to wait for APs successfully. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL or NumberOfAPs >= total number of processors in system. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncWaitForAPs ( + IN OUT SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx, + IN UINTN NumberOfAPs, + IN UINTN BspIndex + ); + +/** + Used by the BSP to release one AP. + + The AP is specified by CpuIndex. The BSP is specified by BspIndex. + + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync context ob= ject. + @param[in] CpuIndex Indicate which AP need to be released. + @param[in] BspIndex The BSP Index to release AP. + + @retval RETURN_SUCCESS BSP to release one AP successfully. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL or CpuIndex is s= ame as BspIndex. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncReleaseOneAp ( + IN OUT SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx, + IN UINTN CpuIndex, + IN UINTN BspIndex + ); + +/** + Used by the AP to wait BSP. + + The AP is specified by CpuIndex. The BSP is specified by BspIndex. + + Note: This function is blocking mode, and it will return only after the = AP released by + calling SmmCpuSyncReleaseOneAp(): + BSP: ReleaseOneAp --> AP: WaitForBsp + + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync context obj= ect. + @param[in] CpuIndex Indicate which AP wait BSP. + @param[in] BspIndex The BSP Index to be waited. + + @retval RETURN_SUCCESS AP to wait BSP successfully. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL or CpuIndex is s= ame as BspIndex. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncWaitForBsp ( + IN OUT SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx, + IN UINTN CpuIndex, + IN UINTN BspIndex + ); + +/** + Used by the AP to release BSP. + + The AP is specified by CpuIndex. The BSP is specified by BspIndex. + + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync context ob= ject. + @param[in] CpuIndex Indicate which AP release BSP. + @param[in] BspIndex The BSP Index to be released. + + @retval RETURN_SUCCESS AP to release BSP successfully. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL or CpuIndex is s= ame as BspIndex. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncReleaseBsp ( + IN OUT SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx, + IN UINTN CpuIndex, + IN UINTN BspIndex + ); + +#endif diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 0b5431dbf7..20ab079219 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -62,10 +62,13 @@ CpuPageTableLib|Include/Library/CpuPageTableLib.h =20 ## @libraryclass Provides functions for manipulating smram savestate r= egisters. MmSaveStateLib|Include/Library/MmSaveStateLib.h =20 + ## @libraryclass Provides functions for SMM CPU Sync Operation. + SmmCpuSyncLib|Include/Library/SmmCpuSyncLib.h + [LibraryClasses.RISCV64] ## @libraryclass Provides functions to manage MMU features on RISCV64 = CPUs. ## RiscVMmuLib|Include/Library/BaseRiscVMmuLib.h =20 --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112110): https://edk2.groups.io/g/devel/message/112110 Mute This Topic: https://groups.io/mt/103010164/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-