From nobody Fri May 17 20:49:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+112109+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112109+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1701856893; cv=none; d=zohomail.com; s=zohoarc; b=W4hWPAwna/JUByIbD1YLZu1W1sltMGNRgVg4lydMTKp9fjoitQ7CYH9Lp9HdgycMMDJBGrufmsrvYHtsK5zT7eD3CNcrFiqJRTiaeS0b0b7MaG5qxMmoMnb0roIBELN1KoGtfK356chVT8bMFPHuZ7KTh+dQMpcPI4mRMcRo8H4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1701856893; h=Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=BA0RN6D/CVRejGuueedxJqa5uHI5YrLIRsTvKM0mmEo=; b=So/kaD8/3R4WyT5hVexp6FwyzDJfIJ7tmltAsybf5V2G76GADOp4/JQzfxz2K3kvL2uvnBf0pBM1mkgTRvyCfahcyDWy/jo7CSsY4lgJWhgsSGcwaU72OB/AE3YJ++oERqXSZaQdV7EOovnlzCCH3dULHeRjOwWjK6IHSVqT1Eg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112109+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 17018568936491010.2262226220581; Wed, 6 Dec 2023 02:01:33 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=gD6p6yr3moFfeTckpg57j8nS6ElTl64HtakxqaOlwSc=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe; s=20140610; t=1701856893; v=1; b=pgXdFnVhr+huq8KktvA+/lbrGG0cMDonPfa+Q+SVkUklhYP+2/J6fUp43VZQfIMwAME3apOL vdT4sdelNGtticPrf68W4ScWxkIWczAZHnTWU36zKHpW71Z7fRtqgisvsZR8awfR8d+UzB9MQrr 8luLoVuokM+teJvYr9MwOcuE= X-Received: by 127.0.0.2 with SMTP id QBUaYY1788612xtvFJ6M4Qdl; Wed, 06 Dec 2023 02:01:33 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by mx.groups.io with SMTP id smtpd.web11.28132.1701856892226271583 for ; Wed, 06 Dec 2023 02:01:32 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10915"; a="1130561" X-IronPort-AV: E=Sophos;i="6.04,254,1695711600"; d="scan'208";a="1130561" X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Dec 2023 02:01:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10915"; a="841775343" X-IronPort-AV: E=Sophos;i="6.04,254,1695711600"; d="scan'208";a="841775343" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by fmsmga004.fm.intel.com with ESMTP; 06 Dec 2023 02:01:26 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Laszlo Ersek , Eric Dong , Ray Ni , Zeng Star , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [PATCH v3 1/6] UefiCpuPkg/PiSmmCpuDxeSmm: Optimize Semaphore Sync between BSP and AP Date: Wed, 6 Dec 2023 18:01:17 +0800 Message-Id: <20231206100122.8028-2-jiaxin.wu@intel.com> In-Reply-To: <20231206100122.8028-1-jiaxin.wu@intel.com> References: <20231206100122.8028-1-jiaxin.wu@intel.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: QuTUMdf1vCvPGnTI8b36Nd1mx1787277AA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1701856894643100002 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch is to define 3 new functions (WaitForBsp & ReleaseBsp & ReleaseOneAp) used for the semaphore sync between BSP & AP. With the change, BSP and AP Sync flow will be easy understand as below: BSP: ReleaseAllAPs or ReleaseOneAp --> AP: WaitForBsp BSP: WaitForAllAPs <-- AP: ReleaseBsp Cc: Laszlo Ersek Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Rahul Kumar Cc: Gerd Hoffmann Signed-off-by: Jiaxin Wu Reviewed-by: Laszlo Ersek --- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 72 ++++++++++++++++++++++++++++---= ---- 1 file changed, 58 insertions(+), 14 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxe= Smm/MpService.c index b279f5dfcc..54542262a2 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -120,10 +120,11 @@ LockdownSemaphore ( =20 return Value; } =20 /** + Used for BSP to wait all APs. Wait all APs to performs an atomic compare exchange operation to release= semaphore. =20 @param NumberOfAPs AP number =20 **/ @@ -139,10 +140,11 @@ WaitForAllAPs ( WaitForSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run); } } =20 /** + Used for BSP to release all APs. Performs an atomic compare exchange operation to release semaphore for each AP. =20 **/ VOID @@ -157,10 +159,52 @@ ReleaseAllAPs ( ReleaseSemaphore (mSmmMpSyncData->CpuData[Index].Run); } } } =20 +/** + Used for BSP to release one AP. + + @param ApSem IN: 32-bit unsigned integer + OUT: original integer + 1 +**/ +VOID +ReleaseOneAp ( + IN OUT volatile UINT32 *ApSem + ) +{ + ReleaseSemaphore (ApSem); +} + +/** + Used for AP to wait BSP. + + @param ApSem IN: 32-bit unsigned integer + OUT: original integer - 1 +**/ +VOID +WaitForBsp ( + IN OUT volatile UINT32 *ApSem + ) +{ + WaitForSemaphore (ApSem); +} + +/** + Used for AP to release BSP. + + @param BspSem IN: 32-bit unsigned integer + OUT: original integer + 1 +**/ +VOID +ReleaseBsp ( + IN OUT volatile UINT32 *BspSem + ) +{ + ReleaseSemaphore (BspSem); +} + /** Check whether the index of CPU perform the package level register programming during System Management Mode initialization. =20 The index of Processor specified by mPackageFirstThreadIndex[PackageInde= x] @@ -632,11 +676,11 @@ BSPHandler ( // Signal all APs it's time for backup MTRRs // ReleaseAllAPs (); =20 // - // WaitForSemaphore() may wait for ever if an AP happens to enter SM= M at + // WaitForAllAPs() may wait for ever if an AP happens to enter SMM at // exactly this point. Please make sure PcdCpuSmmMaxSyncLoops has be= en set // to a large enough value to avoid this situation. // Note: For HT capable CPUs, threads within a core share the same s= et of MTRRs. // We do the backup first and then set MTRR to avoid race condition = for threads // in the same core. @@ -652,11 +696,11 @@ BSPHandler ( // Let all processors program SMM MTRRs together // ReleaseAllAPs (); =20 // - // WaitForSemaphore() may wait for ever if an AP happens to enter SM= M at + // WaitForAllAPs() may wait for ever if an AP happens to enter SMM at // exactly this point. Please make sure PcdCpuSmmMaxSyncLoops has be= en set // to a large enough value to avoid this situation. // ReplaceOSMtrrs (CpuIndex); =20 @@ -898,50 +942,50 @@ APHandler ( =20 if ((SyncMode =3D=3D SmmCpuSyncModeTradition) || SmmCpuFeaturesNeedConfi= gureMtrrs ()) { // // Notify BSP of arrival at this point // - ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run); + ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); } =20 if (SmmCpuFeaturesNeedConfigureMtrrs ()) { // // Wait for the signal from BSP to backup MTRRs // - WaitForSemaphore (mSmmMpSyncData->CpuData[CpuIndex].Run); + WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); =20 // // Backup OS MTRRs // MtrrGetAllMtrrs (&Mtrrs); =20 // // Signal BSP the completion of this AP // - ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run); + ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); =20 // // Wait for BSP's signal to program MTRRs // - WaitForSemaphore (mSmmMpSyncData->CpuData[CpuIndex].Run); + WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); =20 // // Replace OS MTRRs with SMI MTRRs // ReplaceOSMtrrs (CpuIndex); =20 // // Signal BSP the completion of this AP // - ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run); + ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); } =20 while (TRUE) { // // Wait for something to happen // - WaitForSemaphore (mSmmMpSyncData->CpuData[CpuIndex].Run); + WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); =20 // // Check if BSP wants to exit SMM // if (!(*mSmmMpSyncData->InsideSmm)) { @@ -977,16 +1021,16 @@ APHandler ( =20 if (SmmCpuFeaturesNeedConfigureMtrrs ()) { // // Notify BSP the readiness of this AP to program MTRRs // - ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run); + ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); =20 // // Wait for the signal from BSP to program MTRRs // - WaitForSemaphore (mSmmMpSyncData->CpuData[CpuIndex].Run); + WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); =20 // // Restore OS MTRRs // SmmCpuFeaturesReenableSmrr (); @@ -994,26 +1038,26 @@ APHandler ( } =20 // // Notify BSP the readiness of this AP to Reset states/semaphore for thi= s processor // - ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run); + ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); =20 // // Wait for the signal from BSP to Reset states/semaphore for this proce= ssor // - WaitForSemaphore (mSmmMpSyncData->CpuData[CpuIndex].Run); + WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); =20 // // Reset states/semaphore for this processor // *(mSmmMpSyncData->CpuData[CpuIndex].Present) =3D FALSE; =20 // // Notify BSP the readiness of this AP to exit SMM // - ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run); + ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); } =20 /** Checks whether the input token is the current used token. =20 @@ -1277,11 +1321,11 @@ InternalSmmStartupThisAp ( mSmmMpSyncData->CpuData[CpuIndex].Status =3D CpuStatus; if (mSmmMpSyncData->CpuData[CpuIndex].Status !=3D NULL) { *mSmmMpSyncData->CpuData[CpuIndex].Status =3D EFI_NOT_READY; } =20 - ReleaseSemaphore (mSmmMpSyncData->CpuData[CpuIndex].Run); + ReleaseOneAp (mSmmMpSyncData->CpuData[CpuIndex].Run); =20 if (Token =3D=3D NULL) { AcquireSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Busy); ReleaseSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Busy); } --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112109): https://edk2.groups.io/g/devel/message/112109 Mute This Topic: https://groups.io/mt/103010163/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 17 20:49:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+112110+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112110+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1701856894; cv=none; d=zohomail.com; s=zohoarc; b=Luu2/cTef0BJsSIvBELEvVNjYRJE6wRrvcB8oSA+C7Jjh/pEvkuEGEuCo7W8p4JfP5Eyq6Dw6V32CceRKUuFq8GBZfmj1MzFggL04AmWq6hNEyqSdNyn0S2qhXkpngz/rPHNNG6ub24tUYCzbOaNbV1NnNb8ZCXyU9V7m4zmxLU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1701856894; h=Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=t89qXVnKQ0js7IwR53MZcKYtDiprclL1JzVnQOHPr4Y=; b=Ls49Aea46IoF7WK9sxArx+8WrbYntI6+wXCx4mND3T6prEOYoH4AZMrMyocvDFoPdN8ki+JDXQnDwEWU8wpC0jRBoh79Jyu+JQauDw2prYXIIe3S6eQx8XQO/ghs7mso46QR2h19atnfb/Vz/OKexFlnZMO3dIMK533BL6V5YX8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112110+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1701856894111125.69246560753663; Wed, 6 Dec 2023 02:01:34 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=GgqP0Jqgax8iEKhBAnl8pJwEN7XSDfC5Bb8wezZfCF4=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe; s=20140610; t=1701856893; v=1; b=aJmvk3d0UsSV0XexD8MLGhUeeiOYfgCnHZwPuFOswpNNICisNriuZoDvdbSihs9fRjt6fSU8 dKFgop8JKUaUnI/owp1ph/JL+M0g6EvYqRT3UZ6z1jBxiWgeKkfW6BNRoHgd8HDzG2srI6lsgfD 5z3L/I2B1kyxIVAAnqDWUp/U= X-Received: by 127.0.0.2 with SMTP id 7V18YY1788612xJQbAeBIh7X; Wed, 06 Dec 2023 02:01:33 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by mx.groups.io with SMTP id smtpd.web11.28132.1701856892226271583 for ; Wed, 06 Dec 2023 02:01:32 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10915"; a="1130564" X-IronPort-AV: E=Sophos;i="6.04,254,1695711600"; d="scan'208";a="1130564" X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Dec 2023 02:01:33 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10915"; a="841775349" X-IronPort-AV: E=Sophos;i="6.04,254,1695711600"; d="scan'208";a="841775349" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by fmsmga004.fm.intel.com with ESMTP; 06 Dec 2023 02:01:29 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Laszlo Ersek , Eric Dong , Ray Ni , Zeng Star , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v3 2/6] UefiCpuPkg: Adds SmmCpuSyncLib library class Date: Wed, 6 Dec 2023 18:01:18 +0800 Message-Id: <20231206100122.8028-3-jiaxin.wu@intel.com> In-Reply-To: <20231206100122.8028-1-jiaxin.wu@intel.com> References: <20231206100122.8028-1-jiaxin.wu@intel.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: z0BRAO42hfddOSKc1SzFIvH6x1787277AA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1701856896313100011 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Intel is planning to provide different SMM CPU Sync implementation along with some specific registers to improve the SMI performance, hence need SmmCpuSyncLib Library for Intel. This patch is to: 1.Adds SmmCpuSyncLib Library class in UefiCpuPkg.dec. 2.Adds SmmCpuSyncLib.h function declaration header file. For the new SmmCpuSyncLib, it provides 3 sets of APIs: 1. ContextInit/ContextDeinit/ContextReset: ContextInit() is called in driver's entrypoint to allocate and initialize the SMM CPU Sync context. ContextDeinit() is called in driver's unload function to deinitialize SMM CPU Sync context. ContextReset() is called before CPU exist SMI, which allows CPU to check into the next SMI from this point. 2. GetArrivedCpuCount/CheckInCpu/CheckOutCpu/LockDoor: When SMI happens, all processors including BSP enter to SMM mode by calling CheckInCpu(). The elected BSP calls LockDoor() so that CheckInCpu() will return the error code after that. CheckOutCpu() can be called in error handling flow for the CPU who calls CheckInCpu() earlier. GetArrivedCpuCount() returns the number of checked-in CPUs. 3. WaitForAPs/ReleaseOneAp/WaitForBsp/ReleaseBsp WaitForAPs() & ReleaseOneAp() are called from BSP to wait the number of APs and release one specific AP. WaitForBsp() & ReleaseBsp() are called from APs to wait and release BSP. The 4 APIs are used to synchronize the running flow among BSP and APs. BSP and AP Sync flow can be easy understand as below: BSP: ReleaseOneAp --> AP: WaitForBsp BSP: WaitForAPs <-- AP: ReleaseBsp Cc: Laszlo Ersek Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- UefiCpuPkg/Include/Library/SmmCpuSyncLib.h | 275 +++++++++++++++++++++++++= ++++ UefiCpuPkg/UefiCpuPkg.dec | 3 + 2 files changed, 278 insertions(+) create mode 100644 UefiCpuPkg/Include/Library/SmmCpuSyncLib.h diff --git a/UefiCpuPkg/Include/Library/SmmCpuSyncLib.h b/UefiCpuPkg/Includ= e/Library/SmmCpuSyncLib.h new file mode 100644 index 0000000000..0f9eb3414a --- /dev/null +++ b/UefiCpuPkg/Include/Library/SmmCpuSyncLib.h @@ -0,0 +1,275 @@ +/** @file + Library that provides SMM CPU Sync related operations. + The lib provides 3 sets of APIs: + 1. ContextInit/ContextDeinit/ContextReset: + ContextInit() is called in driver's entrypoint to allocate and initializ= e the SMM CPU Sync context. + ContextDeinit() is called in driver's unload function to deinitialize th= e SMM CPU Sync context. + ContextReset() is called before CPU exist SMI, which allows CPU to check= into the next SMI from this point. + + 2. GetArrivedCpuCount/CheckInCpu/CheckOutCpu/LockDoor: + When SMI happens, all processors including BSP enter to SMM mode by call= ing CheckInCpu(). + The elected BSP calls LockDoor() so that CheckInCpu() will return the er= ror code after that. + CheckOutCpu() can be called in error handling flow for the CPU who calls= CheckInCpu() earlier. + GetArrivedCpuCount() returns the number of checked-in CPUs. + + 3. WaitForAPs/ReleaseOneAp/WaitForBsp/ReleaseBsp + WaitForAPs() & ReleaseOneAp() are called from BSP to wait the number of = APs and release one specific AP. + WaitForBsp() & ReleaseBsp() are called from APs to wait and release BSP. + The 4 APIs are used to synchronize the running flow among BSP and APs. B= SP and AP Sync flow can be + easy understand as below: + BSP: ReleaseOneAp --> AP: WaitForBsp + BSP: WaitForAPs <-- AP: ReleaseBsp + + Copyright (c) 2023, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SMM_CPU_SYNC_LIB_H_ +#define SMM_CPU_SYNC_LIB_H_ + +#include + +// +// Opaque structure for SMM CPU Sync context. +// +typedef struct SMM_CPU_SYNC_CONTEXT SMM_CPU_SYNC_CONTEXT; + +/** + Create and initialize the SMM CPU Sync context. + + SmmCpuSyncContextInit() function is to allocate and initialize the SMM C= PU Sync context. + + @param[in] NumberOfCpus The number of Logical Processors in th= e system. + @param[out] SmmCpuSyncCtx Pointer to the new created and initial= ized SMM CPU Sync context object. + NULL will be returned if any error hap= pen during init. + + @retval RETURN_SUCCESS The SMM CPU Sync context was successfu= l created and initialized. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL. + @retval RETURN_BUFFER_TOO_SMALL Overflow happen + @retval RETURN_OUT_OF_RESOURCES There are not enough resources availab= le to create and initialize SMM CPU Sync context. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncContextInit ( + IN UINTN NumberOfCpus, + OUT SMM_CPU_SYNC_CONTEXT **SmmCpuSyncCtx + ); + +/** + Deinit an allocated SMM CPU Sync context. + + SmmCpuSyncContextDeinit() function is to deinitialize SMM CPU Sync conte= xt, the resources allocated in + SmmCpuSyncContextInit() will be freed. + + Note: This function only can be called after SmmCpuSyncContextInit() ret= urn success. + + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync context ob= ject to be deinitialized. + + @retval RETURN_SUCCESS The SMM CPU Sync context was successfu= l deinitialized. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL. + @retval RETURN_UNSUPPORTED Unsupported operation. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncContextDeinit ( + IN OUT SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx + ); + +/** + Reset SMM CPU Sync context. + + SmmCpuSyncContextReset() function is to reset SMM CPU Sync context to th= e initialized state. + + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync context ob= ject to be reset. + + @retval RETURN_SUCCESS The SMM CPU Sync context was successfu= l reset. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncContextReset ( + IN OUT SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx + ); + +/** + Get current number of arrived CPU in SMI. + + For traditional CPU synchronization method, BSP might need to know the c= urrent number of arrived CPU in + SMI to make sure all APs in SMI. This API can be for that purpose. + + @param[in] SmmCpuSyncCtx Pointer to the SMM CPU Sync context ob= ject. + @param[in,out] CpuCount Current count of arrived CPU in SMI. + + @retval RETURN_SUCCESS Get current number of arrived CPU in S= MI successfully. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx or CpuCount is NULL. + @retval RETURN_UNSUPPORTED Unsupported operation. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncGetArrivedCpuCount ( + IN SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx, + IN OUT UINTN *CpuCount + ); + +/** + Performs an atomic operation to check in CPU. + + When SMI happens, all processors including BSP enter to SMM mode by call= ing SmmCpuSyncCheckInCpu(). + + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync context ob= ject. + @param[in] CpuIndex Check in CPU index. + + @retval RETURN_SUCCESS Check in CPU (CpuIndex) successfully. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL. + @retval RETURN_ABORTED Check in CPU failed due to SmmCpuSyncL= ockDoor() has been called by one elected CPU. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncCheckInCpu ( + IN OUT SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx, + IN UINTN CpuIndex + ); + +/** + Performs an atomic operation to check out CPU. + + CheckOutCpu() can be called in error handling flow for the CPU who calls= CheckInCpu() earlier. + + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync context ob= ject. + @param[in] CpuIndex Check out CPU index. + + @retval RETURN_SUCCESS Check out CPU (CpuIndex) successfully. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL. + @retval RETURN_NOT_READY The CPU is not checked-in. + @retval RETURN_UNSUPPORTED Unsupported operation. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncCheckOutCpu ( + IN OUT SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx, + IN UINTN CpuIndex + ); + +/** + Performs an atomic operation lock door for CPU checkin or checkout. + + After this function, CPU can not check in via SmmCpuSyncCheckInCpu(). + + The CPU specified by CpuIndex is elected to lock door. + + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync context ob= ject. + @param[in] CpuIndex Indicate which CPU to lock door. + @param[in,out] CpuCount Number of arrived CPU in SMI after loo= k door. + + @retval RETURN_SUCCESS Lock door for CPU successfully. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx or CpuCount is NULL. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncLockDoor ( + IN OUT SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx, + IN UINTN CpuIndex, + IN OUT UINTN *CpuCount + ); + +/** + Used by the BSP to wait for APs. + + The number of APs need to be waited is specified by NumberOfAPs. The BSP= is specified by BspIndex. + + Note: This function is blocking mode, and it will return only after the = number of APs released by + calling SmmCpuSyncReleaseBsp(): + BSP: WaitForAPs <-- AP: ReleaseBsp + + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync context ob= ject. + @param[in] NumberOfAPs Number of APs need to be waited by BSP. + @param[in] BspIndex The BSP Index to wait for APs. + + @retval RETURN_SUCCESS BSP to wait for APs successfully. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL or NumberOfAPs >= total number of processors in system. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncWaitForAPs ( + IN OUT SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx, + IN UINTN NumberOfAPs, + IN UINTN BspIndex + ); + +/** + Used by the BSP to release one AP. + + The AP is specified by CpuIndex. The BSP is specified by BspIndex. + + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync context ob= ject. + @param[in] CpuIndex Indicate which AP need to be released. + @param[in] BspIndex The BSP Index to release AP. + + @retval RETURN_SUCCESS BSP to release one AP successfully. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL or CpuIndex is s= ame as BspIndex. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncReleaseOneAp ( + IN OUT SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx, + IN UINTN CpuIndex, + IN UINTN BspIndex + ); + +/** + Used by the AP to wait BSP. + + The AP is specified by CpuIndex. The BSP is specified by BspIndex. + + Note: This function is blocking mode, and it will return only after the = AP released by + calling SmmCpuSyncReleaseOneAp(): + BSP: ReleaseOneAp --> AP: WaitForBsp + + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync context obj= ect. + @param[in] CpuIndex Indicate which AP wait BSP. + @param[in] BspIndex The BSP Index to be waited. + + @retval RETURN_SUCCESS AP to wait BSP successfully. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL or CpuIndex is s= ame as BspIndex. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncWaitForBsp ( + IN OUT SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx, + IN UINTN CpuIndex, + IN UINTN BspIndex + ); + +/** + Used by the AP to release BSP. + + The AP is specified by CpuIndex. The BSP is specified by BspIndex. + + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync context ob= ject. + @param[in] CpuIndex Indicate which AP release BSP. + @param[in] BspIndex The BSP Index to be released. + + @retval RETURN_SUCCESS AP to release BSP successfully. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL or CpuIndex is s= ame as BspIndex. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncReleaseBsp ( + IN OUT SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx, + IN UINTN CpuIndex, + IN UINTN BspIndex + ); + +#endif diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 0b5431dbf7..20ab079219 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -62,10 +62,13 @@ CpuPageTableLib|Include/Library/CpuPageTableLib.h =20 ## @libraryclass Provides functions for manipulating smram savestate r= egisters. MmSaveStateLib|Include/Library/MmSaveStateLib.h =20 + ## @libraryclass Provides functions for SMM CPU Sync Operation. + SmmCpuSyncLib|Include/Library/SmmCpuSyncLib.h + [LibraryClasses.RISCV64] ## @libraryclass Provides functions to manage MMU features on RISCV64 = CPUs. ## RiscVMmuLib|Include/Library/BaseRiscVMmuLib.h =20 --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112110): https://edk2.groups.io/g/devel/message/112110 Mute This Topic: https://groups.io/mt/103010164/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 17 20:49:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+112111+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112111+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1701856896; cv=none; d=zohomail.com; s=zohoarc; b=F/tIA+2UMJxE89N1I3w8OYJpNzjJJ237qWH4zkpfjmpk4sIl3GaAD6PKavVBrKt7eSmGwH4A5hCkfAaTJkZB8XGV0omKV8+bIAy7Y2geY2lbWQE6/cma7iJIzzIHwyegIMvrz37zdcoiiAMeYWDUSPo0tAoOVUOc/2ic39QbC94= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1701856896; h=Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=P3SLqegf0FJ/ddUwPscsdIk+hkFyvBb6A9L7iwuOdQQ=; b=ddBfFmaYuwbt+w9T76huYcV4jmiC3WfZIgULGwJ86EskLYBXuQiyh4gnLDKSKBwMU0+x6zjCqH1QgzapEelHeBz30UF5ty2f8/2qqEd5dnUuWzQNzN+2Z3JsUlyzQD8norPfnYCYlbsSRxxZUez74/t5maeQJBHVyy/FsqViJF4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112111+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1701856896488962.6146926491781; Wed, 6 Dec 2023 02:01:36 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=BwsEWh7NjB8tcuAc9CWCXp+mFGviTMAyynGRFM3Dg0M=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe; s=20140610; t=1701856896; v=1; b=crnDFFCQ+zIvEurM81Z+axG/VARgV6adi+MBKneVsDCaexKeo4Pf4i+l8evsRlZ71P/1CIm4 pbY/vZICQeGQRZkqoyH1ONUEAkorT33xAdMY0KMRfECIg4ui1npIGQ3XNBlli6mKbsWIKk6Do7J dlyrMY8U72o57Sz3U7irQY9s= X-Received: by 127.0.0.2 with SMTP id BNF7YY1788612xey4Hak2T3c; Wed, 06 Dec 2023 02:01:36 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by mx.groups.io with SMTP id smtpd.web11.28132.1701856892226271583 for ; Wed, 06 Dec 2023 02:01:35 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10915"; a="1130568" X-IronPort-AV: E=Sophos;i="6.04,254,1695711600"; d="scan'208";a="1130568" X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Dec 2023 02:01:36 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10915"; a="841775357" X-IronPort-AV: E=Sophos;i="6.04,254,1695711600"; d="scan'208";a="841775357" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by fmsmga004.fm.intel.com with ESMTP; 06 Dec 2023 02:01:32 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Laszlo Ersek , Eric Dong , Ray Ni , Zeng Star , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v3 3/6] UefiCpuPkg: Implements SmmCpuSyncLib library instance Date: Wed, 6 Dec 2023 18:01:19 +0800 Message-Id: <20231206100122.8028-4-jiaxin.wu@intel.com> In-Reply-To: <20231206100122.8028-1-jiaxin.wu@intel.com> References: <20231206100122.8028-1-jiaxin.wu@intel.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: B6d3DTu9pvcLI6d7UrJSjZnix1787277AA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1701856898352100015 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implements SmmCpuSyncLib Library instance. The instance refers the existing SMM CPU driver (PiSmmCpuDxeSmm) sync implementation and behavior: 1.Abstract Counter and Run semaphores into SmmCpuSyncCtx. 2.Abstract CPU arrival count operation to SmmCpuSyncGetArrivedCpuCount(), SmmCpuSyncCheckInCpu(), SmmCpuSyncCheckOutCpu(), SmmCpuSyncLockDoor(). Implementation is aligned with existing SMM CPU driver. 3. Abstract SMM CPU Sync flow to: BSP: SmmCpuSyncReleaseOneAp --> AP: SmmCpuSyncWaitForBsp BSP: SmmCpuSyncWaitForAPs <-- AP: SmmCpuSyncReleaseBsp Semaphores release & wait during sync flow is same as existing SMM CPU driver. 4.Same operation to Counter and Run semaphores by leverage the atomic compare exchange. Cc: Laszlo Ersek Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.c | 647 +++++++++++++++++= ++++ UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf | 39 ++ UefiCpuPkg/UefiCpuPkg.dsc | 3 + 3 files changed, 689 insertions(+) create mode 100644 UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.c create mode 100644 UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf diff --git a/UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.c b/UefiCpuPkg/= Library/SmmCpuSyncLib/SmmCpuSyncLib.c new file mode 100644 index 0000000000..3c2835f8de --- /dev/null +++ b/UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.c @@ -0,0 +1,647 @@ +/** @file + SMM CPU Sync lib implementation. + The lib provides 3 sets of APIs: + 1. ContextInit/ContextDeinit/ContextReset: + ContextInit() is called in driver's entrypoint to allocate and initializ= e the SMM CPU Sync context. + ContextDeinit() is called in driver's unload function to deinitialize th= e SMM CPU Sync context. + ContextReset() is called before CPU exist SMI, which allows CPU to check= into the next SMI from this point. + + 2. GetArrivedCpuCount/CheckInCpu/CheckOutCpu/LockDoor: + When SMI happens, all processors including BSP enter to SMM mode by call= ing CheckInCpu(). + The elected BSP calls LockDoor() so that CheckInCpu() will return the er= ror code after that. + CheckOutCpu() can be called in error handling flow for the CPU who calls= CheckInCpu() earlier. + GetArrivedCpuCount() returns the number of checked-in CPUs. + + 3. WaitForAPs/ReleaseOneAp/WaitForBsp/ReleaseBsp + WaitForAPs() & ReleaseOneAp() are called from BSP to wait the number of = APs and release one specific AP. + WaitForBsp() & ReleaseBsp() are called from APs to wait and release BSP. + The 4 APIs are used to synchronize the running flow among BSP and APs. B= SP and AP Sync flow can be + easy understand as below: + BSP: ReleaseOneAp --> AP: WaitForBsp + BSP: WaitForAPs <-- AP: ReleaseBsp + + Copyright (c) 2023, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + /// + /// Indicate how many CPU entered SMM. + /// + volatile UINT32 *Counter; +} SMM_CPU_SYNC_SEMAPHORE_GLOBAL; + +typedef struct { + /// + /// Used for control each CPU continue run or wait for signal + /// + volatile UINT32 *Run; +} SMM_CPU_SYNC_SEMAPHORE_CPU; + +struct SMM_CPU_SYNC_CONTEXT { + /// + /// All global semaphores' pointer in SMM CPU Sync + /// + SMM_CPU_SYNC_SEMAPHORE_GLOBAL *GlobalSem; + /// + /// All semaphores for each processor in SMM CPU Sync + /// + SMM_CPU_SYNC_SEMAPHORE_CPU *CpuSem; + /// + /// The number of processors in the system. + /// This does not indicate the number of processors that entered SMM. + /// + UINTN NumberOfCpus; + /// + /// Address of global and each CPU semaphores + /// + UINTN *SemBuffer; + /// + /// Size in bytes of global and each CPU semaphores + /// + UINTN SemBufferSize; +}; + +/** + Performs an atomic compare exchange operation to get semaphore. + The compare exchange operation must be performed using MP safe + mechanisms. + + @param[in,out] Sem IN: 32-bit unsigned integer + OUT: original integer - 1 + + @retval Original integer - 1 + +**/ +UINT32 +InternalWaitForSemaphore ( + IN OUT volatile UINT32 *Sem + ) +{ + UINT32 Value; + + for ( ; ;) { + Value =3D *Sem; + if ((Value !=3D 0) && + (InterlockedCompareExchange32 ( + (UINT32 *)Sem, + Value, + Value - 1 + ) =3D=3D Value)) + { + break; + } + + CpuPause (); + } + + return Value - 1; +} + +/** + Performs an atomic compare exchange operation to release semaphore. + The compare exchange operation must be performed using MP safe + mechanisms. + + @param[in,out] Sem IN: 32-bit unsigned integer + OUT: original integer + 1 + + @retval Original integer + 1 + +**/ +UINT32 +InternalReleaseSemaphore ( + IN OUT volatile UINT32 *Sem + ) +{ + UINT32 Value; + + do { + Value =3D *Sem; + } while (Value + 1 !=3D 0 && + InterlockedCompareExchange32 ( + (UINT32 *)Sem, + Value, + Value + 1 + ) !=3D Value); + + return Value + 1; +} + +/** + Performs an atomic compare exchange operation to lock semaphore. + The compare exchange operation must be performed using MP safe + mechanisms. + + @param[in,out] Sem IN: 32-bit unsigned integer + OUT: -1 + + @retval Original integer + +**/ +UINT32 +InternalLockdownSemaphore ( + IN OUT volatile UINT32 *Sem + ) +{ + UINT32 Value; + + do { + Value =3D *Sem; + } while (InterlockedCompareExchange32 ( + (UINT32 *)Sem, + Value, + (UINT32)-1 + ) !=3D Value); + + return Value; +} + +/** + Create and initialize the SMM CPU Sync context. + + SmmCpuSyncContextInit() function is to allocate and initialize the SMM C= PU Sync context. + + @param[in] NumberOfCpus The number of Logical Processors in th= e system. + @param[out] SmmCpuSyncCtx Pointer to the new created and initial= ized SMM CPU Sync context object. + NULL will be returned if any error hap= pen during init. + + @retval RETURN_SUCCESS The SMM CPU Sync context was successfu= l created and initialized. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL. + @retval RETURN_BUFFER_TOO_SMALL Overflow happen + @retval RETURN_OUT_OF_RESOURCES There are not enough resources availab= le to create and initialize SMM CPU Sync context. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncContextInit ( + IN UINTN NumberOfCpus, + OUT SMM_CPU_SYNC_CONTEXT **SmmCpuSyncCtx + ) +{ + RETURN_STATUS Status; + UINTN CpuSemInCtxSize; + UINTN CtxSize; + UINTN OneSemSize; + UINTN GlobalSemSize; + UINTN OneCpuSemSize; + UINTN CpuSemSize; + UINTN TotalSemSize; + UINTN SemAddr; + UINTN CpuIndex; + + ASSERT (SmmCpuSyncCtx !=3D NULL); + if (SmmCpuSyncCtx =3D=3D NULL) { + return RETURN_INVALID_PARAMETER; + } + + // + // Count the CtxSize + // + Status =3D SafeUintnMult (NumberOfCpus, sizeof (SMM_CPU_SYNC_SEMAPHORE_C= PU), &CpuSemInCtxSize); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D SafeUintnAdd (sizeof (SMM_CPU_SYNC_CONTEXT), CpuSemInCtxSize,= &CtxSize); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D SafeUintnAdd (CtxSize, sizeof (SMM_CPU_SYNC_SEMAPHORE_GLOBAL)= , &CtxSize); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Allocate CtxSize buffer for the *SmmCpuSyncCtx + // + *SmmCpuSyncCtx =3D NULL; + *SmmCpuSyncCtx =3D (SMM_CPU_SYNC_CONTEXT *)AllocatePages (EFI_SIZE_TO_PA= GES (CtxSize)); + ASSERT (*SmmCpuSyncCtx !=3D NULL); + if (*SmmCpuSyncCtx =3D=3D NULL) { + return RETURN_OUT_OF_RESOURCES; + } + + (*SmmCpuSyncCtx)->GlobalSem =3D (SMM_CPU_SYNC_SEMAPHORE_GLOBAL *)((UI= NT8 *)(*SmmCpuSyncCtx) + sizeof (SMM_CPU_SYNC_CONTEXT)); + (*SmmCpuSyncCtx)->CpuSem =3D (SMM_CPU_SYNC_SEMAPHORE_CPU *)((UINT8= *)(*SmmCpuSyncCtx) + sizeof (SMM_CPU_SYNC_CONTEXT) + sizeof (SMM_CPU_SYNC_= SEMAPHORE_GLOBAL)); + (*SmmCpuSyncCtx)->NumberOfCpus =3D NumberOfCpus; + + // + // Count the TotalSemSize + // + OneSemSize =3D GetSpinLockProperties (); + + Status =3D SafeUintnMult (OneSemSize, sizeof (SMM_CPU_SYNC_SEMAPHORE_GLO= BAL) / sizeof (VOID *), &GlobalSemSize); + if (EFI_ERROR (Status)) { + goto ON_ERROR; + } + + Status =3D SafeUintnMult (OneSemSize, sizeof (SMM_CPU_SYNC_SEMAPHORE_CPU= ) / sizeof (VOID *), &OneCpuSemSize); + if (EFI_ERROR (Status)) { + goto ON_ERROR; + } + + Status =3D SafeUintnMult (NumberOfCpus, OneCpuSemSize, &CpuSemSize); + if (EFI_ERROR (Status)) { + goto ON_ERROR; + } + + Status =3D SafeUintnAdd (GlobalSemSize, CpuSemSize, &TotalSemSize); + if (EFI_ERROR (Status)) { + goto ON_ERROR; + } + + DEBUG ((DEBUG_INFO, "[%a] - One Semaphore Size =3D 0x%x\n", __func__,= OneSemSize)); + DEBUG ((DEBUG_INFO, "[%a] - Total Semaphores Size =3D 0x%x\n", __func__,= TotalSemSize)); + + // + // Allocate for Semaphores in the *SmmCpuSyncCtx + // + (*SmmCpuSyncCtx)->SemBufferSize =3D TotalSemSize; + (*SmmCpuSyncCtx)->SemBuffer =3D AllocatePages (EFI_SIZE_TO_PAGES ((*= SmmCpuSyncCtx)->SemBufferSize)); + ASSERT ((*SmmCpuSyncCtx)->SemBuffer !=3D NULL); + if ((*SmmCpuSyncCtx)->SemBuffer =3D=3D NULL) { + Status =3D RETURN_OUT_OF_RESOURCES; + goto ON_ERROR; + } + + ZeroMem ((*SmmCpuSyncCtx)->SemBuffer, TotalSemSize); + + // + // Assign Global Semaphore pointer + // + SemAddr =3D (UINTN)(*SmmCpuSyncCtx)->SemBu= ffer; + (*SmmCpuSyncCtx)->GlobalSem->Counter =3D (UINT32 *)SemAddr; + *(*SmmCpuSyncCtx)->GlobalSem->Counter =3D 0; + DEBUG ((DEBUG_INFO, "[%a] - (*SmmCpuSyncCtx)->GlobalSem->Counter Address= : 0x%08x\n", __func__, (UINTN)(*SmmCpuSyncCtx)->GlobalSem->Counter)); + + SemAddr +=3D GlobalSemSize; + + // + // Assign CPU Semaphore pointer + // + for (CpuIndex =3D 0; CpuIndex < NumberOfCpus; CpuIndex++) { + (*SmmCpuSyncCtx)->CpuSem[CpuIndex].Run =3D (UINT32 *)(SemAddr + (CpuS= emSize / NumberOfCpus) * CpuIndex); + *(*SmmCpuSyncCtx)->CpuSem[CpuIndex].Run =3D 0; + DEBUG ((DEBUG_INFO, "[%a] - (*SmmCpuSyncCtx)->CpuSem[%d].Run Address: = 0x%08x\n", __func__, CpuIndex, (UINTN)(*SmmCpuSyncCtx)->CpuSem[CpuIndex].Ru= n)); + } + + return RETURN_SUCCESS; + +ON_ERROR: + FreePages (*SmmCpuSyncCtx, EFI_SIZE_TO_PAGES (CtxSize)); + return Status; +} + +/** + Deinit an allocated SMM CPU Sync context. + + SmmCpuSyncContextDeinit() function is to deinitialize SMM CPU Sync conte= xt, the resources allocated in + SmmCpuSyncContextInit() will be freed. + + Note: This function only can be called after SmmCpuSyncContextInit() ret= urn success. + + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync context ob= ject to be deinitialized. + + @retval RETURN_SUCCESS The SMM CPU Sync context was successfu= l deinitialized. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL. + @retval RETURN_UNSUPPORTED Unsupported operation. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncContextDeinit ( + IN OUT SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx + ) +{ + UINTN SmmCpuSyncCtxSize; + + ASSERT (SmmCpuSyncCtx !=3D NULL); + if (SmmCpuSyncCtx =3D=3D NULL) { + return RETURN_INVALID_PARAMETER; + } + + SmmCpuSyncCtxSize =3D sizeof (SMM_CPU_SYNC_CONTEXT) + sizeof (SMM_CPU_SY= NC_SEMAPHORE_GLOBAL) + sizeof (SMM_CPU_SYNC_SEMAPHORE_CPU) * (SmmCpuSyncCtx= ->NumberOfCpus); + + FreePages (SmmCpuSyncCtx->SemBuffer, EFI_SIZE_TO_PAGES (SmmCpuSyncCtx->S= emBufferSize)); + + FreePages (SmmCpuSyncCtx, EFI_SIZE_TO_PAGES (SmmCpuSyncCtxSize)); + + return RETURN_SUCCESS; +} + +/** + Reset SMM CPU Sync context. + + SmmCpuSyncContextReset() function is to reset SMM CPU Sync context to th= e initialized state. + + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync context ob= ject to be reset. + + @retval RETURN_SUCCESS The SMM CPU Sync context was successfu= l reset. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncContextReset ( + IN OUT SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx + ) +{ + ASSERT (SmmCpuSyncCtx !=3D NULL); + if (SmmCpuSyncCtx =3D=3D NULL) { + return RETURN_INVALID_PARAMETER; + } + + *SmmCpuSyncCtx->GlobalSem->Counter =3D 0; + + return RETURN_SUCCESS; +} + +/** + Get current number of arrived CPU in SMI. + + For traditional CPU synchronization method, BSP might need to know the c= urrent number of arrived CPU in + SMI to make sure all APs in SMI. This API can be for that purpose. + + @param[in] SmmCpuSyncCtx Pointer to the SMM CPU Sync context ob= ject. + @param[in,out] CpuCount Current count of arrived CPU in SMI. + + @retval RETURN_SUCCESS Get current number of arrived CPU in S= MI successfully. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx or CpuCount is NULL. + @retval RETURN_UNSUPPORTED Unsupported operation. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncGetArrivedCpuCount ( + IN SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx, + IN OUT UINTN *CpuCount + ) +{ + ASSERT (SmmCpuSyncCtx !=3D NULL && CpuCount !=3D NULL); + if ((SmmCpuSyncCtx =3D=3D NULL) || (CpuCount =3D=3D NULL)) { + return RETURN_INVALID_PARAMETER; + } + + if (*SmmCpuSyncCtx->GlobalSem->Counter < 0) { + return RETURN_UNSUPPORTED; + } + + *CpuCount =3D *SmmCpuSyncCtx->GlobalSem->Counter; + + return RETURN_SUCCESS; +} + +/** + Performs an atomic operation to check in CPU. + + When SMI happens, all processors including BSP enter to SMM mode by call= ing SmmCpuSyncCheckInCpu(). + + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync context ob= ject. + @param[in] CpuIndex Check in CPU index. + + @retval RETURN_SUCCESS Check in CPU (CpuIndex) successfully. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL. + @retval RETURN_ABORTED Check in CPU failed due to SmmCpuSyncL= ockDoor() has been called by one elected CPU. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncCheckInCpu ( + IN OUT SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx, + IN UINTN CpuIndex + ) +{ + ASSERT (SmmCpuSyncCtx !=3D NULL); + if (SmmCpuSyncCtx =3D=3D NULL) { + return RETURN_INVALID_PARAMETER; + } + + // + // Check to return if Counter has already been locked. + // + if ((INT32)InternalReleaseSemaphore (SmmCpuSyncCtx->GlobalSem->Counter) = <=3D 0) { + return RETURN_ABORTED; + } + + return RETURN_SUCCESS; +} + +/** + Performs an atomic operation to check out CPU. + + CheckOutCpu() can be called in error handling flow for the CPU who calls= CheckInCpu() earlier. + + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync context ob= ject. + @param[in] CpuIndex Check out CPU index. + + @retval RETURN_SUCCESS Check out CPU (CpuIndex) successfully. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL. + @retval RETURN_NOT_READY The CPU is not checked-in. + @retval RETURN_UNSUPPORTED Unsupported operation. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncCheckOutCpu ( + IN OUT SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx, + IN UINTN CpuIndex + ) +{ + ASSERT (SmmCpuSyncCtx !=3D NULL); + if (SmmCpuSyncCtx =3D=3D NULL) { + return RETURN_INVALID_PARAMETER; + } + + if (*SmmCpuSyncCtx->GlobalSem->Counter =3D=3D 0) { + return RETURN_NOT_READY; + } + + if ((INT32)InternalWaitForSemaphore (SmmCpuSyncCtx->GlobalSem->Counter) = < 0) { + return RETURN_UNSUPPORTED; + } + + return RETURN_SUCCESS; +} + +/** + Performs an atomic operation lock door for CPU checkin or checkout. + + After this function, CPU can not check in via SmmCpuSyncCheckInCpu(). + + The CPU specified by CpuIndex is elected to lock door. + + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync context ob= ject. + @param[in] CpuIndex Indicate which CPU to lock door. + @param[in,out] CpuCount Number of arrived CPU in SMI after loo= k door. + + @retval RETURN_SUCCESS Lock door for CPU successfully. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx or CpuCount is NULL. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncLockDoor ( + IN OUT SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx, + IN UINTN CpuIndex, + IN OUT UINTN *CpuCount + ) +{ + ASSERT (SmmCpuSyncCtx !=3D NULL && CpuCount !=3D NULL); + if ((SmmCpuSyncCtx =3D=3D NULL) || (CpuCount =3D=3D NULL)) { + return RETURN_INVALID_PARAMETER; + } + + *CpuCount =3D InternalLockdownSemaphore (SmmCpuSyncCtx->GlobalSem->Count= er); + + return RETURN_SUCCESS; +} + +/** + Used by the BSP to wait for APs. + + The number of APs need to be waited is specified by NumberOfAPs. The BSP= is specified by BspIndex. + + Note: This function is blocking mode, and it will return only after the = number of APs released by + calling SmmCpuSyncReleaseBsp(): + BSP: WaitForAPs <-- AP: ReleaseBsp + + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync context ob= ject. + @param[in] NumberOfAPs Number of APs need to be waited by BSP. + @param[in] BspIndex The BSP Index to wait for APs. + + @retval RETURN_SUCCESS BSP to wait for APs successfully. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL or NumberOfAPs >= total number of processors in system. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncWaitForAPs ( + IN OUT SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx, + IN UINTN NumberOfAPs, + IN UINTN BspIndex + ) +{ + ASSERT (SmmCpuSyncCtx !=3D NULL && NumberOfAPs <=3D SmmCpuSyncCtx->Numbe= rOfCpus); + if ((SmmCpuSyncCtx =3D=3D NULL) || (NumberOfAPs > SmmCpuSyncCtx->NumberO= fCpus)) { + return RETURN_INVALID_PARAMETER; + } + + while (NumberOfAPs-- > 0) { + InternalWaitForSemaphore (SmmCpuSyncCtx->CpuSem[BspIndex].Run); + } + + return RETURN_SUCCESS; +} + +/** + Used by the BSP to release one AP. + + The AP is specified by CpuIndex. The BSP is specified by BspIndex. + + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync context ob= ject. + @param[in] CpuIndex Indicate which AP need to be released. + @param[in] BspIndex The BSP Index to release AP. + + @retval RETURN_SUCCESS BSP to release one AP successfully. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL or CpuIndex is s= ame as BspIndex. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncReleaseOneAp ( + IN OUT SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx, + IN UINTN CpuIndex, + IN UINTN BspIndex + ) +{ + ASSERT (SmmCpuSyncCtx !=3D NULL && BspIndex !=3D CpuIndex); + if ((SmmCpuSyncCtx =3D=3D NULL) || (BspIndex =3D=3D CpuIndex)) { + return RETURN_INVALID_PARAMETER; + } + + InternalReleaseSemaphore (SmmCpuSyncCtx->CpuSem[CpuIndex].Run); + + return RETURN_SUCCESS; +} + +/** + Used by the AP to wait BSP. + + The AP is specified by CpuIndex. The BSP is specified by BspIndex. + + Note: This function is blocking mode, and it will return only after the = AP released by + calling SmmCpuSyncReleaseOneAp(): + BSP: ReleaseOneAp --> AP: WaitForBsp + + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync context obj= ect. + @param[in] CpuIndex Indicate which AP wait BSP. + @param[in] BspIndex The BSP Index to be waited. + + @retval RETURN_SUCCESS AP to wait BSP successfully. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL or CpuIndex is s= ame as BspIndex. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncWaitForBsp ( + IN OUT SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx, + IN UINTN CpuIndex, + IN UINTN BspIndex + ) +{ + ASSERT (SmmCpuSyncCtx !=3D NULL && BspIndex !=3D CpuIndex); + if ((SmmCpuSyncCtx =3D=3D NULL) || (BspIndex =3D=3D CpuIndex)) { + return RETURN_INVALID_PARAMETER; + } + + InternalWaitForSemaphore (SmmCpuSyncCtx->CpuSem[CpuIndex].Run); + + return RETURN_SUCCESS; +} + +/** + Used by the AP to release BSP. + + The AP is specified by CpuIndex. The BSP is specified by BspIndex. + + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync context ob= ject. + @param[in] CpuIndex Indicate which AP release BSP. + @param[in] BspIndex The BSP Index to be released. + + @retval RETURN_SUCCESS AP to release BSP successfully. + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL or CpuIndex is s= ame as BspIndex. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncReleaseBsp ( + IN OUT SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx, + IN UINTN CpuIndex, + IN UINTN BspIndex + ) +{ + ASSERT (SmmCpuSyncCtx !=3D NULL && BspIndex !=3D CpuIndex); + if ((SmmCpuSyncCtx =3D=3D NULL) || (BspIndex =3D=3D CpuIndex)) { + return RETURN_INVALID_PARAMETER; + } + + InternalReleaseSemaphore (SmmCpuSyncCtx->CpuSem[BspIndex].Run); + + return RETURN_SUCCESS; +} diff --git a/UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf b/UefiCpuPk= g/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf new file mode 100644 index 0000000000..6bb1895577 --- /dev/null +++ b/UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf @@ -0,0 +1,39 @@ +## @file +# SMM CPU Synchronization lib. +# +# This is SMM CPU Synchronization lib used for SMM CPU sync operations. +# +# Copyright (c) 2023, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SmmCpuSyncLib + FILE_GUID =3D 1ca1bc1a-16a4-46ef-956a-ca500fd3381f + MODULE_TYPE =3D DXE_SMM_DRIVER + LIBRARY_CLASS =3D SmmCpuSyncLib|DXE_SMM_DRIVER + +[Sources] + SmmCpuSyncLib.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + UefiLib + BaseLib + DebugLib + PrintLib + SafeIntLib + SynchronizationLib + BaseMemoryLib + SmmServicesTableLib + MemoryAllocationLib + +[Pcd] + +[Protocols] diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index 074fd77461..f264031c77 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -23,10 +23,11 @@ # =20 !include MdePkg/MdeLibs.dsc.inc =20 [LibraryClasses] + SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf BaseLib|MdePkg/Library/BaseLib/BaseLib.inf BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull= .inf @@ -54,10 +55,11 @@ CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMain= tenanceLib.inf PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCp= uPlatformHookLibNull.inf SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib= .inf + SmmCpuSyncLib|UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeC= offExtraActionLibNull.inf TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem= entLibNull.inf CcExitLib|UefiCpuPkg/Library/CcExitLibNull/CcExitLibNull.inf MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf @@ -154,10 +156,11 @@ UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.inf UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.i= nf UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLib.inf + UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf UefiCpuPkg/Library/CcExitLibNull/CcExitLibNull.inf UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf UefiCpuPkg/SecCore/SecCore.inf UefiCpuPkg/SecCore/SecCoreNative.inf --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112111): https://edk2.groups.io/g/devel/message/112111 Mute This Topic: https://groups.io/mt/103010165/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 17 20:49:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+112112+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112112+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1701856898; cv=none; d=zohomail.com; s=zohoarc; b=gHbkRxIgA46LDPbCreLtRWq47pSpAaaoshGFYQclxuU+wFRGZAHTkaaC5N1F5dd/PuO4hOdVKs+Bq1zSAsqeg/nsMm362lAzWSkPBQ8zsM/iu7RsCFOukLOrru5/JAYOfybdnWjYPPhLzrKCExL4HwC5TUnrP1epk0jhria6arI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1701856898; h=Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=7eAjhun5kWctBDV43UsPDCS8WYpNRXASVs9x4T4gdTs=; b=PRT0hPbytl2TfuzxK5vGsntUMwbldAXYR2mqgSbrPVDIEv2OD/u3xAKnR6hagU7Ye8Cgr7dx67kLe/s0YyoHxY+Th8EzbrRTAnj4yS17+G8lhWzFWuS0Vf5R4cfLsUVfa91/Zs8b5M4+mdww2Q6hl9mUTZBlOcm4VX2Z1JhJ2zY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112112+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1701856898536714.8215861124459; Wed, 6 Dec 2023 02:01:38 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=rUCO+zb8AbI7WJGBRWOiq/SuEkqREUsU5KSWU8UMEEY=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe; s=20140610; t=1701856898; v=1; b=SLCFkdALhls6CE1itvXQaG2qDCSTzvin7TikkUN/ek8ThYTBVm79uLE+XWQNIMGL2Tm+hsi4 1sgUQI8TgfRUvsh8wY+Lc0MZNqxdFwjmTr99eeUrf4Q2RPPOmFqc3i0g1aCvH8ZzHgCg/pz6PCt 74j/p68n9odyX/Bbd5kJuIvQ= X-Received: by 127.0.0.2 with SMTP id n5W2YY1788612x4ArXxzEO9r; Wed, 06 Dec 2023 02:01:38 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by mx.groups.io with SMTP id smtpd.web11.28132.1701856892226271583 for ; Wed, 06 Dec 2023 02:01:37 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10915"; a="1130588" X-IronPort-AV: E=Sophos;i="6.04,254,1695711600"; d="scan'208";a="1130588" X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Dec 2023 02:01:37 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10915"; a="841775366" X-IronPort-AV: E=Sophos;i="6.04,254,1695711600"; d="scan'208";a="841775366" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by fmsmga004.fm.intel.com with ESMTP; 06 Dec 2023 02:01:34 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Laszlo Ersek , Ard Biesheuvel , Jiewen Yao , Jordan Justen , Eric Dong , Ray Ni , Zeng Star , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [PATCH v3 4/6] OvmfPkg: Specifies SmmCpuSyncLib instance Date: Wed, 6 Dec 2023 18:01:20 +0800 Message-Id: <20231206100122.8028-5-jiaxin.wu@intel.com> In-Reply-To: <20231206100122.8028-1-jiaxin.wu@intel.com> References: <20231206100122.8028-1-jiaxin.wu@intel.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: dLnurJCJVaqnFw9JVtjYpghax1787277AA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1701856900345100020 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch is to specify SmmCpuSyncLib instance for OvmfPkg. Cc: Laszlo Ersek Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Rahul Kumar Cc: Gerd Hoffmann Signed-off-by: Jiaxin Wu --- OvmfPkg/CloudHv/CloudHvX64.dsc | 2 ++ OvmfPkg/OvmfPkgIa32.dsc | 2 ++ OvmfPkg/OvmfPkgIa32X64.dsc | 2 ++ OvmfPkg/OvmfPkgX64.dsc | 1 + 4 files changed, 7 insertions(+) diff --git a/OvmfPkg/CloudHv/CloudHvX64.dsc b/OvmfPkg/CloudHv/CloudHvX64.dsc index 821ad1b9fa..f735b69a37 100644 --- a/OvmfPkg/CloudHv/CloudHvX64.dsc +++ b/OvmfPkg/CloudHv/CloudHvX64.dsc @@ -183,10 +183,12 @@ PeiHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/PeiHardwareInfoLib.inf DxeHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/DxeHardwareInfoLib.inf ImagePropertiesRecordLib|MdeModulePkg/Library/ImagePropertiesRecordLib/I= magePropertiesRecordLib.inf !if $(SMM_REQUIRE) =3D=3D FALSE LockBoxLib|OvmfPkg/Library/LockBoxLib/LockBoxBaseLib.inf +!else + SmmCpuSyncLib|UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf !endif CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltL= ib.inf MemEncryptTdxLib|OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemEncryptTdxL= ib.inf =20 diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index bce2aedcd7..b05b13b18c 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -188,10 +188,12 @@ PeiHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/PeiHardwareInfoLib.inf DxeHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/DxeHardwareInfoLib.inf ImagePropertiesRecordLib|MdeModulePkg/Library/ImagePropertiesRecordLib/I= magePropertiesRecordLib.inf !if $(SMM_REQUIRE) =3D=3D FALSE LockBoxLib|OvmfPkg/Library/LockBoxLib/LockBoxBaseLib.inf +!else + SmmCpuSyncLib|UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf !endif CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltL= ib.inf =20 !if $(SOURCE_DEBUG_ENABLE) =3D=3D TRUE diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index 631e909a54..5a16eb7abe 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -193,10 +193,12 @@ PeiHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/PeiHardwareInfoLib.inf DxeHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/DxeHardwareInfoLib.inf ImagePropertiesRecordLib|MdeModulePkg/Library/ImagePropertiesRecordLib/I= magePropertiesRecordLib.inf !if $(SMM_REQUIRE) =3D=3D FALSE LockBoxLib|OvmfPkg/Library/LockBoxLib/LockBoxBaseLib.inf +!else + SmmCpuSyncLib|UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf !endif CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltL= ib.inf =20 !if $(SOURCE_DEBUG_ENABLE) =3D=3D TRUE diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index 4ea3008cc6..6bb4c777b9 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -209,10 +209,11 @@ !if $(SMM_REQUIRE) =3D=3D FALSE LockBoxLib|OvmfPkg/Library/LockBoxLib/LockBoxBaseLib.inf CcProbeLib|OvmfPkg/Library/CcProbeLib/DxeCcProbeLib.inf !else CcProbeLib|MdePkg/Library/CcProbeLibNull/CcProbeLibNull.inf + SmmCpuSyncLib|UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf !endif CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltL= ib.inf =20 !if $(SOURCE_DEBUG_ENABLE) =3D=3D TRUE --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112112): https://edk2.groups.io/g/devel/message/112112 Mute This Topic: https://groups.io/mt/103010166/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 17 20:49:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+112114+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112114+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1701856900; cv=none; d=zohomail.com; s=zohoarc; b=lMUz68NQ3YyIDLcj9yj/aRiGLOafNXls7LdniZY4/YgfJmr4U7z+SIMS5tgO3gNJHCn88ArgIuaHF2GPimYBtoXr8KvG1LLK9UYJJ3osr82Rnjl/WZ39hE5HiW7eUT26LCRBoyRvaiquldVsjFXzxPhFFrsV03IjlKjCoobGwQA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1701856900; h=Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=YgVYX1o3v2WfjvuZMsRHsA9Q50MS8scnZ0u+ztGq7lE=; b=iMto7UVrvcBIqg4qYs1PfVJSNuFqYEEFVX3g8f3dckz7Euy8/vG6VdE+oPemfOjIeO8h45ssEz6lDYo/v/wB4NbH3nISE2BZ5b+WzEZAjwKLyqhF3qQvevwig6h6GkQqIdzHA7jkHIVfzUe3/n2Pqc5Zdf2rVfjQ2Nz+CCxgR+g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112114+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1701856900589884.4017705494267; Wed, 6 Dec 2023 02:01:40 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=m6PFXSWMLoFjjTq7g07HnmJDjAexha/AeZKRdvexrks=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe; s=20140610; t=1701856900; v=1; b=G8+UG/gWVa9gucACw/gOVskmxdljvfEyNbJdyouT545RC6xUadIYQF+COxBb4Ewy7Om3SrkO FgMxl4Gxyd4dqVpzUvfEZQnzdQU0eOb0NPELmx+E+h5/ouNCAxU218LbUxGsEhUU1wqsCu8fBTL Jt46kelfatOAyYHhoFRmbsE8= X-Received: by 127.0.0.2 with SMTP id bdlnYY1788612x0iXTtp9Lkb; Wed, 06 Dec 2023 02:01:40 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by mx.groups.io with SMTP id smtpd.web11.28132.1701856892226271583 for ; Wed, 06 Dec 2023 02:01:39 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10915"; a="1130604" X-IronPort-AV: E=Sophos;i="6.04,254,1695711600"; d="scan'208";a="1130604" X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Dec 2023 02:01:40 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10915"; a="841775373" X-IronPort-AV: E=Sophos;i="6.04,254,1695711600"; d="scan'208";a="841775373" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by fmsmga004.fm.intel.com with ESMTP; 06 Dec 2023 02:01:37 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Laszlo Ersek , Guo Dong , Sean Rhodes , James Lu , Gua Guo , Ray Ni , Zeng Star Subject: [edk2-devel] [PATCH v3 5/6] UefiPayloadPkg: Specifies SmmCpuSyncLib instance Date: Wed, 6 Dec 2023 18:01:21 +0800 Message-Id: <20231206100122.8028-6-jiaxin.wu@intel.com> In-Reply-To: <20231206100122.8028-1-jiaxin.wu@intel.com> References: <20231206100122.8028-1-jiaxin.wu@intel.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: XcLCcGEkQoXU4B2X6AYFK68Dx1787277AA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1701856902578100027 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch is to specify SmmCpuSyncLib instance for UefiPayloadPkg. Cc: Laszlo Ersek Cc: Guo Dong Cc: Sean Rhodes Cc: James Lu Cc: Gua Guo Cc: Ray Ni Cc: Zeng Star Signed-off-by: Jiaxin Wu Reviewed-by: Gua Guo --- UefiPayloadPkg/UefiPayloadPkg.dsc | 1 + 1 file changed, 1 insertion(+) diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayload= Pkg.dsc index a65f9d5b83..b8b13ad201 100644 --- a/UefiPayloadPkg/UefiPayloadPkg.dsc +++ b/UefiPayloadPkg/UefiPayloadPkg.dsc @@ -253,10 +253,11 @@ # MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf + SmmCpuSyncLib|UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf =20 # # Platform # !if $(CPU_TIMER_LIB_ENABLE) =3D=3D TRUE && $(UNIVERSAL_PAYLOAD) =3D=3D TRUE --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112114): https://edk2.groups.io/g/devel/message/112114 Mute This Topic: https://groups.io/mt/103010167/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 17 20:49:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+112115+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112115+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1701856912; cv=none; d=zohomail.com; s=zohoarc; b=bEzcgcdiecEWUr4fN9ycGbN1gCmJdQtRqWGt6TE0WOMgz2Eh8Iz+/qZb7gYRPpyE79Vl/kXUM4rPhJChUUsbuVLZl+GxyUmijOH4uUFM1QL92r52glLi1T+v83fKTT79o1plWTz2CMe61p9HkMuRexyhHNA2rYk1rFGkhapc9aI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1701856912; h=Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=PgodLWbGWfWVldd0in1xOXdCt3AuOmT4rhhQedvMM9U=; b=DhPEqGTmn+wc2Iuj5qhhyQcyv0jQsBvNIPpZprAWRnd1ZnhuhVla2DF3afHJFJAtN/uIxST0syihhoAbHp/vBJM6qRxpS7d9JFVWFvgBdMjtc3FctmWSQd6q+Q8vq0bc7sk0e90n/XYFam8kkTeCN/rtEpc/nSn97cK3SEI+qfU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112115+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1701856912109578.5542170403661; Wed, 6 Dec 2023 02:01:52 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=Y7lWOqDbRqq4u+gBeKmV4aYyTEsz/mdjKHcS/2adpys=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe; s=20140610; t=1701856911; v=1; b=xMmGhjjQOEt9fep4Obs75Yyby9crI3BnAyGIifU6K/SGjwF1BuXXu2RQZ2UELGqeks7FR4Qd CcG/xjSmYBBz1F96jhOvQZnSFb7TRKPifxyKhcZ3sQ2zmxXAXXrBx5kfRImFjLrJueu8FPhwqsy rILkWK0/XCJQ978nn39rzbTk= X-Received: by 127.0.0.2 with SMTP id L9WOYY1788612xvjLXk05qDW; Wed, 06 Dec 2023 02:01:51 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by mx.groups.io with SMTP id smtpd.web10.28366.1701856910741963433 for ; Wed, 06 Dec 2023 02:01:51 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10915"; a="1130679" X-IronPort-AV: E=Sophos;i="6.04,254,1695711600"; d="scan'208";a="1130679" X-Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Dec 2023 02:01:50 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10915"; a="841775476" X-IronPort-AV: E=Sophos;i="6.04,254,1695711600"; d="scan'208";a="841775476" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by fmsmga004.fm.intel.com with ESMTP; 06 Dec 2023 02:01:39 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Laszlo Ersek , Eric Dong , Ray Ni , Zeng Star , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v3 6/6] UefiCpuPkg/PiSmmCpuDxeSmm: Consume SmmCpuSyncLib Date: Wed, 6 Dec 2023 18:01:22 +0800 Message-Id: <20231206100122.8028-7-jiaxin.wu@intel.com> In-Reply-To: <20231206100122.8028-1-jiaxin.wu@intel.com> References: <20231206100122.8028-1-jiaxin.wu@intel.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: Om9dkArB6NUyuEPbYQpik6vCx1787277AA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1701856912558100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There is the SmmCpuSyncLib Library class define the SMM CPU sync flow, which is aligned with existing SMM CPU driver sync behavior. This patch is to consume SmmCpuSyncLib instance directly. With this change, SMM CPU Sync flow/logic can be customized with different implementation no matter for any purpose, e.g. performance tuning, handle specific register, etc. Cc: Laszlo Ersek Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 317 +++++++++--------------= ---- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 6 +- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 1 + 3 files changed, 110 insertions(+), 214 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxe= Smm/MpService.c index 54542262a2..e37c03d0e5 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -27,122 +27,10 @@ MM_COMPLETION mSmmStartupThisApToken; // // Processor specified by mPackageFirstThreadIndex[PackageIndex] will do t= he package-scope register check. // UINT32 *mPackageFirstThreadIndex =3D NULL; =20 -/** - Performs an atomic compare exchange operation to get semaphore. - The compare exchange operation must be performed using - MP safe mechanisms. - - @param Sem IN: 32-bit unsigned integer - OUT: original integer - 1 - @return Original integer - 1 - -**/ -UINT32 -WaitForSemaphore ( - IN OUT volatile UINT32 *Sem - ) -{ - UINT32 Value; - - for ( ; ;) { - Value =3D *Sem; - if ((Value !=3D 0) && - (InterlockedCompareExchange32 ( - (UINT32 *)Sem, - Value, - Value - 1 - ) =3D=3D Value)) - { - break; - } - - CpuPause (); - } - - return Value - 1; -} - -/** - Performs an atomic compare exchange operation to release semaphore. - The compare exchange operation must be performed using - MP safe mechanisms. - - @param Sem IN: 32-bit unsigned integer - OUT: original integer + 1 - @return Original integer + 1 - -**/ -UINT32 -ReleaseSemaphore ( - IN OUT volatile UINT32 *Sem - ) -{ - UINT32 Value; - - do { - Value =3D *Sem; - } while (Value + 1 !=3D 0 && - InterlockedCompareExchange32 ( - (UINT32 *)Sem, - Value, - Value + 1 - ) !=3D Value); - - return Value + 1; -} - -/** - Performs an atomic compare exchange operation to lock semaphore. - The compare exchange operation must be performed using - MP safe mechanisms. - - @param Sem IN: 32-bit unsigned integer - OUT: -1 - @return Original integer - -**/ -UINT32 -LockdownSemaphore ( - IN OUT volatile UINT32 *Sem - ) -{ - UINT32 Value; - - do { - Value =3D *Sem; - } while (InterlockedCompareExchange32 ( - (UINT32 *)Sem, - Value, - (UINT32)-1 - ) !=3D Value); - - return Value; -} - -/** - Used for BSP to wait all APs. - Wait all APs to performs an atomic compare exchange operation to release= semaphore. - - @param NumberOfAPs AP number - -**/ -VOID -WaitForAllAPs ( - IN UINTN NumberOfAPs - ) -{ - UINTN BspIndex; - - BspIndex =3D mSmmMpSyncData->BspIndex; - while (NumberOfAPs-- > 0) { - WaitForSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run); - } -} - /** Used for BSP to release all APs. Performs an atomic compare exchange operation to release semaphore for each AP. =20 @@ -154,57 +42,15 @@ ReleaseAllAPs ( { UINTN Index; =20 for (Index =3D 0; Index < mMaxNumberOfCpus; Index++) { if (IsPresentAp (Index)) { - ReleaseSemaphore (mSmmMpSyncData->CpuData[Index].Run); + SmmCpuSyncReleaseOneAp (mSmmMpSyncData->SmmCpuSyncCtx, Index, gSmmCp= uPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu); } } } =20 -/** - Used for BSP to release one AP. - - @param ApSem IN: 32-bit unsigned integer - OUT: original integer + 1 -**/ -VOID -ReleaseOneAp ( - IN OUT volatile UINT32 *ApSem - ) -{ - ReleaseSemaphore (ApSem); -} - -/** - Used for AP to wait BSP. - - @param ApSem IN: 32-bit unsigned integer - OUT: original integer - 1 -**/ -VOID -WaitForBsp ( - IN OUT volatile UINT32 *ApSem - ) -{ - WaitForSemaphore (ApSem); -} - -/** - Used for AP to release BSP. - - @param BspSem IN: 32-bit unsigned integer - OUT: original integer + 1 -**/ -VOID -ReleaseBsp ( - IN OUT volatile UINT32 *BspSem - ) -{ - ReleaseSemaphore (BspSem); -} - /** Check whether the index of CPU perform the package level register programming during System Management Mode initialization. =20 The index of Processor specified by mPackageFirstThreadIndex[PackageInde= x] @@ -285,42 +131,53 @@ GetSmmDelayedBlockedDisabledCount ( BOOLEAN AllCpusInSmmExceptBlockedDisabled ( VOID ) { + RETURN_STATUS Status; + + UINTN CpuCount; UINT32 BlockedCount; UINT32 DisabledCount; =20 + CpuCount =3D 0; BlockedCount =3D 0; DisabledCount =3D 0; =20 + Status =3D SmmCpuSyncGetArrivedCpuCount (mSmmMpSyncData->SmmCpuSyncCtx, = &CpuCount); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "AllCpusInSmmExceptBlockedDisabled: SmmCpuSyncGet= ArrivedCpuCount return error %r!\n", Status)); + CpuDeadLoop (); + return FALSE; + } + // - // Check to make sure mSmmMpSyncData->Counter is valid and not locked. + // Check to make sure the CPU arrival count is valid and not locked. // - ASSERT (*mSmmMpSyncData->Counter <=3D mNumberOfCpus); + ASSERT (CpuCount <=3D mNumberOfCpus); =20 // // Check whether all CPUs in SMM. // - if (*mSmmMpSyncData->Counter =3D=3D mNumberOfCpus) { + if (CpuCount =3D=3D mNumberOfCpus) { return TRUE; } =20 // // Check for the Blocked & Disabled Exceptions Case. // GetSmmDelayedBlockedDisabledCount (NULL, &BlockedCount, &DisabledCount); =20 // - // *mSmmMpSyncData->Counter might be updated by all APs concurrently. Th= e value + // The CPU arrival count might be updated by all APs concurrently. The v= alue // can be dynamic changed. If some Aps enter the SMI after the BlockedCo= unt & - // DisabledCount check, then the *mSmmMpSyncData->Counter will be increa= sed, thus - // leading the *mSmmMpSyncData->Counter + BlockedCount + DisabledCount >= mNumberOfCpus. + // DisabledCount check, then the CPU arrival count will be increased, th= us + // leading the retrieved CPU arrival count + BlockedCount + DisabledCoun= t > mNumberOfCpus. // since the BlockedCount & DisabledCount are local variable, it's ok he= re only for // the checking of all CPUs In Smm. // - if (*mSmmMpSyncData->Counter + BlockedCount + DisabledCount >=3D mNumber= OfCpus) { + if (CpuCount + BlockedCount + DisabledCount >=3D mNumberOfCpus) { return TRUE; } =20 return FALSE; } @@ -384,23 +241,35 @@ IsLmceSignaled ( VOID SmmWaitForApArrival ( VOID ) { + RETURN_STATUS Status; + + UINTN CpuCount; UINT64 Timer; UINTN Index; BOOLEAN LmceEn; BOOLEAN LmceSignal; UINT32 DelayedCount; UINT32 BlockedCount; =20 PERF_FUNCTION_BEGIN (); =20 + CpuCount =3D 0; DelayedCount =3D 0; BlockedCount =3D 0; =20 - ASSERT (*mSmmMpSyncData->Counter <=3D mNumberOfCpus); + Status =3D SmmCpuSyncGetArrivedCpuCount (mSmmMpSyncData->SmmCpuSyncCtx, = &CpuCount); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "SmmWaitForApArrival: SmmCpuSyncGetArrivedCpuCoun= t return error %r!\n", Status)); + CpuDeadLoop (); + PERF_FUNCTION_END (); + return; + } + + ASSERT (CpuCount <=3D mNumberOfCpus); =20 LmceEn =3D FALSE; LmceSignal =3D FALSE; if (mMachineCheckSupported) { LmceEn =3D IsLmceOsEnabled (); @@ -431,10 +300,21 @@ SmmWaitForApArrival ( } =20 CpuPause (); } =20 + // + // Check the CpuCount after Sync with APs 1st. + // + Status =3D SmmCpuSyncGetArrivedCpuCount (mSmmMpSyncData->SmmCpuSyncCtx, = &CpuCount); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "SmmWaitForApArrival: SmmCpuSyncGetArrivedCpuCoun= t return error %r!\n", Status)); + CpuDeadLoop (); + PERF_FUNCTION_END (); + return; + } + // // Not all APs have arrived, so we need 2nd round of timeout. IPIs shoul= d be sent to ALL none present APs, // because: // a) Delayed AP may have just come out of the delayed state. Blocked AP= may have just been brought out of blocked state by some AP running // normal mode code. These APs need to be guaranteed to have an SMI p= ending to insure that once they are out of delayed / blocked state, they @@ -447,11 +327,11 @@ SmmWaitForApArrival ( // d) We don't add code to check SMI disabling status to skip sending IP= I to SMI disabled APs, because: // - In traditional flow, SMI disabling is discouraged. // - In relaxed flow, CheckApArrival() will check SMI disabling statu= s before calling this function. // In both cases, adding SMI-disabling checking code increases overhe= ad. // - if (*mSmmMpSyncData->Counter < mNumberOfCpus) { + if (CpuCount < mNumberOfCpus) { // // Send SMI IPIs to bring outside processors in // for (Index =3D 0; Index < mMaxNumberOfCpus; Index++) { if (!(*(mSmmMpSyncData->CpuData[Index].Present)) && (gSmmCpuPrivate-= >ProcessorInfo[Index].ProcessorId !=3D INVALID_APIC_ID)) { @@ -610,18 +490,22 @@ VOID BSPHandler ( IN UINTN CpuIndex, IN SMM_CPU_SYNC_MODE SyncMode ) { + RETURN_STATUS Status; + + UINTN CpuCount; UINTN Index; MTRR_SETTINGS Mtrrs; UINTN ApCount; BOOLEAN ClearTopLevelSmiResult; UINTN PresentCount; =20 ASSERT (CpuIndex =3D=3D mSmmMpSyncData->BspIndex); - ApCount =3D 0; + CpuCount =3D 0; + ApCount =3D 0; =20 PERF_FUNCTION_BEGIN (); =20 // // Flag BSP's presence @@ -659,28 +543,35 @@ BSPHandler ( // Wait for APs to arrive // SmmWaitForApArrival (); =20 // - // Lock the counter down and retrieve the number of APs + // Lock door for late comming CPU checkin and retrieve the Arrived num= ber of APs // *mSmmMpSyncData->AllCpusInSync =3D TRUE; - ApCount =3D LockdownSemaphore (mSmmMpSyncData->= Counter) - 1; + + Status =3D SmmCpuSyncLockDoor (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex= , &CpuCount); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "BSPHandler: SmmCpuSyncLockDoor return error %r= !\n", Status)); + CpuDeadLoop (); + } + + ApCount =3D CpuCount - 1; =20 // // Wait for all APs to get ready for programming MTRRs // - WaitForAllAPs (ApCount); + SmmCpuSyncWaitForAPs (mSmmMpSyncData->SmmCpuSyncCtx, ApCount, CpuIndex= ); =20 if (SmmCpuFeaturesNeedConfigureMtrrs ()) { // // Signal all APs it's time for backup MTRRs // ReleaseAllAPs (); =20 // - // WaitForAllAPs() may wait for ever if an AP happens to enter SMM at + // SmmCpuSyncWaitForAPs() may wait for ever if an AP happens to ente= r SMM at // exactly this point. Please make sure PcdCpuSmmMaxSyncLoops has be= en set // to a large enough value to avoid this situation. // Note: For HT capable CPUs, threads within a core share the same s= et of MTRRs. // We do the backup first and then set MTRR to avoid race condition = for threads // in the same core. @@ -688,28 +579,28 @@ BSPHandler ( MtrrGetAllMtrrs (&Mtrrs); =20 // // Wait for all APs to complete their MTRR saving // - WaitForAllAPs (ApCount); + SmmCpuSyncWaitForAPs (mSmmMpSyncData->SmmCpuSyncCtx, ApCount, CpuInd= ex); =20 // // Let all processors program SMM MTRRs together // ReleaseAllAPs (); =20 // - // WaitForAllAPs() may wait for ever if an AP happens to enter SMM at + // SmmCpuSyncWaitForAPs() may wait for ever if an AP happens to ente= r SMM at // exactly this point. Please make sure PcdCpuSmmMaxSyncLoops has be= en set // to a large enough value to avoid this situation. // ReplaceOSMtrrs (CpuIndex); =20 // // Wait for all APs to complete their MTRR programming // - WaitForAllAPs (ApCount); + SmmCpuSyncWaitForAPs (mSmmMpSyncData->SmmCpuSyncCtx, ApCount, CpuInd= ex); } } =20 // // The BUSY lock is initialized to Acquired state @@ -741,14 +632,21 @@ BSPHandler ( // make those APs to exit SMI synchronously. APs which arrive later will= be excluded and // will run through freely. // if ((SyncMode !=3D SmmCpuSyncModeTradition) && !SmmCpuFeaturesNeedConfig= ureMtrrs ()) { // - // Lock the counter down and retrieve the number of APs + // Lock door for late comming CPU checkin and retrieve the Arrived num= ber of APs // *mSmmMpSyncData->AllCpusInSync =3D TRUE; - ApCount =3D LockdownSemaphore (mSmmMpSyncData->= Counter) - 1; + Status =3D SmmCpuSyncLockDoor (mSmmMpSyncData-= >SmmCpuSyncCtx, CpuIndex, &CpuCount); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "BSPHandler: SmmCpuSyncLockDoor return error %r= !\n", Status)); + CpuDeadLoop (); + } + + ApCount =3D CpuCount - 1; + // // Make sure all APs have their Present flag set // while (TRUE) { PresentCount =3D 0; @@ -771,11 +669,11 @@ BSPHandler ( ReleaseAllAPs (); =20 // // Wait for all APs to complete their pending tasks // - WaitForAllAPs (ApCount); + SmmCpuSyncWaitForAPs (mSmmMpSyncData->SmmCpuSyncCtx, ApCount, CpuIndex); =20 if (SmmCpuFeaturesNeedConfigureMtrrs ()) { // // Signal APs to restore MTRRs // @@ -788,11 +686,11 @@ BSPHandler ( MtrrSetAllMtrrs (&Mtrrs); =20 // // Wait for all APs to complete MTRR programming // - WaitForAllAPs (ApCount); + SmmCpuSyncWaitForAPs (mSmmMpSyncData->SmmCpuSyncCtx, ApCount, CpuIndex= ); } =20 // // Stop source level debug in BSP handler, the code below will not be // debugged. @@ -816,11 +714,11 @@ BSPHandler ( =20 // // Gather APs to exit SMM synchronously. Note the Present flag is cleare= d by now but // WaitForAllAps does not depend on the Present flag. // - WaitForAllAPs (ApCount); + SmmCpuSyncWaitForAPs (mSmmMpSyncData->SmmCpuSyncCtx, ApCount, CpuIndex); =20 // // At this point, all APs should have exited from APHandler(). // Migrate the SMM MP performance logging to standard SMM performance lo= gging. // Any SMM MP performance logging after this point will be migrated in n= ext SMI. @@ -842,11 +740,11 @@ BSPHandler ( } =20 // // Allow APs to check in from this point on // - *mSmmMpSyncData->Counter =3D 0; + SmmCpuSyncContextReset (mSmmMpSyncData->SmmCpuSyncCtx); *mSmmMpSyncData->AllCpusInSync =3D FALSE; mSmmMpSyncData->AllApArrivedWithException =3D FALSE; =20 PERF_FUNCTION_END (); } @@ -912,21 +810,21 @@ APHandler ( =20 if (!(*mSmmMpSyncData->InsideSmm)) { // // Give up since BSP is unable to enter SMM // and signal the completion of this AP - // Reduce the mSmmMpSyncData->Counter! + // Reduce the CPU arrival count! // - WaitForSemaphore (mSmmMpSyncData->Counter); + SmmCpuSyncCheckOutCpu (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex); return; } } else { // // Don't know BSP index. Give up without sending IPI to BSP. - // Reduce the mSmmMpSyncData->Counter! + // Reduce the CPU arrival count! // - WaitForSemaphore (mSmmMpSyncData->Counter); + SmmCpuSyncCheckOutCpu (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex); return; } } =20 // @@ -942,50 +840,50 @@ APHandler ( =20 if ((SyncMode =3D=3D SmmCpuSyncModeTradition) || SmmCpuFeaturesNeedConfi= gureMtrrs ()) { // // Notify BSP of arrival at this point // - ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); + SmmCpuSyncReleaseBsp (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex, BspInde= x); } =20 if (SmmCpuFeaturesNeedConfigureMtrrs ()) { // // Wait for the signal from BSP to backup MTRRs // - WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); + SmmCpuSyncWaitForBsp (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex, BspInde= x); =20 // // Backup OS MTRRs // MtrrGetAllMtrrs (&Mtrrs); =20 // // Signal BSP the completion of this AP // - ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); + SmmCpuSyncReleaseBsp (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex, BspInde= x); =20 // // Wait for BSP's signal to program MTRRs // - WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); + SmmCpuSyncWaitForBsp (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex, BspInde= x); =20 // // Replace OS MTRRs with SMI MTRRs // ReplaceOSMtrrs (CpuIndex); =20 // // Signal BSP the completion of this AP // - ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); + SmmCpuSyncReleaseBsp (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex, BspInde= x); } =20 while (TRUE) { // // Wait for something to happen // - WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); + SmmCpuSyncWaitForBsp (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex, BspInde= x); =20 // // Check if BSP wants to exit SMM // if (!(*mSmmMpSyncData->InsideSmm)) { @@ -1021,16 +919,16 @@ APHandler ( =20 if (SmmCpuFeaturesNeedConfigureMtrrs ()) { // // Notify BSP the readiness of this AP to program MTRRs // - ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); + SmmCpuSyncReleaseBsp (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex, BspInde= x); =20 // // Wait for the signal from BSP to program MTRRs // - WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); + SmmCpuSyncWaitForBsp (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex, BspInde= x); =20 // // Restore OS MTRRs // SmmCpuFeaturesReenableSmrr (); @@ -1038,26 +936,26 @@ APHandler ( } =20 // // Notify BSP the readiness of this AP to Reset states/semaphore for thi= s processor // - ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); + SmmCpuSyncReleaseBsp (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex, BspIndex); =20 // // Wait for the signal from BSP to Reset states/semaphore for this proce= ssor // - WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); + SmmCpuSyncWaitForBsp (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex, BspIndex); =20 // // Reset states/semaphore for this processor // *(mSmmMpSyncData->CpuData[CpuIndex].Present) =3D FALSE; =20 // // Notify BSP the readiness of this AP to exit SMM // - ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); + SmmCpuSyncReleaseBsp (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex, BspIndex); } =20 /** Checks whether the input token is the current used token. =20 @@ -1321,11 +1219,11 @@ InternalSmmStartupThisAp ( mSmmMpSyncData->CpuData[CpuIndex].Status =3D CpuStatus; if (mSmmMpSyncData->CpuData[CpuIndex].Status !=3D NULL) { *mSmmMpSyncData->CpuData[CpuIndex].Status =3D EFI_NOT_READY; } =20 - ReleaseOneAp (mSmmMpSyncData->CpuData[CpuIndex].Run); + SmmCpuSyncReleaseOneAp (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex, gSmmCpu= Private->SmmCoreEntryContext.CurrentlyExecutingCpu); =20 if (Token =3D=3D NULL) { AcquireSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Busy); ReleaseSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Busy); } @@ -1450,11 +1348,11 @@ InternalSmmStartupAllAPs ( =20 // // Decrease the count to mark this processor(AP or BSP) as finished. // if (ProcToken !=3D NULL) { - WaitForSemaphore (&ProcToken->RunningApCount); + InterlockedDecrement (&ProcToken->RunningApCount); } } } =20 ReleaseAllAPs (); @@ -1725,14 +1623,15 @@ SmiRendezvous ( // goto Exit; } else { // // Signal presence of this processor - // mSmmMpSyncData->Counter is increased here! - // "ReleaseSemaphore (mSmmMpSyncData->Counter) =3D=3D 0" means BSP has= already ended the synchronization. + // CPU check in here! + // "SmmCpuSyncCheckInCpu (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex)" re= turn error means failed + // to check in CPU. BSP has already ended the synchronization. // - if (ReleaseSemaphore (mSmmMpSyncData->Counter) =3D=3D 0) { + if (RETURN_ERROR (SmmCpuSyncCheckInCpu (mSmmMpSyncData->SmmCpuSyncCtx,= CpuIndex))) { // // BSP has already ended the synchronization, so QUIT!!! // Existing AP is too late now to enter SMI since BSP has already en= ded the synchronization!!! // =20 @@ -1824,12 +1723,10 @@ SmiRendezvous ( } else { APHandler (CpuIndex, ValidSmi, mSmmMpSyncData->EffectiveSyncMode); } } =20 - ASSERT (*mSmmMpSyncData->CpuData[CpuIndex].Run =3D=3D 0); - // // Wait for BSP's signal to exit SMI // while (*mSmmMpSyncData->AllCpusInSync) { CpuPause (); @@ -1945,12 +1842,10 @@ InitializeSmmCpuSemaphores ( SemaphoreBlock =3D AllocatePages (Pages); ASSERT (SemaphoreBlock !=3D NULL); ZeroMem (SemaphoreBlock, TotalSize); =20 SemaphoreAddr =3D (UINTN)SemaphoreBloc= k; - mSmmCpuSemaphores.SemaphoreGlobal.Counter =3D (UINT32 *)SemaphoreA= ddr; - SemaphoreAddr +=3D SemaphoreSize; mSmmCpuSemaphores.SemaphoreGlobal.InsideSmm =3D (BOOLEAN *)Semaphore= Addr; SemaphoreAddr +=3D SemaphoreSize; mSmmCpuSemaphores.SemaphoreGlobal.AllCpusInSync =3D (BOOLEAN *)Semaphore= Addr; SemaphoreAddr +=3D SemaphoreSize; mSmmCpuSemaphores.SemaphoreGlobal.PFLock =3D (SPIN_LOCK *)Semapho= reAddr; @@ -1960,12 +1855,10 @@ InitializeSmmCpuSemaphores ( SemaphoreAddr +=3D SemaphoreSize; =20 SemaphoreAddr =3D (UINTN)SemaphoreBlock + Globa= lSemaphoresSize; mSmmCpuSemaphores.SemaphoreCpu.Busy =3D (SPIN_LOCK *)SemaphoreAddr; SemaphoreAddr +=3D ProcessorCount * SemaphoreSiz= e; - mSmmCpuSemaphores.SemaphoreCpu.Run =3D (UINT32 *)SemaphoreAddr; - SemaphoreAddr +=3D ProcessorCount * SemaphoreSiz= e; mSmmCpuSemaphores.SemaphoreCpu.Present =3D (BOOLEAN *)SemaphoreAddr; =20 mPFLock =3D mSmmCpuSemaphores.SemaphoreGlobal.PFLo= ck; mConfigSmmCodeAccessCheckLock =3D mSmmCpuSemaphores.SemaphoreGlobal.Code= AccessCheckLock; =20 @@ -1980,10 +1873,12 @@ VOID EFIAPI InitializeMpSyncData ( VOID ) { + RETURN_STATUS Status; + UINTN CpuIndex; =20 if (mSmmMpSyncData !=3D NULL) { // // mSmmMpSyncDataSize includes one structure of SMM_DISPATCHER_MP_SYNC= _DATA, one @@ -2009,32 +1904,34 @@ InitializeMpSyncData ( } } =20 mSmmMpSyncData->EffectiveSyncMode =3D mCpuSmmSyncMode; =20 - mSmmMpSyncData->Counter =3D mSmmCpuSemaphores.SemaphoreGlobal.Co= unter; + Status =3D SmmCpuSyncContextInit (gSmmCpuPrivate->SmmCoreEntryContext.= NumberOfCpus, &(mSmmMpSyncData->SmmCpuSyncCtx)); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "InitializeMpSyncData: SmmCpuSyncContextInit re= turn error %r!\n", Status)); + CpuDeadLoop (); + return; + } + mSmmMpSyncData->InsideSmm =3D mSmmCpuSemaphores.SemaphoreGlobal.In= sideSmm; mSmmMpSyncData->AllCpusInSync =3D mSmmCpuSemaphores.SemaphoreGlobal.Al= lCpusInSync; ASSERT ( - mSmmMpSyncData->Counter !=3D NULL && mSmmMpSyncData->InsideSmm !=3D = NULL && + mSmmMpSyncData->SmmCpuSyncCtx !=3D NULL && mSmmMpSyncData->InsideSmm= !=3D NULL && mSmmMpSyncData->AllCpusInSync !=3D NULL ); - *mSmmMpSyncData->Counter =3D 0; *mSmmMpSyncData->InsideSmm =3D FALSE; *mSmmMpSyncData->AllCpusInSync =3D FALSE; =20 mSmmMpSyncData->AllApArrivedWithException =3D FALSE; =20 for (CpuIndex =3D 0; CpuIndex < gSmmCpuPrivate->SmmCoreEntryContext.Nu= mberOfCpus; CpuIndex++) { mSmmMpSyncData->CpuData[CpuIndex].Busy =3D (SPIN_LOCK *)((UINTN)mSmmCpuSemaphores.SemaphoreCpu.Busy + mSemaph= oreSize * CpuIndex); - mSmmMpSyncData->CpuData[CpuIndex].Run =3D - (UINT32 *)((UINTN)mSmmCpuSemaphores.SemaphoreCpu.Run + mSemaphoreS= ize * CpuIndex); mSmmMpSyncData->CpuData[CpuIndex].Present =3D (BOOLEAN *)((UINTN)mSmmCpuSemaphores.SemaphoreCpu.Present + mSemap= horeSize * CpuIndex); *(mSmmMpSyncData->CpuData[CpuIndex].Busy) =3D 0; - *(mSmmMpSyncData->CpuData[CpuIndex].Run) =3D 0; *(mSmmMpSyncData->CpuData[CpuIndex].Present) =3D FALSE; } } } =20 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.h index 20ada465c2..5b18ddde66 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -52,10 +52,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include #include #include +#include =20 #include #include =20 #include @@ -403,11 +404,10 @@ SmmRelocationSemaphoreComplete ( /// typedef struct { SPIN_LOCK *Busy; volatile EFI_AP_PROCEDURE2 Procedure; volatile VOID *Parameter; - volatile UINT32 *Run; volatile BOOLEAN *Present; PROCEDURE_TOKEN *Token; EFI_STATUS *Status; } SMM_CPU_DATA_BLOCK; =20 @@ -421,29 +421,28 @@ typedef struct { // // Pointer to an array. The array should be located immediately after th= is structure // so that UC cache-ability can be set together. // SMM_CPU_DATA_BLOCK *CpuData; - volatile UINT32 *Counter; volatile UINT32 BspIndex; volatile BOOLEAN *InsideSmm; volatile BOOLEAN *AllCpusInSync; volatile SMM_CPU_SYNC_MODE EffectiveSyncMode; volatile BOOLEAN SwitchBsp; volatile BOOLEAN *CandidateBsp; volatile BOOLEAN AllApArrivedWithException; EFI_AP_PROCEDURE StartupProcedure; VOID *StartupProcArgs; + SMM_CPU_SYNC_CONTEXT *SmmCpuSyncCtx; } SMM_DISPATCHER_MP_SYNC_DATA; =20 #define SMM_PSD_OFFSET 0xfb00 =20 /// /// All global semaphores' pointer /// typedef struct { - volatile UINT32 *Counter; volatile BOOLEAN *InsideSmm; volatile BOOLEAN *AllCpusInSync; SPIN_LOCK *PFLock; SPIN_LOCK *CodeAccessCheckLock; } SMM_CPU_SEMAPHORE_GLOBAL; @@ -451,11 +450,10 @@ typedef struct { /// /// All semaphores for each processor /// typedef struct { SPIN_LOCK *Busy; - volatile UINT32 *Run; volatile BOOLEAN *Present; SPIN_LOCK *Token; } SMM_CPU_SEMAPHORE_CPU; =20 /// diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf b/UefiCpuPkg/PiSm= mCpuDxeSmm/PiSmmCpuDxeSmm.inf index 5d52ed7d13..e92b8c747d 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf @@ -101,10 +101,11 @@ SmmCpuFeaturesLib PeCoffGetEntryPointLib PerformanceLib CpuPageTableLib MmSaveStateLib + SmmCpuSyncLib =20 [Protocols] gEfiSmmAccess2ProtocolGuid ## CONSUMES gEfiMpServiceProtocolGuid ## CONSUMES gEfiSmmConfigurationProtocolGuid ## PRODUCES --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112115): https://edk2.groups.io/g/devel/message/112115 Mute This Topic: https://groups.io/mt/103010168/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-