From nobody Mon Feb 9 16:35:02 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+112022+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112022+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1701678656; cv=none; d=zohomail.com; s=zohoarc; b=fgM7Xa8sXu7qsrmp35YwQ7tmuM8Q6SD8yYO3LJXkaWEQgck6gLxYYS9DP69XKXDMCLXKI4fxxYCr9LDFZzEEsznXJzgYtAY1SUjzaUF0YwCfG4Hy8ekN1sfBDp0hjs2JNir+knExE4SN7sJyc+4iqUy67BctF4mQHoF/eQSy8po= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1701678656; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=sLPAb2qJgIvq3TAXpbqoB3PUUGWKkhVuhC7xyqdooZU=; b=mppyt8S3hMxS9xYnZ1UFTszwIQPu0mSmtW3lXq22XAYx0+SG1Kq48jbCK2akRTYLV4shlwRCXeMzGf4LrkOCPuoGQTsAf5uZOMzK+DBLZ9gA6cB55p4Vp4GzaGNSjtDbU1qAsH2oaGiAKkOaBWFqopHMvTU9MhPFwZMcOIduqlg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112022+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1701678656173882.2328485444625; Mon, 4 Dec 2023 00:30:56 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=V9d3CKvvCuMlfnhT2n+peQX5UY7CrgkUTawM3PhzCBE=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1701678655; v=1; b=lySL7c3FrByfIhxKc4hcMcl9hCMAmTlC0D67LjnLoFSkUQa5vuKBV+S8r/+txC8OLo3C4iKQ 6GuLJNeRD2kbF/49WSpJ00q+ZgWMJGhG9Sx8IOLfr/AQTALjL98w+egcZ7iTtxRednmzlve/PMV CAF2tL3hYT8iTYNxXCZe+bYQ= X-Received: by 127.0.0.2 with SMTP id ymtIYY1788612xHgYkXwGsQx; Mon, 04 Dec 2023 00:30:55 -0800 X-Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) by mx.groups.io with SMTP id smtpd.web10.65022.1701678655199032752 for ; Mon, 04 Dec 2023 00:30:55 -0800 X-Received: by mail-pl1-f171.google.com with SMTP id d9443c01a7336-1cfc9c4acb6so14712915ad.0 for ; Mon, 04 Dec 2023 00:30:55 -0800 (PST) X-Gm-Message-State: nzS7Hyew4p1zen8QUwHUD7qIx1787277AA= X-Google-Smtp-Source: AGHT+IFNANn/iipgc2yp+qaMuLj6o65nc7oYsnEeQDtSxPY8TToY1GOW4GnvvJS4A4ndTKgppQTBgA== X-Received: by 2002:a17:902:d2c6:b0:1d0:9d92:f18d with SMTP id n6-20020a170902d2c600b001d09d92f18dmr922190plc.45.1701678654408; Mon, 04 Dec 2023 00:30:54 -0800 (PST) X-Received: from dhaval.blr.rivosinc.com ([49.249.129.34]) by smtp.gmail.com with ESMTPSA id h21-20020a170902f7d500b001d058ad8770sm5754211plw.306.2023.12.04.00.30.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Dec 2023 00:30:54 -0800 (PST) From: "Dhaval Sharma" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Laszlo Ersek Subject: [edk2-devel] [PATCH v9 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V Date: Mon, 4 Dec 2023 13:59:49 +0530 Message-Id: <20231204082950.96914-5-dhaval@rivosinc.com> In-Reply-To: <20231204082950.96914-1-dhaval@rivosinc.com> References: <20231204082950.96914-1-dhaval@rivosinc.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dhaval@rivosinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1701678657695100005 Content-Type: text/plain; charset="utf-8" Use newly defined cache management operations for RISC-V where possible It builds up on the support added for RISC-V cache management instructions in BaseLib. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Laszlo Ersek Signed-off-by: Dhaval Sharma Acked-by: Laszlo Ersek --- Notes: V9: - Fixed an issue with Instruction cache invalidation. Use fence.i instruction as CMO does not support i-cache operations. V8: - Added note to convert PCD into RISC-V feature bitmap pointer - Modified function names to be more explicit about cache ops - Added RB tag V7: - Added PcdLib - Restructure DEBUG message based on feedback on V6 - Make naming consistent to CMO, remove all CBO references - Add ASSERT for not supported functions instead of plain debug message - Added RB tag V6: - Utilize cache management instructions if HW supports it This patch is part of restructuring on top of v5 MdePkg/MdePkg.dec | 8 + MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf | 5 + MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 173 += +++++++++++++++---- MdePkg/MdePkg.uni | 4 + 4 files changed, 160 insertions(+), 30 deletions(-) diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index ac54338089e8..fa92673ff633 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -2399,6 +2399,14 @@ [PcdsFixedAtBuild.AARCH64, PcdsPatchableInModule.AAR= CH64] # @Prompt CPU Rng algorithm's GUID. gEfiMdePkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x00,0x0= 0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID*|0x0000= 0037 =20 +[PcdsFixedAtBuild.RISCV64, PcdsPatchableInModule.RISCV64] + # + # Configurability to override RISC-V CPU Features + # BIT 0 =3D Cache Management Operations. This bit is relevant only if + # previous stage has feature enabled and user wants to disable it. + # + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFF|UINT= 64|0x69 + [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] ## This value is used to set the base address of PCI express hierarchy. # @Prompt PCI Express Base Address. diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib= .inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf index 6fd9cbe5f6c9..601a38d6c109 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf @@ -56,3 +56,8 @@ [LibraryClasses] BaseLib DebugLib =20 +[LibraryClasses.RISCV64] + PcdLib + +[Pcd.RISCV64] + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride ## CONSUMES diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/L= ibrary/BaseCacheMaintenanceLib/RiscVCache.c index ac2a3c23a249..cacc38eff4f4 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c @@ -2,6 +2,7 @@ RISC-V specific functionality for cache. =20 Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2023, Rivos Inc. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -9,10 +10,117 @@ #include #include #include +#include + +// +// TODO: Grab cache block size and make Cache Management Operation +// enabling decision based on RISC-V CPU HOB in +// future when it is available and convert PcdRiscVFeatureOverride +// PCD to a pointer that contains pointer to bitmap structure +// which can be operated more elegantly. +// +#define RISCV_CACHE_BLOCK_SIZE 64 +#define RISCV_CPU_FEATURE_CMO_BITMASK 0x1 + +typedef enum { + CacheOpClean, + CacheOpFlush, + CacheOpInvld, +} CACHE_OP; + +/** +Verify CBOs are supported by this HW +TODO: Use RISC-V CPU HOB once available. + +**/ +STATIC +BOOLEAN +RiscVIsCMOEnabled ( + VOID + ) +{ + // If CMO is disabled in HW, skip Override check + // Otherwise this PCD can override settings + return ((PcdGet64 (PcdRiscVFeatureOverride) & RISCV_CPU_FEATURE_CMO_BITM= ASK) !=3D 0); +} + +/** + Performs required opeartion on cache lines in the cache coherency domain + of the calling CPU. If Address is not aligned on a cache line boundary, + then entire cache line containing Address is operated. If Address + Leng= th + is not aligned on a cache line boundary, then the entire cache line + containing Address + Length -1 is operated. + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + @param Address The base address of the cache lines to + invalidate. + @param Length The number of bytes to invalidate from the instruction + cache. + @param Op Type of CMO operation to be performed + @return Address. + +**/ +STATIC +VOID +CacheOpCacheRange ( + IN VOID *Address, + IN UINTN Length, + IN CACHE_OP Op + ) +{ + UINTN CacheLineSize; + UINTN Start; + UINTN End; + + if (Length =3D=3D 0) { + return; + } + + if ((Op !=3D CacheOpInvld) && (Op !=3D CacheOpFlush) && (Op !=3D CacheOp= Clean)) { + return; + } + + ASSERT ((Length - 1) <=3D (MAX_ADDRESS - (UINTN)Address)); + + CacheLineSize =3D RISCV_CACHE_BLOCK_SIZE; + + Start =3D (UINTN)Address; + // + // Calculate the cache line alignment + // + End =3D (Start + Length + (CacheLineSize - 1)) & ~(CacheLineSize - 1); + Start &=3D ~((UINTN)CacheLineSize - 1); + + DEBUG ( + (DEBUG_INFO, + "CacheOpCacheRange:\ + Performing Cache Management Operation %d \n", Op) + ); + + do { + switch (Op) { + case CacheOpInvld: + RiscVCpuCacheInvalCmoAsm (Start); + break; + case CacheOpFlush: + RiscVCpuCacheFlushCmoAsm (Start); + break; + case CacheOpClean: + RiscVCpuCacheCleanCmoAsm (Start); + break; + default: + break; + } + + Start =3D Start + CacheLineSize; + } while (Start !=3D End); +} =20 /** Invalidates the entire instruction cache in cache coherency domain of the - calling CPU. + calling CPU. Risc-V does not have currently an CBO implementation which = can + invalidate the entire I-cache. Hence using Fence instruction for now. P.= S. + Fence instruction may or may not implement full I-cache invd functionali= ty + on all implementations. =20 **/ VOID @@ -28,17 +136,10 @@ InvalidateInstructionCache ( Invalidates a range of instruction cache lines in the cache coherency do= main of the calling CPU. =20 - Invalidates the instruction cache lines specified by Address and Length.= If - Address is not aligned on a cache line boundary, then entire instruction - cache line containing Address is invalidated. If Address + Length is not - aligned on a cache line boundary, then the entire instruction cache line - containing Address + Length -1 is invalidated. This function may choose = to - invalidate the entire instruction cache if that is more efficient than - invalidating the specified range. If Length is 0, then no instruction ca= che - lines are invalidated. Address is returned. - - If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). - + An operation from a CMO instruction is defined to operate only on the co= pies of a cache block that are + cached in the caches accessible by the explicit memory accesses performe= d by the set of coherent agents. + In other words CMO operations are not applicable to instruction cache. U= se fence.i instruction instead + to achieve the same purpose. @param Address The base address of the instruction cache lines to invalidate. If the CPU is in a physical addressing mode,= then Address is a physical address. If the CPU is in a virtual @@ -56,11 +157,7 @@ InvalidateInstructionCacheRange ( IN UINTN Length ) { - DEBUG ( - (DEBUG_WARN, - "%a:RISC-V unsupported function.\n" - "Invalidating the whole instruction cache instead.\n", __func__) - ); + DEBUG ((DEBUG_VERBOSE, "InvalidateInstructionCache:\n")); InvalidateInstructionCache (); return Address; } @@ -81,7 +178,8 @@ WriteBackInvalidateDataCache ( VOID ) { - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__)); + DEBUG ((DEBUG_ERROR, "WriteBackInvalidateDataCache:\ + RISC-V unsupported function.\n")); } =20 /** @@ -117,7 +215,12 @@ WriteBackInvalidateDataCacheRange ( IN UINTN Length ) { - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__)); + if (RiscVIsCMOEnabled ()) { + CacheOpCacheRange (Address, Length, CacheOpFlush); + } else { + ASSERT (FALSE); + } + return Address; } =20 @@ -137,7 +240,7 @@ WriteBackDataCache ( VOID ) { - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__)); + ASSERT (FALSE); } =20 /** @@ -156,10 +259,7 @@ WriteBackDataCache ( =20 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). =20 - @param Address The base address of the data cache lines to write back. = If - the CPU is in a physical addressing mode, then Address i= s a - physical address. If the CPU is in a virtual addressing - mode, then Address is a virtual address. + @param Address The base address of the data cache lines to write back. @param Length The number of bytes to write back from the data cache. =20 @return Address of cache written in main memory. @@ -172,7 +272,12 @@ WriteBackDataCacheRange ( IN UINTN Length ) { - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__)); + if (RiscVIsCMOEnabled ()) { + CacheOpCacheRange (Address, Length, CacheOpClean); + } else { + ASSERT (FALSE); + } + return Address; } =20 @@ -214,10 +319,7 @@ InvalidateDataCache ( =20 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). =20 - @param Address The base address of the data cache lines to invalidate. = If - the CPU is in a physical addressing mode, then Address i= s a - physical address. If the CPU is in a virtual addressing = mode, - then Address is a virtual address. + @param Address The base address of the data cache lines to invalidate. @param Length The number of bytes to invalidate from the data cache. =20 @return Address. @@ -230,6 +332,17 @@ InvalidateDataCacheRange ( IN UINTN Length ) { - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__)); + if (RiscVIsCMOEnabled ()) { + CacheOpCacheRange (Address, Length, CacheOpInvld); + } else { + DEBUG ( + (DEBUG_VERBOSE, + "InvalidateDataCacheRange:\ + Zicbom not supported.\n" \ + "Invalidating the whole Data cache instead.\n") + ); + InvalidateDataCache (); + } + return Address; } diff --git a/MdePkg/MdePkg.uni b/MdePkg/MdePkg.uni index 5c1fa24065c7..f49c33191054 100644 --- a/MdePkg/MdePkg.uni +++ b/MdePkg/MdePkg.uni @@ -287,6 +287,10 @@ =20 #string STR_gEfiMdePkgTokenSpaceGuid_PcdGuidedExtractHandlerTableAddress_H= ELP #language en-US "This value is used to set the available memory addres= s to store Guided Extract Handlers. The required memory space is decided by= the value of PcdMaximumGuidedExtractHandler." =20 +#string STR_gEfiMdePkgTokenSpaceGuid_PcdRiscVFeatureOverride_PROMPT #lang= uage en-US "RISC-V Feature Override" + +#string STR_gEfiMdePkgTokenSpaceGuid_PcdRiscVFeatureOverride_HELP #langua= ge en-US "This value is used to Override Any RISC-V specific features suppo= rted by this PCD" + #string STR_gEfiMdePkgTokenSpaceGuid_PcdPciExpressBaseAddress_PROMPT #lan= guage en-US "PCI Express Base Address" =20 #string STR_gEfiMdePkgTokenSpaceGuid_PcdPciExpressBaseAddress_HELP #langu= age en-US "This value is used to set the base address of PCI express hierar= chy." --=20 2.39.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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