From nobody Thu May 16 07:26:01 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+110637+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+110637+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1699025422; cv=none; d=zohomail.com; s=zohoarc; b=kbhBxMswvOJEPgjCOzwBehVkJYSIS7pdaqz5dEncqMuCtU1wJXB42MgVGjaXEKIzaCLZDcuksTYqZGl1dJhH+jC2T14DGcKICT8k1ymQ8JrcoqHafKJU9IwgZxCZpHFtceMJs8kC98Sx6EjO5LwFyrtgJRlTX3nN9p7QY3OvqVk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699025422; h=Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=en+ymc1IclpERoyjNIBR1KjAuU8BJZdgcNcdyzb/ieM=; b=mad015tQYtrNuNiARiDKrtX68/mrCtnFBSdtF9FaQ1qML3MNRdafFxFrRKIKQqxwtOrek4R4Zwtgtza7iMl76ldL6yBjTknaP/wSQza4HXM8WkwfILSm9Zy8aw6V3lqPRR2H0TTFQ3iAgv9piH231/Xm4vHctVGKEgc5gkU6awE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+110637+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1699025422772160.35314395003502; Fri, 3 Nov 2023 08:30:22 -0700 (PDT) Return-Path: DKIM-Signature: a=rsa-sha256; bh=Y5TAuewVZkV+usdGOODL0cwcSfbQT2spDWuX/Q4xp8E=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe; s=20140610; t=1699025422; v=1; b=cFENQfwS/jKLFCJXQi+OMw1lHY/IQjQHl1IyddgC1JjB/QYAFMWYjpxq/XyLwNbcuLqVW6rW frir9ObU28rv+rcC/J7MHX4JieTLhXwAO4MHLr1vJ+QMizIBkNLBLx4EkqAjRu+l0e7KMooUooQ I0xCB/q/s6Y+KdzQDyEASQLk= X-Received: by 127.0.0.2 with SMTP id 3KaHYY1788612xDpQE9xKwrk; Fri, 03 Nov 2023 08:30:22 -0700 X-Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by mx.groups.io with SMTP id smtpd.web10.56401.1699025420211463760 for ; Fri, 03 Nov 2023 08:30:21 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10883"; a="1898858" X-IronPort-AV: E=Sophos;i="6.03,273,1694761200"; d="scan'208";a="1898858" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2023 08:30:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10883"; a="790793100" X-IronPort-AV: E=Sophos;i="6.03,273,1694761200"; d="scan'208";a="790793100" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by orsmga008.jf.intel.com with ESMTP; 03 Nov 2023 08:30:19 -0700 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [PATCH v1 1/7] UefiCpuPkg/PiSmmCpuDxeSmm: Optimize Semaphore Sync between BSP and AP Date: Fri, 3 Nov 2023 23:30:06 +0800 Message-Id: <20231103153012.3704-2-jiaxin.wu@intel.com> In-Reply-To: <20231103153012.3704-1-jiaxin.wu@intel.com> References: <20231103153012.3704-1-jiaxin.wu@intel.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: GGy2URyg8rduZXsj3QhUbErbx1787277AA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1699025424985100007 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch is to define 3 new functions (WaitForBsp & ReleaseBsp & ReleaseOneAp) used for the semaphore sync between BSP & AP. With the change, BSP and AP Sync flow will be easy understand as below: BSP: ReleaseAllAPs or ReleaseOneAp --> AP: WaitForBsp BSP: WaitForAllAPs <-- AP: ReleaseBsp Change-Id: I0fb25e26e1015e918800f4d8d62e5276dcd5b5b1 Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Rahul Kumar Cc: Gerd Hoffmann Signed-off-by: Jiaxin Wu --- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 72 ++++++++++++++++++++++++++++---= ---- 1 file changed, 58 insertions(+), 14 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxe= Smm/MpService.c index 25d058c5b9..e96c7f51d6 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -120,10 +120,11 @@ LockdownSemaphore ( =20 return Value; } =20 /** + Used for BSP to wait all APs. Wait all APs to performs an atomic compare exchange operation to release= semaphore. =20 @param NumberOfAPs AP number =20 **/ @@ -139,10 +140,11 @@ WaitForAllAPs ( WaitForSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run); } } =20 /** + Used for BSP to release all APs. Performs an atomic compare exchange operation to release semaphore for each AP. =20 **/ VOID @@ -157,10 +159,52 @@ ReleaseAllAPs ( ReleaseSemaphore (mSmmMpSyncData->CpuData[Index].Run); } } } =20 +/** + Used for BSP to release one AP. + + @param ApSem IN: 32-bit unsigned integer + OUT: original integer + 1 +**/ +VOID +ReleaseOneAp ( + IN OUT volatile UINT32 *ApSem + ) +{ + ReleaseSemaphore (ApSem); +} + +/** + Used for AP to wait BSP. + + @param ApSem IN: 32-bit unsigned integer + OUT: original integer 0 +**/ +VOID +WaitForBsp ( + IN OUT volatile UINT32 *ApSem + ) +{ + WaitForSemaphore (ApSem); +} + +/** + Used for AP to release BSP. + + @param BspSem IN: 32-bit unsigned integer + OUT: original integer + 1 +**/ +VOID +ReleaseBsp ( + IN OUT volatile UINT32 *BspSem + ) +{ + ReleaseSemaphore (BspSem); +} + /** Check whether the index of CPU perform the package level register programming during System Management Mode initialization. =20 The index of Processor specified by mPackageFirstThreadIndex[PackageInde= x] @@ -632,11 +676,11 @@ BSPHandler ( // Signal all APs it's time for backup MTRRs // ReleaseAllAPs (); =20 // - // WaitForSemaphore() may wait for ever if an AP happens to enter SM= M at + // WaitForBsp() may wait for ever if an AP happens to enter SMM at // exactly this point. Please make sure PcdCpuSmmMaxSyncLoops has be= en set // to a large enough value to avoid this situation. // Note: For HT capable CPUs, threads within a core share the same s= et of MTRRs. // We do the backup first and then set MTRR to avoid race condition = for threads // in the same core. @@ -652,11 +696,11 @@ BSPHandler ( // Let all processors program SMM MTRRs together // ReleaseAllAPs (); =20 // - // WaitForSemaphore() may wait for ever if an AP happens to enter SM= M at + // WaitForBsp() may wait for ever if an AP happens to enter SMM at // exactly this point. Please make sure PcdCpuSmmMaxSyncLoops has be= en set // to a large enough value to avoid this situation. // ReplaceOSMtrrs (CpuIndex); =20 @@ -898,50 +942,50 @@ APHandler ( =20 if ((SyncMode =3D=3D SmmCpuSyncModeTradition) || SmmCpuFeaturesNeedConfi= gureMtrrs ()) { // // Notify BSP of arrival at this point // - ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run); + ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); } =20 if (SmmCpuFeaturesNeedConfigureMtrrs ()) { // // Wait for the signal from BSP to backup MTRRs // - WaitForSemaphore (mSmmMpSyncData->CpuData[CpuIndex].Run); + WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); =20 // // Backup OS MTRRs // MtrrGetAllMtrrs (&Mtrrs); =20 // // Signal BSP the completion of this AP // - ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run); + ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); =20 // // Wait for BSP's signal to program MTRRs // - WaitForSemaphore (mSmmMpSyncData->CpuData[CpuIndex].Run); + WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); =20 // // Replace OS MTRRs with SMI MTRRs // ReplaceOSMtrrs (CpuIndex); =20 // // Signal BSP the completion of this AP // - ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run); + ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); } =20 while (TRUE) { // // Wait for something to happen // - WaitForSemaphore (mSmmMpSyncData->CpuData[CpuIndex].Run); + WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); =20 // // Check if BSP wants to exit SMM // if (!(*mSmmMpSyncData->InsideSmm)) { @@ -977,16 +1021,16 @@ APHandler ( =20 if (SmmCpuFeaturesNeedConfigureMtrrs ()) { // // Notify BSP the readiness of this AP to program MTRRs // - ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run); + ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); =20 // // Wait for the signal from BSP to program MTRRs // - WaitForSemaphore (mSmmMpSyncData->CpuData[CpuIndex].Run); + WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); =20 // // Restore OS MTRRs // SmmCpuFeaturesReenableSmrr (); @@ -994,26 +1038,26 @@ APHandler ( } =20 // // Notify BSP the readiness of this AP to Reset states/semaphore for thi= s processor // - ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run); + ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); =20 // // Wait for the signal from BSP to Reset states/semaphore for this proce= ssor // - WaitForSemaphore (mSmmMpSyncData->CpuData[CpuIndex].Run); + WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); =20 // // Reset states/semaphore for this processor // *(mSmmMpSyncData->CpuData[CpuIndex].Present) =3D FALSE; =20 // // Notify BSP the readiness of this AP to exit SMM // - ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run); + ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); } =20 /** Checks whether the input token is the current used token. =20 @@ -1277,11 +1321,11 @@ InternalSmmStartupThisAp ( mSmmMpSyncData->CpuData[CpuIndex].Status =3D CpuStatus; if (mSmmMpSyncData->CpuData[CpuIndex].Status !=3D NULL) { *mSmmMpSyncData->CpuData[CpuIndex].Status =3D EFI_NOT_READY; } =20 - ReleaseSemaphore (mSmmMpSyncData->CpuData[CpuIndex].Run); + ReleaseOneAp (mSmmMpSyncData->CpuData[CpuIndex].Run); =20 if (Token =3D=3D NULL) { AcquireSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Busy); ReleaseSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Busy); } --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110637): https://edk2.groups.io/g/devel/message/110637 Mute This Topic: https://groups.io/mt/102366297/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 16 07:26:01 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+110638+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+110638+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1699025425; cv=none; d=zohomail.com; s=zohoarc; b=LFSrblSTKJQ+5TkFu/9gW7utg5QPZ/quOY90ZFHUeoh5UVvay1CRVXnk1KVBcpSpzu2jI/R+/w+u5lzuX6xaDkpduhUNCfzMCFNU+cIR2JNQQeSo8YtbsBhv2CWdaneM5qEc7/LqkyrEbMpFtLEibg1WYpqjkb6SlShoiIBPnu8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699025425; h=Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=HgrR+zHb+H1iPnIlZIVq689UDEiZb2GhH24Y5P0kx0c=; b=f9eXZpkxlfxK//JkFc7goq9EtbRB0JhSeBkDegbzpi8q+pBCNTZYABHFtF//Bg6PpnpBzZwB5wYP0pT1BkSAn3HZhRStCj3VuUiq16I5UjHc2PnphZkzx5P6Je9mO/lWqhVqFUZT/kMIt076YB9g39uW6G4hF0xvstonNy9YXwM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+110638+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1699025425126380.90417739959526; Fri, 3 Nov 2023 08:30:25 -0700 (PDT) Return-Path: DKIM-Signature: a=rsa-sha256; bh=X/UxJVTvIpW6mkIwIRB1S5UnVlGvV/lHZvewA/SQ5us=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe; s=20140610; t=1699025424; v=1; b=xbTayOElgH4qMY7VasBXP9YTb3tSXTXfm8Z4iwAC3HWFLquqpGCtK6vCJiZP0GvGMcNcTl08 w+TJTSdEI371Sx30h96a4ClsXvpdt4AmxYpZLE2W/i6pwETmtCtVYcNb8EeiATG7FSa530TGKno 2e1LCaFrl3/VdR24GTYTGHHA= X-Received: by 127.0.0.2 with SMTP id umxCYY1788612xbBvQsq9GLn; Fri, 03 Nov 2023 08:30:24 -0700 X-Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by mx.groups.io with SMTP id smtpd.web10.56401.1699025420211463760 for ; Fri, 03 Nov 2023 08:30:24 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10883"; a="1898882" X-IronPort-AV: E=Sophos;i="6.03,273,1694761200"; d="scan'208";a="1898882" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2023 08:30:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10883"; a="790793145" X-IronPort-AV: E=Sophos;i="6.03,273,1694761200"; d="scan'208";a="790793145" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by orsmga008.jf.intel.com with ESMTP; 03 Nov 2023 08:30:21 -0700 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [PATCH v1 2/7] UefiCpuPkg/PiSmmCpuDxeSmm: Reduce times of BSP and AP Sync for SMM Exit Date: Fri, 3 Nov 2023 23:30:07 +0800 Message-Id: <20231103153012.3704-3-jiaxin.wu@intel.com> In-Reply-To: <20231103153012.3704-1-jiaxin.wu@intel.com> References: <20231103153012.3704-1-jiaxin.wu@intel.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 32Ssd4VV8EqeSmd6il0WqrDdx1787277AA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1699025427000100009 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" After review, there are unnecessary steps for BSP and AP sync for SMM exit. This patch is to reduce one round BSP and AP sync so as to improve SMI performance: BSP: WaitForAllAPs <-- AP: ReleaseBsp BSP: ReleaseAllAPs --> AP: WaitForBsp Change-Id: Ic33f42f3daa7ff1847e524d0c3d9cd4fcdefa61b Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Rahul Kumar Cc: Gerd Hoffmann Signed-off-by: Jiaxin Wu --- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 44 +++++++++++++++++++------------= ---- 1 file changed, 24 insertions(+), 20 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxe= Smm/MpService.c index e96c7f51d6..5a42a5dd12 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -665,11 +665,13 @@ BSPHandler ( // *mSmmMpSyncData->AllCpusInSync =3D TRUE; ApCount =3D LockdownSemaphore (mSmmMpSyncData->= Counter) - 1; =20 // - // Wait for all APs to get ready for programming MTRRs + // Wait for all APs: + // 1. Make sure all Aps have set the Present. + // 2. Get ready for programming MTRRs. // WaitForAllAPs (ApCount); =20 if (SmmCpuFeaturesNeedConfigureMtrrs ()) { // @@ -768,16 +770,16 @@ BSPHandler ( // Notify all APs to exit // *mSmmMpSyncData->InsideSmm =3D FALSE; ReleaseAllAPs (); =20 - // - // Wait for all APs to complete their pending tasks - // - WaitForAllAPs (ApCount); - if (SmmCpuFeaturesNeedConfigureMtrrs ()) { + // + // Wait for all APs to complete their pending tasks + // + WaitForAllAPs (ApCount); + // // Signal APs to restore MTRRs // ReleaseAllAPs (); =20 @@ -789,23 +791,23 @@ BSPHandler ( =20 // // Wait for all APs to complete MTRR programming // WaitForAllAPs (ApCount); + + // + // Signal APs to Reset states/semaphore for this processor + // + ReleaseAllAPs (); } =20 // // Stop source level debug in BSP handler, the code below will not be // debugged. // InitializeDebugAgent (DEBUG_AGENT_INIT_EXIT_SMI, NULL, NULL); =20 - // - // Signal APs to Reset states/semaphore for this processor - // - ReleaseAllAPs (); - // // Perform pending operations for hot-plug // SmmCpuUpdate (); =20 @@ -941,10 +943,12 @@ APHandler ( *(mSmmMpSyncData->CpuData[CpuIndex].Present) =3D TRUE; =20 if ((SyncMode =3D=3D SmmCpuSyncModeTradition) || SmmCpuFeaturesNeedConfi= gureMtrrs ()) { // // Notify BSP of arrival at this point + // 1. Set the Present. + // 2. Get ready for programming MTRRs. // ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); } =20 if (SmmCpuFeaturesNeedConfigureMtrrs ()) { @@ -1033,21 +1037,21 @@ APHandler ( // // Restore OS MTRRs // SmmCpuFeaturesReenableSmrr (); MtrrSetAllMtrrs (&Mtrrs); - } =20 - // - // Notify BSP the readiness of this AP to Reset states/semaphore for thi= s processor - // - ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); + // + // Notify BSP the readiness of this AP to Reset states/semaphore for t= his processor + // + ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); =20 - // - // Wait for the signal from BSP to Reset states/semaphore for this proce= ssor - // - WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); + // + // Wait for the signal from BSP to Reset states/semaphore for this pro= cessor + // + WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); + } =20 // // Reset states/semaphore for this processor // *(mSmmMpSyncData->CpuData[CpuIndex].Present) =3D FALSE; --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110638): https://edk2.groups.io/g/devel/message/110638 Mute This Topic: https://groups.io/mt/102366299/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 16 07:26:01 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+110639+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+110639+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1699025427; cv=none; d=zohomail.com; s=zohoarc; b=OzunZrORJqB8DEuDmsLEpOOiT76RGz775IomUl4YN2nv8D0kK3ZNf434AAQa1WzVP53ZtW6wKBn/ozGrhHWycwTGb3D3V6yYUrIh4gdJo0uwtgHszc/Fr+XDJxktSFRtGns+wAvZpqi473eE+vaxqsCWE06iQ7nYshRXkopgCXU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699025427; h=Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=C5LwqIMtQtZDgWhPEsxPk8SCbuzJBukloJPUEKC4KRg=; b=E4ef/8WmWgM1FMmkuHBXddCX804V5PL6H7O5ZNK2OVXRCRAgnDhRmJrIz3QcX2o4T9O1Vg6Y4OyOkrZzv5q5aF804akAQGy1x1oaBTQKPiTdLV/rawQ+M/FCtmDVwAJ4jPiLPQIPJZKPGQmQYyfj+gdhbMSbqBADglOYRigp3uk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+110639+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1699025427115765.5839683442987; Fri, 3 Nov 2023 08:30:27 -0700 (PDT) Return-Path: DKIM-Signature: a=rsa-sha256; bh=mRq1fVheQQ+9Ll7JEdRzCciVSt9wGsaBj33G4XKr4NI=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe; s=20140610; t=1699025426; v=1; b=FUIrkNoO+kYmxe8M2v/y4SDxcem2rryknE/8hLvXC+ye59B82E3ZnKVOolZYX+koCl8kv3RN PtU21pktnBlkLDi1GupkXuNL9eeKGqwNCB4nYKsR+PSUiOjpfyk8Fty6OOFl3zBnPkyn7hsN5Qg IfAmcJ0bPRRItEZpqVmeHL4U= X-Received: by 127.0.0.2 with SMTP id GAXrYY1788612xzHIyhljp25; Fri, 03 Nov 2023 08:30:26 -0700 X-Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by mx.groups.io with SMTP id smtpd.web10.56401.1699025420211463760 for ; Fri, 03 Nov 2023 08:30:26 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10883"; a="1898902" X-IronPort-AV: E=Sophos;i="6.03,273,1694761200"; d="scan'208";a="1898902" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2023 08:30:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10883"; a="790793181" X-IronPort-AV: E=Sophos;i="6.03,273,1694761200"; d="scan'208";a="790793181" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by orsmga008.jf.intel.com with ESMTP; 03 Nov 2023 08:30:23 -0700 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v1 3/7] UefiCpuPkg: Adds SmmCpuSyncLib library class Date: Fri, 3 Nov 2023 23:30:08 +0800 Message-Id: <20231103153012.3704-4-jiaxin.wu@intel.com> In-Reply-To: <20231103153012.3704-1-jiaxin.wu@intel.com> References: <20231103153012.3704-1-jiaxin.wu@intel.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: HXsqBmf2knweX2sQMJlmJJBnx1787277AA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1699025429043100013 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Intel is planning to provide different SMM CPU Sync implementation along with some specific registers to improve the SMI performance, hence need SmmCpuSyncLib Library for Intel. This patch is to: 1.Adds SmmCpuSyncLib Library class in UefiCpuPkg.dec. 2.Adds SmmCpuSyncLib.h function declaration header file. Change-Id: Ib7f5e317526e8b9e29b65e072bdb485dbd678817 Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- UefiCpuPkg/Include/Library/SmmCpuSyncLib.h | 191 +++++++++++++++++++++++++= ++++ UefiCpuPkg/UefiCpuPkg.dec | 3 + 2 files changed, 194 insertions(+) create mode 100644 UefiCpuPkg/Include/Library/SmmCpuSyncLib.h diff --git a/UefiCpuPkg/Include/Library/SmmCpuSyncLib.h b/UefiCpuPkg/Includ= e/Library/SmmCpuSyncLib.h new file mode 100644 index 0000000000..b9b190c516 --- /dev/null +++ b/UefiCpuPkg/Include/Library/SmmCpuSyncLib.h @@ -0,0 +1,191 @@ +/** @file +Library that provides SMM CPU Sync related operations. + +Copyright (c) 2023, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SMM_CPU_SYNC_LIB_H_ +#define SMM_CPU_SYNC_LIB_H_ + +#include + +/** + Creates and Init a new Smm Cpu Sync context. + + @param[in] NumberOfCpus The number of processors in the system. + + @return Pointer to an allocated Smm Cpu Sync context object. + If the creation failed, returns NULL. + +**/ +VOID * +EFIAPI +SmmCpuSyncContextInit ( + IN UINTN NumberOfCpus + ); + +/** + Deinit an allocated Smm Cpu Sync context object. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object = to be released. + +**/ +VOID +EFIAPI +SmmCpuSyncContextDeinit ( + IN VOID *SmmCpuSyncCtx + ); + +/** + Reset Smm Cpu Sync context object. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object = to be released. + +**/ +VOID +EFIAPI +SmmCpuSyncContextReset ( + IN VOID *SmmCpuSyncCtx + ); + +/** + Get current arrived CPU count. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object = to be released. + + @return Current number of arrived CPU count. + -1: indicate the door has been locked. + +**/ +UINT32 +EFIAPI +SmmCpuSyncGetArrivedCpuCount ( + IN VOID *SmmCpuSyncCtx + ); + +/** + Performs an atomic operation to check in CPU. + Check in CPU successfully if the returned arrival CPU count value is + positive, otherwise indicate the door has been locked, the CPU can + not checkin. + + @param[in] SmmCpuSyncCtx Pointer to the Smm CPU Sync context object = to be released. + @param[in] CpuIndex Pointer to the CPU Index to checkin. + + @return Positive value (>0): CPU arrival count number after chec= k in CPU successfully. + Nonpositive value (<=3D0): check in CPU failure. + +**/ +INT32 +EFIAPI +SmmCpuSyncCheckInCpu ( + IN VOID *SmmCpuSyncCtx, + IN UINTN CpuIndex + ); + +/** + Performs an atomic operation to check out CPU. + Check out CPU successfully if the returned arrival CPU count value is + nonnegative, otherwise indicate the door has been locked, the CPU can + not checkout. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object = to be released. + @param[in] CpuIndex Pointer to the Cpu Index to checkout. + + @return Nonnegative value (>=3D0): CPU arrival count number after ch= eck out CPU successfully. + Negative value (<0): Check out CPU failure. + + +**/ +INT32 +EFIAPI +SmmCpuSyncCheckOutCpu ( + IN VOID *SmmCpuSyncCtx, + IN UINTN CpuIndex + ); + +/** + Performs an atomic operation lock door for CPU checkin or checkout. + With this function, CPU can not check in via SmmCpuSyncCheckInCpu () or + check out via SmmCpuSyncCheckOutCpu (). + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object = to be released. + @param[in] CpuIndex Pointer to the Cpu Index to lock door. + + @return CPU arrival count number. + +**/ +UINT32 +EFIAPI +SmmCpuSyncLockDoor ( + IN VOID *SmmCpuSyncCtx, + IN UINTN CpuIndex + ); + +/** + Used for BSP to wait all APs. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object. + @param[in] NumberOfAPs Number of APs need to wait. + @param[in] BspIndex Pointer to the BSP Index. + +**/ +VOID +EFIAPI +SmmCpuSyncWaitForAllAPs ( + IN VOID *SmmCpuSyncCtx, + IN UINTN NumberOfAPs, + IN UINTN BspIndex + ); + +/** + Used for BSP to release one AP. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object. + @param[in] CpuIndex Pointer to the Cpu Index, indicate which AP= need to be released. + @param[in] BspIndex Pointer to the BSP Index. + +**/ +VOID +EFIAPI +SmmCpuSyncReleaseOneAp ( + IN VOID *SmmCpuSyncCtx, + IN UINTN CpuIndex, + IN UINTN BspIndex + ); + +/** + Used for AP to wait BSP. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object. + @param[in] CpuIndex Pointer to the Cpu Index, indicate which AP= wait BSP. + @param[in] BspIndex Pointer to the BSP Index. + +**/ +VOID +EFIAPI +SmmCpuSyncWaitForBsp ( + IN VOID *SmmCpuSyncCtx, + IN UINTN CpuIndex, + IN UINTN BspIndex + ); + +/** + Used for AP to release BSP. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object. + @param[in] CpuIndex Pointer to the Cpu Index, indicate which AP= release BSP. + @param[in] BspIndex Pointer to the BSP Index. + +**/ +VOID +EFIAPI +SmmCpuSyncReleaseBsp ( + IN VOID *SmmCpuSyncCtx, + IN UINTN CpuIndex, + IN UINTN BspIndex + ); + +#endif diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 0b5431dbf7..20ab079219 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -62,10 +62,13 @@ CpuPageTableLib|Include/Library/CpuPageTableLib.h =20 ## @libraryclass Provides functions for manipulating smram savestate r= egisters. MmSaveStateLib|Include/Library/MmSaveStateLib.h =20 + ## @libraryclass Provides functions for SMM CPU Sync Operation. + SmmCpuSyncLib|Include/Library/SmmCpuSyncLib.h + [LibraryClasses.RISCV64] ## @libraryclass Provides functions to manage MMU features on RISCV64 = CPUs. ## RiscVMmuLib|Include/Library/BaseRiscVMmuLib.h =20 --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110639): https://edk2.groups.io/g/devel/message/110639 Mute This Topic: https://groups.io/mt/102366300/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 16 07:26:01 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+110640+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+110640+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1699025429; cv=none; d=zohomail.com; s=zohoarc; b=YfYcVEvOktHYhaaYcvvOnM+7dNdL6acoRri5wW6GLp/BuiJmWLQZb/sgnaaAocRw99dV/oB8lSwiPPO8G+OPb3YQm77fhmWOFD+Hra0qq3W4BYYPnHprK07w7fxxahoYGzNmi2nF7klmelx3m0DAzDN/VdwRio1OWqfdO4mN2gA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699025429; h=Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=otZRKrSgmtIffVC1RPo2shVw3s6D33abtZFzadq6pls=; b=XWDejYPrE+t+shH0TDkInyVmvR//udpNwZjJxBTUJTA9QFb0M/N/KZ23WYu2ogzGDUP9D66vSNAh9O46gAIoBT3ys80S7uVkXSAdO92Q1szj2gxJLfGhnsLptkeoNjVg7eXiBnkKs0u1yFzrGG0r9UOW/BSGStrTP9/UG6+6aVk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+110640+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1699025429257638.5269097565919; Fri, 3 Nov 2023 08:30:29 -0700 (PDT) Return-Path: DKIM-Signature: a=rsa-sha256; bh=D7NGlUHvIx544amXfmuHNVaLD+wmZ8mwcwUpSSY+XsY=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe; s=20140610; t=1699025428; v=1; b=XJXECIq666aVrsOqWEKOoKYbiSfoWhCEFBi7Qow4tGqtSviAUlJFv/EBN20kJzluwYM5e4kP rNBS4IInMLUDcuOsy7JAHQwVwuOJqzj6DFJJPrUfL2F21o2Wg+9flTsR1+8hio/Jq75trSqAnN2 4L4pM1K/JV69uccM07uYptqE= X-Received: by 127.0.0.2 with SMTP id r2GIYY1788612x3gCj6YxF2V; Fri, 03 Nov 2023 08:30:28 -0700 X-Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by mx.groups.io with SMTP id smtpd.web10.56401.1699025420211463760 for ; Fri, 03 Nov 2023 08:30:28 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10883"; a="1898919" X-IronPort-AV: E=Sophos;i="6.03,273,1694761200"; d="scan'208";a="1898919" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2023 08:30:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10883"; a="790793227" X-IronPort-AV: E=Sophos;i="6.03,273,1694761200"; d="scan'208";a="790793227" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by orsmga008.jf.intel.com with ESMTP; 03 Nov 2023 08:30:26 -0700 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v1 4/7] UefiCpuPkg: Implements SmmCpuSyncLib library instance Date: Fri, 3 Nov 2023 23:30:09 +0800 Message-Id: <20231103153012.3704-5-jiaxin.wu@intel.com> In-Reply-To: <20231103153012.3704-1-jiaxin.wu@intel.com> References: <20231103153012.3704-1-jiaxin.wu@intel.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: qmVDusXN7dOL7rk5e9irh4aHx1787277AA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1699025431027100017 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implements SmmCpuSyncLib Library class. The instance follows the existing SMM CPU driver (PiSmmCpuDxeSmm) sync implementation: 1.Abstract Counter and Run semaphores into SmmCpuSyncCtx. 2.Abstract CPU arrival count operation to SmmCpuSyncGetArrivedCpuCount(), SmmCpuSyncCheckInCpu(), SmmCpuSyncCheckOutCpu(), SmmCpuSyncLockDoor(). Implementation is aligned with existing SMM CPU driver. 3. Abstract SMM CPU Sync flow to: BSP: SmmCpuSyncReleaseOneAp --> AP: SmmCpuSyncWaitForBsp BSP: SmmCpuSyncWaitForAllAPs <-- AP: SmmCpuSyncReleaseBsp Semaphores release & wait during sync flow is same as existing SMM CPU driver. 4.Same operation to Counter and Run semaphores by leverage the atomic compare exchange. Change-Id: I5a004637f8b24a90594a794092548b850b187493 Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.c | 481 +++++++++++++++++= ++++ UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf | 38 ++ UefiCpuPkg/UefiCpuLibs.dsc.inc | 15 + UefiCpuPkg/UefiCpuPkg.dsc | 1 + 4 files changed, 535 insertions(+) create mode 100644 UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.c create mode 100644 UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf create mode 100644 UefiCpuPkg/UefiCpuLibs.dsc.inc diff --git a/UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.c b/UefiCpuPkg/= Library/SmmCpuSyncLib/SmmCpuSyncLib.c new file mode 100644 index 0000000000..3bc3ebe49a --- /dev/null +++ b/UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.c @@ -0,0 +1,481 @@ +/** @file + SMM CPU Sync lib implementation. + + Copyright (c) 2023, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + /// + /// Indicate how many CPU entered SMM. + /// + volatile UINT32 *Counter; +} SMM_CPU_SYNC_SEMAPHORE_GLOBAL; + +typedef struct { + /// + /// Used for control each CPU continue run or wait for signal + /// + volatile UINT32 *Run; +} SMM_CPU_SYNC_SEMAPHORE_CPU; + +typedef struct { + /// + /// All global semaphores' pointer in SMM CPU Sync + /// + SMM_CPU_SYNC_SEMAPHORE_GLOBAL *GlobalSem; + /// + /// All semaphores for each processor in SMM CPU Sync + /// + SMM_CPU_SYNC_SEMAPHORE_CPU *CpuSem; + /// + /// The number of processors in the system. + /// This does not indicate the number of processors that entered SMM. + /// + UINTN NumberOfCpus; + /// + /// Address of global and each CPU semaphores + /// + UINTN *SemBlock; + /// + /// Size of global and each CPU semaphores + /// + UINTN SemBlockPages; +} SMM_CPU_SYNC_CTX; + +/** + Performs an atomic compare exchange operation to get semaphore. + The compare exchange operation must be performed using MP safe + mechanisms. + + @param Sem IN: 32-bit unsigned integer + OUT: original integer - 1 + + @return Original integer - 1 + +**/ +UINT32 +InternalWaitForSemaphore ( + IN OUT volatile UINT32 *Sem + ) +{ + UINT32 Value; + + for ( ; ;) { + Value =3D *Sem; + if ((Value !=3D 0) && + (InterlockedCompareExchange32 ( + (UINT32 *)Sem, + Value, + Value - 1 + ) =3D=3D Value)) + { + break; + } + + CpuPause (); + } + + return Value - 1; +} + +/** + Performs an atomic compare exchange operation to release semaphore. + The compare exchange operation must be performed using MP safe + mechanisms. + + @param Sem IN: 32-bit unsigned integer + OUT: original integer + 1 + + @return Original integer + 1 + +**/ +UINT32 +InternalReleaseSemaphore ( + IN OUT volatile UINT32 *Sem + ) +{ + UINT32 Value; + + do { + Value =3D *Sem; + } while (Value + 1 !=3D 0 && + InterlockedCompareExchange32 ( + (UINT32 *)Sem, + Value, + Value + 1 + ) !=3D Value); + + return Value + 1; +} + +/** + Performs an atomic compare exchange operation to lock semaphore. + The compare exchange operation must be performed using MP safe + mechanisms. + + @param Sem IN: 32-bit unsigned integer + OUT: -1 + + @return Original integer + +**/ +UINT32 +InternalLockdownSemaphore ( + IN OUT volatile UINT32 *Sem + ) +{ + UINT32 Value; + + do { + Value =3D *Sem; + } while (InterlockedCompareExchange32 ( + (UINT32 *)Sem, + Value, + (UINT32)-1 + ) !=3D Value); + + return Value; +} + +/** + Creates and Init a new Smm Cpu Sync context. + + @param[in] NumberOfCpus The number of processors in the system. + + @return Pointer to an allocated Smm Cpu Sync context object. + If the creation failed, returns NULL. + +**/ +VOID * +EFIAPI +SmmCpuSyncContextInit ( + IN UINTN NumberOfCpus + ) +{ + SMM_CPU_SYNC_CTX *Ctx; + UINTN CtxSize; + UINTN OneSemSize; + UINTN GlobalSemSize; + UINTN CpuSemSize; + UINTN TotalSemSize; + UINTN SemAddr; + UINTN CpuIndex; + + Ctx =3D NULL; + + // + // Allocate for the Ctx + // + CtxSize =3D sizeof (SMM_CPU_SYNC_CTX) + sizeof (SMM_CPU_SYNC_SEMAPHORE_G= LOBAL) + sizeof (SMM_CPU_SYNC_SEMAPHORE_CPU) * NumberOfCpus; + Ctx =3D (SMM_CPU_SYNC_CTX *)AllocatePages (EFI_SIZE_TO_PAGES (CtxSiz= e)); + ASSERT (Ctx !=3D NULL); + Ctx->GlobalSem =3D (SMM_CPU_SYNC_SEMAPHORE_GLOBAL *)((UINT8 *)Ctx + s= izeof (SMM_CPU_SYNC_CTX)); + Ctx->CpuSem =3D (SMM_CPU_SYNC_SEMAPHORE_CPU *)((UINT8 *)Ctx + size= of (SMM_CPU_SYNC_CTX) + sizeof (SMM_CPU_SYNC_SEMAPHORE_GLOBAL)); + Ctx->NumberOfCpus =3D NumberOfCpus; + + // + // Allocate for Semaphores in the Ctx + // + OneSemSize =3D GetSpinLockProperties (); + GlobalSemSize =3D (sizeof (SMM_CPU_SYNC_SEMAPHORE_GLOBAL) / sizeof (VOID= *)) * OneSemSize; + CpuSemSize =3D (sizeof (SMM_CPU_SYNC_SEMAPHORE_CPU) / sizeof (VOID *)= ) * OneSemSize * NumberOfCpus; + TotalSemSize =3D GlobalSemSize + CpuSemSize; + DEBUG ((DEBUG_INFO, "[%a] - One Semaphore Size =3D 0x%x\n", __FUNCTIO= N__, OneSemSize)); + DEBUG ((DEBUG_INFO, "[%a] - Total Semaphores Size =3D 0x%x\n", __FUNCTIO= N__, TotalSemSize)); + Ctx->SemBlockPages =3D EFI_SIZE_TO_PAGES (TotalSemSize); + Ctx->SemBlock =3D AllocatePages (Ctx->SemBlockPages); + ASSERT (Ctx->SemBlock !=3D NULL); + ZeroMem (Ctx->SemBlock, TotalSemSize); + + SemAddr =3D (UINTN)Ctx->SemBlock; + + // + // Assign Global Semaphore pointer + // + Ctx->GlobalSem->Counter =3D (UINT32 *)SemAddr; + *Ctx->GlobalSem->Counter =3D 0; + DEBUG ((DEBUG_INFO, "[%a] - Ctx->GlobalSem->Counter Address: 0x%08x\n", = __FUNCTION__, (UINTN)Ctx->GlobalSem->Counter)); + + SemAddr +=3D GlobalSemSize; + + // + // Assign CPU Semaphore pointer + // + for (CpuIndex =3D 0; CpuIndex < NumberOfCpus; CpuIndex++) { + Ctx->CpuSem[CpuIndex].Run =3D (UINT32 *)(SemAddr + (CpuSemSize / Numb= erOfCpus) * CpuIndex); + *Ctx->CpuSem[CpuIndex].Run =3D 0; + DEBUG ((DEBUG_INFO, "[%a] - Ctx->CpuSem[%d].Run Address: 0x%08x\n", __= FUNCTION__, CpuIndex, (UINTN)Ctx->CpuSem[CpuIndex].Run)); + } + + // + // Return the new created Smm Cpu Sync context + // + return (VOID *)Ctx; +} + +/** + Deinit an allocated Smm Cpu Sync context object. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object = to be released. + +**/ +VOID +EFIAPI +SmmCpuSyncContextDeinit ( + IN VOID *SmmCpuSyncCtx + ) +{ + SMM_CPU_SYNC_CTX *Ctx; + UINTN CtxSize; + + ASSERT (SmmCpuSyncCtx !=3D NULL); + Ctx =3D (SMM_CPU_SYNC_CTX *)SmmCpuSyncCtx; + + CtxSize =3D sizeof (SMM_CPU_SYNC_CTX) + sizeof (SMM_CPU_SYNC_SEMAPHORE_G= LOBAL) + sizeof (SMM_CPU_SYNC_SEMAPHORE_CPU) * (Ctx->NumberOfCpus); + + FreePages (Ctx->SemBlock, Ctx->SemBlockPages); + + FreePages (Ctx, EFI_SIZE_TO_PAGES (CtxSize)); +} + +/** + Reset Smm Cpu Sync context object. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object = to be released. + +**/ +VOID +EFIAPI +SmmCpuSyncContextReset ( + IN VOID *SmmCpuSyncCtx + ) +{ + SMM_CPU_SYNC_CTX *Ctx; + + ASSERT (SmmCpuSyncCtx !=3D NULL); + Ctx =3D (SMM_CPU_SYNC_CTX *)SmmCpuSyncCtx; + + *Ctx->GlobalSem->Counter =3D 0; +} + +/** + Get current arrived CPU count. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object = to be released. + + @return Current number of arrived CPU count. + -1: indicate the door has been locked. + +**/ +UINT32 +EFIAPI +SmmCpuSyncGetArrivedCpuCount ( + IN VOID *SmmCpuSyncCtx + ) +{ + SMM_CPU_SYNC_CTX *Ctx; + + ASSERT (SmmCpuSyncCtx !=3D NULL); + Ctx =3D (SMM_CPU_SYNC_CTX *)SmmCpuSyncCtx; + + if (*Ctx->GlobalSem->Counter < 0) { + return (UINT32)-1; + } + + return *Ctx->GlobalSem->Counter; +} + +/** + Performs an atomic operation to check in CPU. + Check in CPU successfully if the returned arrival CPU count value is + positive, otherwise indicate the door has been locked, the CPU can + not checkin. + + @param[in] SmmCpuSyncCtx Pointer to the Smm CPU Sync context object = to be released. + @param[in] CpuIndex Pointer to the CPU Index to checkin. + + @return Positive value (>0): CPU arrival count number after chec= k in CPU successfully. + Nonpositive value (<=3D0): check in CPU failure. + +**/ +INT32 +EFIAPI +SmmCpuSyncCheckInCpu ( + IN VOID *SmmCpuSyncCtx, + IN UINTN CpuIndex + ) +{ + SMM_CPU_SYNC_CTX *Ctx; + + ASSERT (SmmCpuSyncCtx !=3D NULL); + Ctx =3D (SMM_CPU_SYNC_CTX *)SmmCpuSyncCtx; + + return (INT32)InternalReleaseSemaphore (Ctx->GlobalSem->Counter); +} + +/** + Performs an atomic operation to check out CPU. + Check out CPU successfully if the returned arrival CPU count value is + nonnegative, otherwise indicate the door has been locked, the CPU can + not checkout. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object = to be released. + @param[in] CpuIndex Pointer to the Cpu Index to checkout. + + @return Nonnegative value (>=3D0): CPU arrival count number after ch= eck out CPU successfully. + Negative value (<0): Check out CPU failure. + + +**/ +INT32 +EFIAPI +SmmCpuSyncCheckOutCpu ( + IN VOID *SmmCpuSyncCtx, + IN UINTN CpuIndex + ) +{ + SMM_CPU_SYNC_CTX *Ctx; + + ASSERT (SmmCpuSyncCtx !=3D NULL); + Ctx =3D (SMM_CPU_SYNC_CTX *)SmmCpuSyncCtx; + + return (INT32)InternalWaitForSemaphore (Ctx->GlobalSem->Counter); +} + +/** + Performs an atomic operation lock door for CPU checkin or checkout. + With this function, CPU can not check in via SmmCpuSyncCheckInCpu () or + check out via SmmCpuSyncCheckOutCpu (). + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object = to be released. + @param[in] CpuIndex Pointer to the Cpu Index to lock door. + + @return CPU arrival count number. + +**/ +UINT32 +EFIAPI +SmmCpuSyncLockDoor ( + IN VOID *SmmCpuSyncCtx, + IN UINTN CpuIndex + ) +{ + SMM_CPU_SYNC_CTX *Ctx; + + ASSERT (SmmCpuSyncCtx !=3D NULL); + Ctx =3D (SMM_CPU_SYNC_CTX *)SmmCpuSyncCtx; + + return InternalLockdownSemaphore (Ctx->GlobalSem->Counter); +} + +/** + Used for BSP to wait all APs. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object. + @param[in] NumberOfAPs Number of APs need to wait. + @param[in] BspIndex Pointer to the BSP Index. + +**/ +VOID +EFIAPI +SmmCpuSyncWaitForAllAPs ( + IN VOID *SmmCpuSyncCtx, + IN UINTN NumberOfAPs, + IN UINTN BspIndex + ) +{ + SMM_CPU_SYNC_CTX *Ctx; + + ASSERT (SmmCpuSyncCtx !=3D NULL); + Ctx =3D (SMM_CPU_SYNC_CTX *)SmmCpuSyncCtx; + + while (NumberOfAPs-- > 0) { + InternalWaitForSemaphore (Ctx->CpuSem[BspIndex].Run); + } +} + +/** + Used for BSP to release one AP. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object. + @param[in] CpuIndex Pointer to the Cpu Index, indicate which AP= need to be released. + @param[in] BspIndex Pointer to the BSP Index. + +**/ +VOID +EFIAPI +SmmCpuSyncReleaseOneAp ( + IN VOID *SmmCpuSyncCtx, + IN UINTN CpuIndex, + IN UINTN BspIndex + ) +{ + SMM_CPU_SYNC_CTX *Ctx; + + ASSERT (SmmCpuSyncCtx !=3D NULL); + Ctx =3D (SMM_CPU_SYNC_CTX *)SmmCpuSyncCtx; + + InternalReleaseSemaphore (Ctx->CpuSem[CpuIndex].Run); +} + +/** + Used for AP to wait BSP. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object. + @param[in] CpuIndex Pointer to the Cpu Index, indicate which AP= wait BSP. + @param[in] BspIndex Pointer to the BSP Index. + +**/ +VOID +EFIAPI +SmmCpuSyncWaitForBsp ( + IN VOID *SmmCpuSyncCtx, + IN UINTN CpuIndex, + IN UINTN BspIndex + ) +{ + SMM_CPU_SYNC_CTX *Ctx; + + ASSERT (SmmCpuSyncCtx !=3D NULL); + Ctx =3D (SMM_CPU_SYNC_CTX *)SmmCpuSyncCtx; + + InternalWaitForSemaphore (Ctx->CpuSem[CpuIndex].Run); +} + +/** + Used for AP to release BSP. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object. + @param[in] CpuIndex Pointer to the Cpu Index, indicate which AP= release BSP. + @param[in] BspIndex Pointer to the BSP Index. + +**/ +VOID +EFIAPI +SmmCpuSyncReleaseBsp ( + IN VOID *SmmCpuSyncCtx, + IN UINTN CpuIndex, + IN UINTN BspIndex + ) +{ + SMM_CPU_SYNC_CTX *Ctx; + + ASSERT (SmmCpuSyncCtx !=3D NULL); + Ctx =3D (SMM_CPU_SYNC_CTX *)SmmCpuSyncCtx; + + InternalReleaseSemaphore (Ctx->CpuSem[BspIndex].Run); +} diff --git a/UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf b/UefiCpuPk= g/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf new file mode 100644 index 0000000000..86475ce64b --- /dev/null +++ b/UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf @@ -0,0 +1,38 @@ +## @file +# SMM CPU Synchronization lib. +# +# This is SMM CPU Synchronization lib used for SMM CPU sync operations. +# +# Copyright (c) 2023, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SmmCpuSyncLib + FILE_GUID =3D 1ca1bc1a-16a4-46ef-956a-ca500fd3381f + MODULE_TYPE =3D DXE_SMM_DRIVER + LIBRARY_CLASS =3D SmmCpuSyncLib|DXE_SMM_DRIVER + +[Sources] + SmmCpuSyncLib.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + UefiLib + BaseLib + DebugLib + PrintLib + SynchronizationLib + BaseMemoryLib + SmmServicesTableLib + MemoryAllocationLib + +[Pcd] + +[Protocols] diff --git a/UefiCpuPkg/UefiCpuLibs.dsc.inc b/UefiCpuPkg/UefiCpuLibs.dsc.inc new file mode 100644 index 0000000000..6b9b362729 --- /dev/null +++ b/UefiCpuPkg/UefiCpuLibs.dsc.inc @@ -0,0 +1,15 @@ +## @file +# UefiCpu DSC include file for [LibraryClasses*] section of all Architectu= res. +# +# This file can be included to the [LibraryClasses*] section(s) of a platf= orm DSC file +# by using "!include UefiCpuPkg/UefiCpuLibs.dsc.inc" to specify the librar= y instances +# of some EDKII basic/common library classes in UefiCpuPkg. +# +# Copyright (c) 2023, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[LibraryClasses] + SmmCpuSyncLib|UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf \ No newline at end of file diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index 074fd77461..338f18eb98 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -21,10 +21,11 @@ # # External libraries to build package # =20 !include MdePkg/MdeLibs.dsc.inc +!include UefiCpuPkg/UefiCpuLibs.dsc.inc =20 [LibraryClasses] BaseLib|MdePkg/Library/BaseLib/BaseLib.inf BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110640): https://edk2.groups.io/g/devel/message/110640 Mute This Topic: https://groups.io/mt/102366301/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 16 07:26:01 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+110641+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+110641+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1699025431; cv=none; d=zohomail.com; s=zohoarc; b=KKKv99E4GJGUSUm0dnwYHmscz/CsrVXV2nM4jEEravrdqWYIORfvgUec8K4N1tqMjHEEMdobQ7mFWlW5ln6bv00WMqVMmT5CPmivaxhC8BTIn5zLVlqwZ9zLA8Sdf1qzwZCXDF46pkNs+348kGtMmKdENQV/hsrYC7ufb0Csk50= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699025431; h=Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=bEH9zL+z7CSoI6SjJyUqEM0nEeMx15DiHKFaUgHhBpc=; b=dYLX8/NuIjznJddcvdNtbsLnLFnqNwsSeF5fAWBSxeFZ/3M0ScDeZQqy7MXsn31PTNyy80t0XXFKnEwzjmfDM8z1vPA4YhwJ2W5CkcaZXCrpAtfIQ6252g+bjSuqIyIz+DrLL8bmmK9AooDBXcJQ4pJvZhTUtDfVy7PvdM+l05k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+110641+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1699025431946362.58347592709197; Fri, 3 Nov 2023 08:30:31 -0700 (PDT) Return-Path: DKIM-Signature: a=rsa-sha256; bh=zepo0trX28iyy+/ApSMA7pVAXMMKSPZtZbtyCCLkuxo=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe; s=20140610; t=1699025431; v=1; b=ssGCya7xlYWalmF0v9NykeM8PXsPP8/ZpvvDfXJY26hniUlUhJ0PPOJsy7oMRtNQvg+4IpxM 9rz2RJ8E4hVcCnWLQxdlOxL7F8EWm/TIviSdQ3uAHhtL1nPHH5Hwzn/D2dsBqFb2QnuQdSGlGsS gJfTfBzVjuDbF/6a7dnxuz2A= X-Received: by 127.0.0.2 with SMTP id b6LhYY1788612xNe0TOIitrw; Fri, 03 Nov 2023 08:30:31 -0700 X-Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by mx.groups.io with SMTP id smtpd.web10.56401.1699025420211463760 for ; Fri, 03 Nov 2023 08:30:31 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10883"; a="1898929" X-IronPort-AV: E=Sophos;i="6.03,273,1694761200"; d="scan'208";a="1898929" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2023 08:30:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10883"; a="790793262" X-IronPort-AV: E=Sophos;i="6.03,273,1694761200"; d="scan'208";a="790793262" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by orsmga008.jf.intel.com with ESMTP; 03 Nov 2023 08:30:28 -0700 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Eric Dong , Ray Ni , Zeng Star , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [PATCH v1 5/7] OvmfPkg: Specifies SmmCpuSyncLib instance Date: Fri, 3 Nov 2023 23:30:10 +0800 Message-Id: <20231103153012.3704-6-jiaxin.wu@intel.com> In-Reply-To: <20231103153012.3704-1-jiaxin.wu@intel.com> References: <20231103153012.3704-1-jiaxin.wu@intel.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: vV5qcc94rL1JHzkW4t9a7S4Jx1787277AA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1699025433020100021 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The SmmCpuSyncLib instance is included in UefiCpuLibs.dsc.inc. This patch is to specify SmmCpuSyncLib instance in OvmfPkg by using "!include UefiCpuPkg/UefiCpuLibs.dsc.inc". Change-Id: I2ab1737425e26a7bfc4f564b3b7f15ca5c2268fb Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Rahul Kumar Cc: Gerd Hoffmann Signed-off-by: Jiaxin Wu --- OvmfPkg/CloudHv/CloudHvX64.dsc | 1 + OvmfPkg/OvmfPkgIa32.dsc | 1 + OvmfPkg/OvmfPkgIa32X64.dsc | 1 + OvmfPkg/OvmfPkgX64.dsc | 1 + 4 files changed, 4 insertions(+) diff --git a/OvmfPkg/CloudHv/CloudHvX64.dsc b/OvmfPkg/CloudHv/CloudHvX64.dsc index c23c7eaf6c..e65767fe16 100644 --- a/OvmfPkg/CloudHv/CloudHvX64.dsc +++ b/OvmfPkg/CloudHv/CloudHvX64.dsc @@ -122,10 +122,11 @@ # Library Class section - list of all Library Classes needed by this Platf= orm. # ##########################################################################= ###### =20 !include MdePkg/MdeLibs.dsc.inc +!include UefiCpuPkg/UefiCpuLibs.dsc.inc =20 [LibraryClasses] PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf TimerLib|OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.inf ResetSystemLib|OvmfPkg/Library/ResetSystemLib/BaseResetSystemLib.inf diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index ed3a19feeb..07d16e6935 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -125,10 +125,11 @@ # Library Class section - list of all Library Classes needed by this Platf= orm. # ##########################################################################= ###### =20 !include MdePkg/MdeLibs.dsc.inc +!include UefiCpuPkg/UefiCpuLibs.dsc.inc =20 [LibraryClasses] PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf TimerLib|OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.inf ResetSystemLib|OvmfPkg/Library/ResetSystemLib/BaseResetSystemLib.inf diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index 16ca139b29..8d243b7075 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -130,10 +130,11 @@ # Library Class section - list of all Library Classes needed by this Platf= orm. # ##########################################################################= ###### =20 !include MdePkg/MdeLibs.dsc.inc +!include UefiCpuPkg/UefiCpuLibs.dsc.inc =20 [LibraryClasses] PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf TimerLib|OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.inf ResetSystemLib|OvmfPkg/Library/ResetSystemLib/BaseResetSystemLib.inf diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index dc1a0942aa..6343789152 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -143,10 +143,11 @@ # Library Class section - list of all Library Classes needed by this Platf= orm. # ##########################################################################= ###### =20 !include MdePkg/MdeLibs.dsc.inc +!include UefiCpuPkg/UefiCpuLibs.dsc.inc =20 [LibraryClasses] PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf TimerLib|OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.inf ResetSystemLib|OvmfPkg/Library/ResetSystemLib/BaseResetSystemLib.inf --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110641): https://edk2.groups.io/g/devel/message/110641 Mute This Topic: https://groups.io/mt/102366302/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 16 07:26:01 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+110642+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+110642+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1699025434; cv=none; d=zohomail.com; s=zohoarc; b=W/ka0KQZtszl3afQoqVMW4JgqcLVGKuQUsbUm8rMlyGVuIzobBN5582051rUNU6Q35hD0+VnBCvls7X8as3EwBngAzqw8gouLnv3gZafXt/VRFw1C+VOj32kpzzwwB72fxD76MUz45NmQrs3+lWBqrqcql4sJpo9+8tFYgTbFMA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699025434; h=Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=WDda4cHvsWD9rzSY9XSbtUcDHaHghDIGgev2JxQYd4w=; b=f6ZGs0ARQRAKWC84eWuiQPNVR4p9xz1i57OLPWJCoK4/iiSP76HAag09L5r9Nd5Ne5Qk6RG6j4x+xwiG9LvYfWvWohCSVP+IRhOPAfZpwYdSP3crglJ56smj2WcVZMT/t3X5lPYWOmqNBWm4EVC2xnH1yI3s9k6etHH4Vn34ffk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+110642+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1699025434306949.2964647362274; Fri, 3 Nov 2023 08:30:34 -0700 (PDT) Return-Path: DKIM-Signature: a=rsa-sha256; bh=BBaVLXs9pEirUdVfGiSNbx+nHECQxVZ2Yk7TxhmAwy0=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe; s=20140610; t=1699025433; v=1; b=T13AkE0lx6AIKSjnEj2WO92QpPDsWhEtaSuRuwIpo5Tj4n6H7jjhI4GiLJvCHl0hlr6BH8ZM R7FYH688aVqnD967eTmrm1nFhyuxieAQy2Ap3xdJI23uQZQAK6XpZEYILB1rqCrMXzjFf89G6/9 czTtlw2gnokhEd7OC4AQ9kgU= X-Received: by 127.0.0.2 with SMTP id d4KLYY1788612xJdwwEtcckJ; Fri, 03 Nov 2023 08:30:33 -0700 X-Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by mx.groups.io with SMTP id smtpd.web10.56401.1699025420211463760 for ; Fri, 03 Nov 2023 08:30:33 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10883"; a="1898958" X-IronPort-AV: E=Sophos;i="6.03,273,1694761200"; d="scan'208";a="1898958" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2023 08:30:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10883"; a="790793299" X-IronPort-AV: E=Sophos;i="6.03,273,1694761200"; d="scan'208";a="790793299" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by orsmga008.jf.intel.com with ESMTP; 03 Nov 2023 08:30:31 -0700 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Guo Dong , Sean Rhodes , James Lu , Gua Guo , Ray Ni , Zeng Star Subject: [edk2-devel] [PATCH v1 6/7] UefiPayloadPkg: Specifies SmmCpuSyncLib instance Date: Fri, 3 Nov 2023 23:30:11 +0800 Message-Id: <20231103153012.3704-7-jiaxin.wu@intel.com> In-Reply-To: <20231103153012.3704-1-jiaxin.wu@intel.com> References: <20231103153012.3704-1-jiaxin.wu@intel.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: mvwHi0BvOdlS6LNom8rSlnx8x1787277AA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1699025435020100025 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The SmmCpuSyncLib instance is included in UefiCpuLibs.dsc.inc. This patch is to specify SmmCpuSyncLib instance in UefiPayloadPkg by using "!include UefiCpuPkg/UefiCpuLibs.dsc.inc". Change-Id: Ib303a9cdf260ac1ffc146e5f2e68834dec00ff25 Cc: Guo Dong Cc: Sean Rhodes Cc: James Lu Cc: Gua Guo Cc: Ray Ni Cc: Zeng Star Signed-off-by: Jiaxin Wu Reviewed-by: Gua Guo --- UefiPayloadPkg/UefiPayloadPkg.dsc | 1 + 1 file changed, 1 insertion(+) diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayload= Pkg.dsc index af9308ef8e..6f6d815c07 100644 --- a/UefiPayloadPkg/UefiPayloadPkg.dsc +++ b/UefiPayloadPkg/UefiPayloadPkg.dsc @@ -169,10 +169,11 @@ # Library Class section - list of all Library Classes needed by this Platf= orm. # ##########################################################################= ###### =20 !include MdePkg/MdeLibs.dsc.inc +!include UefiCpuPkg/UefiCpuLibs.dsc.inc =20 [LibraryClasses] # # Entry point # --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110642): https://edk2.groups.io/g/devel/message/110642 Mute This Topic: https://groups.io/mt/102366304/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 16 07:26:01 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+110643+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+110643+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1699025436; cv=none; d=zohomail.com; s=zohoarc; b=miCSdFU9RZ2JrltWkl04tSh3ojf1Bw0rgwBWhAKlvpyDJYayAdxGx0GAGMkgoPIIldxBiyD9wYicffLK2NdqzMW5xjoIZgVFefQzP6LKsIz+qVzNVIohU8uqR2E1DOHuI6n35zuxSIAVoYsRybwPVgtQrpHbyqUWm1EHvzhqYtw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699025436; h=Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=MlCDC++C8IVQzMcLvLLNIF/JF5KV0e0DdoBrAn51ahE=; b=Wwdo3CkqvXW/rzeUQoI/oTpoanYQCeqzxKyo5n76Lr3/V2Kd0+p34JPV6NIQGj3zoUI/89g7/ydyMQ05U+WG7mBva/tIan9oXmDzqFihAgWTmgK7if1qCTcuJBRqdN1ju8rA+We8iB/rKEzHZBCML0L8m9Gx9G3JVOIjHhaUPpM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+110643+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1699025436584829.4541367027672; Fri, 3 Nov 2023 08:30:36 -0700 (PDT) Return-Path: DKIM-Signature: a=rsa-sha256; bh=i6RcqRhpzt5rOm8EtYON24psypVyK4arGZ+Oetusl7g=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe; s=20140610; t=1699025436; v=1; b=pIuef/fi8dBDk9RVkTc4QvrISY4CbksIMhTREq2mlgQoMEY6hsi+LueddJ/gU7EXldR3H/2H QzFrj7w+JeJXgbKWbPRXOVqu+viwgmGgFl+NrDbsAoCfgafGZF97g+EHSzRXsUOrqo8olrgFOQw ltq8Kzkw0b1BD6GJofu1CYcc= X-Received: by 127.0.0.2 with SMTP id dQagYY1788612xT8H5VSLZUm; Fri, 03 Nov 2023 08:30:36 -0700 X-Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by mx.groups.io with SMTP id smtpd.web10.56401.1699025420211463760 for ; Fri, 03 Nov 2023 08:30:35 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10883"; a="1898964" X-IronPort-AV: E=Sophos;i="6.03,273,1694761200"; d="scan'208";a="1898964" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2023 08:30:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10883"; a="790793363" X-IronPort-AV: E=Sophos;i="6.03,273,1694761200"; d="scan'208";a="790793363" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by orsmga008.jf.intel.com with ESMTP; 03 Nov 2023 08:30:33 -0700 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v1 7/7] UefiCpuPkg/PiSmmCpuDxeSmm: Consume SmmCpuSyncLib Date: Fri, 3 Nov 2023 23:30:12 +0800 Message-Id: <20231103153012.3704-8-jiaxin.wu@intel.com> In-Reply-To: <20231103153012.3704-1-jiaxin.wu@intel.com> References: <20231103153012.3704-1-jiaxin.wu@intel.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: e6J8OIyOLbXcW67Zy4lVoJE8x1787277AA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1699025437108100029 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There is the SmmCpuSyncLib Library class define the SMM CPU sync flow, which is aligned with existing SMM CPU driver sync behavior. This patch is to consume SmmCpuSyncLib instance directly. With this change, SMM CPU Sync flow/logic can be customized with different implementation no matter for any purpose, e.g. performance tuning, handle specific register, etc. Change-Id: Id034de47b85743c125f0d76420947e0dd9e69518 Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 256 +++++------------------= ---- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 6 +- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 1 + 3 files changed, 49 insertions(+), 214 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxe= Smm/MpService.c index 5a42a5dd12..a30b2aa234 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -27,122 +27,10 @@ MM_COMPLETION mSmmStartupThisApToken; // // Processor specified by mPackageFirstThreadIndex[PackageIndex] will do t= he package-scope register check. // UINT32 *mPackageFirstThreadIndex =3D NULL; =20 -/** - Performs an atomic compare exchange operation to get semaphore. - The compare exchange operation must be performed using - MP safe mechanisms. - - @param Sem IN: 32-bit unsigned integer - OUT: original integer - 1 - @return Original integer - 1 - -**/ -UINT32 -WaitForSemaphore ( - IN OUT volatile UINT32 *Sem - ) -{ - UINT32 Value; - - for ( ; ;) { - Value =3D *Sem; - if ((Value !=3D 0) && - (InterlockedCompareExchange32 ( - (UINT32 *)Sem, - Value, - Value - 1 - ) =3D=3D Value)) - { - break; - } - - CpuPause (); - } - - return Value - 1; -} - -/** - Performs an atomic compare exchange operation to release semaphore. - The compare exchange operation must be performed using - MP safe mechanisms. - - @param Sem IN: 32-bit unsigned integer - OUT: original integer + 1 - @return Original integer + 1 - -**/ -UINT32 -ReleaseSemaphore ( - IN OUT volatile UINT32 *Sem - ) -{ - UINT32 Value; - - do { - Value =3D *Sem; - } while (Value + 1 !=3D 0 && - InterlockedCompareExchange32 ( - (UINT32 *)Sem, - Value, - Value + 1 - ) !=3D Value); - - return Value + 1; -} - -/** - Performs an atomic compare exchange operation to lock semaphore. - The compare exchange operation must be performed using - MP safe mechanisms. - - @param Sem IN: 32-bit unsigned integer - OUT: -1 - @return Original integer - -**/ -UINT32 -LockdownSemaphore ( - IN OUT volatile UINT32 *Sem - ) -{ - UINT32 Value; - - do { - Value =3D *Sem; - } while (InterlockedCompareExchange32 ( - (UINT32 *)Sem, - Value, - (UINT32)-1 - ) !=3D Value); - - return Value; -} - -/** - Used for BSP to wait all APs. - Wait all APs to performs an atomic compare exchange operation to release= semaphore. - - @param NumberOfAPs AP number - -**/ -VOID -WaitForAllAPs ( - IN UINTN NumberOfAPs - ) -{ - UINTN BspIndex; - - BspIndex =3D mSmmMpSyncData->BspIndex; - while (NumberOfAPs-- > 0) { - WaitForSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run); - } -} - /** Used for BSP to release all APs. Performs an atomic compare exchange operation to release semaphore for each AP. =20 @@ -154,57 +42,15 @@ ReleaseAllAPs ( { UINTN Index; =20 for (Index =3D 0; Index < mMaxNumberOfCpus; Index++) { if (IsPresentAp (Index)) { - ReleaseSemaphore (mSmmMpSyncData->CpuData[Index].Run); + SmmCpuSyncReleaseOneAp (mSmmMpSyncData->SmmCpuSyncCtx, Index, gSmmCp= uPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu); } } } =20 -/** - Used for BSP to release one AP. - - @param ApSem IN: 32-bit unsigned integer - OUT: original integer + 1 -**/ -VOID -ReleaseOneAp ( - IN OUT volatile UINT32 *ApSem - ) -{ - ReleaseSemaphore (ApSem); -} - -/** - Used for AP to wait BSP. - - @param ApSem IN: 32-bit unsigned integer - OUT: original integer 0 -**/ -VOID -WaitForBsp ( - IN OUT volatile UINT32 *ApSem - ) -{ - WaitForSemaphore (ApSem); -} - -/** - Used for AP to release BSP. - - @param BspSem IN: 32-bit unsigned integer - OUT: original integer + 1 -**/ -VOID -ReleaseBsp ( - IN OUT volatile UINT32 *BspSem - ) -{ - ReleaseSemaphore (BspSem); -} - /** Check whether the index of CPU perform the package level register programming during System Management Mode initialization. =20 The index of Processor specified by mPackageFirstThreadIndex[PackageInde= x] @@ -292,35 +138,35 @@ AllCpusInSmmExceptBlockedDisabled ( =20 BlockedCount =3D 0; DisabledCount =3D 0; =20 // - // Check to make sure mSmmMpSyncData->Counter is valid and not locked. + // Check to make sure the CPU arrival count is valid and not locked. // - ASSERT (*mSmmMpSyncData->Counter <=3D mNumberOfCpus); + ASSERT (SmmCpuSyncGetArrivedCpuCount (mSmmMpSyncData->SmmCpuSyncCtx) <= =3D mNumberOfCpus); =20 // // Check whether all CPUs in SMM. // - if (*mSmmMpSyncData->Counter =3D=3D mNumberOfCpus) { + if (SmmCpuSyncGetArrivedCpuCount (mSmmMpSyncData->SmmCpuSyncCtx) =3D=3D = mNumberOfCpus) { return TRUE; } =20 // // Check for the Blocked & Disabled Exceptions Case. // GetSmmDelayedBlockedDisabledCount (NULL, &BlockedCount, &DisabledCount); =20 // - // *mSmmMpSyncData->Counter might be updated by all APs concurrently. Th= e value + // The CPU arrival count might be updated by all APs concurrently. The v= alue // can be dynamic changed. If some Aps enter the SMI after the BlockedCo= unt & - // DisabledCount check, then the *mSmmMpSyncData->Counter will be increa= sed, thus - // leading the *mSmmMpSyncData->Counter + BlockedCount + DisabledCount >= mNumberOfCpus. + // DisabledCount check, then the CPU arrival count will be increased, th= us + // leading the retrieved CPU arrival count + BlockedCount + DisabledCoun= t > mNumberOfCpus. // since the BlockedCount & DisabledCount are local variable, it's ok he= re only for // the checking of all CPUs In Smm. // - if (*mSmmMpSyncData->Counter + BlockedCount + DisabledCount >=3D mNumber= OfCpus) { + if (SmmCpuSyncGetArrivedCpuCount (mSmmMpSyncData->SmmCpuSyncCtx) + Block= edCount + DisabledCount >=3D mNumberOfCpus) { return TRUE; } =20 return FALSE; } @@ -396,11 +242,11 @@ SmmWaitForApArrival ( PERF_FUNCTION_BEGIN (); =20 DelayedCount =3D 0; BlockedCount =3D 0; =20 - ASSERT (*mSmmMpSyncData->Counter <=3D mNumberOfCpus); + ASSERT (SmmCpuSyncGetArrivedCpuCount (mSmmMpSyncData->SmmCpuSyncCtx) <= =3D mNumberOfCpus); =20 LmceEn =3D FALSE; LmceSignal =3D FALSE; if (mMachineCheckSupported) { LmceEn =3D IsLmceOsEnabled (); @@ -447,11 +293,11 @@ SmmWaitForApArrival ( // d) We don't add code to check SMI disabling status to skip sending IP= I to SMI disabled APs, because: // - In traditional flow, SMI disabling is discouraged. // - In relaxed flow, CheckApArrival() will check SMI disabling statu= s before calling this function. // In both cases, adding SMI-disabling checking code increases overhe= ad. // - if (*mSmmMpSyncData->Counter < mNumberOfCpus) { + if (SmmCpuSyncGetArrivedCpuCount (mSmmMpSyncData->SmmCpuSyncCtx) < mNumb= erOfCpus) { // // Send SMI IPIs to bring outside processors in // for (Index =3D 0; Index < mMaxNumberOfCpus; Index++) { if (!(*(mSmmMpSyncData->CpuData[Index].Present)) && (gSmmCpuPrivate-= >ProcessorInfo[Index].ProcessorId !=3D INVALID_APIC_ID)) { @@ -548,11 +394,11 @@ WaitForAllAPsNotBusy ( Check whether it is an present AP. =20 @param CpuIndex The AP index which calls this function. =20 @retval TRUE It's a present AP. - @retval TRUE This is not an AP or it is not present. + @retval FALSE This is not an AP or it is not present. =20 **/ BOOLEAN IsPresentAp ( IN UINTN CpuIndex @@ -659,30 +505,30 @@ BSPHandler ( // Wait for APs to arrive // SmmWaitForApArrival (); =20 // - // Lock the counter down and retrieve the number of APs + // Lock door for late comming CPU checkin and retrieve the Arrived num= ber of APs // *mSmmMpSyncData->AllCpusInSync =3D TRUE; - ApCount =3D LockdownSemaphore (mSmmMpSyncData->= Counter) - 1; + ApCount =3D SmmCpuSyncLockDoor (mSmmMpSyncData-= >SmmCpuSyncCtx, CpuIndex) - 1; =20 // // Wait for all APs: // 1. Make sure all Aps have set the Present. // 2. Get ready for programming MTRRs. // - WaitForAllAPs (ApCount); + SmmCpuSyncWaitForAllAPs (mSmmMpSyncData->SmmCpuSyncCtx, ApCount, CpuIn= dex); =20 if (SmmCpuFeaturesNeedConfigureMtrrs ()) { // // Signal all APs it's time for backup MTRRs // ReleaseAllAPs (); =20 // - // WaitForBsp() may wait for ever if an AP happens to enter SMM at + // SmmCpuSyncWaitForBsp() may wait for ever if an AP happens to ente= r SMM at // exactly this point. Please make sure PcdCpuSmmMaxSyncLoops has be= en set // to a large enough value to avoid this situation. // Note: For HT capable CPUs, threads within a core share the same s= et of MTRRs. // We do the backup first and then set MTRR to avoid race condition = for threads // in the same core. @@ -690,28 +536,28 @@ BSPHandler ( MtrrGetAllMtrrs (&Mtrrs); =20 // // Wait for all APs to complete their MTRR saving // - WaitForAllAPs (ApCount); + SmmCpuSyncWaitForAllAPs (mSmmMpSyncData->SmmCpuSyncCtx, ApCount, Cpu= Index); =20 // // Let all processors program SMM MTRRs together // ReleaseAllAPs (); =20 // - // WaitForBsp() may wait for ever if an AP happens to enter SMM at + // SmmCpuSyncWaitForBsp() may wait for ever if an AP happens to ente= r SMM at // exactly this point. Please make sure PcdCpuSmmMaxSyncLoops has be= en set // to a large enough value to avoid this situation. // ReplaceOSMtrrs (CpuIndex); =20 // // Wait for all APs to complete their MTRR programming // - WaitForAllAPs (ApCount); + SmmCpuSyncWaitForAllAPs (mSmmMpSyncData->SmmCpuSyncCtx, ApCount, Cpu= Index); } } =20 // // The BUSY lock is initialized to Acquired state @@ -743,14 +589,14 @@ BSPHandler ( // make those APs to exit SMI synchronously. APs which arrive later will= be excluded and // will run through freely. // if ((SyncMode !=3D SmmCpuSyncModeTradition) && !SmmCpuFeaturesNeedConfig= ureMtrrs ()) { // - // Lock the counter down and retrieve the number of APs + // Lock door for late comming CPU checkin and retrieve the Arrived num= ber of APs // *mSmmMpSyncData->AllCpusInSync =3D TRUE; - ApCount =3D LockdownSemaphore (mSmmMpSyncData->= Counter) - 1; + ApCount =3D SmmCpuSyncLockDoor (mSmmMpSyncData-= >SmmCpuSyncCtx, CpuIndex) - 1; // // Make sure all APs have their Present flag set // while (TRUE) { PresentCount =3D 0; @@ -774,11 +620,11 @@ BSPHandler ( =20 if (SmmCpuFeaturesNeedConfigureMtrrs ()) { // // Wait for all APs to complete their pending tasks // - WaitForAllAPs (ApCount); + SmmCpuSyncWaitForAllAPs (mSmmMpSyncData->SmmCpuSyncCtx, ApCount, CpuIn= dex); =20 // // Signal APs to restore MTRRs // ReleaseAllAPs (); @@ -790,11 +636,11 @@ BSPHandler ( MtrrSetAllMtrrs (&Mtrrs); =20 // // Wait for all APs to complete MTRR programming // - WaitForAllAPs (ApCount); + SmmCpuSyncWaitForAllAPs (mSmmMpSyncData->SmmCpuSyncCtx, ApCount, CpuIn= dex); =20 // // Signal APs to Reset states/semaphore for this processor // ReleaseAllAPs (); @@ -818,11 +664,11 @@ BSPHandler ( =20 // // Gather APs to exit SMM synchronously. Note the Present flag is cleare= d by now but // WaitForAllAps does not depend on the Present flag. // - WaitForAllAPs (ApCount); + SmmCpuSyncWaitForAllAPs (mSmmMpSyncData->SmmCpuSyncCtx, ApCount, CpuInde= x); =20 // // At this point, all APs should have exited from APHandler(). // Migrate the SMM MP performance logging to standard SMM performance lo= gging. // Any SMM MP performance logging after this point will be migrated in n= ext SMI. @@ -844,11 +690,11 @@ BSPHandler ( } =20 // // Allow APs to check in from this point on // - *mSmmMpSyncData->Counter =3D 0; + SmmCpuSyncContextReset (mSmmMpSyncData->SmmCpuSyncCtx); *mSmmMpSyncData->AllCpusInSync =3D FALSE; mSmmMpSyncData->AllApArrivedWithException =3D FALSE; =20 PERF_FUNCTION_END (); } @@ -914,21 +760,21 @@ APHandler ( =20 if (!(*mSmmMpSyncData->InsideSmm)) { // // Give up since BSP is unable to enter SMM // and signal the completion of this AP - // Reduce the mSmmMpSyncData->Counter! + // Reduce the CPU arrival count! // - WaitForSemaphore (mSmmMpSyncData->Counter); + SmmCpuSyncCheckOutCpu (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex); return; } } else { // // Don't know BSP index. Give up without sending IPI to BSP. - // Reduce the mSmmMpSyncData->Counter! + // Reduce the CPU arrival count! // - WaitForSemaphore (mSmmMpSyncData->Counter); + SmmCpuSyncCheckOutCpu (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex); return; } } =20 // @@ -946,50 +792,50 @@ APHandler ( // // Notify BSP of arrival at this point // 1. Set the Present. // 2. Get ready for programming MTRRs. // - ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); + SmmCpuSyncReleaseBsp (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex, BspInde= x); } =20 if (SmmCpuFeaturesNeedConfigureMtrrs ()) { // // Wait for the signal from BSP to backup MTRRs // - WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); + SmmCpuSyncWaitForBsp (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex, BspInde= x); =20 // // Backup OS MTRRs // MtrrGetAllMtrrs (&Mtrrs); =20 // // Signal BSP the completion of this AP // - ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); + SmmCpuSyncReleaseBsp (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex, BspInde= x); =20 // // Wait for BSP's signal to program MTRRs // - WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); + SmmCpuSyncWaitForBsp (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex, BspInde= x); =20 // // Replace OS MTRRs with SMI MTRRs // ReplaceOSMtrrs (CpuIndex); =20 // // Signal BSP the completion of this AP // - ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); + SmmCpuSyncReleaseBsp (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex, BspInde= x); } =20 while (TRUE) { // // Wait for something to happen // - WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); + SmmCpuSyncWaitForBsp (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex, BspInde= x); =20 // // Check if BSP wants to exit SMM // if (!(*mSmmMpSyncData->InsideSmm)) { @@ -1025,43 +871,43 @@ APHandler ( =20 if (SmmCpuFeaturesNeedConfigureMtrrs ()) { // // Notify BSP the readiness of this AP to program MTRRs // - ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); + SmmCpuSyncReleaseBsp (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex, BspInde= x); =20 // // Wait for the signal from BSP to program MTRRs // - WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); + SmmCpuSyncWaitForBsp (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex, BspInde= x); =20 // // Restore OS MTRRs // SmmCpuFeaturesReenableSmrr (); MtrrSetAllMtrrs (&Mtrrs); =20 // // Notify BSP the readiness of this AP to Reset states/semaphore for t= his processor // - ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); + SmmCpuSyncReleaseBsp (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex, BspInde= x); =20 // // Wait for the signal from BSP to Reset states/semaphore for this pro= cessor // - WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); + SmmCpuSyncWaitForBsp (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex, BspInde= x); } =20 // // Reset states/semaphore for this processor // *(mSmmMpSyncData->CpuData[CpuIndex].Present) =3D FALSE; =20 // // Notify BSP the readiness of this AP to exit SMM // - ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); + SmmCpuSyncReleaseBsp (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex, BspIndex); } =20 /** Checks whether the input token is the current used token. =20 @@ -1325,11 +1171,11 @@ InternalSmmStartupThisAp ( mSmmMpSyncData->CpuData[CpuIndex].Status =3D CpuStatus; if (mSmmMpSyncData->CpuData[CpuIndex].Status !=3D NULL) { *mSmmMpSyncData->CpuData[CpuIndex].Status =3D EFI_NOT_READY; } =20 - ReleaseOneAp (mSmmMpSyncData->CpuData[CpuIndex].Run); + SmmCpuSyncReleaseOneAp (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex, gSmmCpu= Private->SmmCoreEntryContext.CurrentlyExecutingCpu); =20 if (Token =3D=3D NULL) { AcquireSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Busy); ReleaseSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Busy); } @@ -1454,11 +1300,11 @@ InternalSmmStartupAllAPs ( =20 // // Decrease the count to mark this processor(AP or BSP) as finished. // if (ProcToken !=3D NULL) { - WaitForSemaphore (&ProcToken->RunningApCount); + InterlockedDecrement (&ProcToken->RunningApCount); } } } =20 ReleaseAllAPs (); @@ -1729,14 +1575,14 @@ SmiRendezvous ( // goto Exit; } else { // // Signal presence of this processor - // mSmmMpSyncData->Counter is increased here! - // "ReleaseSemaphore (mSmmMpSyncData->Counter) =3D=3D 0" means BSP has= already ended the synchronization. + // CPU check in here! + // "RSmmCpuSyncIncreaseArrivalCount (mSmmMpSyncData->SmmCpuSyncCtx) <= =3D 0" means BSP has already ended the synchronization. // - if (ReleaseSemaphore (mSmmMpSyncData->Counter) =3D=3D 0) { + if (SmmCpuSyncCheckInCpu (mSmmMpSyncData->SmmCpuSyncCtx, CpuIndex) <= =3D 0) { // // BSP has already ended the synchronization, so QUIT!!! // Existing AP is too late now to enter SMI since BSP has already en= ded the synchronization!!! // =20 @@ -1828,12 +1674,10 @@ SmiRendezvous ( } else { APHandler (CpuIndex, ValidSmi, mSmmMpSyncData->EffectiveSyncMode); } } =20 - ASSERT (*mSmmMpSyncData->CpuData[CpuIndex].Run =3D=3D 0); - // // Wait for BSP's signal to exit SMI // while (*mSmmMpSyncData->AllCpusInSync) { CpuPause (); @@ -1949,12 +1793,10 @@ InitializeSmmCpuSemaphores ( SemaphoreBlock =3D AllocatePages (Pages); ASSERT (SemaphoreBlock !=3D NULL); ZeroMem (SemaphoreBlock, TotalSize); =20 SemaphoreAddr =3D (UINTN)SemaphoreBloc= k; - mSmmCpuSemaphores.SemaphoreGlobal.Counter =3D (UINT32 *)SemaphoreA= ddr; - SemaphoreAddr +=3D SemaphoreSize; mSmmCpuSemaphores.SemaphoreGlobal.InsideSmm =3D (BOOLEAN *)Semaphore= Addr; SemaphoreAddr +=3D SemaphoreSize; mSmmCpuSemaphores.SemaphoreGlobal.AllCpusInSync =3D (BOOLEAN *)Semaphore= Addr; SemaphoreAddr +=3D SemaphoreSize; mSmmCpuSemaphores.SemaphoreGlobal.PFLock =3D (SPIN_LOCK *)Semapho= reAddr; @@ -1964,12 +1806,10 @@ InitializeSmmCpuSemaphores ( SemaphoreAddr +=3D SemaphoreSize; =20 SemaphoreAddr =3D (UINTN)SemaphoreBlock + Globa= lSemaphoresSize; mSmmCpuSemaphores.SemaphoreCpu.Busy =3D (SPIN_LOCK *)SemaphoreAddr; SemaphoreAddr +=3D ProcessorCount * SemaphoreSiz= e; - mSmmCpuSemaphores.SemaphoreCpu.Run =3D (UINT32 *)SemaphoreAddr; - SemaphoreAddr +=3D ProcessorCount * SemaphoreSiz= e; mSmmCpuSemaphores.SemaphoreCpu.Present =3D (BOOLEAN *)SemaphoreAddr; =20 mPFLock =3D mSmmCpuSemaphores.SemaphoreGlobal.PFLo= ck; mConfigSmmCodeAccessCheckLock =3D mSmmCpuSemaphores.SemaphoreGlobal.Code= AccessCheckLock; =20 @@ -2003,32 +1843,28 @@ InitializeMpSyncData ( mSmmMpSyncData->BspIndex =3D (UINT32)-1; } =20 mSmmMpSyncData->EffectiveSyncMode =3D mCpuSmmSyncMode; =20 - mSmmMpSyncData->Counter =3D mSmmCpuSemaphores.SemaphoreGlobal.Co= unter; + mSmmMpSyncData->SmmCpuSyncCtx =3D SmmCpuSyncContextInit (gSmmCpuPrivat= e->SmmCoreEntryContext.NumberOfCpus); mSmmMpSyncData->InsideSmm =3D mSmmCpuSemaphores.SemaphoreGlobal.In= sideSmm; mSmmMpSyncData->AllCpusInSync =3D mSmmCpuSemaphores.SemaphoreGlobal.Al= lCpusInSync; ASSERT ( - mSmmMpSyncData->Counter !=3D NULL && mSmmMpSyncData->InsideSmm !=3D = NULL && + mSmmMpSyncData->SmmCpuSyncCtx !=3D NULL && mSmmMpSyncData->InsideSmm= !=3D NULL && mSmmMpSyncData->AllCpusInSync !=3D NULL ); - *mSmmMpSyncData->Counter =3D 0; *mSmmMpSyncData->InsideSmm =3D FALSE; *mSmmMpSyncData->AllCpusInSync =3D FALSE; =20 mSmmMpSyncData->AllApArrivedWithException =3D FALSE; =20 for (CpuIndex =3D 0; CpuIndex < gSmmCpuPrivate->SmmCoreEntryContext.Nu= mberOfCpus; CpuIndex++) { mSmmMpSyncData->CpuData[CpuIndex].Busy =3D (SPIN_LOCK *)((UINTN)mSmmCpuSemaphores.SemaphoreCpu.Busy + mSemaph= oreSize * CpuIndex); - mSmmMpSyncData->CpuData[CpuIndex].Run =3D - (UINT32 *)((UINTN)mSmmCpuSemaphores.SemaphoreCpu.Run + mSemaphoreS= ize * CpuIndex); mSmmMpSyncData->CpuData[CpuIndex].Present =3D (BOOLEAN *)((UINTN)mSmmCpuSemaphores.SemaphoreCpu.Present + mSemap= horeSize * CpuIndex); *(mSmmMpSyncData->CpuData[CpuIndex].Busy) =3D 0; - *(mSmmMpSyncData->CpuData[CpuIndex].Run) =3D 0; *(mSmmMpSyncData->CpuData[CpuIndex].Present) =3D FALSE; } } } =20 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.h index 654935dc76..b7bb937fbb 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -52,10 +52,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include #include #include +#include =20 #include #include =20 #include @@ -403,11 +404,10 @@ SmmRelocationSemaphoreComplete ( /// typedef struct { SPIN_LOCK *Busy; volatile EFI_AP_PROCEDURE2 Procedure; volatile VOID *Parameter; - volatile UINT32 *Run; volatile BOOLEAN *Present; PROCEDURE_TOKEN *Token; EFI_STATUS *Status; } SMM_CPU_DATA_BLOCK; =20 @@ -421,29 +421,28 @@ typedef struct { // // Pointer to an array. The array should be located immediately after th= is structure // so that UC cache-ability can be set together. // SMM_CPU_DATA_BLOCK *CpuData; - volatile UINT32 *Counter; volatile UINT32 BspIndex; volatile BOOLEAN *InsideSmm; volatile BOOLEAN *AllCpusInSync; volatile SMM_CPU_SYNC_MODE EffectiveSyncMode; volatile BOOLEAN SwitchBsp; volatile BOOLEAN *CandidateBsp; volatile BOOLEAN AllApArrivedWithException; EFI_AP_PROCEDURE StartupProcedure; VOID *StartupProcArgs; + VOID *SmmCpuSyncCtx; } SMM_DISPATCHER_MP_SYNC_DATA; =20 #define SMM_PSD_OFFSET 0xfb00 =20 /// /// All global semaphores' pointer /// typedef struct { - volatile UINT32 *Counter; volatile BOOLEAN *InsideSmm; volatile BOOLEAN *AllCpusInSync; SPIN_LOCK *PFLock; SPIN_LOCK *CodeAccessCheckLock; } SMM_CPU_SEMAPHORE_GLOBAL; @@ -451,11 +450,10 @@ typedef struct { /// /// All semaphores for each processor /// typedef struct { SPIN_LOCK *Busy; - volatile UINT32 *Run; volatile BOOLEAN *Present; SPIN_LOCK *Token; } SMM_CPU_SEMAPHORE_CPU; =20 /// diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf b/UefiCpuPkg/PiSm= mCpuDxeSmm/PiSmmCpuDxeSmm.inf index 5d52ed7d13..e92b8c747d 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf @@ -101,10 +101,11 @@ SmmCpuFeaturesLib PeCoffGetEntryPointLib PerformanceLib CpuPageTableLib MmSaveStateLib + SmmCpuSyncLib =20 [Protocols] gEfiSmmAccess2ProtocolGuid ## CONSUMES gEfiMpServiceProtocolGuid ## CONSUMES gEfiSmmConfigurationProtocolGuid ## PRODUCES --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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