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([171.76.85.25]) by smtp.gmail.com with ESMTPSA id pt11-20020a17090b3d0b00b0027d15bd9fa2sm3783336pjb.35.2023.10.29.07.46.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Oct 2023 07:46:29 -0700 (PDT) From: "Dhaval Sharma" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Sunil V L , Daniel Schaefer , Laszlo Ersek Subject: [edk2-devel] [PATCH v7 3/5] MdePkg: Implement RISC-V Cache Management Operations Date: Sun, 29 Oct 2023 20:16:11 +0530 Message-Id: <20231029144613.150580-4-dhaval@rivosinc.com> In-Reply-To: <20231029144613.150580-1-dhaval@rivosinc.com> References: <20231029144613.150580-1-dhaval@rivosinc.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dhaval@rivosinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1698590792023100005 Content-Type: text/plain; charset="utf-8" Implement Cache Management Operations (CMO) defined by RISC-V spec https://github.com/riscv/riscv-CMOs. Notes: 1. CMO only supports block based Operations. Meaning cache flush/invd/clean Operations are not available for the entire range. In that case we fallback on fence.i instructions. 2. Operations are implemented using Opcodes to make them compiler independent. binutils 2.39+ compilers support CMO instructions. Test: 1. Ensured correct instructions are refelecting in asm 2. Not able to verify actual instruction in HW as Qemu ignores any actual cache operations. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Sunil V L Cc: Daniel Schaefer Cc: Laszlo Ersek Signed-off-by: Dhaval Sharma Reviewed-by: Laszlo Ersek Reviewed-by: Jingyu Li Reviewed-by: Sunil V L --- Notes: V7: - Modify instruction names as per feedback from V6 - Added RB V6: - Implement Cache management instructions in Baselib MdePkg/Library/BaseLib/BaseLib.inf | 2 +- MdePkg/Include/Library/BaseLib.h | 33 +++= +++++++++++++++++ MdePkg/Include/RiscV64/RiscVasm.inc | 19 +++= ++++++++ MdePkg/Library/BaseLib/RiscV64/{FlushCache.S =3D> RiscVCacheMgmt.S} | 17 += +++++++++ 4 files changed, 70 insertions(+), 1 deletion(-) diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 03c7b02e828b..53389389448c 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -400,7 +400,7 @@ [Sources.RISCV64] RiscV64/RiscVCpuBreakpoint.S | GCC RiscV64/RiscVCpuPause.S | GCC RiscV64/RiscVInterrupt.S | GCC - RiscV64/FlushCache.S | GCC + RiscV64/RiscVCacheMgmt.S | GCC RiscV64/CpuScratch.S | GCC RiscV64/ReadTimer.S | GCC RiscV64/RiscVMmu.S | GCC diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index d4b56a9601da..c42cc165dc82 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -226,6 +226,39 @@ RiscVInvalidateDataCacheAsmFence ( VOID ); =20 +/** + RISC-V flush cache block. Atomically perform a clean operation + followed by an invalidate operation + +**/ +VOID +EFIAPI +RiscVCpuCacheFlushAsmCmo ( + IN UINTN + ); + +/** +Perform a write transfer to another cache or to memory if the +data in the copy of the cache block have been modified by a store +operation + +**/ +VOID +EFIAPI +RiscVCpuCacheCleanAsmCmo ( + IN UINTN + ); + +/** +Deallocate the copy of the cache block + +**/ +VOID +EFIAPI +RiscVCpuCacheInvalAsmCmo ( + IN UINTN + ); + #endif // defined (MDE_CPU_RISCV64) =20 #if defined (MDE_CPU_LOONGARCH64) diff --git a/MdePkg/Include/RiscV64/RiscVasm.inc b/MdePkg/Include/RiscV64/R= iscVasm.inc new file mode 100644 index 000000000000..29de7358855c --- /dev/null +++ b/MdePkg/Include/RiscV64/RiscVasm.inc @@ -0,0 +1,19 @@ +/* + * + * RISC-V cache operation encoding. + * Copyright (c) 2023, Rivos Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-2-Clause-Patent + * + */ + +.macro RISCVCMOFLUSH + .word 0x25200f +.endm + +.macro RISCVCMOINVALIDATE + .word 0x05200f +.endm + +.macro RISCVCMOCLEAN + .word 0x15200f +.endm diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S b/MdePkg/Library/B= aseLib/RiscV64/RiscVCacheMgmt.S similarity index 56% rename from MdePkg/Library/BaseLib/RiscV64/FlushCache.S rename to MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S index e0eea0b5fb25..3c7be3229e3b 100644 --- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S @@ -3,10 +3,12 @@ // RISC-V cache operation. // // Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// Copyright (c) 2023, Rivos Inc. All rights reserved.
// // SPDX-License-Identifier: BSD-2-Clause-Patent // //------------------------------------------------------------------------= ------ +.include "RiscVasm.inc" =20 .align 3 ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsmFence) @@ -19,3 +21,18 @@ ASM_PFX(RiscVInvalidateInstCacheAsmFence): ASM_PFX(RiscVInvalidateDataCacheAsmFence): fence ret + +ASM_GLOBAL ASM_PFX (RiscVCpuCacheFlushAsmCmo) +ASM_PFX (RiscVCpuCacheFlushAsmCmo): + RISCVCMOFLUSH + ret + +ASM_GLOBAL ASM_PFX (RiscVCpuCacheCleanAsmCmo) +ASM_PFX (RiscVCpuCacheCleanAsmCmo): + RISCVCMOCLEAN + ret + +ASM_GLOBAL ASM_PFX (RiscVCpuCacheInvalAsmCmo) +ASM_PFX (RiscVCpuCacheInvalAsmCmo): + RISCVCMOINVALIDATE + ret --=20 2.39.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110265): https://edk2.groups.io/g/devel/message/110265 Mute This Topic: https://groups.io/mt/102256466/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-