From nobody Thu May 16 08:38:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+110172+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+110172+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1698377043; cv=none; d=zohomail.com; s=zohoarc; b=ST2YD8J9G5rxTyDQdtQLjcFTKIPIcDMyHWLUkOCWTdCVwbRjyyeqFwaSo1EXQ0TKVuU0e4uGf49wN/odmACnIXsD04LPyqqFGrl690GmVpE7GjpW2JikIJWBGRCqpPFNTFPYDSpdeM+88o5GtqneSzSHjgA4GPC22S/g76Rye/Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698377043; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=nsWxWH0wazsOPdOedhunk+7vAS6JdkgD6FmylQKixno=; b=Mka5C1dhit8gpTpN02SRZiqoX9vMMgG7gq37kYeRecEhwyX3BtS31KAX/fwhKwxupRgCEE0qt/jfXaoB1jHLszT5e8CeyEpTAJMuOCmAjEptAtJEoYnk/AhZsgIgPEdh5YAXiyRvSZZoBnnBOJleiFVb4JEmNZP/boSd4iGgKYc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+110172+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1698377043762771.197329929947; Thu, 26 Oct 2023 20:24:03 -0700 (PDT) Return-Path: DKIM-Signature: a=rsa-sha256; bh=feVfTpkq7G6KqY4TZhMatH0CUHrc+Mn2wN41O9eIFFc=; c=relaxed/simple; d=groups.io; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Transfer-Encoding; s=20140610; t=1698377043; v=1; b=EvhRgxq9iR5gx7ya2kh9XkkHNCwC99Y/T4z/BN9UXi3DcVmoGXX97ZEVg+D6JZJNdleyeDfG QddI4vfdFr60fKnLNic5iYegppBVVnM1Mi0I9lMxcjF7AefHTPzHFnEl2BeGKXmoe25ZETTrf8m OsgOxjMyETxGofWBe7OVIsoo= X-Received: by 127.0.0.2 with SMTP id zk6JYY1788612xAb4afCZzX8; Thu, 26 Oct 2023 20:24:03 -0700 X-Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by mx.groups.io with SMTP id smtpd.web11.89095.1698377041079709977 for ; Thu, 26 Oct 2023 20:24:02 -0700 X-Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 9E84524E29A; Fri, 27 Oct 2023 11:23:50 +0800 (CST) X-Received: from EXMBX073.cuchost.com (172.16.6.83) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 27 Oct 2023 11:23:50 +0800 X-Received: from localhost.localdomain (202.188.176.82) by EXMBX073.cuchost.com (172.16.6.83) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 27 Oct 2023 11:23:44 +0800 From: "John Chew" To: CC: mindachen1987 , Sunil V L , Leif Lindholm , Michael D Kinney , Li Yong , John Chew Subject: [edk2-devel] [PATCH v3 1/5] StarFive/JH7110Pkg: Add Pci controller driver Date: Fri, 27 Oct 2023 11:19:02 +0800 Message-ID: <20231027031906.1814-2-yuinyee.chew@starfivetech.com> In-Reply-To: <20231027031906.1814-1-yuinyee.chew@starfivetech.com> References: <20231027031906.1814-1-yuinyee.chew@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [202.188.176.82] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX073.cuchost.com (172.16.6.83) X-YovoleRuleAgent: yovoleflag Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,yuinyee.chew@starfivetech.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: MKgbcfQ209eAZCvJF9hXGZ40x1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1698377045000100001 Content-Type: text/plain; charset="utf-8" From: mindachen1987 Implement Pci Host Bridge and Pci Segment driver: JH7110 SoC contains two PCI segment: - PCI Segment 0 (USB): 32-bit Memory: 0x3000_0000 ~ 0x3FFF_FFFF 64-bit Memory: 0x9_0000_0000 ~0x9_4000_0000 - PCI Segment 1 (NVME): 32-bit Memory: 0x3800_0000 ~ 0x37FF_FFFF 64-bit Memory: 0x9_8000_0000 ~0x9_C000_0000 Non-prefetachable memory is not used in this configuration. Cc: Sunil V L Cc: Leif Lindholm Cc: Michael D Kinney Cc: Li Yong Co-authored-by: John Chew Signed-off-by: mindachen1987 Acked-by: Sunil V L --- Silicon/StarFive/JH7110Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.c = | 263 ++++ Silicon/StarFive/JH7110Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf = | 61 + Silicon/StarFive/JH7110Pkg/Library/PciHostBridgeLib/PciHostBridgeLibConstr= uctor.c | 406 ++++++ Silicon/StarFive/JH7110Pkg/Library/PciSegmentLib/PciSegmentLib.c = | 1460 ++++++++++++++++++++ Silicon/StarFive/JH7110Pkg/Library/PciSegmentLib/PciSegmentLib.inf = | 33 + 5 files changed, 2223 insertions(+) diff --git a/Silicon/StarFive/JH7110Pkg/Library/PciHostBridgeLib/PciHostBri= dgeLib.c b/Silicon/StarFive/JH7110Pkg/Library/PciHostBridgeLib/PciHostBridg= eLib.c new file mode 100644 index 000000000000..8b46f6ff58e5 --- /dev/null +++ b/Silicon/StarFive/JH7110Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -0,0 +1,263 @@ +/** @file + * + * PCI Host Bridge Library instance for StarFive JH7110 SOC + * + * Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<= BR> + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#pragma pack(1) + +typedef PACKED struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; + +#pragma pack () + +STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[= ] =3D { + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)), + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) + } + }, + EISA_PNP_ID (0x0A08), // PCI Express + 0 + }, + + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + }, + + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)), + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) + } + }, + EISA_PNP_ID (0x0A08), // PCI Express + 1 + }, + + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + }, +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] =3D { + L"Mem", L"I/O", L"Bus" +}; + +// +// See description in MdeModulePkg/Include/Library/PciHostBridgeLib.h +// +PCI_ROOT_BRIDGE mPciRootBridges[] =3D { + { + 0, // Segment + 0, // Supports + 0, // Attributes + FALSE, // DmaAbove4G + FALSE, // NoExtendedConfigSpace (true= =3D256 byte config, false=3D4k) + FALSE, // ResourceAssigned + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, // AllocationAttributes + { + // Bus + FixedPcdGet32 (PcdPciBusMin), + FixedPcdGet32 (PcdPciBusMax) + }, { + // Io + FixedPcdGet64 (PcdPciIoBase), + FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1, + MAX_UINT64 - FixedPcdGet64 (PcdPciIoOffset) + 1 + }, { + // Mem + FixedPcdGet32 (PcdPci0Mmio32Base), + FixedPcdGet32 (PcdPci0Mmio32Base) + FixedPcdGet32 (PcdPci0Mmio32Size= ) - 1 + }, { + // MemAbove4G + FixedPcdGet64 (PcdPci0Mmio64Base), + FixedPcdGet64 (PcdPci0Mmio64Base) + FixedPcdGet64 (PcdPci0Mmio64Size= ) - 1 + }, + { + // Pefetchable Mem + MAX_UINT32, + 0x0 + }, { + // Pefetchable MemAbove4G + MAX_UINT64, + 0x0 + }, + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0] + }, + { + 1, // Segment + 0, // Supports + 0, // Attributes + FALSE, // DmaAbove4G + FALSE, // NoExtendedConfigSpace (true=3D2= 56 byte config, false=3D4k) + FALSE, // ResourceAssigned + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, // AllocationAttributes + { + // Bus + FixedPcdGet32 (PcdPciBusMin), + FixedPcdGet32 (PcdPciBusMax) + }, { + // Io + FixedPcdGet64 (PcdPciIoBase), + FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1, + MAX_UINT64 - FixedPcdGet64 (PcdPciIoOffset) + 1 + }, { + // Mem + FixedPcdGet32 (PcdPci1Mmio32Base), + FixedPcdGet32 (PcdPci1Mmio32Base) + FixedPcdGet32 (PcdPci1Mmio32Size= ) - 1 + }, { + // MemAbove4G + FixedPcdGet64 (PcdPci1Mmio64Base), + FixedPcdGet64 (PcdPci1Mmio64Base) + FixedPcdGet64 (PcdPci1Mmio64Size= ) - 1 + }, + { + // Pefetchable Mem + MAX_UINT32, + 0x0 + }, { + // Pefetchable MemAbove4G + MAX_UINT64, + 0x0 + }, + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1] + } +}; + +/** + Return all the root bridge instances in an array. + + @param Count Return the count of root bridge instances. + + @return All the root bridge instances in an array. + The array should be passed into PciHostBridgeFreeRootBridges() + when it's not used. +**/ +PCI_ROOT_BRIDGE * +EFIAPI +PciHostBridgeGetRootBridges ( + OUT UINTN *Count + ) +{ + *Count =3D ARRAY_SIZE (mPciRootBridges); + return mPciRootBridges; +} + +/** + Free the root bridge instances array returned from PciHostBridgeGetRootB= ridges(). + + @param Bridges The root bridge instances array. + @param Count The count of the array. +**/ +VOID +EFIAPI +PciHostBridgeFreeRootBridges ( + PCI_ROOT_BRIDGE *Bridges, + UINTN Count + ) +{ +} + +/** + Inform the platform that the resource conflict happens. + + @param HostBridgeHandle Handle of the Host Bridge. + @param Configuration Pointer to PCI I/O and PCI memory resource + descriptors. The Configuration contains the reso= urces + for all the root bridges. The resource for each = root + bridge is terminated with END descriptor and an + additional END is appended indicating the end of= the + entire resources. The resource descriptor field + values follow the description in + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + .SubmitResources(). +**/ +VOID +EFIAPI +PciHostBridgeResourceConflict ( + EFI_HANDLE HostBridgeHandle, + VOID *Configuration + ) +{ + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; + UINTN RootBridgeIndex; + + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n")); + + RootBridgeIndex =3D 0; + Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Configuration; + while (Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR) { + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++)); + for ( ; Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR; Descrip= tor++) { + ASSERT ( + Descriptor->ResType < + ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr) + ); + DEBUG ( + (DEBUG_ERROR, " %s: Length/Alignment =3D 0x%lx / 0x%lx\n", + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType= ], + Descriptor->AddrLen, Descriptor->AddrRangeMax + ) + ); + if (Descriptor->ResType =3D=3D ACPI_ADDRESS_SPACE_TYPE_MEM) { + DEBUG ( + (DEBUG_ERROR, " Granularity/SpecificFlag =3D %ld / %02x= %s\n", + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag, + ((Descriptor->SpecificFlag & + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETC= HABLE + ) !=3D 0) ? L" (Prefetchable)" : L"" + ) + ); + } + } + + // + // Skip the END descriptor for root bridge + // + ASSERT (Descriptor->Desc =3D=3D ACPI_END_TAG_DESCRIPTOR); + Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)( + (EFI_ACPI_END_TAG_D= ESCRIPTOR *)Descriptor + 1 + ); + } +} diff --git a/Silicon/StarFive/JH7110Pkg/Library/PciHostBridgeLib/PciHostBri= dgeLib.inf b/Silicon/StarFive/JH7110Pkg/Library/PciHostBridgeLib/PciHostBri= dgeLib.inf new file mode 100644 index 000000000000..e18e8e57829f --- /dev/null +++ b/Silicon/StarFive/JH7110Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.= inf @@ -0,0 +1,61 @@ +## @file +# +# PCI Host Bridge Library instance for StarFive JH7110 SOC +# Liberally borrowed from the SynQuacer +# +# Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<= BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010019 + BASE_NAME =3D PciHostBridgeLib + FILE_GUID =3D 606d906f-eba7-d5c6-fcf0-6aeedea00193 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PciHostBridgeLib|DXE_DRIVER + CONSTRUCTOR =3D JH7110PciHostBridgeLibConstructor + +# +# The following information is for reference only and not required by the = build +# tools. +# +# VALID_ARCHITECTURES =3D ARM AARCH64 RISCV64 +# + +[Sources] + PciHostBridgeLib.c + PciHostBridgeLibConstructor.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/StarFive/JH7110Pkg/JH7110Pkg.dec + +[LibraryClasses] + DebugLib + DevicePathLib + MemoryAllocationLib + PcdLib + UefiBootServicesTableLib + +[FixedPcd] + gJH7110TokenSpaceGuid.PcdPciRegBase + gJH7110TokenSpaceGuid.PcdPciBusMmioAdr + gJH7110TokenSpaceGuid.PcdPciBusMmioLen + gJH7110TokenSpaceGuid.PcdPciCpuMmioAdr + gJH7110TokenSpaceGuid.PcdPciBusMin + gJH7110TokenSpaceGuid.PcdPciBusMax + gJH7110TokenSpaceGuid.PcdPciIoBase + gJH7110TokenSpaceGuid.PcdPciIoSize + gJH7110TokenSpaceGuid.PcdPciIoOffset + gJH7110TokenSpaceGuid.PcdPci0Mmio32Base + gJH7110TokenSpaceGuid.PcdPci0Mmio32Size + gJH7110TokenSpaceGuid.PcdPci0Mmio64Base + gJH7110TokenSpaceGuid.PcdPci0Mmio64Size + gJH7110TokenSpaceGuid.PcdPci1Mmio32Base + gJH7110TokenSpaceGuid.PcdPci1Mmio32Size + gJH7110TokenSpaceGuid.PcdPci1Mmio64Base + gJH7110TokenSpaceGuid.PcdPci1Mmio64Size diff --git a/Silicon/StarFive/JH7110Pkg/Library/PciHostBridgeLib/PciHostBri= dgeLibConstructor.c b/Silicon/StarFive/JH7110Pkg/Library/PciHostBridgeLib/P= ciHostBridgeLibConstructor.c new file mode 100644 index 000000000000..cc505f2723d1 --- /dev/null +++ b/Silicon/StarFive/JH7110Pkg/Library/PciHostBridgeLib/PciHostBridgeLibC= onstructor.c @@ -0,0 +1,406 @@ +/** @file + * + * PCI Host Bridge Library instance for StarFive JH7110 SOC + * + * Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<= BR> + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + * This module initializes the Pci as close to a standard + * PCI root complex as possible. The general information + * for this driver was sourced from. + * + * + **/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RegWrite(addr, data) MmioWrite32((addr), (data)) +#define RegRead(addr, data) ((data) =3D MmioRead32 (addr)) + +#define STG_SYSCON_BASE 0x10240000 + +#define STG_SYSCON_K_RP_NEP_MASK (1 << 8) +#define STG_SYSCON_CKREF_SRC_SHIFT 18 +#define STG_SYSCON_CKREF_SRC_MASK (0x3 << 18) +#define STG_SYSCON_CLKREQ_MASK (1 << 22) +#define STG_SYSCON_BASE 0x10240000 +#define SYS_CLK_BASE 0x13020000 +#define STG_CLK_BASE 0x10230000 +#define SYS_CLK_NOC_OFFSET 0x98 +#define STG_PCIE_CLK_OFFSET 0x20 +#define STG_PCIE_CLKS 0xc +#define STG_PCIE_RESET_OFFSET 0x74 +#define SYS_GPIO_BASE 0x13040000 + +#define PREF_MEM_WIN_64_SUPPORT (1 << 3) +#define PMSG_LTR_SUPPORT (1 << 2) +#define PDLA_LINK_SPEED_GEN2 (1 << 12) +#define PLDA_FUNCTION_DIS (1 << 15) +#define PLDA_FUNC_NUM 4 +#define PLDA_PHY_FUNC_SHIFT 9 +#define PLDA_RP_ENABLE 1 + +#define PCIE_BASIC_STATUS 0x018 +#define PCIE_CFGNUM 0x140 +#define IMASK_LOCAL 0x180 +#define ISTATUS_LOCAL 0x184 +#define IMSI_ADDR 0x190 +#define ISTATUS_MSI 0x194 +#define CFG_SPACE 0x1000 +#define GEN_SETTINGS 0x80 +#define PCIE_PCI_IDS 0x9C +#define PCIE_WINROM 0xFC +#define PMSG_SUPPORT_RX 0x3F0 +#define PCI_MISC 0xB4 + +#define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK 0x7FFF00 +#define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT 0x8 +#define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK 0x7FFF +#define STG_SYSCON_AXI4_SLVL_AWFUNC_SHIFT 0x0 + +#define XR3PCI_ATR_AXI4_SLV0 0x800 +#define XR3PCI_ATR_SRC_ADDR_LOW 0x0 +#define XR3PCI_ATR_SRC_ADDR_HIGH 0x4 +#define XR3PCI_ATR_TRSL_ADDR_LOW 0x8 +#define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc +#define XR3PCI_ATR_TRSL_PARAM 0x10 +#define XR3PCI_ATR_TABLE_OFFSET 0x20 +#define XR3PCI_ATR_MAX_TABLE_NUM 8 + +#define XR3PCI_ATR_SRC_ADDR_MASK 0xfffff000 +#define XR3PCI_ATR_TRSL_ADDR_MASK 0xfffff000 +#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT 1 +#define XR3_PCI_ECAM_SIZE 28 + +#define IDS_PCI_TO_PCI_BRIDGE 0x060400 +#define IDS_CLASS_CODE_SHIFT 8 +#define SYS_GPIO_OUTPUT_OFF 0x40 + +UINT32 AtrTableNum; +UINT64 PCIE_CFG_BASE[2] =3D { FixedPcdGet32 (PcdPci0Mmio64Base) + Fi= xedPcdGet32 (PcdPci0Mmio64Size), + FixedPcdGet32 (PcdPci1Mmio64Base) + Fixe= dPcdGet32 (PcdPci1Mmio64Size) }; +UINT64 PCI_MEMREGION_32[2] =3D { FixedPcdGet32 (PcdPci0Mmio32Base), Fix= edPcdGet32 (PcdPci1Mmio32Base) }; +UINT64 PCI_MEMREGION_64[2] =3D { FixedPcdGet32 (PcdPci0Mmio64Base), Fix= edPcdGet32 (PcdPci1Mmio64Base) }; +UINT64 PCI_MEMREGION_SIZE[2] =3D { 27, 30 }; +UINT32 STG_ARFUNC_OFFSET[2] =3D { 0xc0, 0x270 }; +UINT32 STG_AWFUNC_OFFSET[2] =3D { 0xc4, 0x274 }; +UINT32 STG_RP_REP_OFFSET[2] =3D { 0x130, 0x2e0 }; +UINT32 PCIE_GPIO[2] =3D { 26, 28 }; + +STATIC inline UINT64 +GetPcieRegBase ( + IN UINT32 Port + ) +{ + return PCIE_REG_BASE + Port * 0x1000000; +} + +VOID +PcieRegWrite ( + IN UINT32 Port, + IN UINTN Offset, + IN UINT32 Value + ) +{ + UINT64 Base =3D GetPcieRegBase (Port); + + RegWrite ((UINT64)Base + Offset, Value); +} + +UINT32 +PcieRegRead ( + IN UINT32 Port, + IN UINTN Offset + ) +{ + UINT32 Value =3D 0; + UINT64 Base =3D GetPcieRegBase (Port); + + RegRead ((UINT64)Base + Offset, Value); + return Value; +} + +STATIC VOID +PcieUpdatebits ( + IN UINT64 Base, + IN UINTN Offset, + IN UINT32 Mask, + IN UINT32 val + ) +{ + UINT32 Value =3D 0; + + Value =3D MmioRead32 ((UINT64)Base + Offset); + Value &=3D ~Mask; + Value |=3D val; + MmioWrite32 ((UINT64)Base + Offset, Value); +} + +STATIC +VOID +PcieFuncSet ( + IN UINT32 Port + ) +{ + INTN i; + UINT32 Value; + UINT64 Base =3D GetPcieRegBase (Port); + + /* Disable physical functions except #0 */ + for (i =3D 1; i < PLDA_FUNC_NUM; i++) { + PcieUpdatebits ( + STG_SYSCON_BASE, + STG_ARFUNC_OFFSET[Port], + STG_SYSCON_AXI4_SLVL_ARFUNC_MASK, + (i << PLDA_PHY_FUNC_SHIFT) << + STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT + ); + PcieUpdatebits ( + STG_SYSCON_BASE, + STG_AWFUNC_OFFSET[Port], + STG_SYSCON_AXI4_SLVL_AWFUNC_MASK, + (i << PLDA_PHY_FUNC_SHIFT) << + STG_SYSCON_AXI4_SLVL_AWFUNC_SHIFT + ); + PcieUpdatebits ( + Base, + PCI_MISC, + PLDA_FUNCTION_DIS, + PLDA_FUNCTION_DIS + ); + } + + PcieUpdatebits ( + STG_SYSCON_BASE, + STG_ARFUNC_OFFSET[Port], + STG_SYSCON_AXI4_SLVL_ARFUNC_MASK, + 0 + ); + PcieUpdatebits ( + STG_SYSCON_BASE, + STG_AWFUNC_OFFSET[Port], + STG_SYSCON_AXI4_SLVL_AWFUNC_MASK, + 0 + ); + + /* Enable root port*/ + PcieUpdatebits ( + Base, + GEN_SETTINGS, + PLDA_RP_ENABLE, + PLDA_RP_ENABLE + ); + + Value =3D (IDS_PCI_TO_PCI_BRIDGE << IDS_CLASS_CODE_SHIFT); + PcieRegWrite (Port, PCIE_PCI_IDS, Value); + + PcieUpdatebits ( + Base, + PMSG_SUPPORT_RX, + PMSG_LTR_SUPPORT, + 0 + ); + + /* Prefetchable memory window 64-bit addressing support */ + PcieUpdatebits ( + Base, + PCIE_WINROM, + PREF_MEM_WIN_64_SUPPORT, + PREF_MEM_WIN_64_SUPPORT + ); +} + +STATIC +VOID +PcieSTGInit ( + IN UINT32 Port + ) +{ + PcieUpdatebits ( + STG_SYSCON_BASE, + STG_RP_REP_OFFSET[Port], + STG_SYSCON_K_RP_NEP_MASK, + STG_SYSCON_K_RP_NEP_MASK + ); + PcieUpdatebits ( + STG_SYSCON_BASE, + STG_AWFUNC_OFFSET[Port], + STG_SYSCON_CKREF_SRC_MASK, + 2 << STG_SYSCON_CKREF_SRC_SHIFT + ); + PcieUpdatebits ( + STG_SYSCON_BASE, + STG_AWFUNC_OFFSET[Port], + STG_SYSCON_CLKREQ_MASK, + STG_SYSCON_CLKREQ_MASK + ); +} + +STATIC +VOID +PcieClockInit ( + IN UINT32 Port + ) +{ + RegWrite ( + STG_CLK_BASE + STG_PCIE_CLK_OFFSET + + Port * STG_PCIE_CLKS, + 1 << 31 + ); /*axi mst0*/ + RegWrite ( + STG_CLK_BASE + STG_PCIE_CLK_OFFSET + + Port * STG_PCIE_CLKS + 4, + 1 << 31 + ); /* apb */ + RegWrite ( + STG_CLK_BASE + STG_PCIE_CLK_OFFSET + + Port * STG_PCIE_CLKS + 8, + 1 << 31 + ); /* tl0 */ +} + +STATIC +VOID +PcieResetDeassert ( + IN UINT32 Port + ) +{ + UINT32 PortOffset =3D Port * 6 + 11; + + PcieUpdatebits ( + STG_CLK_BASE, + STG_PCIE_RESET_OFFSET, + 0x3f << (PortOffset), + 0 + ); /*reset all*/ +} + +VOID +PcieResetAssert ( + IN UINT32 Port + ) +{ + UINT32 PortOffset =3D Port * 6 + 11; + + PcieUpdatebits ( + STG_CLK_BASE, + STG_PCIE_RESET_OFFSET, + 0x3f << (PortOffset), + 0x3f << (PortOffset) + ); /*axi mst0*/ +} + +STATIC +VOID +PcieGpioResetSet ( + IN UINT32 Port, + IN UINT32 Value + ) +{ + UINT32 Remain, Mask; + + Remain =3D PCIE_GPIO[Port] & 0x3; + Mask =3D 0xff << (Remain * 8); + PcieUpdatebits ( + SYS_GPIO_BASE, + SYS_GPIO_OUTPUT_OFF + (PCIE_GPIO[Port] & 0xfffc), + Mask, + Value << (Remain * 8) + ); +} + +STATIC +VOID +PcieAtrInit ( + IN UINT32 Port, + IN UINT64 SrcAddr, + IN UINT64 TrslAddr, + IN UINT32 WinSize, + IN UINT32 Config + ) +{ + UINT64 Base =3D GetPcieRegBase (Port) + XR3PCI_ATR_AXI4_SLV0; + UINT32 Value; + + Base +=3D XR3PCI_ATR_TABLE_OFFSET * AtrTableNum; + AtrTableNum++; + + /* X3PCI_ATR_SRC_ADDR_LOW: + * - bit 0: enable entry, + * - bits 1-6: ATR window size: total size in bytes: 2^(ATR_WSIZE + 1) + * - bits 7-11: reserved + * - bits 12-31: start of source address + */ + Value =3D SrcAddr; + + RegWrite ( + Base + XR3PCI_ATR_SRC_ADDR_LOW, + (Value & XR3PCI_ATR_SRC_ADDR_MASK) | ((WinSize - 1) << 1) | 0x1 + ); + Value =3D SrcAddr >> 32; + + RegWrite (Base + XR3PCI_ATR_SRC_ADDR_HIGH, Value); + Value =3D TrslAddr; + RegWrite (Base + XR3PCI_ATR_TRSL_ADDR_LOW, Value); + Value =3D TrslAddr >> 32; + RegWrite (Base + XR3PCI_ATR_TRSL_ADDR_HIGH, Value); + RegWrite (Base + XR3PCI_ATR_TRSL_PARAM, Config); +} + +EFI_STATUS +EFIAPI +JH7110PciHostBridgeLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + UINT32 PortIndex; + + DEBUG ((DEBUG_ERROR, "PCIe RootBridge constructor\n")); + for (PortIndex =3D 0; PortIndex < 2; PortIndex++) { + PcieSTGInit (PortIndex); + RegWrite (SYS_CLK_BASE + SYS_CLK_NOC_OFFSET, 1 << 31); + PcieClockInit (PortIndex); + PcieResetDeassert (PortIndex); + PcieGpioResetSet (PortIndex, 0); + PcieFuncSet (PortIndex); + + PcieAtrInit ( + PortIndex, + PCIE_CFG_BASE[PortIndex], + 0, + XR3_PCI_ECAM_SIZE, + 1 + ); + PcieAtrInit ( + PortIndex, + PCI_MEMREGION_32[PortIndex], + PCI_MEMREGION_32[PortIndex], + PCI_MEMREGION_SIZE[0], + 0 + ); + PcieAtrInit ( + PortIndex, + PCI_MEMREGION_64[PortIndex], + PCI_MEMREGION_64[PortIndex], + PCI_MEMREGION_SIZE[1], + 0 + ); + PcieGpioResetSet (PortIndex, 1); + MicroSecondDelay (300); + + DEBUG ((DEBUG_ERROR, "PCIe port %d init\n", PortIndex)); + } + + return EFI_SUCCESS; +} diff --git a/Silicon/StarFive/JH7110Pkg/Library/PciSegmentLib/PciSegmentLib= .c b/Silicon/StarFive/JH7110Pkg/Library/PciSegmentLib/PciSegmentLib.c new file mode 100644 index 000000000000..43dca2a6236a --- /dev/null +++ b/Silicon/StarFive/JH7110Pkg/Library/PciSegmentLib/PciSegmentLib.c @@ -0,0 +1,1460 @@ +/** @file + * + * PCI Segment Library for StarFive JH7110 SoC + * + * Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<= BR> + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef enum { + PciCfgWidthUint8 =3D 0, + PciCfgWidthUint16, + PciCfgWidthUint32, + PciCfgWidthMax +} PCI_CFG_WIDTH; + +/* + * This PCIe config space is unusual... + * The root port is the first bytes of the register space (offset 0) + * The individual devices are then selected by computing their BDF index + * and writing that into the CFG_INDEX register (offset 0x9000) + * the "ECAM" data is then read/writeable at CFG_DATA (offset 0x8000) + */ + +#define EFI_PCI_ADDR_BUS(bus) ((bus >> 20) & 0xFF) /* Note PCI_SEGMENT_= LIB_ADDRESS */ +#define EFI_PCI_ADDR_DEV(dev) ((dev >> 15) & 0x1F) +#define EFI_PCI_ADDR_FUN(fun) ((fun >> 12) & 0x07) + +/** + Assert the validity of a PCI Segment address. + A valid PCI Segment address should not contain 1's in bits 28..31 and 48= ..63 + + @param A The address to validate. + @param M Additional bits to assert to be zero. + +**/ +#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A, M) \ + ASSERT (((A) & (0xffff0000f0000000ULL | (M))) =3D=3D 0) + +/** + Given the nature of how we access PCI devices, we ensure that + read/write accesses are serialized through the use of a lock. +**/ +STATIC +EFI_LOCK mPciSegmentReadWriteLock =3D EFI_INITIALIZE_LOCK_VARIABLE (TPL_H= IGH_LEVEL); + +// STATIC UINT64 mPciSegmentLastAccess; /* Avoid repeat CFG_INDEX upda= tes */ + +/** + Internal worker function to obtain config space base address. + + @param Address The address that encodes the PCI Bus, Device, Function a= nd + Register. + + @return The value read from the PCI configuration register. + +**/ +STATIC +UINT64 +PciSegmentLibGetConfigBase ( + IN UINT64 Address, + IN UINT16 Segment, + IN UINT32 Write + ) +{ + UINT64 Base; + UINT64 Offset; + UINT32 Dev; + UINT32 Bus; + + Base =3D PCIE_CONFIG_BASE; + Offset =3D Address & 0xFFF; /* Pick off the 4k register offset */ + Address &=3D 0xFFFF000; /* Clear the offset leave only the BD= F */ + + /* The root port is at the base of the PCIe register space */ + if (Address !=3D 0) { + Dev =3D EFI_PCI_ADDR_DEV (Address); + Bus =3D EFI_PCI_ADDR_BUS (Address); + + /* + * There can only be a single device on bus 1 (downstream of root). + * Subsequent busses (behind a PCIe switch) can have more. + */ + if (Dev > 0) { + return 0xFFFFFFFF; + } + + return Base + Segment * 0x80000000 + Address + Offset; + } else { + if (Write && ((Offset =3D=3D 0x10) || (Offset =3D=3D 0x14))) { + return 0xFFFFFFFF; + } + } + + return Base + Segment * 0x80000000 + Offset; +} + +/** + Internal worker function to read a PCI configuration register. + + @param Address The address that encodes the PCI Bus, Device, Function a= nd + Register. + @param Width The width of data to read + + @return The value read from the PCI configuration register. + +**/ +STATIC +UINT32 +PciSegmentLibReadWorker ( + IN UINT64 Address, + IN PCI_CFG_WIDTH Width + ) +{ + UINT64 Base; + UINT32 Ret; + UINT16 Segment =3D (Address >> 32); + + EfiAcquireLock (&mPciSegmentReadWriteLock); + Base =3D PciSegmentLibGetConfigBase (Address, Segment, 0); + + if (Base =3D=3D 0xFFFFFFFF) { + EfiReleaseLock (&mPciSegmentReadWriteLock); + return Base; + } + + switch (Width) { + case PciCfgWidthUint8: + Ret =3D MmioRead8 (Base); + break; + case PciCfgWidthUint16: + Ret =3D MmioRead16 (Base); + break; + case PciCfgWidthUint32: + Ret =3D MmioRead32 (Base); + break; + default: + ASSERT (FALSE); + Ret =3D 0; + } + + EfiReleaseLock (&mPciSegmentReadWriteLock); + // DEBUG ((DEBUG_ERROR, "PCIe seg read Address %lx %lx width %d val %x S= egment %d\n", Base, Address, Width, Ret, Segment)); + return Ret; +} + +/** + Internal worker function to writes a PCI configuration register. + + @param Address The address that encodes the PCI Bus, Device, Function a= nd + Register. + @param Width The width of data to write + @param Data The value to write. + + @return The value written to the PCI configuration register. + +**/ +STATIC +UINT32 +PciSegmentLibWriteWorker ( + IN UINT64 Address, + IN PCI_CFG_WIDTH Width, + IN UINT32 Data + ) +{ + UINT64 Base; + UINT16 Segment =3D (Address >> 32); + + EfiAcquireLock (&mPciSegmentReadWriteLock); + Base =3D PciSegmentLibGetConfigBase (Address, Segment, 1); + + if (Base =3D=3D 0xFFFFFFFF) { + EfiReleaseLock (&mPciSegmentReadWriteLock); + return Data; + } + + switch (Width) { + case PciCfgWidthUint8: + MmioWrite8 (Base, Data); + break; + case PciCfgWidthUint16: + MmioWrite16 (Base, Data); + break; + case PciCfgWidthUint32: + MmioWrite32 (Base, Data); + break; + default: + ASSERT (FALSE); + } + + EfiReleaseLock (&mPciSegmentReadWriteLock); + return Data; +} + +/** + Register a PCI device so PCI configuration registers may be accessed aft= er + SetVirtualAddressMap(). + + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function a= nd + Register. + + @retval RETURN_SUCCESS The PCI device was registered for runti= me access. + @retval RETURN_UNSUPPORTED An attempt was made to call this functi= on + after ExitBootServices(). + @retval RETURN_UNSUPPORTED The resources required to access the PC= I device + at runtime could not be mapped. + @retval RETURN_OUT_OF_RESOURCES There are not enough resources availabl= e to + complete the registration. + +**/ +RETURN_STATUS +EFIAPI +PciSegmentRegisterForRuntimeAccess ( + IN UINTN Address + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); + return RETURN_UNSUPPORTED; +} + +/** + Reads an 8-bit PCI configuration register. + + Reads and returns the 8-bit PCI configuration register specified by Addr= ess. + This function must guarantee that all PCI read and write operations are = serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, + and Register. + + @return The 8-bit PCI configuration register specified by Address. + +**/ +UINT8 +EFIAPI +PciSegmentRead8 ( + IN UINT64 Address + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); + + return (UINT8)PciSegmentLibReadWorker (Address, PciCfgWidthUint8); +} + +/** + Writes an 8-bit PCI configuration register. + + Writes the 8-bit PCI configuration register specified by Address with th= e value specified by Value. + Value is returned. This function must guarantee that all PCI read and w= rite operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Devic= e, Function, and Register. + @param Value The value to write. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentWrite8 ( + IN UINT64 Address, + IN UINT8 Value + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); + + return (UINT8)PciSegmentLibWriteWorker (Address, PciCfgWidthUint8, Value= ); +} + +/** + Performs a bitwise OR of an 8-bit PCI configuration register with an 8-b= it value. + + Reads the 8-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified by= OrData, + and writes the result to the 8-bit PCI configuration register specified = by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are = serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentOr8 ( + IN UINT64 Address, + IN UINT8 OrData + ) +{ + return PciSegmentWrite8 (Address, (UINT8)(PciSegmentRead8 (Address) | Or= Data)); +} + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-= bit value. + + Reads the 8-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified b= y AndData, + and writes the result to the 8-bit PCI configuration register specified = by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are = serialized. + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentAnd8 ( + IN UINT64 Address, + IN UINT8 AndData + ) +{ + return PciSegmentWrite8 (Address, (UINT8)(PciSegmentRead8 (Address) & An= dData)); +} + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-= bit value, + followed a bitwise OR with another 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified b= y AndData, + performs a bitwise OR between the result of the AND operation and the va= lue specified by OrData, + and writes the result to the 8-bit PCI configuration register specified = by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are = serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentAndThenOr8 ( + IN UINT64 Address, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + return PciSegmentWrite8 (Address, (UINT8)((PciSegmentRead8 (Address) & A= ndData) | OrData)); +} + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in an 8-bit PCI configuration register. The bit fiel= d is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address The PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..7. + + @return The value of the bit field read from the PCI configuration regis= ter. + +**/ +UINT8 +EFIAPI +PciSegmentBitFieldRead8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit); +} + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of t= he + 8-bit register is returned. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit an= d EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..7. + @param Value The new value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentBitFieldWrite8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 Value + ) +{ + return PciSegmentWrite8 ( + Address, + BitFieldWrite8 (PciSegmentRead8 (Address), Star= tBit, EndBit, Value) + ); +} + +/** + Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, = and + writes the result back to the bit field in the 8-bit port. + + Reads the 8-bit PCI configuration register specified by Address, perform= s a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 8-bit PCI configuration register + specified by Address. The value written to the PCI configuration registe= r is + returned. This function must guarantee that all PCI read and write opera= tions + are serialized. Extra left bits in OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..7. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentBitFieldOr8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 OrData + ) +{ + return PciSegmentWrite8 ( + Address, + BitFieldOr8 (PciSegmentRead8 (Address), StartBi= t, EndBit, OrData) + ); +} + +/** + Reads a bit field in an 8-bit PCI configuration register, performs a bit= wise + AND, and writes the result back to the bit field in the 8-bit register. + + Reads the 8-bit PCI configuration register specified by Address, perform= s a + bitwise AND between the read result and the value specified by AndData, = and + writes the result to the 8-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..7. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentBitFieldAnd8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData + ) +{ + return PciSegmentWrite8 ( + Address, + BitFieldAnd8 (PciSegmentRead8 (Address), StartB= it, EndBit, AndData) + ); +} + +/** + Reads a bit field in an 8-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 8-bit port. + + Reads the 8-bit PCI configuration register specified by Address, perform= s a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 8-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that al= l PCI + read and write operations are serialized. Extra left bits in both AndDat= a and + OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..7. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentBitFieldAndThenOr8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + return PciSegmentWrite8 ( + Address, + BitFieldAndThenOr8 (PciSegmentRead8 (Address), = StartBit, EndBit, AndData, OrData) + ); +} + +/** + Reads a 16-bit PCI configuration register. + + Reads and returns the 16-bit PCI configuration register specified by Add= ress. + This function must guarantee that all PCI read and write operations are = serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register. + + @return The 16-bit PCI configuration register specified by Address. + +**/ +UINT16 +EFIAPI +PciSegmentRead16 ( + IN UINT64 Address + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1); + + return (UINT16)PciSegmentLibReadWorker (Address, PciCfgWidthUint16); +} + +/** + Writes a 16-bit PCI configuration register. + + Writes the 16-bit PCI configuration register specified by Address with t= he value specified by Value. + Value is returned. This function must guarantee that all PCI read and w= rite operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Devic= e, Function, and Register. + @param Value The value to write. + + @return The parameter of Value. + +**/ +UINT16 +EFIAPI +PciSegmentWrite16 ( + IN UINT64 Address, + IN UINT16 Value + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1); + + return (UINT16)PciSegmentLibWriteWorker (Address, PciCfgWidthUint16, Val= ue); +} + +/** + Performs a bitwise OR of a 16-bit PCI configuration register with + a 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 16-bit PCI configuration register + specified by Address. The value written to the PCI configuration registe= r is + returned. This function must guarantee that all PCI read and write opera= tions + are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, F= unction and + Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentOr16 ( + IN UINT64 Address, + IN UINT16 OrData + ) +{ + return PciSegmentWrite16 (Address, (UINT16)(PciSegmentRead16 (Address) |= OrData)); +} + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-= bit value. + + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified b= y AndData, + and writes the result to the 16-bit PCI configuration register specified= by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are = serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentAnd16 ( + IN UINT64 Address, + IN UINT16 AndData + ) +{ + return PciSegmentWrite16 (Address, (UINT16)(PciSegmentRead16 (Address) &= AndData)); +} + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-= bit value, + followed a bitwise OR with another 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified b= y AndData, + performs a bitwise OR between the result of the AND operation and the va= lue specified by OrData, + and writes the result to the 16-bit PCI configuration register specified= by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are = serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentAndThenOr16 ( + IN UINT64 Address, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + return PciSegmentWrite16 (Address, (UINT16)((PciSegmentRead16 (Address) = & AndData) | OrData)); +} + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in a 16-bit PCI configuration register. The bit fiel= d is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address The PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..15. + + @return The value of the bit field read from the PCI configuration regis= ter. + +**/ +UINT16 +EFIAPI +PciSegmentBitFieldRead16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit); +} + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of t= he + 16-bit register is returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit an= d EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..15. + @param Value The new value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentBitFieldWrite16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 Value + ) +{ + return PciSegmentWrite16 ( + Address, + BitFieldWrite16 (PciSegmentRead16 (Address), S= tartBit, EndBit, Value) + ); +} + +/** + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified by= OrData, + and writes the result to the 16-bit PCI configuration register specified= by Address. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..15. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentBitFieldOr16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 OrData + ) +{ + return PciSegmentWrite16 ( + Address, + BitFieldOr16 (PciSegmentRead16 (Address), Star= tBit, EndBit, OrData) + ); +} + +/** + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, + and writes the result back to the bit field in the 16-bit port. + + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified by= OrData, + and writes the result to the 16-bit PCI configuration register specified= by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are = serialized. + Extra left bits in OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + The ordinal of the least significant bit in a byte is = bit 0. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + The ordinal of the most significant bit in a byte is b= it 7. + @param AndData The value to AND with the read value from the PCI conf= iguration register. + + @return The value written to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentBitFieldAnd16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData + ) +{ + return PciSegmentWrite16 ( + Address, + BitFieldAnd16 (PciSegmentRead16 (Address), Sta= rtBit, EndBit, AndData) + ); +} + +/** + Reads a bit field in a 16-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 16-bit port. + + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 16-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that al= l PCI + read and write operations are serialized. Extra left bits in both AndDat= a and + OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..15. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentBitFieldAndThenOr16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + return PciSegmentWrite16 ( + Address, + BitFieldAndThenOr16 (PciSegmentRead16 (Address= ), StartBit, EndBit, AndData, OrData) + ); +} + +/** + Reads a 32-bit PCI configuration register. + + Reads and returns the 32-bit PCI configuration register specified by Add= ress. + This function must guarantee that all PCI read and write operations are = serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, + and Register. + + @return The 32-bit PCI configuration register specified by Address. + +**/ +UINT32 +EFIAPI +PciSegmentRead32 ( + IN UINT64 Address + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3); + + return PciSegmentLibReadWorker (Address, PciCfgWidthUint32); +} + +/** + Writes a 32-bit PCI configuration register. + + Writes the 32-bit PCI configuration register specified by Address with t= he value specified by Value. + Value is returned. This function must guarantee that all PCI read and w= rite operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Devic= e, + Function, and Register. + @param Value The value to write. + + @return The parameter of Value. + +**/ +UINT32 +EFIAPI +PciSegmentWrite32 ( + IN UINT64 Address, + IN UINT32 Value + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3); + + return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32, Value); +} + +/** + Performs a bitwise OR of a 32-bit PCI configuration register with a 32-b= it value. + + Reads the 32-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified by= OrData, + and writes the result to the 32-bit PCI configuration register specified= by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are = serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentOr32 ( + IN UINT64 Address, + IN UINT32 OrData + ) +{ + return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData); +} + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-= bit value. + + Reads the 32-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified b= y AndData, + and writes the result to the 32-bit PCI configuration register specified= by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are = serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, + and Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentAnd32 ( + IN UINT64 Address, + IN UINT32 AndData + ) +{ + return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData); +} + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-= bit value, + followed a bitwise OR with another 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified b= y AndData, + performs a bitwise OR between the result of the AND operation and the va= lue specified by OrData, + and writes the result to the 32-bit PCI configuration register specified= by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are = serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, + and Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentAndThenOr32 ( + IN UINT64 Address, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData= ) | OrData); +} + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in a 32-bit PCI configuration register. The bit fiel= d is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address The PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..31. + + @return The value of the bit field read from the PCI configuration regis= ter. + +**/ +UINT32 +EFIAPI +PciSegmentBitFieldRead32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit); +} + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of t= he + 32-bit register is returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit an= d EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..31. + @param Value The new value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentBitFieldWrite32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 Value + ) +{ + return PciSegmentWrite32 ( + Address, + BitFieldWrite32 (PciSegmentRead32 (Address), S= tartBit, EndBit, Value) + ); +} + +/** + Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, = and + writes the result back to the bit field in the 32-bit port. + + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 32-bit PCI configuration register + specified by Address. The value written to the PCI configuration registe= r is + returned. This function must guarantee that all PCI read and write opera= tions + are serialized. Extra left bits in OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..31. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentBitFieldOr32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 OrData + ) +{ + return PciSegmentWrite32 ( + Address, + BitFieldOr32 (PciSegmentRead32 (Address), Star= tBit, EndBit, OrData) + ); +} + +/** + Reads a bit field in a 32-bit PCI configuration register, performs a bit= wise + AND, and writes the result back to the bit field in the 32-bit register. + + + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a bitwise + AND between the read result and the value specified by AndData, and writ= es the result + to the 32-bit PCI configuration register specified by Address. The value= written to + the PCI configuration register is returned. This function must guarante= e that all PCI + read and write operations are serialized. Extra left bits in AndData ar= e stripped. + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..31. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentBitFieldAnd32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData + ) +{ + return PciSegmentWrite32 ( + Address, + BitFieldAnd32 (PciSegmentRead32 (Address), Sta= rtBit, EndBit, AndData) + ); +} + +/** + Reads a bit field in a 32-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 32-bit port. + + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 32-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that al= l PCI + read and write operations are serialized. Extra left bits in both AndDat= a and + OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit fi= eld. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit fie= ld. + Range 0..31. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentBitFieldAndThenOr32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + return PciSegmentWrite32 ( + Address, + BitFieldAndThenOr32 (PciSegmentRead32 (Address= ), StartBit, EndBit, AndData, OrData) + ); +} + +/** + Reads a range of PCI configuration registers into a caller supplied buff= er. + + Reads the range of PCI configuration registers specified by StartAddress= and + Size into the buffer specified by Buffer. This function only allows the = PCI + configuration registers from a single PCI function to be read. Size is + returned. When possible 32-bit PCI configuration read cycles are used to= read + from StartAdress to StartAddress + Size. Due to alignment restrictions, = 8-bit + and 16-bit PCI configuration read cycles may be used at the beginning an= d the + end of the range. + + If any reserved bits in StartAddress are set, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress The starting address that encodes the PCI Segment,= Bus, + Device, Function and Register. + @param Size The size in bytes of the transfer. + @param Buffer The pointer to a buffer receiving the data read. + + @return Size + +**/ +UINTN +EFIAPI +PciSegmentReadBuffer ( + IN UINT64 StartAddress, + IN UINTN Size, + OUT VOID *Buffer + ) +{ + UINTN ReturnValue; + + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0); + ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000); + + if (Size =3D=3D 0) { + return Size; + } + + ASSERT (Buffer !=3D NULL); + + // + // Save Size for return + // + ReturnValue =3D Size; + + if ((StartAddress & BIT0) !=3D 0) { + // + // Read a byte if StartAddress is byte aligned + // + *(volatile UINT8 *)Buffer =3D PciSegmentRead8 (StartAddress); + StartAddress +=3D sizeof (UINT8); + Size -=3D sizeof (UINT8); + Buffer =3D (UINT8 *)Buffer + 1; + } + + if ((Size >=3D sizeof (UINT16)) && ((StartAddress & BIT1) !=3D 0)) { + // + // Read a word if StartAddress is word aligned + // + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress)); + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16 *)Buffer + 1; + } + + while (Size >=3D sizeof (UINT32)) { + // + // Read as many double words as possible + // + WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress)); + StartAddress +=3D sizeof (UINT32); + Size -=3D sizeof (UINT32); + Buffer =3D (UINT32 *)Buffer + 1; + } + + if (Size >=3D sizeof (UINT16)) { + // + // Read the last remaining word if exist + // + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress)); + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16 *)Buffer + 1; + } + + if (Size >=3D sizeof (UINT8)) { + // + // Read the last remaining byte if exist + // + *(volatile UINT8 *)Buffer =3D PciSegmentRead8 (StartAddress); + } + + return ReturnValue; +} + +/** + Copies the data in a caller supplied buffer to a specified range of PCI + configuration space. + + Writes the range of PCI configuration registers specified by StartAddres= s and + Size from the buffer specified by Buffer. This function only allows the = PCI + configuration registers from a single PCI function to be written. Size is + returned. When possible 32-bit PCI configuration write cycles are used to + write from StartAdress to StartAddress + Size. Due to alignment restrict= ions, + 8-bit and 16-bit PCI configuration write cycles may be used at the begin= ning + and the end of the range. + + If any reserved bits in StartAddress are set, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress The starting address that encodes the PCI Segment,= Bus, + Device, Function and Register. + @param Size The size in bytes of the transfer. + @param Buffer The pointer to a buffer containing the data to wri= te. + + @return The parameter of Size. + +**/ +UINTN +EFIAPI +PciSegmentWriteBuffer ( + IN UINT64 StartAddress, + IN UINTN Size, + IN VOID *Buffer + ) +{ + UINTN ReturnValue; + + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0); + ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000); + + if (Size =3D=3D 0) { + return 0; + } + + ASSERT (Buffer !=3D NULL); + + // The Bcm/Rpi has a single cfg which can be mapped + // to any given device on the bus, which means we need to remap + // it basically everytime a new config access is done + + // + // Save Size for return + // + ReturnValue =3D Size; + + if ((StartAddress & BIT0) !=3D 0) { + // + // Write a byte if StartAddress is byte aligned + // + PciSegmentWrite8 (StartAddress, *(UINT8 *)Buffer); + StartAddress +=3D sizeof (UINT8); + Size -=3D sizeof (UINT8); + Buffer =3D (UINT8 *)Buffer + 1; + } + + if ((Size >=3D sizeof (UINT16)) && ((StartAddress & BIT1) !=3D 0)) { + // + // Write a word if StartAddress is word aligned + // + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer)); + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16 *)Buffer + 1; + } + + while (Size >=3D sizeof (UINT32)) { + // + // Write as many double words as possible + // + PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer)); + StartAddress +=3D sizeof (UINT32); + Size -=3D sizeof (UINT32); + Buffer =3D (UINT32 *)Buffer + 1; + } + + if (Size >=3D sizeof (UINT16)) { + // + // Write the last remaining word if exist + // + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer)); + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16 *)Buffer + 1; + } + + if (Size >=3D sizeof (UINT8)) { + // + // Write the last remaining byte if exist + // + PciSegmentWrite8 (StartAddress, *(UINT8 *)Buffer); + } + + return ReturnValue; +} diff --git a/Silicon/StarFive/JH7110Pkg/Library/PciSegmentLib/PciSegmentLib= .inf b/Silicon/StarFive/JH7110Pkg/Library/PciSegmentLib/PciSegmentLib.inf new file mode 100644 index 000000000000..063c85ebc428 --- /dev/null +++ b/Silicon/StarFive/JH7110Pkg/Library/PciSegmentLib/PciSegmentLib.inf @@ -0,0 +1,33 @@ +## @file +# PCI Segment Library for StarFive JH7110 SoC +# +# Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D PciSegmentLib + FILE_GUID =3D 832163a2-41f5-c529-3f02-77fb68abbc2c + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PciSegmentLib + +[Sources] + PciSegmentLib.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/StarFive/JH7110Pkg/JH7110Pkg.dec + +[LibraryClasses] + BaseLib + DebugLib + IoLib + PcdLib + UefiLib + +[FixedPcd] + gJH7110TokenSpaceGuid.PcdPciConfigRegBase --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110172): https://edk2.groups.io/g/devel/message/110172 Mute This Topic: https://groups.io/mt/102214518/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 16 08:38:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+110176+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+110176+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1698377071; cv=none; d=zohomail.com; s=zohoarc; b=cNVAzKY/j2VDCY98A8PI+SiMf/NEn4EoZSZG+OJfjkTtMNafLegnKDUYQ3ZePsxXjeYNUf7jimd+VNkjlNfpCO4BTv0RTJwa9y/33yBCU3Xukf7RdH3x0SrsZ2c2izHDsI8410r5msldgJBnKwt76GRPhP/YU9UrJI+bnLObX9E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698377071; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=Kc9BSB2cqPiiXFNvuTeqjSHJxpjVj4hGoEPuwTqGH7A=; b=d09mInZyxM/3JPfGWYrHEKGQqSCJ6kPDfzjMm8iYCsCifYPq6g3uKr9S11XQV+ff4RJvsQBcYeaXGIP3mHA2ti7JckKL7AxpYD15DKYXE+XPnZVDhFqIPymGZ6B4gJsODh3nmtcWQkw0Oiby3JDON0PZI5vrVslc8xp3DgDT0RI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+110176+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1698377071659211.04936823366472; Thu, 26 Oct 2023 20:24:31 -0700 (PDT) Return-Path: DKIM-Signature: a=rsa-sha256; bh=mAL4SUtXuyvbPTgkrWsD6LaCoUstodv31hNiTxR6Hq0=; c=relaxed/simple; d=groups.io; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Transfer-Encoding; s=20140610; t=1698377071; v=1; b=fxuoPGSLNu/dy+osr9TrfX9j0Jz/1uutt6ImozKmfNikwdaYxV+DHeLhIiEcyv0Ytdofsnqi OzpzXTMrPMWsaFvMIDSFJ3D7LXZqST8QVyQX3zrU8BqVi0zMoFhMDwFKRY5poK2rjKsb5pBUZ5U PjjES2uJZ9FoxPa1ENJ40yzo= X-Received: by 127.0.0.2 with SMTP id OiMKYY1788612xzBwRUNjCMU; Thu, 26 Oct 2023 20:24:31 -0700 X-Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by mx.groups.io with SMTP id smtpd.web10.218633.1698377057391309831 for ; Thu, 26 Oct 2023 20:24:30 -0700 X-Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id F06A924E2A1; Fri, 27 Oct 2023 11:23:56 +0800 (CST) X-Received: from EXMBX073.cuchost.com (172.16.6.83) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 27 Oct 2023 11:23:57 +0800 X-Received: from localhost.localdomain (202.188.176.82) by EXMBX073.cuchost.com (172.16.6.83) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 27 Oct 2023 11:23:51 +0800 From: "John Chew" To: CC: John Chew , Sunil V L , Leif Lindholm , Michael D Kinney , Li Yong Subject: [edk2-devel] [PATCH v3 2/5] StarFive/JH7110Pkg: Add SPI protocol and driver support Date: Fri, 27 Oct 2023 11:19:03 +0800 Message-ID: <20231027031906.1814-3-yuinyee.chew@starfivetech.com> In-Reply-To: <20231027031906.1814-1-yuinyee.chew@starfivetech.com> References: <20231027031906.1814-1-yuinyee.chew@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [202.188.176.82] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX073.cuchost.com (172.16.6.83) X-YovoleRuleAgent: yovoleflag Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,yuinyee.chew@starfivetech.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: HWDZ8d2dzgR8otn4nerZv8X7x1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1698377073445100007 Content-Type: text/plain; charset="utf-8" This patch include QSPI driver and Flash driver protocol. QSPI driver: 1. Used indirect read/write 2. Master mode only 3. Require to setup qspi driver after located protocol 4. Require to free device if no longer needed 5. Support command read/write & data read/write Flash driver: 1. Require QSPI protocol as prerequisite 2. Support for flash read/write/update/erase 3. Require to init flash driver after allocated protocol Cc: Sunil V L Cc: Leif Lindholm Cc: Michael D Kinney Cc: Li Yong Signed-off-by: John Chew Acked-by: Sunil V L --- Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiDxe/SpiDxe.c = | 893 ++++++++++++++++++++ Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiDxe/SpiDxe.h = | 188 +++++ Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiDxe/SpiDxe.inf = | 52 ++ Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiFlashDxe/SpiFlashDx= e.c | 571 +++++++++++++ Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiFlashDxe/SpiFlashDx= e.h | 35 + Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiFlashDxe/SpiFlashDx= e.inf | 44 + Silicon/StarFive/JH7110Pkg/Include/Protocol/Spi.h = | 163 ++++ Silicon/StarFive/JH7110Pkg/Include/Protocol/SpiFlash.h = | 88 ++ 8 files changed, 2034 insertions(+) diff --git a/Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiDxe/Spi= Dxe.c b/Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiDxe/SpiDxe.c new file mode 100755 index 000000000000..c345556f8abf --- /dev/null +++ b/Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiDxe/SpiDxe.c @@ -0,0 +1,893 @@ +/** @file + * + * Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.=
+ * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "SpiDxe.h" + +SPI_MASTER *mSpiMasterInstance; + +STATIC +VOID +SpiControllerEnable ( + IN UINT32 RegBase + ) +{ + UINT32 Reg; + + Reg =3D MmioRead32 (RegBase + SPI_REG_CONFIG); + Reg |=3D SPI_REG_CONFIG_ENABLE; + MmioWrite32 (RegBase + SPI_REG_CONFIG, Reg); +} + +STATIC +VOID +SpiControllerDisable ( + IN UINT32 RegBase + ) +{ + UINT32 Reg; + + Reg =3D MmioRead32 (RegBase + SPI_REG_CONFIG); + Reg &=3D ~SPI_REG_CONFIG_ENABLE; + MmioWrite32 (RegBase + SPI_REG_CONFIG, Reg); +} + +STATIC +VOID +SpiWriteSpeed ( + IN SPI_DEVICE_PARAMS *Slave, + IN UINT32 SclkHz, + IN SPI_TIMING_PARAMS *Timing + ) +{ + UINT32 Reg, Div, RefClkNs, SclkNs; + UINT32 Tshsl, Tchsh, Tslch, Tsd2d; + + SpiControllerDisable (Slave->RegBase); + + /* Configure baudrate */ + Reg =3D MmioRead32 (Slave->RegBase + SPI_REG_CONFIG); + Reg &=3D ~(SPI_REG_CONFIG_BAUD_MASK << SPI_REG_CONFIG_BAUD_LSB); + + Div =3D DIV_ROUND_UP (Timing->RefClkHz, SclkHz * 2) - 1; + + if (Div > SPI_REG_CONFIG_BAUD_MASK) { + Div =3D SPI_REG_CONFIG_BAUD_MASK; + } + + DEBUG ( + (DEBUG_INFO, "%a(): RefClk %dHz sclk %dHz Div 0x%x, actual %dHz\n= ", __func__, + Timing->RefClkHz, SclkHz, Div, Timing->RefClkHz / (2 * (Div + 1)= )) + ); + + Reg |=3D (Div << SPI_REG_CONFIG_BAUD_LSB); + MmioWrite32 (Slave->RegBase + SPI_REG_CONFIG, Reg); + + /* Configure delay timing */ + RefClkNs =3D DIV_ROUND_UP (1000000000, Timing->RefClkHz); + SclkNs =3D DIV_ROUND_UP (1000000000, SclkHz); + + if (Timing->TshslNs >=3D SclkNs + RefClkNs) { + Timing->TshslNs -=3D SclkNs + RefClkNs; + } + + if (Timing->TchshNs >=3D SclkNs + 3 * RefClkNs) { + Timing->TchshNs -=3D SclkNs + 3 * RefClkNs; + } + + Tshsl =3D DIV_ROUND_UP (Timing->TshslNs, RefClkNs); + Tchsh =3D DIV_ROUND_UP (Timing->TchshNs, RefClkNs); + Tslch =3D DIV_ROUND_UP (Timing->TslchNs, RefClkNs); + Tsd2d =3D DIV_ROUND_UP (Timing->Tsd2dNs, RefClkNs); + + Reg =3D ((Tshsl & SPI_REG_DELAY_TSHSL_MASK) + << SPI_REG_DELAY_TSHSL_LSB); + Reg |=3D ((Tchsh & SPI_REG_DELAY_TCHSH_MASK) + << SPI_REG_DELAY_TCHSH_LSB); + Reg |=3D ((Tslch & SPI_REG_DELAY_TSLCH_MASK) + << SPI_REG_DELAY_TSLCH_LSB); + Reg |=3D ((Tsd2d & SPI_REG_DELAY_TSD2D_MASK) + << SPI_REG_DELAY_TSD2D_LSB); + MmioWrite32 (Slave->RegBase + SPI_REG_DELAY, Reg); + + SpiControllerEnable (Slave->RegBase); +} + +STATIC +EFI_STATUS +SpiWaitIdle ( + IN UINT32 RegBase + ) +{ + BOOLEAN IsIdle; + UINT32 Count =3D 0; + UINT32 TimeoutMs =3D 5000000; + + do { + IsIdle =3D (BOOLEAN)((MmioRead32(RegBase + SPI_REG_CONFIG) >> + SPI_REG_CONFIG_IDLE_LSB) & 0x1); + Count =3D (IsIdle) ? (Count+1) : 0; + + /* + * Make sure the QSPI controller is in really idle + * for n period of time before proceed + */ + if (Count >=3D SPI_POLL_IDLE_RETRY) { + return EFI_SUCCESS; + } + + gBS->Stall (1); + } while (TimeoutMs); + + return EFI_TIMEOUT; +} + +STATIC +EFI_STATUS +SpiExecFlashCmd ( + IN UINT32 RegBase, + IN UINT32 Reg + ) +{ + EFI_STATUS Status; + UINT32 Retry =3D SPI_REG_RETRY; + + /* Write the CMDCTRL without start execution */ + MmioWrite32 (RegBase + SPI_REG_CMDCTRL, Reg); + /* Start execute */ + Reg |=3D SPI_REG_CMDCTRL_EXECUTE; + MmioWrite32 (RegBase + SPI_REG_CMDCTRL, Reg); + + while (Retry--) { + Reg =3D MmioRead32 (RegBase + SPI_REG_CMDCTRL); + if ((Reg & SPI_REG_CMDCTRL_INPROGRESS) =3D=3D 0) { + break; + } + gBS->Stall (1); + } + + if (!Retry) { + DEBUG ((DEBUG_ERROR, "%a(): flash command execution Timeout\n", __func= __)); + return EFI_TIMEOUT; + } + + /* Polling QSPI idle status */ + Status =3D SpiWaitIdle (RegBase); + if (EFI_ERROR (Status)) { + return EFI_TIMEOUT; + } + + return EFI_SUCCESS; +} + +/* For command RDID, RDSR. */ +EFI_STATUS +SpiCommandRead ( + IN SPI_MASTER_PROTOCOL *This, + IN SPI_DEVICE_PARAMS *Slave, + IN OUT SPI_OP_PARAMS *Cmds + ) +{ + UINT32 Reg; + UINT32 ReadLen; + EFI_STATUS Status; + SPI_MASTER *SpiMaster; + UINT32 RxLen =3D Cmds->Data.NBytes; + VOID *RxBuf =3D Cmds->Data.Buf.In; + + SpiMaster =3D SPI_MASTER_FROM_SPI_MASTER_PROTOCOL (This); + if (!EfiAtRuntime ()) { + EfiAcquireLock (&SpiMaster->Lock); + } + + if ((RxLen > SPI_STIG_DATA_LEN_MAX) || !RxBuf) { + DEBUG ((DEBUG_ERROR, "%a(): Invalid input arguments RxLen %d\n", __fun= c__, RxLen)); + Status =3D EFI_INVALID_PARAMETER; + goto Fail; + } + + Reg =3D Cmds->Cmd.OpCode << SPI_REG_CMDCTRL_OPCODE_LSB; + Reg |=3D (0x1 << SPI_REG_CMDCTRL_RD_EN_LSB); + + /* 0 means 1 byte */ + Reg |=3D (((RxLen - 1) & SPI_REG_CMDCTRL_RD_BYTES_MASK) + << SPI_REG_CMDCTRL_RD_BYTES_LSB); + Status =3D SpiExecFlashCmd (Slave->RegBase, Reg); + if (EFI_ERROR (Status)) { + goto Fail; + } + + Reg =3D MmioRead32 (Slave->RegBase + SPI_REG_CMDREADDATALOWER); + + /* Put the read value into rx_buf */ + ReadLen =3D (RxLen > 4) ? 4 : RxLen; + CopyMem (RxBuf, &Reg, ReadLen); + RxBuf +=3D ReadLen; + + if (RxLen > 4) { + Reg =3D MmioRead32 (Slave->RegBase + SPI_REG_CMDREADDATAUPPER); + + ReadLen =3D RxLen - ReadLen; + CopyMem (RxBuf, &Reg, ReadLen); + } + + if (!EfiAtRuntime ()) { + EfiReleaseLock (&SpiMaster->Lock); + } + return EFI_SUCCESS; + +Fail: + if (!EfiAtRuntime ()) { + EfiReleaseLock (&SpiMaster->Lock); + } + return Status; +} + +STATIC +EFI_STATUS +SpiGetReadSramLevel ( + IN UINT32 RegBase, + OUT UINT16 *SramLvl + ) +{ + UINT32 Reg =3D MmioRead32 (RegBase + SPI_REG_SDRAMLEVEL); + Reg >>=3D SPI_REG_SDRAMLEVEL_RD_LSB; + *SramLvl =3D (UINT16)(Reg & SPI_REG_SDRAMLEVEL_RD_MASK); + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +SpiWaitForData ( + IN UINT32 RegBase, + UINT16 *SramLvl + ) +{ + UINT32 Timeout =3D 10000; + + while (Timeout--) { + SpiGetReadSramLevel (RegBase, SramLvl); + if (SramLvl !=3D 0) { + return EFI_SUCCESS; + } + gBS->Stall (1); + } + + return EFI_TIMEOUT; +} + +STATIC +EFI_STATUS +SpiWaitForBitLe32 ( + IN INT32 Reg, + IN CONST UINT32 Mask, + IN CONST BOOLEAN Set, + IN CONST UINT32 TimeoutMs + ) +{ + UINT32 Val; + UINTN Start =3D TimeoutMs*1000; + + while(1) { + Val =3D MmioRead32 (Reg); + + if (!Set) { + Val =3D ~Val; + } + + if ((Val & Mask) =3D=3D Mask) { + return EFI_SUCCESS; + } + + if (Start =3D=3D 0) { + break; + } else { + Start--; + } + + gBS->Stall (1); + } + + DEBUG ((DEBUG_ERROR, "Timeout (Reg=3D%lx Mask=3D%x wait_set=3D%d)\n", Re= g, Mask, Set)); + + return EFI_TIMEOUT; +} + +STATIC +VOID +SpiReadByte ( + IN VOID *Addr, + IN VOID *Data, + IN UINT16 ByteLen + ) +{ + UINT8 *AddrPtr; + UINT8 *DataPtr; + + AddrPtr =3D (UINT8 *)Addr; + DataPtr =3D (UINT8 *)Data; + + while (ByteLen) { + *DataPtr =3D *AddrPtr; + DataPtr++; + ByteLen--; + } +} + +STATIC +VOID +SpiReadLong ( + VOID *Addr, + VOID *Data, + UINT16 LongLen + ) +{ + UINT32 *AddrPtr; + UINT32 *DataPtr; + + AddrPtr =3D (UINT32 *)Addr; + DataPtr =3D (UINT32 *)Data; + + while (LongLen) { + *DataPtr =3D *AddrPtr; + DataPtr++; + LongLen--; + } +} + +EFI_STATUS +SpiDataRead ( + IN SPI_MASTER_PROTOCOL *This, + IN SPI_DEVICE_PARAMS *Slave, + IN OUT SPI_OP_PARAMS *Cmds + ) +{ + SPI_MASTER *SpiMaster; + UINT8 *RxBuf =3D Cmds->Data.Buf.In; + UINT32 Remaining =3D Cmds->Data.NBytes; + UINT16 BytesToRead =3D 0; + EFI_STATUS Status; + UINT32 Reg; + + SpiMaster =3D SPI_MASTER_FROM_SPI_MASTER_PROTOCOL (This); + if (!EfiAtRuntime ()) { + EfiAcquireLock (&SpiMaster->Lock); + } + + if (!Cmds->Addr.NBytes) { + Status =3D EFI_ABORTED; + goto Fail; + } + + /* Setup the indirect trigger start address */ + MmioWrite32 (Slave->RegBase + SPI_REG_INDIRECTRDSTARTADDR, Cmds->Addr.Va= l); + + /* Register command */ + Reg =3D Cmds->Cmd.OpCode << SPI_REG_RD_INSTR_OPCODE_LSB; + MmioWrite32 (Slave->RegBase + SPI_REG_RD_INSTR, Reg); + + /* Set device size */ + Reg =3D MmioRead32 (Slave->RegBase + SPI_REG_SIZE); + Reg &=3D ~SPI_REG_SIZE_ADDRESS_MASK; + Reg |=3D (Cmds->Addr.NBytes - 1); + MmioWrite32 (Slave->RegBase + SPI_REG_SIZE, Reg); + + /* Setup indirect read bytes */ + MmioWrite32 (Slave->RegBase + SPI_REG_INDIRECTRDBYTES, Remaining); + + /* Start the indirect read transfer */ + MmioWrite32 (Slave->RegBase + SPI_REG_INDIRECTRD, SPI_REG_INDIRECTRD_STA= RT); + + while (Remaining > 0) { + Status =3D SpiWaitForData (Slave->RegBase, &BytesToRead); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "%a(): Indirect write timed out\n", __func__)); + goto Fail; + } + + while (BytesToRead !=3D 0) { + BytesToRead *=3D Slave->FifoWidth; + if (BytesToRead > Remaining) { + BytesToRead =3D Remaining; + } + + if (((UINTN)RxBuf % 4) || (BytesToRead % 4)) { + SpiReadByte (Slave->AhbBase, RxBuf, BytesToRead); + } else { + SpiReadLong (Slave->AhbBase, RxBuf, BytesToRead >> 2); + } + + RxBuf +=3D BytesToRead; + Remaining -=3D BytesToRead; + SpiGetReadSramLevel (Slave->RegBase, &BytesToRead); + } + } + + /* Check indirect done status */ + Status =3D SpiWaitForBitLe32 ( + Slave->RegBase + SPI_REG_INDIRECTRD, + SPI_REG_INDIRECTRD_DONE, + 1, + 10 + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Indirect read completion error\n")); + goto Fail; + } + + /* Clear indirect completion status */ + MmioWrite32 (Slave->RegBase + SPI_REG_INDIRECTRD, SPI_REG_INDIRECTRD_DON= E); + + if (!EfiAtRuntime ()) { + EfiReleaseLock (&SpiMaster->Lock); + } + return EFI_SUCCESS; + +Fail: + MmioWrite32 (Slave->RegBase + SPI_REG_INDIRECTRD, SPI_REG_INDIRECTRD_CAN= CEL); + if (!EfiAtRuntime ()) { + EfiReleaseLock (&SpiMaster->Lock); + } + return EFI_ABORTED; +} + +/* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */ +EFI_STATUS +SpiCommandWrite ( + IN SPI_MASTER_PROTOCOL *This, + IN SPI_DEVICE_PARAMS *Slave, + IN OUT SPI_OP_PARAMS *Cmds + ) +{ + UINT32 Reg; + UINT32 WriteData; + UINT32 WriteLen; + SPI_MASTER *SpiMaster; + UINT32 TxLen =3D Cmds->Data.NBytes; + CONST VOID *TxBuf =3D Cmds->Data.Buf.Out; + UINT32 Addr; + EFI_STATUS Status; + + SpiMaster =3D SPI_MASTER_FROM_SPI_MASTER_PROTOCOL (This); + if (!EfiAtRuntime ()) { + EfiAcquireLock (&SpiMaster->Lock); + } + + /* Reorder address to SPI bus order if only transferring address */ + if (!TxLen) { + Addr =3D SwapBytes32 (Cmds->Addr.Val); + if (Cmds->Addr.NBytes =3D=3D 3) { + Addr >>=3D 8; + } + + TxBuf =3D &Addr; + TxLen =3D Cmds->Addr.NBytes; + } + + if (TxLen > SPI_STIG_DATA_LEN_MAX) { + DEBUG ((DEBUG_ERROR, "QSPI: Invalid input arguments TxLen %d\n", TxLen= )); + Status =3D EFI_INVALID_PARAMETER; + goto Fail; + } + + Reg =3D Cmds->Cmd.OpCode << SPI_REG_CMDCTRL_OPCODE_LSB; + + if (TxLen) { + Reg |=3D (0x1 << SPI_REG_CMDCTRL_WR_EN_LSB); + Reg |=3D ((TxLen - 1) & SPI_REG_CMDCTRL_WR_BYTES_MASK) + << SPI_REG_CMDCTRL_WR_BYTES_LSB; + + WriteLen =3D TxLen > 4 ? 4 : TxLen; + CopyMem (&WriteData, TxBuf, WriteLen); + MmioWrite32 (Slave->RegBase + SPI_REG_CMDWRITEDATALOWER, WriteData); + + if (TxLen > 4) { + TxBuf +=3D WriteLen; + WriteLen =3D TxLen - WriteLen; + CopyMem (&WriteData, TxBuf, WriteLen); + MmioWrite32 (Slave->RegBase + SPI_REG_CMDWRITEDATAUPPER, WriteData); + } + } + + Status =3D SpiExecFlashCmd (Slave->RegBase, Reg); + if (EFI_ERROR (Status)) { + goto Fail; + } + + if (!EfiAtRuntime ()) { + EfiReleaseLock (&SpiMaster->Lock); + } + return EFI_SUCCESS; + +Fail: + if (!EfiAtRuntime ()) { + EfiReleaseLock (&SpiMaster->Lock); + } + return Status; +} + +STATIC +VOID +SpiDelayNanoSec ( + IN UINTN nsec + ) +{ + UINT32 Timeout =3D DIV_ROUND_UP (nsec, 1000); + + do { + Timeout--; + gBS->Stall (1); + } while (Timeout); +} + +STATIC +VOID +SpiWriteLong ( + IN VOID *Addr, + IN CONST VOID *Data, + IN INTN LongLen + ) +{ + UINT32 *AddrPtr; + UINT32 *DataPtr; + + AddrPtr =3D (UINT32 *)Addr; + DataPtr =3D (UINT32 *)Data; + + while (LongLen) { + *AddrPtr =3D *DataPtr; + DataPtr++; + LongLen--; + } +} + +STATIC +VOID +SpiWriteByte ( + IN VOID *Addr, + IN CONST VOID *Data, + IN INTN ByteLen + ) +{ + UINT8 *AddrPtr; + UINT8 *DataPtr; + + AddrPtr =3D (UINT8 *)Addr; + DataPtr =3D (UINT8 *)Data; + + while (ByteLen) { + *AddrPtr =3D *DataPtr; + DataPtr++; + ByteLen--; + } +} + +EFI_STATUS +SpiDataWrite ( + IN SPI_MASTER_PROTOCOL *This, + IN SPI_DEVICE_PARAMS *Slave, + IN OUT SPI_OP_PARAMS *Cmds + ) +{ + UINT32 Reg; + SPI_MASTER *SpiMaster; + UINT32 PageSize =3D Slave->Info->PageSize; + UINT32 Remaining =3D Cmds->Data.NBytes; + CONST UINT8 *TxBuf =3D Cmds->Data.Buf.Out; + UINT32 WriteBytes; + EFI_STATUS Status; + + SpiMaster =3D SPI_MASTER_FROM_SPI_MASTER_PROTOCOL (This); + if (!EfiAtRuntime ()) { + EfiAcquireLock (&SpiMaster->Lock); + } + + if (!Cmds->Addr.NBytes) { + return EFI_ABORTED; + } + + /* Write opcode to write instruction register */ + Reg =3D Cmds->Cmd.OpCode << SPI_REG_WR_INSTR_OPCODE_LSB; + MmioWrite32 (Slave->RegBase + SPI_REG_WR_INSTR, Reg); + + /* Set buffer address */ + MmioWrite32 (Slave->RegBase + SPI_REG_INDIRECTWRSTARTADDR, Cmds->Addr.Va= l); + + /* Configure device size */ + Reg =3D MmioRead32 (Slave->RegBase + SPI_REG_SIZE); + Reg &=3D ~SPI_REG_SIZE_ADDRESS_MASK; + Reg |=3D (Cmds->Addr.NBytes - 1); + MmioWrite32 (Slave->RegBase + SPI_REG_SIZE, Reg); + + /* Configure the indirect read transfer bytes */ + MmioWrite32 (Slave->RegBase + SPI_REG_INDIRECTWRBYTES, Remaining); + + /* Start the indirect write transfer */ + MmioWrite32 (Slave->RegBase + SPI_REG_INDIRECTWR, SPI_REG_INDIRECTWR_STA= RT); + + /* Delay is required for QSPI module to synchronized internally */ + SpiDelayNanoSec (Slave->WriteDelay); + + while (Remaining > 0) { + WriteBytes =3D Remaining > PageSize ? PageSize : Remaining; + SpiWriteLong (Slave->AhbBase, TxBuf, WriteBytes >> 2); + if (WriteBytes % 4) { + SpiWriteByte ( + Slave->AhbBase, + TxBuf + ROUND_DOWN (WriteBytes, 4), + WriteBytes % 4 + ); + } + + Status =3D SpiWaitForBitLe32 ( + Slave->RegBase + SPI_REG_SDRAMLEVEL, + SPI_REG_SDRAMLEVEL_WR_MASK << + SPI_REG_SDRAMLEVEL_WR_LSB, + 0, + 10 + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(): Indirect write timed out (%d)\n", __func= __, Status)); + goto FailWrite; + } + + TxBuf +=3D WriteBytes; + Remaining -=3D WriteBytes; + } + + /* Check indirect done status */ + Status =3D SpiWaitForBitLe32 ( + Slave->RegBase + SPI_REG_INDIRECTWR, + SPI_REG_INDIRECTWR_DONE, + 1, + 10 + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Indirect write completion error (%d)\n", Status)= ); + goto FailWrite; + } + + /* Clear indirect completion status */ + MmioWrite32 (Slave->RegBase + SPI_REG_INDIRECTWR, SPI_REG_INDIRECTWR_DON= E); + if (!EfiAtRuntime ()) { + EfiReleaseLock (&SpiMaster->Lock); + } + return EFI_SUCCESS; + +FailWrite: + MmioWrite32 (Slave->RegBase + SPI_REG_INDIRECTWR, SPI_REG_INDIRECTWR_CAN= CEL); + if (!EfiAtRuntime ()) { + EfiReleaseLock (&SpiMaster->Lock); + } + return Status; +} + +STATIC +VOID +SpiConfigGetDataCapture ( + IN UINT32 RegBase, + IN UINT32 ByPass, + IN UINT32 Delay + ) +{ + UINT32 Reg; + + SpiControllerDisable (RegBase); + + Reg =3D MmioRead32 (RegBase + SPI_REG_RD_DATA_CAPTURE); + + if (ByPass) { + Reg |=3D SPI_REG_RD_DATA_CAPTURE_BYPASS; + } else { + Reg &=3D ~SPI_REG_RD_DATA_CAPTURE_BYPASS; + } + + Reg &=3D ~(SPI_REG_RD_DATA_CAPTURE_DELAY_MASK + << SPI_REG_RD_DATA_CAPTURE_DELAY_LSB); + + Reg |=3D (Delay & SPI_REG_RD_DATA_CAPTURE_DELAY_MASK) + << SPI_REG_RD_DATA_CAPTURE_DELAY_LSB; + + MmioWrite32 (RegBase + SPI_REG_RD_DATA_CAPTURE, Reg); + + SpiControllerEnable (RegBase); +} + +STATIC +EFI_STATUS +SpiSpeedCalibration ( + IN SPI_MASTER_PROTOCOL *This, + IN SPI_DEVICE_PARAMS *Slave, + IN SPI_TIMING_PARAMS *Timing + ) +{ + UINT8 IdLen =3D 3; + UINT32 IdInit =3D 0, IdCali =3D 0; + INTN RangeLow =3D -1, RangeHigh =3D -1; + SPI_OP_PARAMS CmdsInitialId =3D SPI_READID_OP ((UINT8 *)&IdInit, IdLen); + SPI_OP_PARAMS CmdsCalibrateId =3D SPI_READID_OP ((UINT8 *)&IdCali, IdLe= n); + EFI_STATUS Status; + + /* Start calibration with slowest clock speed at 1 MHz */ + SpiWriteSpeed (Slave, SPI_MIN_HZ, Timing); + + /* Set the read data capture delay register to 0 */ + SpiConfigGetDataCapture (Slave->RegBase, 1, 0); + + /* Get flash ID value as reference */ + Status =3D SpiCommandRead (This, Slave, &CmdsInitialId); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Spi: Calibration failed (read id)\n")); + return EFI_ABORTED; + } + + /* Use the input speed */ + SpiWriteSpeed (Slave, SPI_MAX_HZ, Timing); + + /* Find high and low range */ + for (UINT8 i =3D 0; i < SPI_READ_CAPTURE_MAX_DELAY; i++) { + /* Change the read data capture delay register */ + SpiConfigGetDataCapture (Slave->RegBase, 1, i); + + /* Read flash ID for comparison later */ + Status =3D SpiCommandRead (This, Slave, &CmdsCalibrateId); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Spi: Calibration failed (read)\n")); + return EFI_ABORTED; + } + + /* Verify low range */ + if ((RangeLow =3D=3D -1) && (IdCali =3D=3D IdInit)) { + RangeLow =3D i; + continue; + } + + /* Verify high range */ + if ((RangeLow !=3D -1) && (IdCali !=3D IdInit)) { + RangeHigh =3D i - 1; + break; + } + + RangeHigh =3D i; + } + + if (RangeLow =3D=3D -1) { + DEBUG ((DEBUG_ERROR, "Spi: Calibration failed\n")); + return EFI_ABORTED; + } + + /* + * Set the final value for read data capture delay register based + * on the calibrated value + */ + SpiConfigGetDataCapture (Slave->RegBase, 1, (RangeHigh + RangeLow) / 2); + DEBUG ( + (DEBUG_INFO, "Spi: Read data capture delay calibrated to %d (%d -= %d)\n", + (RangeHigh + RangeLow) / 2, RangeLow, RangeHigh) + ); + + return EFI_SUCCESS; +} + +EFI_STATUS +SpiSetupDevice ( + IN SPI_MASTER_PROTOCOL *This, + OUT SPI_DEVICE_PARAMS *Slave + ) +{ + SPI_TIMING_PARAMS *Timing; + EFI_STATUS Status; + + if (!Slave) { + Slave =3D AllocateZeroPool (sizeof (SPI_DEVICE_PARAMS)); + if (Slave =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a(): Cannot allocate memory Slave\n", __func_= _)); + Status =3D EFI_OUT_OF_RESOURCES; + goto Fail; + } + } + + if (!Slave->Info) { + Slave->Info =3D AllocateZeroPool (sizeof (NOR_FLASH_INFO)); + if (Slave->Info =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a(): Cannot allocate memory Slave->Info\n", _= _func__)); + Status =3D EFI_OUT_OF_RESOURCES; + goto Fail; + } + } + + Timing =3D AllocateZeroPool (sizeof (SPI_TIMING_PARAMS)); + if (Timing =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a(): Cannot allocate memory Timing\n", __func__= )); + FreePool(Slave); + Status =3D EFI_OUT_OF_RESOURCES; + goto Fail; + } + + Slave->RegBase =3D PcdGet32 (PcdSpiFlashRegBase); + Slave->AhbBase =3D (VOID *)(UINTN)PcdGet64 (PcdSpiFlashAhbBase); + Slave->FifoWidth =3D PcdGet8 (PcdSpiFlashFifoWidth); + Timing->RefClkHz =3D PcdGet32 (PcdSpiFlashRefClkHz); + Timing->TshslNs =3D PcdGet32 (PcdSpiFlashTshslNs); + Timing->Tsd2dNs =3D PcdGet32 (PcdSpiFlashTsd2dNs); + Timing->TchshNs =3D PcdGet32 (PcdSpiFlashTchshNs); + Timing->TslchNs =3D PcdGet32 (PcdSpiFlashTslchNs); + + Slave->WriteDelay =3D 50 * DIV_ROUND_UP (NSEC_PER_SEC, Timing->RefClkHz); + + Status =3D SpiSpeedCalibration (This, Slave, Timing); + if (EFI_ERROR (Status)) { + goto Fail; + } + + FreePool(Timing); + return EFI_SUCCESS; + +Fail: + FreePool(Slave); + FreePool(Timing); + return Status; +} + +EFI_STATUS +SpiFreeDevice ( + IN SPI_DEVICE_PARAMS *Slave + ) +{ + FreePool (Slave); + + return EFI_SUCCESS; +} + +EFI_STATUS +SpiMasterInitProtocol ( + IN SPI_MASTER_PROTOCOL *SpiMasterProtocol + ) +{ + SpiMasterProtocol->SetupDevice =3D SpiSetupDevice; + SpiMasterProtocol->FreeDevice =3D SpiFreeDevice; + SpiMasterProtocol->CmdRead =3D SpiCommandRead; + SpiMasterProtocol->DataRead =3D SpiDataRead; + SpiMasterProtocol->CmdWrite =3D SpiCommandWrite; + SpiMasterProtocol->DataWrite =3D SpiDataWrite; + + return EFI_SUCCESS; +} + +EFI_STATUS +SpiEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + mSpiMasterInstance =3D AllocateRuntimeZeroPool (sizeof (SPI_MASTER)); + if (mSpiMasterInstance =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + EfiInitializeLock (&mSpiMasterInstance->Lock, TPL_NOTIFY); + + SpiMasterInitProtocol (&mSpiMasterInstance->SpiMasterProtocol); + + mSpiMasterInstance->Signature =3D SPI_MASTER_SIGNATURE; + + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &(mSpiMasterInstance->H= andle), + &gJH7110SpiMasterProtoc= olGuid, + &(mSpiMasterInstance->S= piMasterProtocol), + NULL + ); + if (EFI_ERROR (Status)) { + FreePool (mSpiMasterInstance); + return EFI_DEVICE_ERROR; + } + + return EFI_SUCCESS; +} diff --git a/Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiDxe/Spi= Dxe.h b/Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiDxe/SpiDxe.h new file mode 100644 index 000000000000..804ee29c5ff1 --- /dev/null +++ b/Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiDxe/SpiDxe.h @@ -0,0 +1,188 @@ +/** @file + * + * Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.=
+ * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef __SPI_DXE_H__ +#define __SPI_DXE_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define SPI_MASTER_SIGNATURE SIGNATURE_32 ('M', 'S', = 'P', 'I') +#define SPI_MASTER_FROM_SPI_MASTER_PROTOCOL(a) CR (a, SPI_MASTER, SpiMast= erProtocol, SPI_MASTER_SIGNATURE) + +#ifndef BIT +#define BIT(nr) (1 << (nr)) +#endif + +#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) +#define ROUND_DOWN(x, y) (\ +{ \ + typeof(x) __x =3D (x); \ + __x - (__x % (y)); \ +} \ +) +#define NSEC_PER_SEC 1000000000L + +/* Configs */ +#define SPI_READ_CAPTURE_MAX_DELAY 16 +#define SPI_REG_RETRY 10000 +#define SPI_POLL_IDLE_RETRY 3 +#define SPI_STIG_DATA_LEN_MAX 8 +#define SPI_MIN_HZ 1000000 +#define SPI_MAX_HZ 100000000 + +/* +* QSPI controller's config and status register (offset from QSPI_BASE) +*/ +#define SPI_REG_CONFIG 0x00 +#define SPI_REG_CONFIG_ENABLE BIT(0) +#define SPI_REG_CONFIG_CLK_POL BIT(1) +#define SPI_REG_CONFIG_CLK_PHA BIT(2) +#define SPI_REG_CONFIG_DIRECT BIT(7) +#define SPI_REG_CONFIG_DECODE BIT(9) +#define SPI_REG_CONFIG_XIP_IMM BIT(18) +#define SPI_REG_CONFIG_CHIPSELECT_LSB 10 +#define SPI_REG_CONFIG_BAUD_LSB 19 +#define SPI_REG_CONFIG_DTR_PROTO BIT(24) +#define SPI_REG_CONFIG_DUAL_OPCODE BIT(30) +#define SPI_REG_CONFIG_IDLE_LSB 31 +#define SPI_REG_CONFIG_CHIPSELECT_MASK 0xF +#define SPI_REG_CONFIG_BAUD_MASK 0xF + +#define SPI_REG_RD_INSTR 0x04 +#define SPI_REG_RD_INSTR_OPCODE_LSB 0 +#define SPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 +#define SPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 +#define SPI_REG_RD_INSTR_TYPE_DATA_LSB 16 +#define SPI_REG_RD_INSTR_MODE_EN_LSB 20 +#define SPI_REG_RD_INSTR_DUMMY_LSB 24 +#define SPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 +#define SPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 +#define SPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 +#define SPI_REG_RD_INSTR_DUMMY_MASK 0x1F + +#define SPI_REG_WR_INSTR 0x08 +#define SPI_REG_WR_INSTR_OPCODE_LSB 0 +#define SPI_REG_WR_INSTR_TYPE_ADDR_LSB 12 +#define SPI_REG_WR_INSTR_TYPE_DATA_LSB 16 + +#define SPI_REG_DELAY 0x0C +#define SPI_REG_DELAY_TSLCH_LSB 0 +#define SPI_REG_DELAY_TCHSH_LSB 8 +#define SPI_REG_DELAY_TSD2D_LSB 16 +#define SPI_REG_DELAY_TSHSL_LSB 24 +#define SPI_REG_DELAY_TSLCH_MASK 0xFF +#define SPI_REG_DELAY_TCHSH_MASK 0xFF +#define SPI_REG_DELAY_TSD2D_MASK 0xFF +#define SPI_REG_DELAY_TSHSL_MASK 0xFF + +#define SPI_REG_RD_DATA_CAPTURE 0x10 +#define SPI_REG_RD_DATA_CAPTURE_BYPASS BIT(0) +#define SPI_REG_RD_DATA_CAPTURE_DELAY_LSB 1 +#define SPI_REG_RD_DATA_CAPTURE_DELAY_MASK 0xF + +#define SPI_REG_SIZE 0x14 +#define SPI_REG_SIZE_ADDRESS_LSB 0 +#define SPI_REG_SIZE_PAGE_LSB 4 +#define SPI_REG_SIZE_BLOCK_LSB 16 +#define SPI_REG_SIZE_ADDRESS_MASK 0xF +#define SPI_REG_SIZE_PAGE_MASK 0xFFF +#define SPI_REG_SIZE_BLOCK_MASK 0x3F + +#define SPI_REG_SRAMPARTITION 0x18 +#define SPI_REG_INDIRECTTRIGGER 0x1C + +#define SPI_REG_REMAP 0x24 +#define SPI_REG_MODE_BIT 0x28 + +#define SPI_REG_SDRAMLEVEL 0x2C +#define SPI_REG_SDRAMLEVEL_RD_LSB 0 +#define SPI_REG_SDRAMLEVEL_WR_LSB 16 +#define SPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF +#define SPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF + +#define SPI_REG_WR_COMPLETION_CTRL 0x38 +#define SPI_REG_WR_DISABLE_AUTO_POLL BIT(14) + +#define SPI_REG_IRQSTATUS 0x40 +#define SPI_REG_IRQMASK 0x44 + +#define SPI_REG_INDIRECTRD 0x60 +#define SPI_REG_INDIRECTRD_START BIT(0) +#define SPI_REG_INDIRECTRD_CANCEL BIT(1) +#define SPI_REG_INDIRECTRD_INPROGRESS BIT(2) +#define SPI_REG_INDIRECTRD_DONE BIT(5) + +#define SPI_REG_INDIRECTRDWATERMARK 0x64 +#define SPI_REG_INDIRECTRDSTARTADDR 0x68 +#define SPI_REG_INDIRECTRDBYTES 0x6C + +#define SPI_REG_CMDCTRL 0x90 +#define SPI_REG_CMDCTRL_EXECUTE BIT(0) +#define SPI_REG_CMDCTRL_INPROGRESS BIT(1) +#define SPI_REG_CMDCTRL_DUMMY_LSB 7 +#define SPI_REG_CMDCTRL_WR_BYTES_LSB 12 +#define SPI_REG_CMDCTRL_WR_EN_LSB 15 +#define SPI_REG_CMDCTRL_ADD_BYTES_LSB 16 +#define SPI_REG_CMDCTRL_ADDR_EN_LSB 19 +#define SPI_REG_CMDCTRL_RD_BYTES_LSB 20 +#define SPI_REG_CMDCTRL_RD_EN_LSB 23 +#define SPI_REG_CMDCTRL_OPCODE_LSB 24 +#define SPI_REG_CMDCTRL_DUMMY_MASK 0x1F +#define SPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 +#define SPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 +#define SPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 +#define SPI_REG_CMDCTRL_OPCODE_MASK 0xFF + +#define SPI_REG_INDIRECTWR 0x70 +#define SPI_REG_INDIRECTWR_START BIT(0) +#define SPI_REG_INDIRECTWR_CANCEL BIT(1) +#define SPI_REG_INDIRECTWR_INPROGRESS BIT(2) +#define SPI_REG_INDIRECTWR_DONE BIT(5) + +#define SPI_REG_INDIRECTWRWATERMARK 0x74 +#define SPI_REG_INDIRECTWRSTARTADDR 0x78 +#define SPI_REG_INDIRECTWRBYTES 0x7C + +#define SPI_REG_CMDADDRESS 0x94 +#define SPI_REG_CMDREADDATALOWER 0xA0 +#define SPI_REG_CMDREADDATAUPPER 0xA4 +#define SPI_REG_CMDWRITEDATALOWER 0xA8 +#define SPI_REG_CMDWRITEDATAUPPER 0xAC + +#define SPI_REG_OP_EXT_LOWER 0xE0 +#define SPI_REG_OP_EXT_READ_LSB 24 +#define SPI_REG_OP_EXT_WRITE_LSB 16 +#define SPI_REG_OP_EXT_STIG_LSB 0 + +typedef struct { + SPI_MASTER_PROTOCOL SpiMasterProtocol; + UINTN Signature; + EFI_HANDLE Handle; + EFI_LOCK Lock; +} SPI_MASTER; + +typedef struct { + UINT32 RefClkHz; + UINT32 TshslNs; + UINT32 TchshNs; + UINT32 TslchNs; + UINT32 Tsd2dNs; +}SPI_TIMING_PARAMS; + +#endif //__SPI_DXE_H__ diff --git a/Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiDxe/Spi= Dxe.inf b/Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiDxe/SpiDxe= .inf new file mode 100644 index 000000000000..ed3f639346b2 --- /dev/null +++ b/Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiDxe/SpiDxe.inf @@ -0,0 +1,52 @@ +## @file +# +# Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<= BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SpiDxe + FILE_GUID =3D 2FBD9E55-9BC7-4EEF-BF93-0D5582FE647B + MODULE_TYPE =3D DXE_RUNTIME_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SpiEntryPoint + +[Sources] + SpiDxe.c + SpiDxe.h + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Silicon/StarFive/JH7110Pkg/JH7110Pkg.dec + +[LibraryClasses] + DebugLib + DxeServicesTableLib + IoLib + MemoryAllocationLib + NorFlashInfoLib + TimerLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + UefiRuntimeLib + +[FixedPcd] + gJH7110TokenSpaceGuid.PcdSpiFlashRegBase + gJH7110TokenSpaceGuid.PcdSpiFlashAhbBase + gJH7110TokenSpaceGuid.PcdSpiFlashFifoWidth + gJH7110TokenSpaceGuid.PcdSpiFlashRefClkHz + gJH7110TokenSpaceGuid.PcdSpiFlashTshslNs + gJH7110TokenSpaceGuid.PcdSpiFlashTsd2dNs + gJH7110TokenSpaceGuid.PcdSpiFlashTchshNs + gJH7110TokenSpaceGuid.PcdSpiFlashTslchNs + +[Protocols] + gJH7110SpiMasterProtocolGuid + +[Depex] + TRUE diff --git a/Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiFlashDx= e/SpiFlashDxe.c b/Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiFl= ashDxe/SpiFlashDxe.c new file mode 100755 index 000000000000..cd508e53eb06 --- /dev/null +++ b/Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiFlashDxe/SpiFl= ashDxe.c @@ -0,0 +1,571 @@ +/** @file + * + * Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.=
+ * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include "SpiFlashDxe.h" + +SPI_MASTER_PROTOCOL *SpiMasterProtocol; +SPI_FLASH_INSTANCE *mSpiFlashInstance; + +STATIC +EFI_STATUS +SpiFlashWriteEnableCmd ( + IN SPI_DEVICE_PARAMS *Slave + ) +{ + EFI_STATUS Status; + SPI_OP_PARAMS Op =3D SPI_WRITE_EN_OP(); + + /* Send write enable command */ + Status =3D SpiMasterProtocol->CmdWrite (SpiMasterProtocol, Slave, &Op); + + return Status; +} + +STATIC +EFI_STATUS +SpiFlashWriteDisableCmd ( + IN SPI_DEVICE_PARAMS *Slave + ) +{ + EFI_STATUS Status; + SPI_OP_PARAMS Op =3D SPI_WRITE_DIS_OP(); + + /* Send write disable command */ + Status =3D SpiMasterProtocol->CmdWrite (SpiMasterProtocol, Slave, &Op); + + return Status; +} + +STATIC +EFI_STATUS +SpiFlashPoll ( + IN SPI_DEVICE_PARAMS *Slave +) +{ + EFI_STATUS Status; + UINT16 State; + UINT32 Counter =3D 0xFFFFF; + UINT8 ReadLength =3D 2; + + SPI_OP_PARAMS OpRdSts =3D SPI_OP ( + SPI_OP_CMD (SPI_CMD_READ_STATUS), + SPI_OP_NO_ADDR, + SPI_OP_NO_DUMMY, + SPI_OP_DATA_IN (ReadLength, (VOID *)&Sta= te) + ); + + Status =3D SpiMasterProtocol->CmdRead (SpiMasterProtocol, Slave, &OpRdSt= s); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(): Spi error while reading status\n", __func_= _)); + return Status; + } + + do { + Status =3D SpiMasterProtocol->CmdRead (SpiMasterProtocol, Slave, &OpRd= Sts); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(): Spi error while reading status\n", __fun= c__)); + return Status; + } + + Counter--; + if (!(State & STATUS_REG_POLL_WIP_MSK)) { + break; + } + } while (Counter > 0); + + if (Counter =3D=3D 0) { + DEBUG ((DEBUG_ERROR, "%a(): Timeout while writing to spi flash\n", __f= unc__)); + return EFI_TIMEOUT; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +SpiFlashErase ( + IN SPI_DEVICE_PARAMS *Slave, + IN UINT32 Offset, + IN UINTN Length + ) +{ + EFI_STATUS Status; + UINT32 EraseAddr; + UINTN EraseSize; + UINT8 EraseCmd; + + if (Slave->Info->Flags & NOR_FLASH_ERASE_4K) { + EraseCmd =3D SPI_CMD_ERASE_4K; + EraseSize =3D SIZE_4KB; + } else if (Slave->Info->Flags & NOR_FLASH_ERASE_32K) { + EraseCmd =3D SPI_CMD_ERASE_32K; + EraseSize =3D SIZE_32KB; + } else { + EraseCmd =3D SPI_CMD_ERASE_64K; + EraseSize =3D Slave->Info->SectorSize; + } + + /* Verify input parameters */ + if (Offset % EraseSize || Length % EraseSize) { + DEBUG ( + (DEBUG_ERROR, "%a(): Either erase offset or length " + "is not multiple of erase size\n, __func__") + ); + return EFI_DEVICE_ERROR; + } + + Status =3D SpiFlashWriteEnableCmd (Slave); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(): Error while setting write_enable\n", __fun= c__)); + return Status; + } + + while (Length) { + EraseAddr =3D Offset; + + SPI_OP_PARAMS OpErase =3D SPI_OP ( + SPI_OP_CMD (EraseCmd), + SPI_OP_ADDR (3, EraseAddr), + SPI_OP_NO_DUMMY, + SPI_OP_NO_DATA + ); + + Status =3D SpiMasterProtocol->CmdWrite (SpiMasterProtocol, Slave, &OpE= rase); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(): Spi erase fail\n", __func__)); + return Status; + } + + Status =3D SpiFlashPoll(Slave); + if (EFI_ERROR (Status)) { + return Status; + } + + Offset +=3D EraseSize; + Length -=3D EraseSize; + } + + Status =3D SpiFlashWriteDisableCmd (Slave); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(): Error while setting write_disable\n", __fu= nc__)); + return Status; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +SpiFlashRead ( + IN SPI_DEVICE_PARAMS *Slave, + IN UINT32 Offset, + IN UINTN Length, + OUT VOID *Buffer + ) +{ + EFI_STATUS Status; + UINTN ReadAddr, ReadLength, RemainLength; + UINT32 FlashSize; + + FlashSize =3D Slave->Info->PageSize * Slave->Info->SectorSize; + + /* Current handling is only limit for single flash Bank */ + while (Length) { + ReadAddr =3D Offset; + + RemainLength =3D (FlashSize - Offset); + if (Length < RemainLength) { + ReadLength =3D Length; + } else { + ReadLength =3D RemainLength; + } + + /* Send read command */ + SPI_OP_PARAMS OpRead =3D SPI_OP ( + SPI_OP_CMD (SPI_CMD_READ_DATA), + SPI_OP_ADDR (Slave->AddrSize, ReadAddr), + SPI_OP_NO_DUMMY, + SPI_OP_DATA_IN (ReadLength, Buffer) + ); + + Status =3D SpiMasterProtocol->DataRead (SpiMasterProtocol, Slave, &OpR= ead); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(): Spi error while reading data\n", __func_= _)); + return Status; + } + + Offset +=3D ReadLength; + Length -=3D ReadLength; + Buffer =3D (VOID *)((UINTN)Buffer + ReadLength); + } + + return EFI_SUCCESS; +} + +EFI_STATUS +SpiFlashWrite ( + IN SPI_DEVICE_PARAMS *Slave, + IN UINT32 Offset, + IN UINTN Length, + IN VOID *Buffer + ) +{ + EFI_STATUS Status; + UINTN ByteAddr, ChunkLength, ActualIndex, PageSize; + UINT32 WriteAddr; + + PageSize =3D Slave->Info->PageSize; + + Status =3D SpiFlashWriteEnableCmd (Slave); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(): Error while setting write enable\n", __fun= c__)); + return Status; + } + + for (ActualIndex =3D 0; ActualIndex < Length; ActualIndex +=3D ChunkLeng= th) { + WriteAddr =3D Offset; + + ByteAddr =3D Offset % PageSize; + ChunkLength =3D MIN (Length - ActualIndex, (UINT64)(PageSize - ByteAdd= r)); + + SPI_OP_PARAMS OpPgProg =3D SPI_OP ( + SPI_OP_CMD (SPI_CMD_PAGE_PROGRAM), + SPI_OP_ADDR (3, WriteAddr), + SPI_OP_NO_DUMMY, + SPI_OP_DATA_OUT (ChunkLength, (VOID = *)((UINTN)Buffer + ActualIndex)) + ); + + Status =3D SpiMasterProtocol->DataWrite (SpiMasterProtocol, Slave, &Op= PgProg); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(): Error while programming write address\n"= , __func__)); + return Status; + } + + Status =3D SpiFlashPoll(Slave); + if (EFI_ERROR (Status)) { + return Status; + } + + Offset +=3D ChunkLength; + } + + Status =3D SpiFlashWriteDisableCmd (Slave); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(): Error while setting write disable\n", __fu= nc__)); + return Status; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +SpiFlashUpdateBlock ( + IN SPI_DEVICE_PARAMS *Slave, + IN UINT32 Offset, + IN UINTN ToUpdate, + IN UINT8 *Buffer, + IN UINT8 *TmpBuf, + IN UINTN EraseSize + ) +{ + EFI_STATUS Status; + + /* Read backup */ + Status =3D SpiFlashRead (Slave, Offset, EraseSize, TmpBuf); + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_ERROR, "%a(): Update: Error while reading old data\n", = __func__)); + return Status; + } + + /* Erase entire sector */ + Status =3D SpiFlashErase (Slave, Offset, EraseSize); + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_ERROR, "%a(): Update: Error while erasing block\n", __f= unc__)); + return Status; + } + + /* Write new data */ + SpiFlashWrite (Slave, Offset, ToUpdate, Buffer); + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_ERROR, "%a(): Update: Error while writing new data\n", = __func__)); + return Status; + } + + /* Write backup */ + if (ToUpdate !=3D EraseSize) { + Status =3D SpiFlashWrite (Slave, Offset + ToUpdate, EraseSize - ToUpda= te, + &TmpBuf[ToUpdate]); + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_ERROR, "%a(): Update: Error while writing backup\n", __= func__)); + return Status; + } + } + + return EFI_SUCCESS; +} + +EFI_STATUS +SpiFlashUpdate ( + IN SPI_DEVICE_PARAMS *Slave, + IN UINT32 Offset, + IN UINTN ByteCount, + IN UINT8 *Buffer + ) +{ + EFI_STATUS Status; + UINT64 SectorSize, ToUpdate, Scale =3D 1; + UINT8 *TmpBuf, *End; + + SectorSize =3D Slave->Info->SectorSize; + + End =3D Buffer + ByteCount; + + TmpBuf =3D (UINT8 *)AllocateZeroPool (SectorSize); + if (TmpBuf =3D=3D NULL) { + DEBUG((DEBUG_ERROR, "%a(): Cannot allocate memory\n", __func__)); + return EFI_OUT_OF_RESOURCES; + } + + if (End - Buffer >=3D 200) + Scale =3D (End - Buffer) / 100; + + for (; Buffer < End; Buffer +=3D ToUpdate, Offset +=3D ToUpdate) { + ToUpdate =3D MIN((UINT64)(End - Buffer), SectorSize); + Print (L" \rUpdating, %d%%", 100 - (End - Buffer) / Scale); + Status =3D SpiFlashUpdateBlock (Slave, Offset, ToUpdate, Buffer, TmpBu= f, SectorSize); + + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_ERROR, "%a(): Error while updating\n", __func__)); + return Status; + } + } + + Print(L"\n"); + FreePool (TmpBuf); + + return EFI_SUCCESS; +} + +EFI_STATUS +SpiFlashUpdateWithProgress ( + IN SPI_DEVICE_PARAMS *Slave, + IN UINT32 Offset, + IN UINTN ByteCount, + IN UINT8 *Buffer, + IN EFI_FIRMWARE_MANAGEMENT_UPDATE_IMAGE_PROGRESS Progress, OPTIO= NAL + IN UINTN StartPercentage, + IN UINTN EndPercentage + ) +{ + EFI_STATUS Status; + UINTN SectorSize; + UINTN SectorNum; + UINTN ToUpdate; + UINTN Index; + UINT8 *TmpBuf; + + SectorSize =3D Slave->Info->SectorSize; + SectorNum =3D (ByteCount / SectorSize) + 1; + ToUpdate =3D SectorSize; + + TmpBuf =3D (UINT8 *)AllocateZeroPool (SectorSize); + if (TmpBuf =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a(): Cannot allocate memory\n", __func__)); + return EFI_OUT_OF_RESOURCES; + } + + for (Index =3D 0; Index < SectorNum; Index++) { + if (Progress !=3D NULL) { + Progress (StartPercentage + + ((Index * (EndPercentage - StartPercentage)) / SectorNum)); + } + + /* In the last chunk update only an actual number of remaining bytes */ + if (Index + 1 =3D=3D SectorNum) { + ToUpdate =3D ByteCount % SectorSize; + } + + Status =3D SpiFlashUpdateBlock (Slave, + Offset + Index * SectorSize, + ToUpdate, + Buffer + Index * SectorSize, + TmpBuf, + SectorSize); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(): Error while updating\n", __func__)); + return Status; + } + } + FreePool (TmpBuf); + + if (Progress !=3D NULL) { + Progress (EndPercentage); + } + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +SpiFlashReadId ( + IN SPI_DEVICE_PARAMS *Slave, + IN BOOLEAN UseInRuntime + ) +{ + EFI_STATUS Status; + UINT8 IdLen =3D 3; + UINT8 Id[IdLen]; + + SPI_OP_PARAMS Op =3D SPI_READID_OP (Id, IdLen); + + Status =3D SpiMasterProtocol->CmdRead (SpiMasterProtocol, Slave, &Op); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(): Spi error while reading id\n", __func__)); + return Status; + } + + Status =3D NorFlashGetInfo (Id, &Slave->Info, UseInRuntime); + + if (EFI_ERROR (Status)) { + DEBUG ( + (DEBUG_ERROR, + "%a: Unrecognized JEDEC Id bytes: 0x%02x%02x%02x\n", + __func__, + Id[0], + Id[1], + Id[2]) + ); + return Status; + } + + NorFlashPrintInfo (Slave->Info); + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +SpiFlashInit ( + IN SPI_FLASH_PROTOCOL *This, + IN SPI_DEVICE_PARAMS *Slave + ) +{ + EFI_STATUS Status; + UINT8 StatusRegister; + + Slave->AddrSize =3D (Slave->Info->Flags & NOR_FLASH_4B_ADDR) ? 4 : 3; + + Status =3D SpiFlashWriteEnableCmd (Slave); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(): Error while setting write enable\n", __fun= c__)); + return Status; + } + + if (Slave->AddrSize =3D=3D 4) { + + /* Enable 4byte addressing */ + SPI_OP_PARAMS Op4BAddEn =3D SPI_OP ( + SPI_OP_CMD (SPI_CMD_4B_ADDR_ENABLE= ), + SPI_OP_NO_ADDR, + SPI_OP_NO_DUMMY, + SPI_OP_NO_DATA + ); + Status =3D SpiMasterProtocol->CmdWrite (SpiMasterProtocol, Slave, &Op4= BAddEn); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(): Error while setting 4B address\n", __fun= c__)); + return Status; + } + } + + /* Initialize flash status register */ + StatusRegister =3D 0x0; + SPI_OP_PARAMS OpWrSts =3D SPI_OP ( + SPI_OP_CMD (SPI_CMD_WRITE_STATUS_REG), + SPI_OP_NO_ADDR, + SPI_OP_NO_DUMMY, + SPI_OP_DATA_OUT (1, (VOID *)&StatusReg= ister) + ); + + Status =3D SpiMasterProtocol->CmdWrite (SpiMasterProtocol, Slave, &OpWrS= ts); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(): Error while writing status register\n", __= func__)); + return Status; + } + + Status =3D SpiFlashWriteDisableCmd (Slave); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(): Error while setting write disable\n", __fu= nc__)); + return Status; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +SpiFlashInitProtocol ( + IN SPI_FLASH_PROTOCOL *SpiFlashProtocol + ) +{ + SpiFlashProtocol->Read =3D SpiFlashRead; + SpiFlashProtocol->Write =3D SpiFlashWrite; + SpiFlashProtocol->Update =3D SpiFlashUpdate; + SpiFlashProtocol->UpdateWithProgress =3D SpiFlashUpdateWithProgress; + SpiFlashProtocol->Erase =3D SpiFlashErase; + SpiFlashProtocol->ReadId =3D SpiFlashReadId; + SpiFlashProtocol->Init =3D SpiFlashInit; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +SpiFlashEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + Status =3D gBS->LocateProtocol ( + &gJH7110SpiMasterProtocolGuid, + NULL, + (VOID **)&SpiMasterProtocol + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(): Cannot locate SPI Master protocol\n", __fu= nc__)); + return EFI_DEVICE_ERROR; + } + + mSpiFlashInstance =3D AllocateRuntimeZeroPool (sizeof (SPI_FLASH_INSTANC= E)); + if (mSpiFlashInstance =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a(): Cannot allocate memory\n", __func__)); + return EFI_OUT_OF_RESOURCES; + } + + SpiFlashInitProtocol (&mSpiFlashInstance->SpiFlashProtocol); + + mSpiFlashInstance->Signature =3D SPI_FLASH_SIGNATURE; + + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &(mSpiFlashInstance->Ha= ndle), + &gJH7110SpiFlashProtoco= lGuid, + &(mSpiFlashInstance->Sp= iFlashProtocol), + NULL + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(): Cannot install SPI flash protocol\n", __fu= nc__)); + goto ErrorInstallProto; + } + + return EFI_SUCCESS; + +ErrorInstallProto: + FreePool (mSpiFlashInstance); + + return EFI_SUCCESS; +} diff --git a/Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiFlashDx= e/SpiFlashDxe.h b/Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiFl= ashDxe/SpiFlashDxe.h new file mode 100755 index 000000000000..f3bb300334c0 --- /dev/null +++ b/Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiFlashDxe/SpiFl= ashDxe.h @@ -0,0 +1,35 @@ +/** @file + * + * Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.=
+ * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef __SPI_FLASH_DXE_H__ +#define __SPI_FLASH_DXE_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define SPI_FLASH_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'I') + +#define STATUS_REG_POLL_WIP_MSK (1 << 0) + +typedef struct { + SPI_FLASH_PROTOCOL SpiFlashProtocol; + UINTN Signature; + EFI_HANDLE Handle; +} SPI_FLASH_INSTANCE; + +#endif //__SPI_FLASH_DXE_H__ diff --git a/Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiFlashDx= e/SpiFlashDxe.inf b/Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/Spi= FlashDxe/SpiFlashDxe.inf new file mode 100644 index 000000000000..3ca429fdc2dd --- /dev/null +++ b/Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiFlashDxe/SpiFl= ashDxe.inf @@ -0,0 +1,44 @@ +## @file +# +# Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<= BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SpiFlashDxe + FILE_GUID =3D D3DF07BE-3810-4521-89EF-C4E22E0B2484 + MODULE_TYPE =3D DXE_RUNTIME_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SpiFlashEntryPoint + +[Sources] + SpiFlashDxe.c + SpiFlashDxe.h + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + Silicon/StarFive/JH7110Pkg/JH7110Pkg.dec + +[LibraryClasses] + DebugLib + MemoryAllocationLib + NorFlashInfoLib + TimerLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + UefiRuntimeLib + +[Guids] + gEfiEventVirtualAddressChangeGuid + +[Protocols] + gJH7110SpiFlashProtocolGuid + gJH7110SpiMasterProtocolGuid + +[Depex] + gJH7110SpiMasterProtocolGuid diff --git a/Silicon/StarFive/JH7110Pkg/Include/Protocol/Spi.h b/Silicon/St= arFive/JH7110Pkg/Include/Protocol/Spi.h new file mode 100644 index 000000000000..b8db3ad4c5b0 --- /dev/null +++ b/Silicon/StarFive/JH7110Pkg/Include/Protocol/Spi.h @@ -0,0 +1,163 @@ +/** @file + * + * Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.=
+ * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef __SPI_MASTER_PROTOCOL_H__ +#define __SPI_MASTER_PROTOCOL_H__ + +#include + +typedef struct _SPI_MASTER_PROTOCOL SPI_MASTER_PROTOCOL; + + +#define SPI_CMD_WRITE_STATUS_REG 0x01 +#define SPI_CMD_PAGE_PROGRAM 0x02 +#define SPI_CMD_READ_DATA 0x03 +#define SPI_CMD_WRITE_DISABLE 0x04 +#define SPI_CMD_READ_STATUS 0x05 +#define SPI_CMD_WRITE_ENABLE 0x06 +#define SPI_CMD_READ_ARRAY_FAST 0x0b +#define SPI_CMD_BANKADDR_BRWR 0x17 +#define SPI_CMD_ERASE_4K 0x20 +#define SPI_CMD_ERASE_32K 0x52 +#define SPI_CMD_FLAG_STATUS 0x70 +#define SPI_CMD_READ_ID 0x9f +#define SPI_CMD_4B_ADDR_ENABLE 0xb7 +#define SPI_CMD_BANK_WRITE 0xc5 +#define SPI_CMD_ERASE_64K 0xd8 + + + +#define SPI_OP_CMD(__OpCode) \ + { \ + .OpCode =3D __OpCode, \ + .NBytes =3D 1, \ + } + +#define SPI_OP_ADDR(__NBytes, __Val) \ + { \ + .NBytes =3D __NBytes, \ + .Val =3D __Val, \ + } + +#define SPI_OP_NO_ADDR { } + +#define SPI_OP_DUMMY(__NBytes) \ + { \ + .NBytes =3D __NBytes, \ + } + +#define SPI_OP_NO_DUMMY { } + +#define SPI_OP_DATA_IN(__NBytes, __Buf) \ + { \ + .NBytes =3D __NBytes, \ + .Buf.In =3D __Buf, \ + } + +#define SPI_OP_DATA_OUT(__NBytes, __Buf) \ + { \ + .NBytes =3D __NBytes, \ + .Buf.Out =3D __Buf, \ + } + +#define SPI_OP_NO_DATA { } + +#define SPI_OP(__Cmd, __Addr, __Dummy, __Data) \ + { \ + .Cmd =3D __Cmd, \ + .Addr =3D __Addr, \ + .Dummy =3D __Dummy, \ + .Data =3D __Data, \ + } + +/** + * Standard SPI NOR flash operations + */ +#define SPI_WRITE_EN_OP() \ + SPI_OP(SPI_OP_CMD(SPI_CMD_WRITE_ENABLE), \ + SPI_OP_NO_ADDR, \ + SPI_OP_NO_DUMMY, \ + SPI_OP_NO_DATA) + +#define SPI_WRITE_DIS_OP() \ + SPI_OP(SPI_OP_CMD(SPI_CMD_WRITE_DISABLE), \ + SPI_OP_NO_ADDR, \ + SPI_OP_NO_DUMMY, \ + SPI_OP_NO_DATA) + +#define SPI_READID_OP(Buf, Len) \ + SPI_OP(SPI_OP_CMD(SPI_CMD_READ_ID), \ + SPI_OP_NO_ADDR, \ + SPI_OP_NO_DUMMY, \ + SPI_OP_DATA_IN(Len, Buf)) + +typedef struct { + struct { + UINT8 NBytes; + UINT16 OpCode; + } Cmd; + + struct { + UINT8 NBytes; + UINT64 Val; + } Addr; + + struct { + UINT8 NBytes; + } Dummy; + + struct { + UINT32 NBytes; + union { + VOID *In; + CONST VOID *Out; + } Buf; + } Data; +} SPI_OP_PARAMS; + +typedef struct { + UINT32 AddrSize; + NOR_FLASH_INFO *Info; + UINT32 RegBase; + VOID *AhbBase; + UINT8 FifoWidth; + UINT32 WriteDelay; +} SPI_DEVICE_PARAMS; + +typedef + EFI_STATUS +(EFIAPI *SPI_DEVICE_SETUP)( + IN SPI_MASTER_PROTOCOL *This, + OUT SPI_DEVICE_PARAMS *Slave + ); + +typedef + EFI_STATUS +(EFIAPI *SPI_DEVICE_FREE)( + IN SPI_DEVICE_PARAMS *Slave + ); + + +typedef + EFI_STATUS +(EFIAPI *SPI_EXECUTE_RW)( + IN SPI_MASTER_PROTOCOL *This, + IN SPI_DEVICE_PARAMS *Slave, + IN OUT SPI_OP_PARAMS *Cmds + ); + +struct _SPI_MASTER_PROTOCOL { + SPI_DEVICE_SETUP SetupDevice; + SPI_DEVICE_FREE FreeDevice; + SPI_EXECUTE_RW CmdRead; + SPI_EXECUTE_RW DataRead; + SPI_EXECUTE_RW CmdWrite; + SPI_EXECUTE_RW DataWrite; +}; + +#endif // __SPI_MASTER_PROTOCOL_H__ diff --git a/Silicon/StarFive/JH7110Pkg/Include/Protocol/SpiFlash.h b/Silic= on/StarFive/JH7110Pkg/Include/Protocol/SpiFlash.h new file mode 100644 index 000000000000..cdbe4d0b6b67 --- /dev/null +++ b/Silicon/StarFive/JH7110Pkg/Include/Protocol/SpiFlash.h @@ -0,0 +1,88 @@ +/** @file + * + * Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.=
+ * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef __SPI_FLASH_PROTOCOL_H__ +#define __SPI_FLASH_PROTOCOL_H__ + +#include +#include + +typedef struct _SPI_FLASH_PROTOCOL SPI_FLASH_PROTOCOL; + +typedef + EFI_STATUS +(EFIAPI *SPI_FLASH_INIT) ( + IN SPI_FLASH_PROTOCOL *This, + IN SPI_DEVICE_PARAMS *SpiDev + ); + +typedef + EFI_STATUS +(EFIAPI *SPI_FLASH_READ_ID) ( + IN SPI_DEVICE_PARAMS *Slave, + IN BOOLEAN UseInRuntime + ); + +typedef + EFI_STATUS +(EFIAPI *SPI_FLASH_READ) ( + IN SPI_DEVICE_PARAMS *Slave, + IN UINT32 Offset, + IN UINTN Length, + OUT VOID *Buffer + ); + +typedef + EFI_STATUS +(EFIAPI *SPI_FLASH_WRITE) ( + IN SPI_DEVICE_PARAMS *Slave, + IN UINT32 Offset, + IN UINTN Length, + IN VOID *Buffer + ); + +typedef + EFI_STATUS +(EFIAPI *SPI_FLASH_ERASE) ( + IN SPI_DEVICE_PARAMS *Slave, + IN UINT32 Offset, + IN UINTN Length + ); + +typedef + EFI_STATUS +(EFIAPI *SPI_FLASH_UPDATE) ( + IN SPI_DEVICE_PARAMS *Slave, + IN UINT32 Address, + IN UINTN DataByteCount, + IN UINT8 *Buffer + ); + +typedef + EFI_STATUS +(EFIAPI *SPI_FLASH_UPDATE_WITH_PROGRESS) ( + IN SPI_DEVICE_PARAMS *Slave, + IN UINT32 Offset, + IN UINTN ByteCount, + IN UINT8 *Buffer, + IN EFI_FIRMWARE_MANAGEMENT_UPDATE_IMAGE_PROGRESS Progress, OPTIONAL + IN UINTN StartPercentage, + IN UINTN EndPercentage + ); + +struct _SPI_FLASH_PROTOCOL { + SPI_FLASH_INIT Init; + SPI_FLASH_READ_ID ReadId; + SPI_FLASH_READ Read; + SPI_FLASH_WRITE Write; + SPI_FLASH_ERASE Erase; + SPI_FLASH_UPDATE Update; + SPI_FLASH_UPDATE_WITH_PROGRESS UpdateWithProgress; +}; + +#endif // __SPI_FLASH_PROTOCOL_H__ --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110176): https://edk2.groups.io/g/devel/message/110176 Mute This Topic: https://groups.io/mt/102214529/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 16 08:38:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+110174+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+110174+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1698377060; cv=none; d=zohomail.com; s=zohoarc; b=aOXfy7el4d3uaI2TaUd07j7k8Ihp7CC52J1go36al5iy/LHUv4wMWiIfdXb/YC0tKxtSEjTSg7LxBhtinlddpmLTcDq0Szt8uKtzLBiXw6fOzboUoDFAFoLn1fqtzW0dTsfnaC8YbeaAijoRkDK7Dm8n4fX3iS70I8Ol7TO2VOo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698377060; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=0vjC+DJHLkFjbPmysm/28MklZDHgb+VRTJkzK2PaKok=; b=aXHWR+92a1dcMpOl2/aV1hfsRl6J3eTXGCAhAMwDqfeLa7b3E6Hg4LbKaJfWvYunJLCY9D9m4BdeQI0zK4KaYtcB+DCC9v9rHXMMC2NqNhmZWweUBaa5oKMuAd6RkWUPzGt+FRbRpJdZbK1z4Xg0fJB9q33GnTY6iKpGADE6514= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+110174+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1698377060071102.98142199508368; Thu, 26 Oct 2023 20:24:20 -0700 (PDT) Return-Path: DKIM-Signature: a=rsa-sha256; bh=zwsjDpyIKZwVfFuWkaFVdfhD3gn8nrJqUZy4KqR1qTk=; c=relaxed/simple; d=groups.io; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Transfer-Encoding; s=20140610; t=1698377059; v=1; b=vFSQyRKfBM923hAGhTjryLrOjLqJCynhh+dlftqwJLWBDcqHzyXEKj7xURaA9t1fb0J5VnIN GlhCcyt511E5aHRVCVDE+cXly+lvWPyUTA+v/FiKjuwExek8SrL4dVMNA97pcEBJ6R4CzvJE1PQ wz1ltd8qREPZt75zfq1oRnvY= X-Received: by 127.0.0.2 with SMTP id obB7YY1788612xxHkeECgu1X; Thu, 26 Oct 2023 20:24:19 -0700 X-Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by mx.groups.io with SMTP id smtpd.web10.218631.1698377048600961756 for ; Thu, 26 Oct 2023 20:24:19 -0700 X-Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 7360B24E1CD; Fri, 27 Oct 2023 11:24:02 +0800 (CST) X-Received: from EXMBX073.cuchost.com (172.16.6.83) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 27 Oct 2023 11:24:02 +0800 X-Received: from localhost.localdomain (202.188.176.82) by EXMBX073.cuchost.com (172.16.6.83) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 27 Oct 2023 11:23:57 +0800 From: "John Chew" To: CC: John Chew , Sunil V L , Leif Lindholm , Michael D Kinney , Li Yong Subject: [edk2-devel] [PATCH v3 3/5] StarFive/JH7110Pkg: Add firmware volume block protocol Date: Fri, 27 Oct 2023 11:19:04 +0800 Message-ID: <20231027031906.1814-4-yuinyee.chew@starfivetech.com> In-Reply-To: <20231027031906.1814-1-yuinyee.chew@starfivetech.com> References: <20231027031906.1814-1-yuinyee.chew@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [202.188.176.82] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX073.cuchost.com (172.16.6.83) X-YovoleRuleAgent: yovoleflag Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,yuinyee.chew@starfivetech.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: QhpxjbzHlTPG0jiZTVjpFjoox1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1698377061262100001 Content-Type: text/plain; charset="utf-8" Support for efi variable to store in QSPI flash. This driver is responsible to initialize both QSPI and Flash driver. Firmware Volume(FV) Initialization: 1. Copy flash content into allocated shadow buffer (RAM) 2. Check FV header validity 3. If not valid, erase flash based on the region defined in PCDs , else skip 4. If erased, write flash with new FV header, else skip EFI Variable read: 1. Read anbd return the content from the shadow buffer (RAM) EFI Variable write: 1. Write the data into flash 2. Update shadow buffer (RAM) Cc: Sunil V L Cc: Leif Lindholm Cc: Michael D Kinney Cc: Li Yong Signed-off-by: John Chew Acked-by: Sunil V L --- Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/FvbDxe/FvbDxe.c | 90= 9 ++++++++++++++++++++ Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/FvbDxe/FvbDxe.h | 13= 8 +++ Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/FvbDxe/FvbDxe.inf | 7= 0 ++ 3 files changed, 1117 insertions(+) diff --git a/Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/FvbDxe/Fvb= Dxe.c b/Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/FvbDxe/FvbDxe.c new file mode 100644 index 000000000000..c30e82ed0871 --- /dev/null +++ b/Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/FvbDxe/FvbDxe.c @@ -0,0 +1,909 @@ +/** @file + * + * Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.=
+ * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "FvbDxe.h" + +STATIC FVB_DEVICE *mFvbDevice; + +STATIC CONST FVB_DEVICE mFvbFlashInstanceTemplate =3D { + { + 0, /* AddrSize ... NEED TO BE FILLED */ + NULL, /* Read from NOR FLASH ... NEED TO BE FILLED */ + 0, /* RegBase ... NEED TO BE FILLED */ + 0, /* AbhBase ... NEED TO BE FILLED */ + 0, /* FifoWidth ... NEED TO BE FILLED */ + 0, /* WriteDelay ... NEED TO BE FILLED */ + }, /* SPI_DEVICE_PARAMS */ + + NULL, /* SpiFlashProtocol ... NEED TO BE FILLED */ + NULL, /* SpiMasterProtocol ... NEED TO BE FILLED */ + NULL, /* Handle ... NEED TO BE FILLED */ + + FVB_FLASH_SIGNATURE, /* Signature ... NEED TO BE FILLED */ + + 0, /* ShadowBufBaseAddr ... NEED TO BE FILLED */ + 0, /* ShadowBufSize ... NEED TO BE FILLED */ + 0, /* FvbFlashVarOffset ... NEED TO BE FILLED */ + 0, /* FvbFlashVarSize ... NEED TO BE FILLED */ + 0, /* BlockSize ... NEED TO BE FILLED */ + 0, /* LastBlock ... NEED TO BE FILLED */ + 0, /* StartLba */ + + { + FvbGetAttributes, /* GetAttributes */ + FvbSetAttributes, /* SetAttributes */ + FvbGetPhysicalAddress, /* GetPhysicalAddress */ + FvbGetBlockSize, /* GetBlockSize */ + FvbRead, /* Read */ + FvbWrite, /* Write */ + FvbEraseBlocks, /* EraseBlocks */ + NULL, /* ParentHandle */ + }, /* EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL */ + + { + { + { + HARDWARE_DEVICE_PATH, + HW_VENDOR_DP, + { + (UINT8)sizeof (VENDOR_DEVICE_PATH), + (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8) + } + }, + { 0xfc0cb972, 0x21df, 0x44d2, { 0x92, 0xa5, 0x78, 0x98, 0x99, 0xcb, = 0xf6, 0x61 } + } + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 } + } + } /* FVB_DEVICE_PATH */ +}; + +STATIC +EFI_STATUS +FvbInitFvAndVariableStoreHeaders ( + IN FVB_DEVICE *FlashInstance + ) +{ + EFI_FIRMWARE_VOLUME_HEADER *FirmwareVolumeHeader; + VARIABLE_STORE_HEADER *VariableStoreHeader; + EFI_STATUS Status; + VOID *Headers; + UINTN HeadersLength; + UINTN BlockSize; + + HeadersLength =3D sizeof (EFI_FIRMWARE_VOLUME_HEADER) + + sizeof (EFI_FV_BLOCK_MAP_ENTRY) + + sizeof (VARIABLE_STORE_HEADER); + Headers =3D AllocateZeroPool (HeadersLength); + + BlockSize =3D FlashInstance->BlockSize; + + /* VariableBase -> FtwWOrkingBase -> FtwSpareBase are declared + * consecutively in contiguous memory + */ + ASSERT ( + PcdGet64 (PcdFlashNvStorageVariableBase64) + + PcdGet32 (PcdFlashNvStorageVariableSize) =3D=3D + PcdGet64 (PcdFlashNvStorageFtwWorkingBase64) + ); + ASSERT ( + PcdGet64 (PcdFlashNvStorageFtwWorkingBase64) + + PcdGet32 (PcdFlashNvStorageFtwWorkingSize) =3D=3D + PcdGet64 (PcdFlashNvStorageFtwSpareBase64) + ); + + /* Ensure the size of the variable area is at least one block size */ + ASSERT ( + (PcdGet32 (PcdFlashNvStorageVariableSize) > 0) && + (PcdGet32 (PcdFlashNvStorageVariableSize) / BlockSize > 0) + ); + ASSERT ( + (PcdGet32 (PcdFlashNvStorageFtwWorkingSize) > 0) && + (PcdGet32 (PcdFlashNvStorageFtwWorkingSize) / BlockSize > 0) + ); + ASSERT ( + (PcdGet32 (PcdFlashNvStorageFtwSpareSize) > 0) && + (PcdGet32 (PcdFlashNvStorageFtwSpareSize) / BlockSize > 0) + ); + + /* Ensure the Variable areas are aligned on block size boundaries */ + ASSERT ((PcdGet64 (PcdFlashNvStorageVariableBase64) % BlockSize) =3D=3D = 0); + ASSERT ((PcdGet64 (PcdFlashNvStorageFtwWorkingBase64) % BlockSize) =3D= =3D 0); + ASSERT ((PcdGet64 (PcdFlashNvStorageFtwSpareBase64) % BlockSize) =3D=3D = 0); + + /* --------------------------------------------- + * | Firmware Volume Header | | + * -------------------------- Non-Volatile | + * | Variable Store Header | Storage Variable | + * -------------------------- Region | + * | Variables | | + * --------------------------------------------- + */ + + /* Prepare Firmware Volume Header */ + FirmwareVolumeHeader =3D (EFI_FIRMWARE_VOLUME_HEADER *)Headers; + CopyGuid (&FirmwareVolumeHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid= ); + FirmwareVolumeHeader->FvLength =3D FlashInstance->FvbFlashVarSize; + FirmwareVolumeHeader->Signature =3D EFI_FVH_SIGNATURE; + FirmwareVolumeHeader->Attributes =3D EFI_FVB2_READ_ENABLED_CAP | /* Read= s may be enabled */ + EFI_FVB2_READ_STATUS | /* Reads = are currently enabled */ + EFI_FVB2_STICKY_WRITE | /* A bloc= k erase is required to flip bits into EFI_FVB2_ERASE_POLARITY */ + EFI_FVB2_ERASE_POLARITY | /* After = erasure all bits take this value (i.e. '1') */ + EFI_FVB2_WRITE_STATUS | /* Writes= are currently enabled */ + EFI_FVB2_WRITE_ENABLED_CAP; /* Writes= may be enabled */ + + FirmwareVolumeHeader->HeaderLength =3D sizeof (EFI_FIRMWARE_VOLUME_HEADE= R) + + sizeof (EFI_FV_BLOCK_MAP_ENTRY); + FirmwareVolumeHeader->Revision =3D EFI_FVH_REVISION; + FirmwareVolumeHeader->BlockMap[0].NumBlocks =3D FlashInstance->LastBlock= + 1; + FirmwareVolumeHeader->BlockMap[0].Length =3D FlashInstance->BlockSize; + FirmwareVolumeHeader->BlockMap[1].NumBlocks =3D 0; + FirmwareVolumeHeader->BlockMap[1].Length =3D 0; + FirmwareVolumeHeader->Checksum =3D CalculateCheckSum16 ( + (UINT= 16 *)FirmwareVolumeHeader, + Firmw= areVolumeHeader->HeaderLength + ); + + /* Prepare Variable Store Header */ + VariableStoreHeader =3D (VOID *)((UINTN)Headers + + FirmwareVolumeHeader->HeaderLength); + CopyGuid (&VariableStoreHeader->Signature, &gEfiAuthenticatedVariableGui= d); + VariableStoreHeader->Size =3D PcdGet32 (PcdFlashNvStorageVariableSize) - + FirmwareVolumeHeader->HeaderLength; + VariableStoreHeader->Format =3D VARIABLE_STORE_FORMATTED; + VariableStoreHeader->State =3D VARIABLE_STORE_HEALTHY; + + /* Write both header to the flash device on the base address of the + * declared variable base address in the flash. CAUTIONS! This will + * replace the existing firmware volume and variable header or possibly + * cause data corruption. Make sure the declared base address and size + * in the flash is only use for EFI Variable Storage. + * Offset =3D 0, LastBlockAdress =3D 0; + */ + Status =3D FvbWrite (&FlashInstance->FvbProtocol, 0, 0, &HeadersLength, = Headers); + + FreePool (Headers); + + return Status; +} + +STATIC +EFI_STATUS +FvbValidateFvHeader ( + IN FVB_DEVICE *FlashInstance + ) +{ + UINT16 Checksum; + EFI_FIRMWARE_VOLUME_HEADER *FirmwareVolumeHeader; + VARIABLE_STORE_HEADER *VariableStoreHeader; + UINTN VariableStoreLength; + + FirmwareVolumeHeader =3D (EFI_FIRMWARE_VOLUME_HEADER *)FlashInstance->Sh= adowBufBaseAddr; + + /* Verify the header revision, header signature, length from the flash */ + if ((FirmwareVolumeHeader->Revision !=3D EFI_FVH_REVISION) || + (FirmwareVolumeHeader->Signature !=3D EFI_FVH_SIGNATURE) || + (FirmwareVolumeHeader->FvLength !=3D FlashInstance->FvbFlashVarSize= )) + { + DEBUG ( + (DEBUG_ERROR, + "%a(): No Firmware Volume header present\n", + __func__) + ); + return EFI_NOT_FOUND; + } + + /* Verify the Firmware Volume Guid from the flash */ + if (!CompareGuid (&FirmwareVolumeHeader->FileSystemGuid, &gEfiSystemNvDa= taFvGuid)) { + DEBUG ( + (DEBUG_ERROR, + "%a(): Firmware Volume Guid non-compatible\n", + __func__) + ); + return EFI_NOT_FOUND; + } + + /* Verify the header checksum from the flash */ + Checksum =3D CalculateSum16 ((UINT16 *)FirmwareVolumeHeader, FirmwareVol= umeHeader->HeaderLength); + if (Checksum !=3D 0) { + DEBUG ( + (DEBUG_ERROR, + "%a(): FV checksum is invalid (Checksum:0x%x)\n", + __func__, + Checksum) + ); + return EFI_NOT_FOUND; + } + + VariableStoreHeader =3D (VOID *)((UINTN)FirmwareVolumeHeader + FirmwareV= olumeHeader->HeaderLength); + + /* Verify the Variable Store Guid */ + if (!CompareGuid (&VariableStoreHeader->Signature, &gEfiVariableGuid) && + !CompareGuid ( + &VariableStoreHeader->Signature, + &gEfiAuthenticatedVariableGuid + )) + { + DEBUG ( + (DEBUG_ERROR, + "%a(): Variable Store Guid non-compatible\n", + __func__) + ); + return EFI_NOT_FOUND; + } + + /* Verify the actual Variable Store length with declare size in header*/ + VariableStoreLength =3D PcdGet32 (PcdFlashNvStorageVariableSize) - + FirmwareVolumeHeader->HeaderLength; + if (VariableStoreHeader->Size !=3D VariableStoreLength) { + DEBUG ( + (DEBUG_ERROR, + "%a(): Variable Store Length does not match\n", + __func__) + ); + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +FvbGetAttributes ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ) +{ + EFI_FIRMWARE_VOLUME_HEADER *FirmwareVolumeHeader; + EFI_FVB_ATTRIBUTES_2 *FlashFvbAttributes; + FVB_DEVICE *FlashInstance; + + FlashInstance =3D INSTANCE_FROM_FVB_THIS (This); + + FirmwareVolumeHeader =3D (EFI_FIRMWARE_VOLUME_HEADER *)FlashInsta= nce->ShadowBufBaseAddr; + FlashFvbAttributes =3D (EFI_FVB_ATTRIBUTES_2 *)&(FirmwareVolumeHeader->A= ttributes); + + *Attributes =3D *FlashFvbAttributes; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +FvbSetAttributes ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ) +{ + EFI_FVB_ATTRIBUTES_2 OldAttributes; + EFI_FVB_ATTRIBUTES_2 FlashFvbAttributes; + EFI_FVB_ATTRIBUTES_2 UnchangedAttributes; + FVB_DEVICE *FlashInstance; + UINT32 Capabilities; + UINT32 OldStatus; + UINT32 NewStatus; + + FlashInstance =3D INSTANCE_FROM_FVB_THIS (This); + + /* Read current attribute from the Frimware Volume Header */ + FvbGetAttributes (This, &FlashFvbAttributes); + + OldAttributes =3D FlashFvbAttributes; + Capabilities =3D OldAttributes & EFI_FVB2_CAPABILITIES; + OldStatus =3D OldAttributes & EFI_FVB2_STATUS; + NewStatus =3D *Attributes & EFI_FVB2_STATUS; + + UnchangedAttributes =3D EFI_FVB2_READ_DISABLED_CAP | \ + EFI_FVB2_READ_ENABLED_CAP | \ + EFI_FVB2_WRITE_DISABLED_CAP | \ + EFI_FVB2_WRITE_ENABLED_CAP | \ + EFI_FVB2_LOCK_CAP | \ + EFI_FVB2_STICKY_WRITE | \ + EFI_FVB2_ERASE_POLARITY | \ + EFI_FVB2_READ_LOCK_CAP | \ + EFI_FVB2_WRITE_LOCK_CAP | \ + EFI_FVB2_ALIGNMENT; + + /* Some attributes of FV is read only can *not* be set */ + if ((OldAttributes & UnchangedAttributes) ^ + (*Attributes & UnchangedAttributes)) + { + return EFI_INVALID_PARAMETER; + } + + /* If firmware volume is locked, no status bit can be updated */ + if (OldAttributes & EFI_FVB2_LOCK_STATUS) { + if (OldStatus ^ NewStatus) { + return EFI_ACCESS_DENIED; + } + } + + /* Test read disable */ + if ((Capabilities & EFI_FVB2_READ_DISABLED_CAP) =3D=3D 0) { + if ((NewStatus & EFI_FVB2_READ_STATUS) =3D=3D 0) { + return EFI_INVALID_PARAMETER; + } + } + + /* Test read enable */ + if ((Capabilities & EFI_FVB2_READ_ENABLED_CAP) =3D=3D 0) { + if (NewStatus & EFI_FVB2_READ_STATUS) { + return EFI_INVALID_PARAMETER; + } + } + + /* Test write disable */ + if ((Capabilities & EFI_FVB2_WRITE_DISABLED_CAP) =3D=3D 0) { + if ((NewStatus & EFI_FVB2_WRITE_STATUS) =3D=3D 0) { + return EFI_INVALID_PARAMETER; + } + } + + /* Test write enable */ + if ((Capabilities & EFI_FVB2_WRITE_ENABLED_CAP) =3D=3D 0) { + if (NewStatus & EFI_FVB2_WRITE_STATUS) { + return EFI_INVALID_PARAMETER; + } + } + + /* Test lock */ + if ((Capabilities & EFI_FVB2_LOCK_CAP) =3D=3D 0) { + if (NewStatus & EFI_FVB2_LOCK_STATUS) { + return EFI_INVALID_PARAMETER; + } + } + + FlashFvbAttributes =3D FlashFvbAttributes & (0xFFFFFFFF & (~EFI_FVB2_STA= TUS)); + FlashFvbAttributes =3D FlashFvbAttributes | NewStatus; + *Attributes =3D FlashFvbAttributes; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +FvbGetPhysicalAddress ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + OUT EFI_PHYSICAL_ADDRESS *Address + ) +{ + FVB_DEVICE *FlashInstance; + + ASSERT (Address !=3D NULL); + + FlashInstance =3D INSTANCE_FROM_FVB_THIS (This); + + /* Do not support MMIO, return the shadow buffer instead */ + *Address =3D FlashInstance->ShadowBufBaseAddr; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +FvbGetBlockSize ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + OUT UINTN *BlockSize, + OUT UINTN *NumberOfBlocks + ) +{ + FVB_DEVICE *FlashInstance; + + FlashInstance =3D INSTANCE_FROM_FVB_THIS (This); + + if (Lba > FlashInstance->LastBlock) { + DEBUG ( + (DEBUG_ERROR, + "%a(): Error: Requested LBA %ld is beyond the last available L= BA (%ld).\n", + __func__, + Lba, + FlashInstance->LastBlock) + ); + return EFI_INVALID_PARAMETER; + } else { + /* Assume equal sized blocks in all flash devices */ + *BlockSize =3D (UINTN)FlashInstance->BlockSize; + *NumberOfBlocks =3D (UINTN)(FlashInstance->LastBlock - Lba + 1); + + return EFI_SUCCESS; + } +} + +EFI_STATUS +EFIAPI +FvbRead ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN OUT UINT8 *Buffer + ) +{ + FVB_DEVICE *FlashInstance; + UINTN BlockSize; + UINTN DataOffset; + + FlashInstance =3D INSTANCE_FROM_FVB_THIS (This); + + /* Cache the block size to avoid de-referencing pointers all the time */ + BlockSize =3D FlashInstance->BlockSize; + + /* Offset + byte have to be within the define block size. + * The read must not span block boundaries. We need to + * check each variable individually because adding two + * large values together migght cause overflows. + */ + if ((Offset >=3D BlockSize) || + (*NumBytes > BlockSize) || + ((Offset + *NumBytes) > BlockSize)) + { + DEBUG ( + (DEBUG_ERROR, + "%a(): Wrong buffer size: (Offset=3D0x%x + NumBytes=3D0x%x) > = BlockSize=3D0x%x\n", + __func__, + Offset, + *NumBytes, + BlockSize) + ); + return EFI_BAD_BUFFER_SIZE; + } + + /* No bytes to read */ + if (*NumBytes =3D=3D 0) { + return EFI_SUCCESS; + } + + DataOffset =3D GET_DATA_OFFSET ( + FlashInstance->ShadowBufBaseAddr + Offset, + FlashInstance->StartLba + Lba, + FlashInstance->BlockSize + ); + + /* Copy variable from the shadow buffer */ + CopyMem (Buffer, (UINTN *)DataOffset, *NumBytes); + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +FvbWrite ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ) +{ + EFI_STATUS Status; + FVB_DEVICE *FlashInstance; + UINTN DataOffset; + + FlashInstance =3D INSTANCE_FROM_FVB_THIS (This); + + DataOffset =3D GET_DATA_OFFSET ( + FlashInstance->FvbFlashVarOffset + Offset, + FlashInstance->StartLba + Lba, + FlashInstance->BlockSize + ); + + Status =3D FlashInstance->SpiFlashProtocol->Write ( + &FlashInstance->SpiDevi= ce, + DataOffset, + *NumBytes, + Buffer + ); + if (EFI_ERROR (Status)) { + DEBUG ( + (DEBUG_ERROR, + "%a(): Failed to write to Spi device\n", + __func__) + ); + return Status; + } + + DataOffset =3D GET_DATA_OFFSET ( + FlashInstance->ShadowBufBaseAddr + Offset, + FlashInstance->StartLba + Lba, + FlashInstance->BlockSize + ); + + /* Update shadow buffer */ + CopyMem ((UINTN *)DataOffset, Buffer, *NumBytes); + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +FvbEraseBlocks ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + ... + ) +{ + EFI_FVB_ATTRIBUTES_2 FlashFvbAttributes; + FVB_DEVICE *FlashInstance; + EFI_STATUS Status; + VA_LIST Args; + UINTN BlockAddress; /* Physical address of Lba to erase= */ + EFI_LBA StartingLba; /* Lba from which we start erasing = */ + UINTN NumOfLba; /* Number of Lba blocks to erase */ + + FlashInstance =3D INSTANCE_FROM_FVB_THIS (This); + + Status =3D EFI_SUCCESS; + + /* Detect WriteDisabled state */ + FvbGetAttributes (This, &FlashFvbAttributes); + if ((FlashFvbAttributes & EFI_FVB2_WRITE_STATUS) =3D=3D 0) { + DEBUG ( + (DEBUG_ERROR, + "%a(): Device is in WriteDisabled state.\n", + __func__) + ); + return EFI_ACCESS_DENIED; + } + + /* + * Before erasing, check the entire list of parameters to ensure + * all specified blocks are valid. + */ + VA_START (Args, This); + do { + /* Get the Lba from which we start erasing */ + StartingLba =3D VA_ARG (Args, EFI_LBA); + + /* Have we reached the end of the list? */ + if (StartingLba =3D=3D EFI_LBA_LIST_TERMINATOR) { + break; + } + + /* How many Lba blocks are we requested to erase? */ + NumOfLba =3D VA_ARG (Args, UINT32); + + /* All blocks must be within range */ + if ((NumOfLba =3D=3D 0) || + ((FlashInstance->StartLba + StartingLba + NumOfLba - 1) > + FlashInstance->LastBlock)) + { + DEBUG ( + (DEBUG_ERROR, + "%a(): Error: Requested LBA are beyond the last available LB= A (%ld).\n", + __func__, + FlashInstance->LastBlock) + ); + + VA_END (Args); + + return EFI_INVALID_PARAMETER; + } + } while (TRUE); + + VA_END (Args); + + /* Start erasing */ + VA_START (Args, This); + do { + /* Get the Lba from which we start erasing */ + StartingLba =3D VA_ARG (Args, EFI_LBA); + + /* Have we reached the end of the list? */ + if (StartingLba =3D=3D EFI_LBA_LIST_TERMINATOR) { + break; + } + + /* How many Lba blocks are we requested to erase? */ + NumOfLba =3D VA_ARG (Args, UINT32); + + /* Go through each requested block and erase it */ + while (NumOfLba > 0) { + /* Get the offset address of Lba to erase */ + BlockAddress =3D GET_DATA_OFFSET ( + FlashInstance->FvbFlashVarOffset, + FlashInstance->StartLba + StartingLb= a, + FlashInstance->BlockSize + ); + + /* Erase single block */ + Status =3D FlashInstance->SpiFlashProtocol->Erase ( + &FlashInstance->Spi= Device, + BlockAddress, + FlashInstance->Bloc= kSize + ); + if (EFI_ERROR (Status)) { + VA_END (Args); + return EFI_DEVICE_ERROR; + } + + StartingLba++; + NumOfLba--; + } + } while (TRUE); + + VA_END (Args); + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +FvbFlashProbe ( + IN FVB_DEVICE *FlashInstance + ) +{ + SPI_FLASH_PROTOCOL *SpiFlashProtocol; + EFI_STATUS Status; + + SpiFlashProtocol =3D FlashInstance->SpiFlashProtocol; + + /* Read SPI flash ID */ + Status =3D SpiFlashProtocol->ReadId (&FlashInstance->SpiDevice, TRUE); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + Status =3D SpiFlashProtocol->Init (SpiFlashProtocol, &FlashInstance->Spi= Device); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(): Cannot initialize flash device\n", __func_= _)); + return EFI_DEVICE_ERROR; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +FvbPrepareFvHeader ( + IN FVB_DEVICE *FlashInstance + ) +{ + EFI_BOOT_MODE BootMode; + EFI_STATUS Status; + + /* Check if it is required to use default environment */ + BootMode =3D GetBootModeHob (); + if (BootMode =3D=3D BOOT_WITH_DEFAULT_SETTINGS) { + Status =3D EFI_INVALID_PARAMETER; + } else { + /* Validate header at the beginning of FV region */ + Status =3D FvbValidateFvHeader (FlashInstance); + } + + /* Install the default FVB header if required */ + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(): The FVB Header is not valid.\n", __func__)= ); + DEBUG ( + (DEBUG_ERROR, + "%a(): Installing a correct one for this volume.\n", + __func__) + ); + + /* Erase entire region that is reserved for variable storage in flash = */ + Status =3D FlashInstance->SpiFlashProtocol->Erase ( + &FlashInstance->SpiDe= vice, + FlashInstance->FvbFla= shVarOffset, + FlashInstance->FvbFla= shVarSize + ); + if (EFI_ERROR (Status)) { + return Status; + } + + /* Write a new firmware volume and varaible storage headers */ + Status =3D FvbInitFvAndVariableStoreHeaders (FlashInstance); + if (EFI_ERROR (Status)) { + return Status; + } + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +FvbConfigureFlashInstance ( + IN OUT FVB_DEVICE *FlashInstance + ) +{ + EFI_STATUS Status; + UINTN DataOffset; + UINTN VariableSize, FtwWorkingSize, FtwSpareSize, MemorySize; + + Status =3D gBS->LocateProtocol ( + &gJH7110SpiFlashProtocolGuid, + NULL, + (VOID **)&FlashInstance->SpiFlashProtocol + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(): Cannot locate SpiFlash protocol\n", __func= __)); + return Status; + } + + Status =3D gBS->LocateProtocol ( + &gJH7110SpiMasterProtocolGuid, + NULL, + (VOID **)&FlashInstance->SpiMasterProtocol + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(): Cannot locate SpiMaster protocol\n", __fun= c__)); + return Status; + } + + /* Setup and probe SPI flash */ + FlashInstance->SpiMasterProtocol->SetupDevice ( + FlashInstance->SpiMasterP= rotocol, + &FlashInstance->SpiDevice + ); + Status =3D FvbFlashProbe (FlashInstance); + if (EFI_ERROR (Status)) { + DEBUG ( + (DEBUG_ERROR, + "%a(): Error while performing SPI flash probe\n", + __func__) + ); + return Status; + } + + /* Fill remaining flash description */ + VariableSize =3D PcdGet32 (PcdFlashNvStorageVariableSize); + FtwWorkingSize =3D PcdGet32 (PcdFlashNvStorageFtwWorkingSize); + FtwSpareSize =3D PcdGet32 (PcdFlashNvStorageFtwSpareSize); + + FlashInstance->FvbFlashVarSize =3D VariableSize + FtwWorkingSize + Ft= wSpareSize; + FlashInstance->FvbFlashVarOffset =3D PcdGet32(PcdJH7110FlashVarOffset); + FlashInstance->BlockSize =3D FlashInstance->SpiDevice.Info->SectorSize; + FlashInstance->LastBlock =3D (FlashInstance->FvbFlashVarSize / + FlashInstance->BlockSize) - 1; + FlashInstance->ShadowBufSize =3D FlashInstance->FvbFlashVarSize; + + /* Allocate memory for shadow buffer */ + MemorySize =3D EFI_SIZE_TO_PAGES (FlashInstance->FvbFlashVarSize); + + /* FaultTolerantWriteDxe requires memory to be aligned to FtwWorkingSize= */ + FlashInstance->ShadowBufBaseAddr =3D (UINTN)AllocateAlignedRuntimePages ( + = MemorySize, + = SIZE_64KB + = ); + if (FlashInstance->ShadowBufBaseAddr =3D=3D (UINTN)NULL) { + return EFI_OUT_OF_RESOURCES; + } + + /* Update PCDs value according to allocated memory */ + Status =3D PcdSet64S ( + PcdFlashNvStorageVariableBase64, + (UINT64)FlashInstance->ShadowBufBaseAddr + ); + ASSERT_EFI_ERROR (Status); + Status =3D PcdSet64S ( + PcdFlashNvStorageFtwWorkingBase64, + (UINT64)FlashInstance->ShadowBufBaseAddr + + VariableSize + ); + ASSERT_EFI_ERROR (Status); + Status =3D PcdSet64S ( + PcdFlashNvStorageFtwSpareBase64, + (UINT64)FlashInstance->ShadowBufBaseAddr + + VariableSize + + FtwWorkingSize + ); + ASSERT_EFI_ERROR (Status); + + /* ill the shadow buffer with data from flash */ + DataOffset =3D GET_DATA_OFFSET ( + FlashInstance->FvbFlashVarOffset, + FlashInstance->StartLba, + FlashInstance->BlockSize + ); + Status =3D FlashInstance->SpiFlashProtocol->Read ( + &FlashInstance->SpiDevic= e, + DataOffset, + FlashInstance->FvbFlashV= arSize, + (VOID *)FlashInstance->S= hadowBufBaseAddr + ); + if (EFI_ERROR (Status)) { + goto ErrorFreeAllocatedPages; + } + + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &FlashInstance->Handle, + &gEfiDevicePathProtocol= Guid, + &FlashInstance->DeviceP= ath, + &gEfiFirmwareVolumeBloc= kProtocolGuid, + &FlashInstance->FvbProt= ocol, + NULL + ); + if (EFI_ERROR (Status)) { + goto ErrorFreeAllocatedPages; + } + + Status =3D FvbPrepareFvHeader (FlashInstance); + if (EFI_ERROR (Status)) { + goto ErrorPrepareFvbHeader; + } + + return EFI_SUCCESS; + +ErrorPrepareFvbHeader: + gBS->UninstallMultipleProtocolInterfaces ( + &FlashInstance->Handle, + &gEfiDevicePathProtocolGuid, + &gEfiFirmwareVolumeBlockProtoc= olGuid, + NULL + ); + +ErrorFreeAllocatedPages: + FreeAlignedPages ( + (VOID *)FlashInstance->ShadowBufBaseAddr, + MemorySize + ); + + return Status; +} + +EFI_STATUS +EFIAPI +FvbEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + /* Allocate memory for FVB flash device*/ + mFvbDevice =3D AllocateRuntimeCopyPool ( + sizeof (mFvbFlashInstanceTemplate), + &mFvbFlashInstanceTemplate + ); + if (mFvbDevice =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a(): Cannot allocate memory\n", __func__)); + return EFI_OUT_OF_RESOURCES; + } + + /* Detect and configure flash device */ + Status =3D FvbConfigureFlashInstance (mFvbDevice); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(): Fail to configure Fvb SPI device\n", __fun= c__)); + goto ErrorConfigureFlash; + } + + /* The driver implementing the variable read service can now be dispatch= ed; + * the varstore headers are in place. + */ + Status =3D gBS->InstallProtocolInterface ( + &gImageHandle, + &gEdkiiNvVarStoreFormattedGuid, + EFI_NATIVE_INTERFACE, + NULL + ); + if (EFI_ERROR (Status)) { + DEBUG ( + (DEBUG_ERROR, + "%a(): Failed to install gEdkiiNvVarStoreFormattedGuid\n", + __func__) + ); + goto ErrorInstallNvVarStoreFormatted; + } + + return Status; + +ErrorInstallNvVarStoreFormatted: + gBS->UninstallMultipleProtocolInterfaces ( + &mFvbDevice->Handle, + &gEfiDevicePathProtocolGuid, + &gEfiFirmwareVolumeBlockProtoc= olGuid, + NULL + ); + +ErrorConfigureFlash: + FreePool (mFvbDevice); + + return Status; +} diff --git a/Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/FvbDxe/Fvb= Dxe.h b/Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/FvbDxe/FvbDxe.h new file mode 100644 index 000000000000..6b0450b17275 --- /dev/null +++ b/Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/FvbDxe/FvbDxe.h @@ -0,0 +1,138 @@ +/** @file + * + * Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.=
+ * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef __FVB_DXE_H__ +#define __FVB_DXE_H__ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#define GET_DATA_OFFSET(BaseAddr, Lba, LbaSize) ((BaseAddr) + (UINTN)((Lb= a) * (LbaSize))) + +#define FVB_FLASH_SIGNATURE SIGNATURE_32('S', 'n', 'o', 'r') +#define INSTANCE_FROM_FVB_THIS(a) CR(a, FVB_DEVICE, FvbProtocol, FVB_FLAS= H_SIGNATURE) + +// +// Define two helper macro to extract the Capability field or Status field= in FVB +// bit fields. +// +#define EFI_FVB2_CAPABILITIES (EFI_FVB2_READ_DISABLED_CAP |\ + EFI_FVB2_READ_ENABLED_CAP | \ + EFI_FVB2_WRITE_DISABLED_CAP | \ + EFI_FVB2_WRITE_ENABLED_CAP | \ + EFI_FVB2_LOCK_CAP) + +#define EFI_FVB2_STATUS (EFI_FVB2_READ_STATUS | \ + EFI_FVB2_WRITE_STATUS | \ + EFI_FVB2_LOCK_STATUS) + +typedef struct { + VENDOR_DEVICE_PATH Vendor; + EFI_DEVICE_PATH_PROTOCOL End; +} FVB_DEVICE_PATH; + +typedef struct { + SPI_DEVICE_PARAMS SpiDevice; + + SPI_FLASH_PROTOCOL *SpiFlashProtocol; + SPI_MASTER_PROTOCOL *SpiMasterProtocol; + + EFI_HANDLE Handle; + + UINT32 Signature; + + UINTN ShadowBufBaseAddr; + UINTN ShadowBufSize; + UINTN FvbFlashVarOffset; + UINTN FvbFlashVarSize; + UINTN BlockSize; + UINTN LastBlock; + EFI_LBA StartLba; + + EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol; + + FVB_DEVICE_PATH DevicePath; +} FVB_DEVICE; + +EFI_STATUS +EFIAPI +FvbGetAttributes ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ); + +EFI_STATUS +EFIAPI +FvbSetAttributes ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ); + +EFI_STATUS +EFIAPI +FvbGetPhysicalAddress ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + OUT EFI_PHYSICAL_ADDRESS *Address + ); + +EFI_STATUS +EFIAPI +FvbGetBlockSize ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + OUT UINTN *BlockSize, + OUT UINTN *NumberOfBlocks + ); + +EFI_STATUS +EFIAPI +FvbRead ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN OUT UINT8 *Buffer + ); + +EFI_STATUS +EFIAPI +FvbWrite ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ); + +EFI_STATUS +EFIAPI +FvbEraseBlocks ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + ... + ); + +#endif //__FVB_DXE_H__ diff --git a/Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/FvbDxe/Fvb= Dxe.inf b/Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/FvbDxe/FvbDxe= .inf new file mode 100644 index 000000000000..715989bfcc2b --- /dev/null +++ b/Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/FvbDxe/FvbDxe.inf @@ -0,0 +1,70 @@ +## @file +# +# Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<= BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D FvbDxe + FILE_GUID =3D DB8BFC83-6DEA-4AD1-AD3D-FDC579430233 + MODULE_TYPE =3D DXE_RUNTIME_DRIVER + VERSION_STRING =3D 0.1 + ENTRY_POINT =3D FvbEntryPoint + +[Sources] + FvbDxe.c + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/StarFive/JH7110Pkg/JH7110Pkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + DevicePathLib + DxeServicesTableLib + HobLib + IoLib + MemoryAllocationLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + UefiRuntimeLib + UefiRuntimeServicesTableLib + +[Guids] + gEdkiiNvVarStoreFormattedGuid + gEfiAuthenticatedVariableGuid + gEfiEventVirtualAddressChangeGuid + gEfiSystemNvDataFvGuid + gEfiVariableGuid + +[Protocols] + gEfiDevicePathProtocolGuid + gEfiFirmwareVolumeBlockProtocolGuid + gJH7110SpiFlashProtocolGuid + gJH7110SpiMasterProtocolGuid + +[FixedPcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + gJH7110TokenSpaceGuid.PcdJH7110FlashVarOffset + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64 + +[Depex] + gEfiCpuArchProtocolGuid AND + gJH7110SpiMasterProtocolGuid AND + gJH7110SpiFlashProtocolGuid --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Cc: Sunil V L Cc: Leif Lindholm Cc: Michael D Kinney Cc: Li Yong Co-authored-by: John Chew Signed-off-by: mindachen1987 Acked-by: Sunil V L --- Silicon/StarFive/JH7110Pkg/Include/IndustryStandard/JH7110.h | 21 ++++++++ Silicon/StarFive/JH7110Pkg/JH7110Pkg.dec | 57 ++++++++= ++++++++++++ 2 files changed, 78 insertions(+) diff --git a/Silicon/StarFive/JH7110Pkg/Include/IndustryStandard/JH7110.h b= /Silicon/StarFive/JH7110Pkg/Include/IndustryStandard/JH7110.h new file mode 100644 index 000000000000..142e7be10c48 --- /dev/null +++ b/Silicon/StarFive/JH7110Pkg/Include/IndustryStandard/JH7110.h @@ -0,0 +1,21 @@ +/** @file + * + * Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.=
+ * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef JH7110_H__ +#define JH7110_H__ + +/* Generic PCI addresses */ +#define PCIE_TOP_OF_MEM_WIN (FixedPcdGet64 (PcdPciBusMmioAdr)) +#define PCIE_CPU_MMIO_WINDOW (FixedPcdGet64 (PcdPciCpuMmioAdr)) +#define PCIE_BRIDGE_MMIO_LEN (FixedPcdGet32 (PcdPciBusMmioLen)) + +/* PCI root bridge control registers location */ +#define PCIE_REG_BASE (FixedPcdGet64 (PcdPciRegBase)) +#define PCIE_CONFIG_BASE (FixedPcdGet64 (PcdPciConfigRegBase)) + +#endif /* JH7110_H__ */ diff --git a/Silicon/StarFive/JH7110Pkg/JH7110Pkg.dec b/Silicon/StarFive/JH= 7110Pkg/JH7110Pkg.dec new file mode 100644 index 000000000000..f9dc5ab3781d --- /dev/null +++ b/Silicon/StarFive/JH7110Pkg/JH7110Pkg.dec @@ -0,0 +1,57 @@ +## @file +# +# Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<= BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + DEC_SPECIFICATION =3D 0x0001001A + PACKAGE_NAME =3D JH7110Pkg + PACKAGE_GUID =3D D4B585C5-EBCA-4779-B974-05A3CF2F10C4 + PACKAGE_VERSION =3D 1.0 + +[Includes] + Include + +[Guids] + gJH7110TokenSpaceGuid =3D {0x44045e56, 0x7056, 0x4be6, {0x88, 0xc0, 0x49= , 0x0c, 0x67, 0x90, 0x2f, 0xba}} + +[PcdsFixedAtBuild.common] +# Memory map + gJH7110TokenSpaceGuid.PcdJH7110FlashVarOffset|0x0|UINT32|0x00000001 + +# PCIe + gJH7110TokenSpaceGuid.PcdPciRegBase|0x2b000000|UINT64|0x00000002 + gJH7110TokenSpaceGuid.PcdPciBusMmioAdr|0x0|UINT64|0x00000003 + gJH7110TokenSpaceGuid.PcdPciBusMmioLen|0x0|UINT32|0x00000004 + gJH7110TokenSpaceGuid.PcdPciCpuMmioAdr|0x0|UINT64|0x00000005 + gJH7110TokenSpaceGuid.PcdPciConfigRegBase|0x940000000|UINT64|0x00000006 + gJH7110TokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x10000007 + gJH7110TokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x10000008 + gJH7110TokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x10000009 + gJH7110TokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x1000000A + gJH7110TokenSpaceGuid.PcdPciIoOffset|0x0|UINT64|0x1000000B + gJH7110TokenSpaceGuid.PcdPci0Mmio32Base|0x0|UINT32|0x1000000C + gJH7110TokenSpaceGuid.PcdPci0Mmio32Size|0x0|UINT32|0x1000000D + gJH7110TokenSpaceGuid.PcdPci0Mmio64Base|0x0|UINT64|0x1000000E + gJH7110TokenSpaceGuid.PcdPci0Mmio64Size|0x0|UINT64|0x1000000F + gJH7110TokenSpaceGuid.PcdPci1Mmio32Base|0x0|UINT32|0x10000010 + gJH7110TokenSpaceGuid.PcdPci1Mmio32Size|0x0|UINT32|0x1000011 + gJH7110TokenSpaceGuid.PcdPci1Mmio64Base|0x0|UINT64|0x1000012 + gJH7110TokenSpaceGuid.PcdPci1Mmio64Size|0x0|UINT64|0x1000013 + +# SPI + gJH7110TokenSpaceGuid.PcdSpiFlashRegBase|0|UINT32|0x1000014 + gJH7110TokenSpaceGuid.PcdSpiFlashAhbBase|0|UINT64|0x1000015 + gJH7110TokenSpaceGuid.PcdSpiFlashFifoWidth|0|UINT8|0x10000016 + gJH7110TokenSpaceGuid.PcdSpiFlashRefClkHz|0|UINT32|0x10000017 + gJH7110TokenSpaceGuid.PcdSpiFlashTshslNs|0|UINT32|0x10000018 + gJH7110TokenSpaceGuid.PcdSpiFlashTsd2dNs|0|UINT32|0x1000019 + gJH7110TokenSpaceGuid.PcdSpiFlashTchshNs|0|UINT32|0x100001A + gJH7110TokenSpaceGuid.PcdSpiFlashTslchNs|0|UINT32|0x100001B + +[Protocols] + gJH7110SpiMasterProtocolGuid =3D { 0xA33C46E0, 0x4FB6, 0x4AA3, { 0x8E, 0= x66, 0x00, 0x06, 0x9F, 0x3A, 0x11, 0x81 }} + gJH7110SpiFlashProtocolGuid =3D { 0x5ECECDF6, 0x81DA, 0x4E10, { 0x9D, 0= x4B, 0x26, 0x65, 0x8C, 0x03, 0xAB, 0xBC }} --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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charset="utf-8" From: mindachen1987 - Added new platform support for VisionFive2 SBC. - Boot flow in VF2 using EDK2 as bootloader: BootROM -> U-Boot SPL -> OpenSBI -> EDK2 -> Linux -> OS - Supported boot source for Linux from EDK2: - SD Card - eMMC - NVMe - USB Cc: Sunil V L Cc: Leif Lindholm Cc: Michael D Kinney Cc: Li Yong Co-authored-by: John Chew Signed-off-by: mindachen1987 Acked-by: Sunil V L --- Platform/StarFive/VisionFive2/DeviceTree/Gpio.h | 42 + Platform/StarFive/VisionFive2/DeviceTree/Irq.h | 20 + Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkGen.h | 398 = +++++ Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkIsp.h | 57 + Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkVout.h | 68 + Platform/StarFive/VisionFive2/DeviceTree/JH7110PinCtrl.h | 1573 = +++++++++++++++++ Platform/StarFive/VisionFive2/DeviceTree/JH7110Power.h | 22 + Platform/StarFive/VisionFive2/DeviceTree/JH7110Rst.h | 228 = +++ Platform/StarFive/VisionFive2/DeviceTree/Led.h | 90 + Platform/StarFive/VisionFive2/DeviceTree/StarFiveClk.dtsi | 130 = ++ Platform/StarFive/VisionFive2/DeviceTree/StarFiveHdmi.dtsi | 28 + Platform/StarFive/VisionFive2/DeviceTree/StarFiveJH7110.dtsi | 1812 = ++++++++++++++++++++ Platform/StarFive/VisionFive2/DeviceTree/StarFivePwmDac.dtsi | 26 + Platform/StarFive/VisionFive2/DeviceTree/StarFiveVisionFive2.dts | 211 = +++ Platform/StarFive/VisionFive2/DeviceTree/StarFiveVisionFive2.dtsi | 838 = +++++++++ Platform/StarFive/VisionFive2/DeviceTree/Thermal.h | 16 + Platform/StarFive/VisionFive2/DeviceTree/VisionFive2DeviceTree.inf | 36 + Platform/StarFive/VisionFive2/VarStore.fdf.inc | 77 + Platform/StarFive/VisionFive2/VisionFive2.dsc | 596 = +++++++ Platform/StarFive/VisionFive2/VisionFive2.fdf | 284 = +++ Platform/StarFive/VisionFive2/VisionFive2.fdf.inc | 48 + 21 files changed, 6600 insertions(+) diff --git a/Platform/StarFive/VisionFive2/DeviceTree/Gpio.h b/Platform/Sta= rFive/VisionFive2/DeviceTree/Gpio.h new file mode 100644 index 000000000000..89f4c44eaec0 --- /dev/null +++ b/Platform/StarFive/VisionFive2/DeviceTree/Gpio.h @@ -0,0 +1,42 @@ +/** @file + This header provide all the general purpose input/output device tree bin= dings + + Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __DT_BINDINGS_GPIO_H__ +#define __DT_BINDINGS_GPIO_H__ + +/* Bit 0 express polarity */ +#define GPIO_ACTIVE_HIGH 0 +#define GPIO_ACTIVE_LOW 1 + +/* Bit 1 express single-endedness */ +#define GPIO_PUSH_PULL 0 +#define GPIO_SINGLE_ENDED 2 + +/* Bit 2 express Open drain or open source */ +#define GPIO_LINE_OPEN_SOURCE 0 +#define GPIO_LINE_OPEN_DRAIN 4 + +/* + * Open Drain/Collector is the combination of single-ended open drain inte= rface. + * Open Source/Emitter is the combination of single-ended open source inte= rface. + */ +#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) +#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) + +/* Bit 3 express GPIO suspend/resume and reset persistence */ +#define GPIO_PERSISTENT 0 +#define GPIO_TRANSITORY 8 + +/* Bit 4 express pull up */ +#define GPIO_PULL_UP 16 + +/* Bit 5 express pull down */ +#define GPIO_PULL_DOWN 32 + +#endif /* __DT_BINDINGS_GPIO_H__ */ diff --git a/Platform/StarFive/VisionFive2/DeviceTree/Irq.h b/Platform/Star= Five/VisionFive2/DeviceTree/Irq.h new file mode 100644 index 000000000000..19d08bc4a816 --- /dev/null +++ b/Platform/StarFive/VisionFive2/DeviceTree/Irq.h @@ -0,0 +1,20 @@ +/** @file + This header provide all the interrupt device tree bindings + + Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H__ +#define __DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H__ + +#define IRQ_TYPE_NONE 0 +#define IRQ_TYPE_EDGE_RISING 1 +#define IRQ_TYPE_EDGE_FALLING 2 +#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISI= NG) +#define IRQ_TYPE_LEVEL_HIGH 4 +#define IRQ_TYPE_LEVEL_LOW 8 + +#endif /* __DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H__ */ diff --git a/Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkGen.h b/Plat= form/StarFive/VisionFive2/DeviceTree/JH7110ClkGen.h new file mode 100644 index 000000000000..475967eff848 --- /dev/null +++ b/Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkGen.h @@ -0,0 +1,398 @@ +/** @file + This header provide all JH7110 clock generator device tree bindings + + Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __DT_BINDINGS_JH7110_CLK_GEN_H__ +#define __DT_BINDINGS_JH7110_CLK_GEN_H__ + +/* sys regisger */ +#define JH7110_CPU_ROOT 0 +#define JH7110_CPU_CORE 1 +#define JH7110_CPU_BUS 2 +#define JH7110_GPU_ROOT 3 +#define JH7110_PERH_ROOT 4 +#define JH7110_BUS_ROOT 5 +#define JH7110_NOCSTG_BUS 6 +#define JH7110_AXI_CFG0 7 +#define JH7110_STG_AXIAHB 8 +#define JH7110_AHB0 9 +#define JH7110_AHB1 10 +#define JH7110_APB_BUS_FUNC 11 +#define JH7110_APB0 12 +#define JH7110_PLL0_DIV2 13 +#define JH7110_PLL1_DIV2 14 +#define JH7110_PLL2_DIV2 15 +#define JH7110_AUDIO_ROOT 16 +#define JH7110_MCLK_INNER 17 +#define JH7110_MCLK 18 +#define JH7110_MCLK_OUT 19 +#define JH7110_ISP_2X 20 +#define JH7110_ISP_AXI 21 +#define JH7110_GCLK0 22 +#define JH7110_GCLK1 23 +#define JH7110_GCLK2 24 +#define JH7110_U7_CORE_CLK 25 +#define JH7110_U7_CORE_CLK1 26 +#define JH7110_U7_CORE_CLK2 27 +#define JH7110_U7_CORE_CLK3 28 +#define JH7110_U7_CORE_CLK4 29 +#define JH7110_U7_DEBUG_CLK 30 +#define JH7110_U7_RTC_TOGGLE 31 +#define JH7110_U7_TRACE_CLK0 32 +#define JH7110_U7_TRACE_CLK1 33 +#define JH7110_U7_TRACE_CLK2 34 +#define JH7110_U7_TRACE_CLK3 35 +#define JH7110_U7_TRACE_CLK4 36 +#define JH7110_U7_TRACE_COM_CLK 37 +#define JH7110_NOC_BUS_CLK_CPU_AXI 38 +#define JH7110_NOC_BUS_CLK_AXICFG0_AXI 39 +#define JH7110_OSC_DIV2 40 +#define JH7110_PLL1_DIV4 41 +#define JH7110_PLL1_DIV8 42 +#define JH7110_DDR_BUS 43 +#define JH7110_DDR_CLK_AXI 44 +#define JH7110_GPU_CORE 45 +#define JH7110_GPU_CORE_CLK 46 +#define JH7110_GPU_SYS_CLK 47 +#define JH7110_GPU_CLK_APB 48 +#define JH7110_GPU_RTC_TOGGLE 49 +#define JH7110_NOC_BUS_CLK_GPU_AXI 50 +#define JH7110_ISP_TOP_CLK_ISPCORE_2X 51 +#define JH7110_ISP_TOP_CLK_ISP_AXI 52 +#define JH7110_NOC_BUS_CLK_ISP_AXI 53 +#define JH7110_HIFI4_CORE 54 +#define JH7110_HIFI4_AXI 55 +#define JH7110_AXI_CFG1_DEC_CLK_MAIN 56 +#define JH7110_AXI_CFG1_DEC_CLK_AHB 57 +#define JH7110_VOUT_SRC 58 +#define JH7110_VOUT_AXI 59 +#define JH7110_NOC_BUS_CLK_DISP_AXI 60 +#define JH7110_VOUT_TOP_CLK_VOUT_AHB 61 +#define JH7110_VOUT_TOP_CLK_VOUT_AXI 62 +#define JH7110_VOUT_TOP_CLK_HDMITX0_MCLK 63 +#define JH7110_VOUT_TOP_CLK_MIPIPHY_REF 64 +#define JH7110_JPEGC_AXI 65 +#define JH7110_CODAJ12_CLK_AXI 66 +#define JH7110_CODAJ12_CLK_CORE 67 +#define JH7110_CODAJ12_CLK_APB 68 +#define JH7110_VDEC_AXI 69 +#define JH7110_WAVE511_CLK_AXI 70 +#define JH7110_WAVE511_CLK_BPU 71 +#define JH7110_WAVE511_CLK_VCE 72 +#define JH7110_WAVE511_CLK_APB 73 +#define JH7110_VDEC_JPG_ARB_JPGCLK 74 +#define JH7110_VDEC_JPG_ARB_MAINCLK 75 +#define JH7110_NOC_BUS_CLK_VDEC_AXI 76 +#define JH7110_VENC_AXI 77 +#define JH7110_WAVE420L_CLK_AXI 78 +#define JH7110_WAVE420L_CLK_BPU 79 +#define JH7110_WAVE420L_CLK_VCE 80 +#define JH7110_WAVE420L_CLK_APB 81 +#define JH7110_NOC_BUS_CLK_VENC_AXI 82 +#define JH7110_AXI_CFG0_DEC_CLK_MAIN_DIV 83 +#define JH7110_AXI_CFG0_DEC_CLK_MAIN 84 +#define JH7110_AXI_CFG0_DEC_CLK_HIFI4 85 +#define JH7110_AXIMEM2_128B_CLK_AXI 86 +#define JH7110_QSPI_CLK_AHB 87 +#define JH7110_QSPI_CLK_APB 88 +#define JH7110_QSPI_REF_SRC 89 +#define JH7110_QSPI_CLK_REF 90 +#define JH7110_SDIO0_CLK_AHB 91 +#define JH7110_SDIO1_CLK_AHB 92 +#define JH7110_SDIO0_CLK_SDCARD 93 +#define JH7110_SDIO1_CLK_SDCARD 94 +#define JH7110_USB_125M 95 +#define JH7110_NOC_BUS_CLK_STG_AXI 96 +#define JH7110_GMAC5_CLK_AHB 97 +#define JH7110_GMAC5_CLK_AXI 98 +#define JH7110_GMAC_SRC 99 +#define JH7110_GMAC1_GTXCLK 100 +#define JH7110_GMAC1_RMII_RTX 101 +#define JH7110_GMAC5_CLK_PTP 102 +#define JH7110_GMAC5_CLK_RX 103 +#define JH7110_GMAC5_CLK_RX_INV 104 +#define JH7110_GMAC5_CLK_TX 105 +#define JH7110_GMAC5_CLK_TX_INV 106 +#define JH7110_GMAC1_GTXC 107 +#define JH7110_GMAC0_GTXCLK 108 +#define JH7110_GMAC0_PTP 109 +#define JH7110_GMAC_PHY 110 +#define JH7110_GMAC0_GTXC 111 +#define JH7110_SYS_IOMUX_PCLK 112 +#define JH7110_MAILBOX_CLK_APB 113 +#define JH7110_INT_CTRL_CLK_APB 114 +#define JH7110_CAN0_CTRL_CLK_APB 115 +#define JH7110_CAN0_CTRL_CLK_TIMER 116 +#define JH7110_CAN0_CTRL_CLK_CAN 117 +#define JH7110_CAN1_CTRL_CLK_APB 118 +#define JH7110_CAN1_CTRL_CLK_TIMER 119 +#define JH7110_CAN1_CTRL_CLK_CAN 120 +#define JH7110_PWM_CLK_APB 121 +#define JH7110_DSKIT_WDT_CLK_APB 122 +#define JH7110_DSKIT_WDT_CLK_WDT 123 +#define JH7110_TIMER_CLK_APB 124 +#define JH7110_TIMER_CLK_TIMER0 125 +#define JH7110_TIMER_CLK_TIMER1 126 +#define JH7110_TIMER_CLK_TIMER2 127 +#define JH7110_TIMER_CLK_TIMER3 128 +#define JH7110_TEMP_SENSOR_CLK_APB 129 +#define JH7110_TEMP_SENSOR_CLK_TEMP 130 +#define JH7110_SPI0_CLK_APB 131 +#define JH7110_SPI1_CLK_APB 132 +#define JH7110_SPI2_CLK_APB 133 +#define JH7110_SPI3_CLK_APB 134 +#define JH7110_SPI4_CLK_APB 135 +#define JH7110_SPI5_CLK_APB 136 +#define JH7110_SPI6_CLK_APB 137 +#define JH7110_I2C0_CLK_APB 138 +#define JH7110_I2C1_CLK_APB 139 +#define JH7110_I2C2_CLK_APB 140 +#define JH7110_I2C3_CLK_APB 141 +#define JH7110_I2C4_CLK_APB 142 +#define JH7110_I2C5_CLK_APB 143 +#define JH7110_I2C6_CLK_APB 144 +#define JH7110_UART0_CLK_APB 145 +#define JH7110_UART0_CLK_CORE 146 +#define JH7110_UART1_CLK_APB 147 +#define JH7110_UART1_CLK_CORE 148 +#define JH7110_UART2_CLK_APB 149 +#define JH7110_UART2_CLK_CORE 150 +#define JH7110_UART3_CLK_APB 151 +#define JH7110_UART3_CLK_CORE 152 +#define JH7110_UART4_CLK_APB 153 +#define JH7110_UART4_CLK_CORE 154 +#define JH7110_UART5_CLK_APB 155 +#define JH7110_UART5_CLK_CORE 156 +#define JH7110_PWMDAC_CLK_APB 157 +#define JH7110_PWMDAC_CLK_CORE 158 +#define JH7110_SPDIF_CLK_APB 159 +#define JH7110_SPDIF_CLK_CORE 160 +#define JH7110_I2STX0_4CHCLK_APB 161 +#define JH7110_I2STX_4CH0_BCLK_MST 162 +#define JH7110_I2STX_4CH0_BCLK_MST_INV 163 +#define JH7110_I2STX_4CH0_LRCK_MST 164 +#define JH7110_I2STX0_4CHBCLK 165 +#define JH7110_I2STX0_4CHBCLK_N 166 +#define JH7110_I2STX0_4CHLRCK 167 +#define JH7110_I2STX1_4CHCLK_APB 168 +#define JH7110_I2STX_4CH1_BCLK_MST 169 +#define JH7110_I2STX_4CH1_BCLK_MST_INV 170 +#define JH7110_I2STX_4CH1_LRCK_MST 171 +#define JH7110_I2STX1_4CHBCLK 172 +#define JH7110_I2STX1_4CHBCLK_N 173 +#define JH7110_I2STX1_4CHLRCK 174 +#define JH7110_I2SRX0_3CH_CLK_APB 175 +#define JH7110_I2SRX_3CH_BCLK_MST 176 +#define JH7110_I2SRX_3CH_BCLK_MST_INV 177 +#define JH7110_I2SRX_3CH_LRCK_MST 178 +#define JH7110_I2SRX0_3CH_BCLK 179 +#define JH7110_I2SRX0_3CH_BCLK_N 180 +#define JH7110_I2SRX0_3CH_LRCK 181 +#define JH7110_PDM_CLK_DMIC 182 +#define JH7110_PDM_CLK_APB 183 +#define JH7110_TDM_CLK_AHB 184 +#define JH7110_TDM_CLK_APB 185 +#define JH7110_TDM_INTERNAL 186 +#define JH7110_TDM_CLK_TDM 187 +#define JH7110_TDM_CLK_TDM_N 188 +#define JH7110_JTAG_CERTIFICATION_TRNG_CLK 189 + +#define JH7110_CLK_SYS_REG_END 190 + +/* stg regisger */ +#define JH7110_HIFI4_CLK_CORE 190 +#define JH7110_USB0_CLK_USB_APB 191 +#define JH7110_USB0_CLK_UTMI_APB 192 +#define JH7110_USB0_CLK_AXI 193 +#define JH7110_USB0_CLK_LPM 194 +#define JH7110_USB0_CLK_STB 195 +#define JH7110_USB0_CLK_APP_125 196 +#define JH7110_USB0_REFCLK 197 +#define JH7110_PCIE0_CLK_AXI_MST0 198 +#define JH7110_PCIE0_CLK_APB 199 +#define JH7110_PCIE0_CLK_TL 200 +#define JH7110_PCIE1_CLK_AXI_MST0 201 +#define JH7110_PCIE1_CLK_APB 202 +#define JH7110_PCIE1_CLK_TL 203 +#define JH7110_PCIE01_SLV_DEC_MAINCLK 204 +#define JH7110_SEC_HCLK 205 +#define JH7110_SEC_MISCAHB_CLK 206 +#define JH7110_STG_MTRX_GRP0_CLK_MAIN 207 +#define JH7110_STG_MTRX_GRP0_CLK_BUS 208 +#define JH7110_STG_MTRX_GRP0_CLK_STG 209 +#define JH7110_STG_MTRX_GRP1_CLK_MAIN 210 +#define JH7110_STG_MTRX_GRP1_CLK_BUS 211 +#define JH7110_STG_MTRX_GRP1_CLK_STG 212 +#define JH7110_STG_MTRX_GRP1_CLK_HIFI 213 +#define JH7110_E2_RTC_CLK 214 +#define JH7110_E2_CLK_CORE 215 +#define JH7110_E2_CLK_DBG 216 +#define JH7110_DMA1P_CLK_AXI 217 +#define JH7110_DMA1P_CLK_AHB 218 + +#define JH7110_CLK_STG_REG_END 219 + +/* aon regisger */ +#define JH7110_OSC_DIV4 219 +#define JH7110_AON_APB_FUNC 220 +#define JH7110_U0_GMAC5_CLK_AHB 221 +#define JH7110_U0_GMAC5_CLK_AXI 222 +#define JH7110_GMAC0_RMII_RTX 223 +#define JH7110_U0_GMAC5_CLK_TX 224 +#define JH7110_U0_GMAC5_CLK_TX_INV 225 +#define JH7110_U0_GMAC5_CLK_RX 226 +#define JH7110_U0_GMAC5_CLK_RX_INV 227 +#define JH7110_OTPC_CLK_APB 228 +#define JH7110_RTC_HMS_CLK_APB 229 +#define JH7110_RTC_INTERNAL 230 +#define JH7110_RTC_HMS_CLK_OSC32K 231 +#define JH7110_RTC_HMS_CLK_CAL 232 + +#define JH7110_CLK_REG_END 233 + +/* sys other */ +#define JH7110_PLL0_OUT 233 +#define JH7110_PLL1_OUT 234 +#define JH7110_PLL2_OUT 235 +#define JH7110_AON_APB 236 +#define JH7110_RESET1_CTRL_CLK_SRC 237 +#define JH7110_DDR_ROOT 238 +#define JH7110_VDEC_ROOT 239 +#define JH7110_VENC_ROOT 240 +#define JH7110_VOUT_ROOT 241 +#define JH7110_GMACUSB_ROOT 242 +#define JH7110_PCLK2_MUX_FUNC_PCLK 243 +#define JH7110_PCLK2_MUX_BIST_PCLK 244 +#define JH7110_APB_BUS 245 +#define JH7110_APB12 246 +#define JH7110_AXI_CFG1 247 +#define JH7110_PLL_WRAP_CRG_GCLK0 248 +#define JH7110_PLL_WRAP_CRG_GCLK1 249 +#define JH7110_PLL_WRAP_CRG_GCLK2 250 +#define JH7110_JTAG2APB_PCLK 251 +#define JH7110_U7_BUS_CLK 252 +#define JH7110_U7_IRQ_SYNC_BUS_CLK 253 +#define JH7110_NOC_BUS_CLK2_CPU_AXI 254 +#define JH7110_NOC_BUS_CLK_APB_BUS 255 +#define JH7110_NOC_BUS_CLK2_APB_BUS 256 +#define JH7110_NOC_BUS_CLK2_AXICFG0_AXI 257 +#define JH7110_DDR_CLK_DDRPHY_PLL_BYPASS 258 +#define JH7110_DDR_CLK_OSC 259 +#define JH7110_DDR_CLK_APB 260 +#define JH7110_NOC_BUS_CLK_DDRC 261 +#define JH7110_NOC_BUS_CLK2_DDRC 262 +#define JH7110_SYS_AHB_DEC_CLK_AHB 263 +#define JH7110_STG_AHB_DEC_CLK_AHB 264 +#define JH7110_NOC_BUS_CLK2_GPU_AXI 265 +#define JH7110_ISP_TOP_CLK_DVP 266 +#define JH7110_NOC_BUS_CLK2_ISP_AXI 267 +#define JH7110_ISP_TOP_CLK_BIST_APB 268 +#define JH7110_NOC_BUS_CLK2_DISP_AXI 269 +#define JH7110_VOUT_TOP_CLK_HDMITX0_BCLK 270 +#define JH7110_VOUT_TOP_U0_HDMI_TX_PIN_WS 271 +#define JH7110_VOUT_TOP_CLK_HDMIPHY_REF 272 +#define JH7110_VOUT_TOP_BIST_PCLK 273 +#define JH7110_AXIMEM0_128B_CLK_AXI 274 +#define JH7110_VDEC_INTSRAM_CLK_VDEC_AXI 275 +#define JH7110_NOC_BUS_CLK2_VDEC_AXI 276 +#define JH7110_AXIMEM1_128B_CLK_AXI 277 +#define JH7110_VENC_INTSRAM_CLK_VENC_AXI 278 +#define JH7110_NOC_BUS_CLK2_VENC_AXI 279 +#define JH7110_SRAM_CLK_ROM 280 +#define JH7110_NOC_BUS_CLK2_STG_AXI 281 +#define JH7110_GMAC5_CLK_RMII 282 +#define JH7110_AON_AHB 283 +#define JH7110_SYS_CRG_PCLK 284 +#define JH7110_SYS_SYSCON_PCLK 285 +#define JH7110_SPI0_CLK_CORE 286 +#define JH7110_SPI1_CLK_CORE 287 +#define JH7110_SPI2_CLK_CORE 288 +#define JH7110_SPI3_CLK_CORE 289 +#define JH7110_SPI4_CLK_CORE 290 +#define JH7110_SPI5_CLK_CORE 291 +#define JH7110_SPI6_CLK_CORE 292 +#define JH7110_I2C0_CLK_CORE 293 +#define JH7110_I2C1_CLK_CORE 294 +#define JH7110_I2C2_CLK_CORE 295 +#define JH7110_I2C3_CLK_CORE 296 +#define JH7110_I2C4_CLK_CORE 297 +#define JH7110_I2C5_CLK_CORE 298 +#define JH7110_I2C6_CLK_CORE 299 +#define JH7110_I2STX_BCLK_MST 300 +#define JH7110_I2STX_LRCK_MST 301 +#define JH7110_I2SRX_BCLK_MST 302 +#define JH7110_I2SRX_LRCK_MST 303 +#define JH7110_PDM_CLK_DMIC0_BCLK_SLV 304 +#define JH7110_PDM_CLK_DMIC0_LRCK_SLV 305 +#define JH7110_PDM_CLK_DMIC1_BCLK_SLV 306 +#define JH7110_PDM_CLK_DMIC1_LRCK_SLV 307 +#define JH7110_TDM_CLK_MST 308 +#define JH7110_AHB2APB_CLK_AHB 309 +#define JH7110_P2P_ASYNC_CLK_APBS 310 +#define JH7110_P2P_ASYNC_CLK_APBM 311 +#define JH7110_JTAG_DAISY_CHAIN_JTAG_TCK 312 +#define JH7110_U7_DEBUG_SYSTEMJTAG_JTAG_TCK 313 +#define JH7110_E2_DEBUG_SYSTEMJTAG_TCK 314 +#define JH7110_JTAG_CERTIFICATION_TCK 315 +#define JH7110_SEC_SKP_CLK 316 +#define JH7110_U2_PCLK_MUX_PCLK 317 + +#define JH7110_CLK_SYS_END 318 + +/* stg other */ +#define JH7110_PCIE0_CLK_AXI_SLV0 318 +#define JH7110_PCIE0_CLK_AXI_SLV 319 +#define JH7110_PCIE0_CLK_OSC 320 +#define JH7110_PCIE1_CLK_AXI_SLV0 321 +#define JH7110_PCIE1_CLK_AXI_SLV 322 +#define JH7110_PCIE1_CLK_OSC 323 +#define JH7110_E2_IRQ_SYNC_CLK_CORE 324 +#define JH7110_STG_CRG_PCLK 325 +#define JH7110_STG_SYSCON_PCLK 326 + +#define JH7110_CLK_STG_END 327 + +/* aon other */ +#define JH7110_U0_GMAC5_CLK_PTP 327 +#define JH7110_U0_GMAC5_CLK_RMII 328 +#define JH7110_AON_SYSCON_PCLK 329 +#define JH7110_AON_IOMUX_PCLK 330 +#define JH7110_AON_CRG_PCLK 331 +#define JH7110_PMU_CLK_APB 332 +#define JH7110_PMU_CLK_WKUP 333 +#define JH7110_RTC_HMS_CLK_OSC32K_G 334 +#define JH7110_32K_OUT 335 +#define JH7110_RESET0_CTRL_CLK_SRC 336 +/* aon other and source */ +#define JH7110_PCLK_MUX_FUNC_PCLK 337 +#define JH7110_PCLK_MUX_BIST_PCLK 338 + +#define JH7110_CLK_END 339 + +/* sys external clocks */ +#define JH7110_OSC (JH7110_CLK_END + 0) +#define JH7110_GMAC1_RMII_REFIN (JH7110_CLK_END + 1) +#define JH7110_GMAC1_RGMII_RXIN (JH7110_CLK_END + 2) +#define JH7110_I2STX_BCLK_EXT (JH7110_CLK_END + 3) +#define JH7110_I2STX_LRCK_EXT (JH7110_CLK_END + 4) +#define JH7110_I2SRX_BCLK_EXT (JH7110_CLK_END + 5) +#define JH7110_I2SRX_LRCK_EXT (JH7110_CLK_END + 6) +#define JH7110_TDM_EXT (JH7110_CLK_END + 7) +#define JH7110_MCLK_EXT (JH7110_CLK_END + 8) +#define JH7110_JTAG_TCK_INNER (JH7110_CLK_END + 9) +#define JH7110_BIST_APB (JH7110_CLK_END + 10) + +/* stg external clocks */ +#define JH7110_STG_APB (JH7110_CLK_END + 11) + +/* aon external clocks */ +#define JH7110_GMAC0_RMII_REFIN (JH7110_CLK_END + 12) +#define JH7110_GMAC0_RGMII_RXIN (JH7110_CLK_END + 13) +#define JH7110_CLK_RTC (JH7110_CLK_END + 14) + +#endif /* __DT_BINDINGS_JH7110_CLK_GEN_H__ */ diff --git a/Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkIsp.h b/Plat= form/StarFive/VisionFive2/DeviceTree/JH7110ClkIsp.h new file mode 100644 index 000000000000..756c51529a3a --- /dev/null +++ b/Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkIsp.h @@ -0,0 +1,57 @@ +/** @file + This header provide all JH7110 clock isp device tree bindings + + Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __DT_BINDINGS_JH7110_CLK_ISP_H__ +#define __DT_BINDINGS_JH7110_CLK_ISP_H__ + +/* register */ +#define JH7110_DOM4_APB_FUNC 0 +#define JH7110_MIPI_RX0_PXL 1 +#define JH7110_DVP_INV 2 +#define JH7110_U0_M31DPHY_CFGCLK_IN 3 +#define JH7110_U0_M31DPHY_REFCLK_IN 4 +#define JH7110_U0_M31DPHY_TXCLKESC_LAN0 5 +#define JH7110_U0_VIN_PCLK 6 +#define JH7110_U0_VIN_SYS_CLK 7 +#define JH7110_U0_VIN_PIXEL_CLK_IF0 8 +#define JH7110_U0_VIN_PIXEL_CLK_IF1 9 +#define JH7110_U0_VIN_PIXEL_CLK_IF2 10 +#define JH7110_U0_VIN_PIXEL_CLK_IF3 11 +#define JH7110_U0_VIN_CLK_P_AXIWR 12 +#define JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C 13 + +#define JH7110_CLK_ISP_REG_END 14 + +/* other */ +#define JH7110_U3_PCLK_MUX_FUNC_PCLK 14 +#define JH7110_U3_PCLK_MUX_BIST_PCLK 15 +#define JH7110_DOM4_APB 16 +#define JH7110_U0_VIN_PCLK_FREE 17 +#define JH7110_U0_VIN_CLK_P_AXIRD 18 +#define JH7110_U0_VIN_ACLK 19 +#define JH7110_U0_ISPV2_TOP_WRAPPER_CLK_ISP_AXI_IN 20 +#define JH7110_U0_ISPV2_TOP_WRAPPER_CLK_ISP_X2 21 +#define JH7110_U0_ISPV2_TOP_WRAPPER_CLK_ISP 22 +#define JH7110_U0_ISPV2_TOP_WRAPPER_CLK_P 23 +#define JH7110_U0_CRG_PCLK 24 +#define JH7110_U0_SYSCON_PCLK 25 +#define JH7110_U0_M31DPHY_APBCFG_PCLK 26 +#define JH7110_U0_AXI2APB_BRIDGE_CLK_DOM4_APB 27 +#define JH7110_U0_AXI2APB_BRIDGE_ISP_AXI4SLV_CLK 28 +#define JH7110_U3_PCLK_MUX_PCLK 29 + +#define JH7110_CLK_ISP_END 30 + +/* external clocks */ +#define JH7110_ISP_TOP_CLK_ISPCORE_2X_CLKGEN (JH7110_CLK_ISP_END + 0) +#define JH7110_ISP_TOP_CLK_ISP_AXI_CLKGEN (JH7110_CLK_ISP_END + 1) +#define JH7110_ISP_TOP_CLK_BIST_APB_CLKGEN (JH7110_CLK_ISP_END + 2) +#define JH7110_ISP_TOP_CLK_DVP_CLKGEN (JH7110_CLK_ISP_END + 3) + +#endif /* __DT_BINDINGS_JH7110_CLK_ISP_H__ */ diff --git a/Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkVout.h b/Pla= tform/StarFive/VisionFive2/DeviceTree/JH7110ClkVout.h new file mode 100644 index 000000000000..9775d9eadbdd --- /dev/null +++ b/Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkVout.h @@ -0,0 +1,68 @@ +/** @file + This header provide all JH7110 clock vout device tree bindings + + Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __DT_BINDINGS_JH7110_CLK_VOUT_H__ +#define __DT_BINDINGS_JH7110_CLK_VOUT_H__ + +/* register */ +#define JH7110_APB 0 +#define JH7110_DC8200_PIX0 1 +#define JH7110_DSI_SYS 2 +#define JH7110_TX_ESC 3 +#define JH7110_U0_DC8200_CLK_AXI 4 +#define JH7110_U0_DC8200_CLK_CORE 5 +#define JH7110_U0_DC8200_CLK_AHB 6 +#define JH7110_U0_DC8200_CLK_PIX0 7 +#define JH7110_U0_DC8200_CLK_PIX1 8 +#define JH7110_DOM_VOUT_TOP_LCD_CLK 9 +#define JH7110_U0_CDNS_DSITX_CLK_APB 10 +#define JH7110_U0_CDNS_DSITX_CLK_SYS 11 +#define JH7110_U0_CDNS_DSITX_CLK_DPI 12 +#define JH7110_U0_CDNS_DSITX_CLK_TXESC 13 +#define JH7110_U0_MIPITX_DPHY_CLK_TXESC 14 +#define JH7110_U0_HDMI_TX_CLK_MCLK 15 +#define JH7110_U0_HDMI_TX_CLK_BCLK 16 +#define JH7110_U0_HDMI_TX_CLK_SYS 17 + +#define JH7110_CLK_VOUT_REG_END 18 + +/* other */ +#define JH7110_DISP_ROOT 18 +#define JH7110_DISP_AXI 19 +#define JH7110_DISP_AHB 20 +#define JH7110_HDMI_PHY_REF 21 +#define JH7110_HDMITX0_MCLK 22 +#define JH7110_HDMITX0_SCK 23 + +#define JH7110_MIPI_DPHY_REF 24 +#define JH7110_U0_PCLK_MUX_BIST_PCLK 25 +#define JH7110_DISP_APB 26 +#define JH7110_U0_PCLK_MUX_FUNC_PCLK 27 +#define JH7110_U0_DOM_VOUT_CRG_PCLK 28 +#define JH7110_U0_DOM_VOUT_SYSCON_PCLK 29 +#define JH7110_U0_SAIF_AMBA_DOM_VOUT_AHB_DEC_CLK_AHB 30 +#define JH7110_U0_AHB2APB_CLK_AHB 31 +#define JH7110_U0_P2P_ASYNC_CLK_APBS 32 +#define JH7110_U0_CDNS_DSITX_CLK_RXESC 33 +#define JH7110_U0_CDNS_DSITX_CLK_TXBYTEHS 34 +#define JH7110_U0_MIPITX_DPHY_CLK_SYS 35 +#define JH7110_U0_MIPITX_DPHY_CLK_DPHY_REF 36 +#define JH7110_U0_MIPITX_APBIF_PCLK 37 +#define JH7110_HDMI_TX_CLK_REF 38 +#define JH7110_U0_DC8200_CLK_PIX0_OUT 39 +#define JH7110_U0_DC8200_CLK_PIX1_OUT 40 + +#define JH7110_CLK_VOUT_END 41 + +/* external clocks */ +#define JH7110_HDMITX0_PIXELCLK (JH7110_CLK_VOUT_END + 0) +#define JH7110_MIPITX_DPHY_RXESC (JH7110_CLK_VOUT_END + 1) +#define JH7110_MIPITX_DPHY_TXBYTEHS (JH7110_CLK_VOUT_END + 2) + +#endif /* __DT_BINDINGS_JH7110_CLK_VOUT_H__ */ diff --git a/Platform/StarFive/VisionFive2/DeviceTree/JH7110PinCtrl.h b/Pla= tform/StarFive/VisionFive2/DeviceTree/JH7110PinCtrl.h new file mode 100755 index 000000000000..0df2e6991548 --- /dev/null +++ b/Platform/StarFive/VisionFive2/DeviceTree/JH7110PinCtrl.h @@ -0,0 +1,1573 @@ +/** @file + This header provide all JH7110 pin control device tree bindings + + Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __DT_BINDINGS_JH7110_PIN_CTRL_H__ +#define __DT_BINDINGS_JH7110_PIN_CTRL_H__ + +/************************aon_iomux***************************/ +// aon_iomux pin +#define PAD_TESTEN 0 +#define PAD_RGPIO0 1 +#define PAD_RGPIO1 2 +#define PAD_RGPIO2 3 +#define PAD_RGPIO3 4 +#define PAD_RSTN 5 +#define PAD_GMAC0_MDC 6 +#define PAD_GMAC0_MDIO 7 +#define PAD_GMAC0_RXD0 8 +#define PAD_GMAC0_RXD1 9 +#define PAD_GMAC0_RXD2 10 +#define PAD_GMAC0_RXD3 11 +#define PAD_GMAC0_RXDV 12 +#define PAD_GMAC0_RXC 13 +#define PAD_GMAC0_TXD0 14 +#define PAD_GMAC0_TXD1 15 +#define PAD_GMAC0_TXD2 16 +#define PAD_GMAC0_TXD3 17 +#define PAD_GMAC0_TXEN 18 +#define PAD_GMAC0_TXC 19 + +// aon_iomux dout +#define GPO_AON_IOMUX_U0_AON_CRG_CLK_32K_OUT 2 +#define GPO_AON_IOMUX_U0_PWM_8CH_PTC_PWM_4 3 +#define GPO_AON_IOMUX_U0_PWM_8CH_PTC_PWM_5 4 +#define GPO_AON_IOMUX_U0_PWM_8CH_PTC_PWM_6 5 +#define GPO_AON_IOMUX_U0_PWM_8CH_PTC_PWM_7 6 +#define GPO_AON_IOMUX_U0_SYS_CRG_CLK_GCLK0 7 +#define GPO_AON_IOMUX_U0_SYS_CRG_CLK_GCLK1 8 +#define GPO_AON_IOMUX_U0_SYS_CRG_CLK_GCLK2 9 +// aon_iomux doen +#define GPEN_AON_IOMUX_U0_PWM_8CH_PTC_OE_N_4 2 +#define GPEN_AON_IOMUX_U0_PWM_8CH_PTC_OE_N_5 3 +#define GPEN_AON_IOMUX_U0_PWM_8CH_PTC_OE_N_6 4 +#define GPEN_AON_IOMUX_U0_PWM_8CH_PTC_OE_N_7 5 +// aon_iomux gin +#define GPI_AON_IOMUX_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0 0 +#define GPI_AON_IOMUX_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1 1 +#define GPI_AON_IOMUX_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2 2 +#define GPI_AON_IOMUX_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3 3 + +// =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3DGPIO_OUT_SELECT=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D +// gpio_out config: +// every define below is a couple of signal and signal idx +// use macros in corresponding syscfg_macro.h and idx defined below to con= fig gpio_out +// e.g. SET_AON_IOMUX_GPO[gpio_num]_DOUT_CFG([signal]) +// e.g. SET_AON_IOMUX_GPO0_DOUT_CFG(__LOW) +// =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +#define __LOW 0 +#define __HIGH 1 +#define U0_AON_CRG_CLK_32K_OUT 2 +#define U0_PWM_8CH_PTC_PWM_4 3 +#define U0_PWM_8CH_PTC_PWM_5 4 +#define U0_PWM_8CH_PTC_PWM_6 5 +#define U0_PWM_8CH_PTC_PWM_7 6 +#define U0_SYS_CRG_CLK_GCLK0 7 +#define U0_SYS_CRG_CLK_GCLK1 8 +#define U0_SYS_CRG_CLK_GCLK2 9 + +// =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3DGPIO_OEN_SELECT=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D +// gpio_oen config: +// every define below is a couple of signal and signal idx +// use macros in corresponding syscfg_macro.h and idx defined below to con= fig gpio_oen +// e.g. SET_AON_IOMUX_GPO[gpio_num]_DOEN_CFG([signal]) +// e.g. SET_AON_IOMUX_GPO0_DOEN_CFG(__LOW) +// =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +#define __LOW 0 +#define __HIGH 1 +#define U0_PWM_8CH_PTC_OE_N_4 2 +#define U0_PWM_8CH_PTC_OE_N_5 3 +#define U0_PWM_8CH_PTC_OE_N_6 4 +#define U0_PWM_8CH_PTC_OE_N_7 5 + +// aon_iomux gmac0 syscon +#define AON_IOMUX_CFG__SAIF__SYSCFG_88_ADDR (0x58U) +#define AON_IOMUX_CFG__SAIF__SYSCFG_92_ADDR (0x5cU) +#define AON_IOMUX_CFG__SAIF__SYSCFG_96_ADDR (0x60U) +#define AON_IOMUX_CFG__SAIF__SYSCFG_100_ADDR (0x64U) +#define AON_IOMUX_CFG__SAIF__SYSCFG_104_ADDR (0x68U) +#define AON_IOMUX_CFG__SAIF__SYSCFG_108_ADDR (0x6cU) +#define AON_IOMUX_CFG__SAIF__SYSCFG_112_ADDR (0x70U) +#define AON_IOMUX_CFG__SAIF__SYSCFG_116_ADDR (0x74U) +#define AON_IOMUX_CFG__SAIF__SYSCFG_120_ADDR (0x78U) +#define AON_IOMUX_CFG__SAIF__SYSCFG_124_ADDR (0x7cU) +#define AON_IOMUX_CFG__SAIF__SYSCFG_128_ADDR (0x80U) +#define AON_IOMUX_CFG__SAIF__SYSCFG_132_ADDR (0x84U) +#define AON_IOMUX_CFG__SAIF__SYSCFG_136_ADDR (0x88U) +#define AON_IOMUX_CFG__SAIF__SYSCFG_140_ADDR (0x8cU) + +#define PADCFG_PAD_GMAC0_MDC_SYSCON AON_IOMUX_CFG__SAIF__SYSCFG_88_ADDR +#define PADCFG_PAD_GMAC0_MDIO_SYSCON AON_IOMUX_CFG__SAIF__SYSCFG_92_ADDR +#define PADCFG_PAD_GMAC0_RXD0_SYSCON AON_IOMUX_CFG__SAIF__SYSCFG_96_ADDR +#define PADCFG_PAD_GMAC0_RXD1_SYSCON AON_IOMUX_CFG__SAIF__SYSCFG_100_ADDR +#define PADCFG_PAD_GMAC0_RXD2_SYSCON AON_IOMUX_CFG__SAIF__SYSCFG_104_ADDR +#define PADCFG_PAD_GMAC0_RXD3_SYSCON AON_IOMUX_CFG__SAIF__SYSCFG_108_ADDR +#define PADCFG_PAD_GMAC0_RXDV_SYSCON AON_IOMUX_CFG__SAIF__SYSCFG_112_ADDR +#define PADCFG_PAD_GMAC0_RXC_SYSCON AON_IOMUX_CFG__SAIF__SYSCFG_116_ADDR +#define PADCFG_PAD_GMAC0_TXD0_SYSCON AON_IOMUX_CFG__SAIF__SYSCFG_120_ADDR +#define PADCFG_PAD_GMAC0_TXD1_SYSCON AON_IOMUX_CFG__SAIF__SYSCFG_124_ADDR +#define PADCFG_PAD_GMAC0_TXD2_SYSCON AON_IOMUX_CFG__SAIF__SYSCFG_128_ADDR +#define PADCFG_PAD_GMAC0_TXD3_SYSCON AON_IOMUX_CFG__SAIF__SYSCFG_132_ADDR +#define PADCFG_PAD_GMAC0_TXEN_SYSCON AON_IOMUX_CFG__SAIF__SYSCFG_136_ADDR +#define PADCFG_PAD_GMAC0_TXC_SYSCON AON_IOMUX_CFG__SAIF__SYSCFG_140_ADDR + +// aon_iomux func sel +#define AON_IOMUX_CFGSAIF__SYSCFG_144_ADDR (0x90U) +#define PAD_GMAC0_RXC_FUNC_SEL_SHIFT 0x0U +#define PAD_GMAC0_RXC_FUNC_SEL_MASK 0x3U + +#define PAD_GMAC0_RXC_FUNC_SEL \ + AON_IOMUX_CFGSAIF__SYSCFG_144_ADDR \ + PAD_GMAC0_RXC_FUNC_SEL_SHIFT \ + PAD_GMAC0_RXC_FUNC_SEL_MASK +/************************aon_iomux***************************/ + +/************************sys_iomux***************************/ +// sys_iomux pin +#define PAD_GPIO0 0 +#define PAD_GPIO1 1 +#define PAD_GPIO2 2 +#define PAD_GPIO3 3 +#define PAD_GPIO4 4 +#define PAD_GPIO5 5 +#define PAD_GPIO6 6 +#define PAD_GPIO7 7 +#define PAD_GPIO8 8 +#define PAD_GPIO9 9 +#define PAD_GPIO10 10 +#define PAD_GPIO11 11 +#define PAD_GPIO12 12 +#define PAD_GPIO13 13 +#define PAD_GPIO14 14 +#define PAD_GPIO15 15 +#define PAD_GPIO16 16 +#define PAD_GPIO17 17 +#define PAD_GPIO18 18 +#define PAD_GPIO19 19 +#define PAD_GPIO20 20 +#define PAD_GPIO21 21 +#define PAD_GPIO22 22 +#define PAD_GPIO23 23 +#define PAD_GPIO24 24 +#define PAD_GPIO25 25 +#define PAD_GPIO26 26 +#define PAD_GPIO27 27 +#define PAD_GPIO28 28 +#define PAD_GPIO29 29 +#define PAD_GPIO30 30 +#define PAD_GPIO31 31 +#define PAD_GPIO32 32 +#define PAD_GPIO33 33 +#define PAD_GPIO34 34 +#define PAD_GPIO35 35 +#define PAD_GPIO36 36 +#define PAD_GPIO37 37 +#define PAD_GPIO38 38 +#define PAD_GPIO39 39 +#define PAD_GPIO40 40 +#define PAD_GPIO41 41 +#define PAD_GPIO42 42 +#define PAD_GPIO43 43 +#define PAD_GPIO44 44 +#define PAD_GPIO45 45 +#define PAD_GPIO46 46 +#define PAD_GPIO47 47 +#define PAD_GPIO48 48 +#define PAD_GPIO49 49 +#define PAD_GPIO50 50 +#define PAD_GPIO51 51 +#define PAD_GPIO52 52 +#define PAD_GPIO53 53 +#define PAD_GPIO54 54 +#define PAD_GPIO55 55 +#define PAD_GPIO56 56 +#define PAD_GPIO57 57 +#define PAD_GPIO58 58 +#define PAD_GPIO59 59 +#define PAD_GPIO60 60 +#define PAD_GPIO61 61 +#define PAD_GPIO62 62 +#define PAD_GPIO63 63 +#define PAD_SD0_CLK 64 +#define PAD_SD0_CMD 65 +#define PAD_SD0_DATA0 66 +#define PAD_SD0_DATA1 67 +#define PAD_SD0_DATA2 68 +#define PAD_SD0_DATA3 69 +#define PAD_SD0_DATA4 70 +#define PAD_SD0_DATA5 71 +#define PAD_SD0_DATA6 72 +#define PAD_SD0_DATA7 73 +#define PAD_SD0_STRB 74 +#define PAD_GMAC1_MDC 75 +#define PAD_GMAC1_MDIO 76 +#define PAD_GMAC1_RXD0 77 +#define PAD_GMAC1_RXD1 78 +#define PAD_GMAC1_RXD2 79 +#define PAD_GMAC1_RXD3 80 +#define PAD_GMAC1_RXDV 81 +#define PAD_GMAC1_RXC 82 +#define PAD_GMAC1_TXD0 83 +#define PAD_GMAC1_TXD1 84 +#define PAD_GMAC1_TXD2 85 +#define PAD_GMAC1_TXD3 86 +#define PAD_GMAC1_TXEN 87 +#define PAD_GMAC1_TXC 88 +#define PAD_QSPI_SCLK 89 +#define PAD_QSPI_CSn0 90 +#define PAD_QSPI_DATA0 91 +#define PAD_QSPI_DATA1 92 +#define PAD_QSPI_DATA2 93 +#define PAD_QSPI_DATA3 94 + +// oen and out idx is for chosen, in idx is for reg offset +#define GPO_SYS_IOMUX_U0_WAVE511_O_UART_TXSOUT 2 +#define GPO_SYS_IOMUX_U0_CAN_CTRL_STBY 3 +#define GPO_SYS_IOMUX_U0_CAN_CTRL_TST_NEXT_BIT 4 +#define GPO_SYS_IOMUX_U0_CAN_CTRL_TST_SAMPLE_POINT 5 +#define GPO_SYS_IOMUX_U0_CAN_CTRL_TXD 6 +#define GPO_SYS_IOMUX_U0_CDN_USB_DRIVE_VBUS_IO 7 +#define GPO_SYS_IOMUX_U0_CDNS_QSPI_CSN1 8 +#define GPO_SYS_IOMUX_U0_CDNS_SPDIF_SPDIFO 9 +#define GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_OUT 10 +#define GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_OUT 11 +#define GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_OUT 12 +#define GPO_SYS_IOMUX_U0_DSKIT_WDT_WDOGRES 13 +#define GPO_SYS_IOMUX_U0_DW_I2C_IC_CLK_OUT_A 14 +#define GPO_SYS_IOMUX_U0_DW_I2C_IC_DATA_OUT_A 15 +#define GPO_SYS_IOMUX_U0_DW_SDIO_BACK_END_POWER 16 +#define GPO_SYS_IOMUX_U0_DW_SDIO_CARD_POWER_EN 17 +#define GPO_SYS_IOMUX_U0_DW_SDIO_CCMD_OD_PULLUP_EN_N 18 +#define GPO_SYS_IOMUX_U0_DW_SDIO_RST_N 19 +#define GPO_SYS_IOMUX_U0_DW_UART_SOUT 20 +#define GPO_SYS_IOMUX_U0_HIFI4_JTDO 21 +#define GPO_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDO 22 +#define GPO_SYS_IOMUX_U0_PDM_4MIC_DMIC_MCLK 23 +#define GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_0 24 +#define GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_1 25 +#define GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_2 26 +#define GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_3 27 +#define GPO_SYS_IOMUX_U0_PWMDAC_PWMDAC_LEFT_OUTPUT 28 +#define GPO_SYS_IOMUX_U0_PWMDAC_PWMDAC_RIGHT_OUTPUT 29 +#define GPO_SYS_IOMUX_U0_SSP_SPI_SSPCLKOUT 30 +#define GPO_SYS_IOMUX_U0_SSP_SPI_SSPFSSOUT 31 +#define GPO_SYS_IOMUX_U0_SSP_SPI_SSPTXD 32 +#define GPO_SYS_IOMUX_U0_SYS_CRG_CLK_GMAC_PHY 33 +#define GPO_SYS_IOMUX_U0_SYS_CRG_I2SRX_BCLK_MST 34 +#define GPO_SYS_IOMUX_U0_SYS_CRG_I2SRX_LRCK_MST 35 +#define GPO_SYS_IOMUX_U0_SYS_CRG_I2STX_BCLK_MST 36 +#define GPO_SYS_IOMUX_U0_SYS_CRG_I2STX_LRCK_MST 37 +#define GPO_SYS_IOMUX_U0_SYS_CRG_MCLK_OUT 38 +#define GPO_SYS_IOMUX_U0_SYS_CRG_TDM_CLK_MST 39 +#define GPO_SYS_IOMUX_U0_TDM16SLOT_PCM_SYNCOUT 40 +#define GPO_SYS_IOMUX_U0_TDM16SLOT_PCM_TXD 41 +#define GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_0 42 +#define GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_1 43 +#define GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_2 44 +#define GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_3 45 +#define GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TREF 46 +#define GPO_SYS_IOMUX_U1_CAN_CTRL_STBY 47 +#define GPO_SYS_IOMUX_U1_CAN_CTRL_TST_NEXT_BIT 48 +#define GPO_SYS_IOMUX_U1_CAN_CTRL_TST_SAMPLE_POINT 49 +#define GPO_SYS_IOMUX_U1_CAN_CTRL_TXD 50 +#define GPO_SYS_IOMUX_U1_DW_I2C_IC_CLK_OUT_A 51 +#define GPO_SYS_IOMUX_U1_DW_I2C_IC_DATA_OUT_A 52 +#define GPO_SYS_IOMUX_U1_DW_SDIO_BACK_END_POWER 53 +#define GPO_SYS_IOMUX_U1_DW_SDIO_CARD_POWER_EN 54 +#define GPO_SYS_IOMUX_U1_DW_SDIO_CCLK_OUT 55 +#define GPO_SYS_IOMUX_U1_DW_SDIO_CCMD_OD_PULLUP_EN_N 56 +#define GPO_SYS_IOMUX_U1_DW_SDIO_CCMD_OUT 57 +#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_0 58 +#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_1 59 +#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_2 60 +#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_3 61 +#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_4 62 +#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_5 63 +#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_6 64 +#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_7 65 +#define GPO_SYS_IOMUX_U1_DW_SDIO_RST_N 66 +#define GPO_SYS_IOMUX_U1_DW_UART_RTS_N 67 +#define GPO_SYS_IOMUX_U1_DW_UART_SOUT 68 +#define GPO_SYS_IOMUX_U1_I2STX_4CH_SDO0 69 +#define GPO_SYS_IOMUX_U1_I2STX_4CH_SDO1 70 +#define GPO_SYS_IOMUX_U1_I2STX_4CH_SDO2 71 +#define GPO_SYS_IOMUX_U1_I2STX_4CH_SDO3 72 +#define GPO_SYS_IOMUX_U1_SSP_SPI_SSPCLKOUT 73 +#define GPO_SYS_IOMUX_U1_SSP_SPI_SSPFSSOUT 74 +#define GPO_SYS_IOMUX_U1_SSP_SPI_SSPTXD 75 +#define GPO_SYS_IOMUX_U2_DW_I2C_IC_CLK_OUT_A 76 +#define GPO_SYS_IOMUX_U2_DW_I2C_IC_DATA_OUT_A 77 +#define GPO_SYS_IOMUX_U2_DW_UART_RTS_N 78 +#define GPO_SYS_IOMUX_U2_DW_UART_SOUT 79 +#define GPO_SYS_IOMUX_U2_SSP_SPI_SSPCLKOUT 80 +#define GPO_SYS_IOMUX_U2_SSP_SPI_SSPFSSOUT 81 +#define GPO_SYS_IOMUX_U2_SSP_SPI_SSPTXD 82 +#define GPO_SYS_IOMUX_U3_DW_I2C_IC_CLK_OUT_A 83 +#define GPO_SYS_IOMUX_U3_DW_I2C_IC_DATA_OUT_A 84 +#define GPO_SYS_IOMUX_U3_DW_UART_SOUT 85 +#define GPO_SYS_IOMUX_U3_SSP_SPI_SSPCLKOUT 86 +#define GPO_SYS_IOMUX_U3_SSP_SPI_SSPFSSOUT 87 +#define GPO_SYS_IOMUX_U3_SSP_SPI_SSPTXD 88 +#define GPO_SYS_IOMUX_U4_DW_I2C_IC_CLK_OUT_A 89 +#define GPO_SYS_IOMUX_U4_DW_I2C_IC_DATA_OUT_A 90 +#define GPO_SYS_IOMUX_U4_DW_UART_RTS_N 91 +#define GPO_SYS_IOMUX_U4_DW_UART_SOUT 92 +#define GPO_SYS_IOMUX_U4_SSP_SPI_SSPCLKOUT 93 +#define GPO_SYS_IOMUX_U4_SSP_SPI_SSPFSSOUT 94 +#define GPO_SYS_IOMUX_U4_SSP_SPI_SSPTXD 95 +#define GPO_SYS_IOMUX_U5_DW_I2C_IC_CLK_OUT_A 96 +#define GPO_SYS_IOMUX_U5_DW_I2C_IC_DATA_OUT_A 97 +#define GPO_SYS_IOMUX_U5_DW_UART_RTS_N 98 +#define GPO_SYS_IOMUX_U5_DW_UART_SOUT 99 +#define GPO_SYS_IOMUX_U5_SSP_SPI_SSPCLKOUT 100 +#define GPO_SYS_IOMUX_U5_SSP_SPI_SSPFSSOUT 101 +#define GPO_SYS_IOMUX_U5_SSP_SPI_SSPTXD 102 +#define GPO_SYS_IOMUX_U6_DW_I2C_IC_CLK_OUT_A 103 +#define GPO_SYS_IOMUX_U6_DW_I2C_IC_DATA_OUT_A 104 +#define GPO_SYS_IOMUX_U6_SSP_SPI_SSPCLKOUT 105 +#define GPO_SYS_IOMUX_U6_SSP_SPI_SSPFSSOUT 106 +#define GPO_SYS_IOMUX_U6_SSP_SPI_SSPTXD 107 + +#define GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_OEN 2 +#define GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_OEN 3 +#define GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_OEN 4 +#define GPEN_SYS_IOMUX_U0_DW_I2C_IC_CLK_OE 5 +#define GPEN_SYS_IOMUX_U0_DW_I2C_IC_DATA_OE 6 +#define GPEN_SYS_IOMUX_U0_HIFI4_JTDOEN 7 +#define GPEN_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDO_OE 8 +#define GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_0 9 +#define GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_1 10 +#define GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_2 11 +#define GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_3 12 +#define GPEN_SYS_IOMUX_U0_SSP_SPI_NSSPCTLOE 13 +#define GPEN_SYS_IOMUX_U0_SSP_SPI_NSSPOE 14 +#define GPEN_SYS_IOMUX_U0_TDM16SLOT_NPCM_SYNCOE 15 +#define GPEN_SYS_IOMUX_U0_TDM16SLOT_NPCM_TXDOE 16 +#define GPEN_SYS_IOMUX_U1_DW_I2C_IC_CLK_OE 17 +#define GPEN_SYS_IOMUX_U1_DW_I2C_IC_DATA_OE 18 +#define GPEN_SYS_IOMUX_U1_DW_SDIO_CCMD_OUT_EN 19 +#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_0 20 +#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_1 21 +#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_2 22 +#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_3 23 +#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_4 24 +#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_5 25 +#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_6 26 +#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_7 27 +#define GPEN_SYS_IOMUX_U1_SSP_SPI_NSSPCTLOE 28 +#define GPEN_SYS_IOMUX_U1_SSP_SPI_NSSPOE 29 +#define GPEN_SYS_IOMUX_U2_DW_I2C_IC_CLK_OE 30 +#define GPEN_SYS_IOMUX_U2_DW_I2C_IC_DATA_OE 31 +#define GPEN_SYS_IOMUX_U2_SSP_SPI_NSSPCTLOE 32 +#define GPEN_SYS_IOMUX_U2_SSP_SPI_NSSPOE 33 +#define GPEN_SYS_IOMUX_U3_DW_I2C_IC_CLK_OE 34 +#define GPEN_SYS_IOMUX_U3_DW_I2C_IC_DATA_OE 35 +#define GPEN_SYS_IOMUX_U3_SSP_SPI_NSSPCTLOE 36 +#define GPEN_SYS_IOMUX_U3_SSP_SPI_NSSPOE 37 +#define GPEN_SYS_IOMUX_U4_DW_I2C_IC_CLK_OE 38 +#define GPEN_SYS_IOMUX_U4_DW_I2C_IC_DATA_OE 39 +#define GPEN_SYS_IOMUX_U4_SSP_SPI_NSSPCTLOE 40 +#define GPEN_SYS_IOMUX_U4_SSP_SPI_NSSPOE 41 +#define GPEN_SYS_IOMUX_U5_DW_I2C_IC_CLK_OE 42 +#define GPEN_SYS_IOMUX_U5_DW_I2C_IC_DATA_OE 43 +#define GPEN_SYS_IOMUX_U5_SSP_SPI_NSSPCTLOE 44 +#define GPEN_SYS_IOMUX_U5_SSP_SPI_NSSPOE 45 +#define GPEN_SYS_IOMUX_U6_DW_I2C_IC_CLK_OE 46 +#define GPEN_SYS_IOMUX_U6_DW_I2C_IC_DATA_OE 47 +#define GPEN_SYS_IOMUX_U6_SSP_SPI_NSSPCTLOE 48 +#define GPEN_SYS_IOMUX_U6_SSP_SPI_NSSPOE 49 + +#define GPI_SYS_IOMUX_U0_WAVE511_I_UART_RXSIN 0 +#define GPI_SYS_IOMUX_U0_CAN_CTRL_RXD 1 +#define GPI_SYS_IOMUX_U0_CDN_USB_OVERCURRENT_N_IO 2 +#define GPI_SYS_IOMUX_U0_CDNS_SPDIF_SPDIFI 3 +#define GPI_SYS_IOMUX_U0_CLKRST_SRC_BYPASS_JTAG_TRSTN 4 +#define GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_IN 5 +#define GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_IN 6 +#define GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_IN 7 +#define GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_HPD 8 +#define GPI_SYS_IOMUX_U0_DW_I2C_IC_CLK_IN_A 9 +#define GPI_SYS_IOMUX_U0_DW_I2C_IC_DATA_IN_A 10 +#define GPI_SYS_IOMUX_U0_DW_SDIO_CARD_DETECT_N 11 +#define GPI_SYS_IOMUX_U0_DW_SDIO_CARD_INT_N 12 +#define GPI_SYS_IOMUX_U0_DW_SDIO_CARD_WRITE_PRT 13 +#define GPI_SYS_IOMUX_U0_DW_UART_SIN 14 +#define GPI_SYS_IOMUX_U0_HIFI4_JTCK 15 +#define GPI_SYS_IOMUX_U0_HIFI4_JTDI 16 +#define GPI_SYS_IOMUX_U0_HIFI4_JTMS 17 +#define GPI_SYS_IOMUX_U0_HIFI4_JTRSTN 18 +#define GPI_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDI 19 +#define GPI_SYS_IOMUX_U0_JTAG_CERTIFICATION_TMS 20 +#define GPI_SYS_IOMUX_U0_PDM_4MIC_DMIC0_DIN 21 +#define GPI_SYS_IOMUX_U0_PDM_4MIC_DMIC1_DIN 22 +#define GPI_SYS_IOMUX_U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN0 23 +#define GPI_SYS_IOMUX_U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN1 24 +#define GPI_SYS_IOMUX_U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN2 25 +#define GPI_SYS_IOMUX_U0_SSP_SPI_SSPCLKIN 26 +#define GPI_SYS_IOMUX_U0_SSP_SPI_SSPFSSIN 27 +#define GPI_SYS_IOMUX_U0_SSP_SPI_SSPRXD 28 +#define GPI_SYS_IOMUX_U0_SYS_CRG_CLK_JTAG_TCK 29 +#define GPI_SYS_IOMUX_U0_SYS_CRG_EXT_MCLK 30 +#define GPI_SYS_IOMUX_U0_SYS_CRG_I2SRX_BCLK_SLV 31 +#define GPI_SYS_IOMUX_U0_SYS_CRG_I2SRX_LRCK_SLV 32 +#define GPI_SYS_IOMUX_U0_SYS_CRG_I2STX_BCLK_SLV 33 +#define GPI_SYS_IOMUX_U0_SYS_CRG_I2STX_LRCK_SLV 34 +#define GPI_SYS_IOMUX_U0_SYS_CRG_TDM_CLK_SLV 35 +#define GPI_SYS_IOMUX_U0_TDM16SLOT_PCM_RXD 36 +#define GPI_SYS_IOMUX_U0_TDM16SLOT_PCM_SYNCIN 37 +#define GPI_SYS_IOMUX_U1_CAN_CTRL_RXD 38 +#define GPI_SYS_IOMUX_U1_DW_I2C_IC_CLK_IN_A 39 +#define GPI_SYS_IOMUX_U1_DW_I2C_IC_DATA_IN_A 40 +#define GPI_SYS_IOMUX_U1_DW_SDIO_CARD_DETECT_N 41 +#define GPI_SYS_IOMUX_U1_DW_SDIO_CARD_INT_N 42 +#define GPI_SYS_IOMUX_U1_DW_SDIO_CARD_WRITE_PRT 43 +#define GPI_SYS_IOMUX_U1_DW_SDIO_CCMD_IN 44 +#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_0 45 +#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_1 46 +#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_2 47 +#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_3 48 +#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_4 49 +#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_5 50 +#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_6 51 +#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_7 52 +#define GPI_SYS_IOMUX_U1_DW_SDIO_DATA_STROBE 53 +#define GPI_SYS_IOMUX_U1_DW_UART_CTS_N 54 +#define GPI_SYS_IOMUX_U1_DW_UART_SIN 55 +#define GPI_SYS_IOMUX_U1_SSP_SPI_SSPCLKIN 56 +#define GPI_SYS_IOMUX_U1_SSP_SPI_SSPFSSIN 57 +#define GPI_SYS_IOMUX_U1_SSP_SPI_SSPRXD 58 +#define GPI_SYS_IOMUX_U2_DW_I2C_IC_CLK_IN_A 59 +#define GPI_SYS_IOMUX_U2_DW_I2C_IC_DATA_IN_A 60 +#define GPI_SYS_IOMUX_U2_DW_UART_CTS_N 61 +#define GPI_SYS_IOMUX_U2_DW_UART_SIN 62 +#define GPI_SYS_IOMUX_U2_SSP_SPI_SSPCLKIN 63 +#define GPI_SYS_IOMUX_U2_SSP_SPI_SSPFSSIN 64 +#define GPI_SYS_IOMUX_U2_SSP_SPI_SSPRXD 65 +#define GPI_SYS_IOMUX_U3_DW_I2C_IC_CLK_IN_A 66 +#define GPI_SYS_IOMUX_U3_DW_I2C_IC_DATA_IN_A 67 +#define GPI_SYS_IOMUX_U3_DW_UART_SIN 68 +#define GPI_SYS_IOMUX_U3_SSP_SPI_SSPCLKIN 69 +#define GPI_SYS_IOMUX_U3_SSP_SPI_SSPFSSIN 70 +#define GPI_SYS_IOMUX_U3_SSP_SPI_SSPRXD 71 +#define GPI_SYS_IOMUX_U4_DW_I2C_IC_CLK_IN_A 72 +#define GPI_SYS_IOMUX_U4_DW_I2C_IC_DATA_IN_A 73 +#define GPI_SYS_IOMUX_U4_DW_UART_CTS_N 74 +#define GPI_SYS_IOMUX_U4_DW_UART_SIN 75 +#define GPI_SYS_IOMUX_U4_SSP_SPI_SSPCLKIN 76 +#define GPI_SYS_IOMUX_U4_SSP_SPI_SSPFSSIN 77 +#define GPI_SYS_IOMUX_U4_SSP_SPI_SSPRXD 78 +#define GPI_SYS_IOMUX_U5_DW_I2C_IC_CLK_IN_A 79 +#define GPI_SYS_IOMUX_U5_DW_I2C_IC_DATA_IN_A 80 +#define GPI_SYS_IOMUX_U5_DW_UART_CTS_N 81 +#define GPI_SYS_IOMUX_U5_DW_UART_SIN 82 +#define GPI_SYS_IOMUX_U5_SSP_SPI_SSPCLKIN 83 +#define GPI_SYS_IOMUX_U5_SSP_SPI_SSPFSSIN 84 +#define GPI_SYS_IOMUX_U5_SSP_SPI_SSPRXD 85 +#define GPI_SYS_IOMUX_U6_DW_I2C_IC_CLK_IN_A 86 +#define GPI_SYS_IOMUX_U6_DW_I2C_IC_DATA_IN_A 87 +#define GPI_SYS_IOMUX_U6_SSP_SPI_SSPCLKIN 88 +#define GPI_SYS_IOMUX_U6_SSP_SPI_SSPFSSIN 89 +#define GPI_SYS_IOMUX_U6_SSP_SPI_SSPRXD 90 + +// gpo(n)_dout signal pool +#define GPO_LOW 0 +#define GPO_HIGH 1 +#define GPO_CAN0_CTRL_STBY \ + GPO_SYS_IOMUX_U0_CAN_CTRL_STBY +#define GPO_CAN0_CTRL_TST_NEXT_BIT \ + GPO_SYS_IOMUX_U0_CAN_CTRL_TST_NEXT_BIT +#define GPO_CAN0_CTRL_TST_SAMPLE_POINT \ + GPO_SYS_IOMUX_U0_CAN_CTRL_TST_SAMPLE_POINT +#define GPO_CAN0_CTRL_TXD \ + GPO_SYS_IOMUX_U0_CAN_CTRL_TXD +#define GPO_CAN1_CTRL_STBY \ + GPO_SYS_IOMUX_U1_CAN_CTRL_STBY +#define GPO_CAN1_CTRL_TST_NEXT_BIT \ + GPO_SYS_IOMUX_U1_CAN_CTRL_TST_NEXT_BIT +#define GPO_CAN1_CTRL_TST_SAMPLE_POINT \ + GPO_SYS_IOMUX_U1_CAN_CTRL_TST_SAMPLE_POINT +#define GPO_CAN1_CTRL_TXD \ + GPO_SYS_IOMUX_U1_CAN_CTRL_TXD +#define GPO_CRG0_MCLK_OUT \ + GPO_SYS_IOMUX_U0_SYS_CRG_MCLK_OUT +#define GPO_GMAC0_CLK_PHY \ + GPO_SYS_IOMUX_U0_SYS_CRG_CLK_GMAC_PHY +#define GPO_HDMI0_CEC_SDA_OUT \ + GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_OUT +#define GPO_HDMI0_DDC_SCL_OUT \ + GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_OUT +#define GPO_HDMI0_DDC_SDA_OUT \ + GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_OUT +#define GPO_I2C0_IC_CLK_OUT_A \ + GPO_SYS_IOMUX_U0_DW_I2C_IC_CLK_OUT_A +#define GPO_I2C0_IC_DATA_OUT_A \ + GPO_SYS_IOMUX_U0_DW_I2C_IC_DATA_OUT_A +#define GPO_I2C1_IC_CLK_OUT_A \ + GPO_SYS_IOMUX_U1_DW_I2C_IC_CLK_OUT_A +#define GPO_I2C1_IC_DATA_OUT_A \ + GPO_SYS_IOMUX_U1_DW_I2C_IC_DATA_OUT_A +#define GPO_I2C2_IC_CLK_OUT_A \ + GPO_SYS_IOMUX_U2_DW_I2C_IC_CLK_OUT_A +#define GPO_I2C2_IC_DATA_OUT_A \ + GPO_SYS_IOMUX_U2_DW_I2C_IC_DATA_OUT_A +#define GPO_I2C3_IC_CLK_OUT_A \ + GPO_SYS_IOMUX_U3_DW_I2C_IC_CLK_OUT_A +#define GPO_I2C3_IC_DATA_OUT_A \ + GPO_SYS_IOMUX_U3_DW_I2C_IC_DATA_OUT_A +#define GPO_I2C4_IC_CLK_OUT_A \ + GPO_SYS_IOMUX_U4_DW_I2C_IC_CLK_OUT_A +#define GPO_I2C4_IC_DATA_OUT_A \ + GPO_SYS_IOMUX_U4_DW_I2C_IC_DATA_OUT_A +#define GPO_I2C5_IC_CLK_OUT_A \ + GPO_SYS_IOMUX_U5_DW_I2C_IC_CLK_OUT_A +#define GPO_I2C5_IC_DATA_OUT_A \ + GPO_SYS_IOMUX_U5_DW_I2C_IC_DATA_OUT_A +#define GPO_I2C6_IC_CLK_OUT_A \ + GPO_SYS_IOMUX_U6_DW_I2C_IC_CLK_OUT_A +#define GPO_I2C6_IC_DATA_OUT_A \ + GPO_SYS_IOMUX_U6_DW_I2C_IC_DATA_OUT_A +#define GPO_I2SRX0_BCLK_MST \ + GPO_SYS_IOMUX_U0_SYS_CRG_I2SRX_BCLK_MST +#define GPO_I2SRX0_LRCK_MST \ + GPO_SYS_IOMUX_U0_SYS_CRG_I2SRX_LRCK_MST +#define GPO_I2STX_4CH1_SDO0 \ + GPO_SYS_IOMUX_U1_I2STX_4CH_SDO0 +#define GPO_I2STX_4CH1_SDO1 \ + GPO_SYS_IOMUX_U1_I2STX_4CH_SDO1 +#define GPO_I2STX_4CH1_SDO2 \ + GPO_SYS_IOMUX_U1_I2STX_4CH_SDO2 +#define GPO_I2STX_4CH1_SDO3 \ + GPO_SYS_IOMUX_U1_I2STX_4CH_SDO3 +#define GPO_I2STX0_BCLK_MST \ + GPO_SYS_IOMUX_U0_SYS_CRG_I2STX_BCLK_MST +#define GPO_I2STX0_LRCK_MST \ + GPO_SYS_IOMUX_U0_SYS_CRG_I2STX_LRCK_MST +#define GPO_JTAG_CPU_CERTIFICATION_TDO \ + GPO_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDO +#define GPO_JTAG_DSP_TDO \ + GPO_SYS_IOMUX_U0_HIFI4_JTDO +#define GPO_PDM_4MIC0_DMIC_MCLK \ + GPO_SYS_IOMUX_U0_PDM_4MIC_DMIC_MCLK +#define GPO_PTC0_PWM_0 \ + GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_0 +#define GPO_PTC0_PWM_1 \ + GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_1 +#define GPO_PTC0_PWM_2 \ + GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_2 +#define GPO_PTC0_PWM_3 \ + GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_3 +#define GPO_PWMDAC0_LEFT_OUTPUT \ + GPO_SYS_IOMUX_U0_PWMDAC_PWMDAC_LEFT_OUTPUT +#define GPO_PWMDAC0_RIGHT_OUTPUT \ + GPO_SYS_IOMUX_U0_PWMDAC_PWMDAC_RIGHT_OUTPUT +#define GPO_QSPI0_CSN1 \ + GPO_SYS_IOMUX_U0_CDNS_QSPI_CSN1 +#define GPO_SDIO0_BACK_END_POWER \ + GPO_SYS_IOMUX_U0_DW_SDIO_BACK_END_POWER +#define GPO_SDIO0_CARD_POWER_EN \ + GPO_SYS_IOMUX_U0_DW_SDIO_CARD_POWER_EN +#define GPO_SDIO0_CCMD_OD_PULLUP_EN_N \ + GPO_SYS_IOMUX_U0_DW_SDIO_CCMD_OD_PULLUP_EN_N +#define GPO_SDIO0_RST_N \ + GPO_SYS_IOMUX_U0_DW_SDIO_RST_N +#define GPO_SDIO1_BACK_END_POWER \ + GPO_SYS_IOMUX_U1_DW_SDIO_BACK_END_POWER +#define GPO_SDIO1_CARD_POWER_EN \ + GPO_SYS_IOMUX_U1_DW_SDIO_CARD_POWER_EN +#define GPO_SDIO1_CCLK_OUT \ + GPO_SYS_IOMUX_U1_DW_SDIO_CCLK_OUT +#define GPO_SDIO1_CCMD_OD_PULLUP_EN_N \ + GPO_SYS_IOMUX_U1_DW_SDIO_CCMD_OD_PULLUP_EN_N +#define GPO_SDIO1_CCMD_OUT \ + GPO_SYS_IOMUX_U1_DW_SDIO_CCMD_OUT +#define GPO_SDIO1_CDATA_OUT_0 \ + GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_0 +#define GPO_SDIO1_CDATA_OUT_1 \ + GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_1 +#define GPO_SDIO1_CDATA_OUT_2 \ + GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_2 +#define GPO_SDIO1_CDATA_OUT_3 \ + GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_3 +#define GPO_SDIO1_CDATA_OUT_4 \ + GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_4 +#define GPO_SDIO1_CDATA_OUT_5 \ + GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_5 +#define GPO_SDIO1_CDATA_OUT_6 \ + GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_6 +#define GPO_SDIO1_CDATA_OUT_7 \ + GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_7 +#define GPO_SDIO1_RST_N \ + GPO_SYS_IOMUX_U1_DW_SDIO_RST_N +#define GPO_SPDIF0_SPDIFO \ + GPO_SYS_IOMUX_U0_CDNS_SPDIF_SPDIFO +#define GPO_SPI0_SSPCLKOUT \ + GPO_SYS_IOMUX_U0_SSP_SPI_SSPCLKOUT +#define GPO_SPI0_SSPFSSOUT \ + GPO_SYS_IOMUX_U0_SSP_SPI_SSPFSSOUT +#define GPO_SPI0_SSPTXD \ + GPO_SYS_IOMUX_U0_SSP_SPI_SSPTXD +#define GPO_SPI1_SSPCLKOUT \ + GPO_SYS_IOMUX_U1_SSP_SPI_SSPCLKOUT +#define GPO_SPI1_SSPFSSOUT \ + GPO_SYS_IOMUX_U1_SSP_SPI_SSPFSSOUT +#define GPO_SPI1_SSPTXD \ + GPO_SYS_IOMUX_U1_SSP_SPI_SSPTXD +#define GPO_SPI2_SSPCLKOUT \ + GPO_SYS_IOMUX_U2_SSP_SPI_SSPCLKOUT +#define GPO_SPI2_SSPFSSOUT \ + GPO_SYS_IOMUX_U2_SSP_SPI_SSPFSSOUT +#define GPO_SPI2_SSPTXD \ + GPO_SYS_IOMUX_U2_SSP_SPI_SSPTXD +#define GPO_SPI3_SSPCLKOUT \ + GPO_SYS_IOMUX_U3_SSP_SPI_SSPCLKOUT +#define GPO_SPI3_SSPFSSOUT \ + GPO_SYS_IOMUX_U3_SSP_SPI_SSPFSSOUT +#define GPO_SPI3_SSPTXD \ + GPO_SYS_IOMUX_U3_SSP_SPI_SSPTXD +#define GPO_SPI4_SSPCLKOUT \ + GPO_SYS_IOMUX_U4_SSP_SPI_SSPCLKOUT +#define GPO_SPI4_SSPFSSOUT \ + GPO_SYS_IOMUX_U4_SSP_SPI_SSPFSSOUT +#define GPO_SPI4_SSPTXD \ + GPO_SYS_IOMUX_U4_SSP_SPI_SSPTXD +#define GPO_SPI5_SSPCLKOUT \ + GPO_SYS_IOMUX_U5_SSP_SPI_SSPCLKOUT +#define GPO_SPI5_SSPFSSOUT \ + GPO_SYS_IOMUX_U5_SSP_SPI_SSPFSSOUT +#define GPO_SPI5_SSPTXD \ + GPO_SYS_IOMUX_U5_SSP_SPI_SSPTXD +#define GPO_SPI6_SSPCLKOUT \ + GPO_SYS_IOMUX_U6_SSP_SPI_SSPCLKOUT +#define GPO_SPI6_SSPFSSOUT \ + GPO_SYS_IOMUX_U6_SSP_SPI_SSPFSSOUT +#define GPO_SPI6_SSPTXD \ + GPO_SYS_IOMUX_U6_SSP_SPI_SSPTXD +#define GPO_TDM0_CLK_MST \ + GPO_SYS_IOMUX_U0_SYS_CRG_TDM_CLK_MST +#define GPO_TDM0_PCM_SYNCOUT \ + GPO_SYS_IOMUX_U0_TDM16SLOT_PCM_SYNCOUT +#define GPO_TDM0_PCM_TXD \ + GPO_SYS_IOMUX_U0_TDM16SLOT_PCM_TXD +#define GPO_U7MC_TRACE0_TDATA_0 \ + GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_0 +#define GPO_U7MC_TRACE0_TDATA_1 \ + GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_1 +#define GPO_U7MC_TRACE0_TDATA_2 \ + GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_2 +#define GPO_U7MC_TRACE0_TDATA_3 \ + GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_3 +#define GPO_U7MC_TRACE0_TREF \ + GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TREF +#define GPO_UART0_SOUT \ + GPO_SYS_IOMUX_U0_DW_UART_SOUT +#define GPO_UART1_RTS_N \ + GPO_SYS_IOMUX_U1_DW_UART_RTS_N +#define GPO_UART1_SOUT \ + GPO_SYS_IOMUX_U1_DW_UART_SOUT +#define GPO_UART2_RTS_N \ + GPO_SYS_IOMUX_U2_DW_UART_RTS_N +#define GPO_UART2_SOUT \ + GPO_SYS_IOMUX_U2_DW_UART_SOUT +#define GPO_UART3_SOUT \ + GPO_SYS_IOMUX_U3_DW_UART_SOUT +#define GPO_UART4_RTS_N \ + GPO_SYS_IOMUX_U4_DW_UART_RTS_N +#define GPO_UART4_SOUT \ + GPO_SYS_IOMUX_U4_DW_UART_SOUT +#define GPO_UART5_RTS_N \ + GPO_SYS_IOMUX_U5_DW_UART_RTS_N +#define GPO_UART5_SOUT \ + GPO_SYS_IOMUX_U5_DW_UART_SOUT +#define GPO_USB0_DRIVE_VBUS_IO \ + GPO_SYS_IOMUX_U0_CDN_USB_DRIVE_VBUS_IO +#define GPO_WAVE511_0_O_UART_TXSOUT \ + GPO_SYS_IOMUX_U0_WAVE511_O_UART_TXSOUT +#define GPO_WDT0_WDOGRES \ + GPO_SYS_IOMUX_U0_DSKIT_WDT_WDOGRES +#define GPO_NONE \ + GPO_SYS_IOMUX_U6_SSP_SPI_SSPTXD + 1 + +// gpo(n)_doen signal pool +#define OEN_LOW 0 +#define OEN_HIGH 1 +#define OEN_HDMI0_CEC_SDA_OEN \ + GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_OEN +#define OEN_HDMI0_DDC_SCL_OEN \ + GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_OEN +#define OEN_HDMI0_DDC_SDA_OEN \ + GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_OEN +#define OEN_I2C0_IC_CLK_OE \ + GPEN_SYS_IOMUX_U0_DW_I2C_IC_CLK_OE +#define OEN_I2C0_IC_DATA_OE \ + GPEN_SYS_IOMUX_U0_DW_I2C_IC_DATA_OE +#define OEN_I2C1_IC_CLK_OE \ + GPEN_SYS_IOMUX_U1_DW_I2C_IC_CLK_OE +#define OEN_I2C1_IC_DATA_OE \ + GPEN_SYS_IOMUX_U1_DW_I2C_IC_DATA_OE +#define OEN_I2C2_IC_CLK_OE \ + GPEN_SYS_IOMUX_U2_DW_I2C_IC_CLK_OE +#define OEN_I2C2_IC_DATA_OE \ + GPEN_SYS_IOMUX_U2_DW_I2C_IC_DATA_OE +#define OEN_I2C3_IC_CLK_OE \ + GPEN_SYS_IOMUX_U3_DW_I2C_IC_CLK_OE +#define OEN_I2C3_IC_DATA_OE \ + GPEN_SYS_IOMUX_U3_DW_I2C_IC_DATA_OE +#define OEN_I2C4_IC_CLK_OE \ + GPEN_SYS_IOMUX_U4_DW_I2C_IC_CLK_OE +#define OEN_I2C4_IC_DATA_OE \ + GPEN_SYS_IOMUX_U4_DW_I2C_IC_DATA_OE +#define OEN_I2C5_IC_CLK_OE \ + GPEN_SYS_IOMUX_U5_DW_I2C_IC_CLK_OE +#define OEN_I2C5_IC_DATA_OE \ + GPEN_SYS_IOMUX_U5_DW_I2C_IC_DATA_OE +#define OEN_I2C6_IC_CLK_OE \ + GPEN_SYS_IOMUX_U6_DW_I2C_IC_CLK_OE +#define OEN_I2C6_IC_DATA_OE \ + GPEN_SYS_IOMUX_U6_DW_I2C_IC_DATA_OE +#define OEN_JTAG_CPU_CERTIFICATION_TDO_OE \ + GPEN_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDO_OE +#define OEN_JTAG_DSP_TDO_OEN \ + GPEN_SYS_IOMUX_U0_HIFI4_JTDOEN +#define OEN_PTC0_PWM_0_OE_N \ + GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_0 +#define OEN_PTC0_PWM_1_OE_N \ + GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_1 +#define OEN_PTC0_PWM_2_OE_N \ + GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_2 +#define OEN_PTC0_PWM_3_OE_N \ + GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_3 +#define OEN_SDIO1_CCMD_OUT_EN \ + GPEN_SYS_IOMUX_U1_DW_SDIO_CCMD_OUT_EN +#define OEN_SDIO1_CDATA_OUT_EN_0 \ + GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_0 +#define OEN_SDIO1_CDATA_OUT_EN_1 \ + GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_1 +#define OEN_SDIO1_CDATA_OUT_EN_2 \ + GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_2 +#define OEN_SDIO1_CDATA_OUT_EN_3 \ + GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_3 +#define OEN_SDIO1_CDATA_OUT_EN_4 \ + GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_4 +#define OEN_SDIO1_CDATA_OUT_EN_5 \ + GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_5 +#define OEN_SDIO1_CDATA_OUT_EN_6 \ + GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_6 +#define OEN_SDIO1_CDATA_OUT_EN_7 \ + GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_7 +#define OEN_SPI0_NSSPCTLOE \ + GPEN_SYS_IOMUX_U0_SSP_SPI_NSSPCTLOE +#define OEN_SPI0_NSSPOE \ + GPEN_SYS_IOMUX_U0_SSP_SPI_NSSPOE +#define OEN_SPI1_NSSPCTLOE \ + GPEN_SYS_IOMUX_U1_SSP_SPI_NSSPCTLOE +#define OEN_SPI1_NSSPOE \ + GPEN_SYS_IOMUX_U1_SSP_SPI_NSSPOE +#define OEN_SPI2_NSSPCTLOE \ + GPEN_SYS_IOMUX_U2_SSP_SPI_NSSPCTLOE +#define OEN_SPI2_NSSPOE \ + GPEN_SYS_IOMUX_U2_SSP_SPI_NSSPOE +#define OEN_SPI3_NSSPCTLOE \ + GPEN_SYS_IOMUX_U3_SSP_SPI_NSSPCTLOE +#define OEN_SPI3_NSSPOE \ + GPEN_SYS_IOMUX_U3_SSP_SPI_NSSPOE +#define OEN_SPI4_NSSPCTLOE \ + GPEN_SYS_IOMUX_U4_SSP_SPI_NSSPCTLOE +#define OEN_SPI4_NSSPOE \ + GPEN_SYS_IOMUX_U4_SSP_SPI_NSSPOE +#define OEN_SPI5_NSSPCTLOE \ + GPEN_SYS_IOMUX_U5_SSP_SPI_NSSPCTLOE +#define OEN_SPI5_NSSPOE \ + GPEN_SYS_IOMUX_U5_SSP_SPI_NSSPOE +#define OEN_SPI6_NSSPCTLOE \ + GPEN_SYS_IOMUX_U6_SSP_SPI_NSSPCTLOE +#define OEN_SPI6_NSSPOE \ + GPEN_SYS_IOMUX_U6_SSP_SPI_NSSPOE +#define OEN_TDM0_NPCM_SYNCOE \ + GPEN_SYS_IOMUX_U0_TDM16SLOT_NPCM_SYNCOE +#define OEN_TDM0_NPCM_TXDOE \ + GPEN_SYS_IOMUX_U0_TDM16SLOT_NPCM_TXDOE +#define OEN_NONE \ + GPEN_SYS_IOMUX_U6_SSP_SPI_NSSPOE + 1 + +// sys_iomux gpi din +#define GPI_CAN0_CTRL_RXD \ + GPI_SYS_IOMUX_U0_CAN_CTRL_RXD +#define GPI_CAN1_CTRL_RXD \ + GPI_SYS_IOMUX_U1_CAN_CTRL_RXD +#define GPI_CRG0_EXT_MCLK \ + GPI_SYS_IOMUX_U0_SYS_CRG_EXT_MCLK +#define GPI_HDMI0_CEC_SDA_IN \ + GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_IN +#define GPI_HDMI0_DDC_SCL_IN \ + GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_IN +#define GPI_HDMI0_DDC_SDA_IN \ + GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_IN +#define GPI_HDMI0_HPD \ + GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_HPD +#define GPI_I2C0_IC_CLK_IN_A \ + GPI_SYS_IOMUX_U0_DW_I2C_IC_CLK_IN_A +#define GPI_I2C0_IC_DATA_IN_A \ + GPI_SYS_IOMUX_U0_DW_I2C_IC_DATA_IN_A +#define GPI_I2C1_IC_CLK_IN_A \ + GPI_SYS_IOMUX_U1_DW_I2C_IC_CLK_IN_A +#define GPI_I2C1_IC_DATA_IN_A \ + GPI_SYS_IOMUX_U1_DW_I2C_IC_DATA_IN_A +#define GPI_I2C2_IC_CLK_IN_A \ + GPI_SYS_IOMUX_U2_DW_I2C_IC_CLK_IN_A +#define GPI_I2C2_IC_DATA_IN_A \ + GPI_SYS_IOMUX_U2_DW_I2C_IC_DATA_IN_A +#define GPI_I2C3_IC_CLK_IN_A \ + GPI_SYS_IOMUX_U3_DW_I2C_IC_CLK_IN_A +#define GPI_I2C3_IC_DATA_IN_A \ + GPI_SYS_IOMUX_U3_DW_I2C_IC_DATA_IN_A +#define GPI_I2C4_IC_CLK_IN_A \ + GPI_SYS_IOMUX_U4_DW_I2C_IC_CLK_IN_A +#define GPI_I2C4_IC_DATA_IN_A \ + GPI_SYS_IOMUX_U4_DW_I2C_IC_DATA_IN_A +#define GPI_I2C5_IC_CLK_IN_A \ + GPI_SYS_IOMUX_U5_DW_I2C_IC_CLK_IN_A +#define GPI_I2C5_IC_DATA_IN_A \ + GPI_SYS_IOMUX_U5_DW_I2C_IC_DATA_IN_A +#define GPI_I2C6_IC_CLK_IN_A \ + GPI_SYS_IOMUX_U6_DW_I2C_IC_CLK_IN_A +#define GPI_I2C6_IC_DATA_IN_A \ + GPI_SYS_IOMUX_U6_DW_I2C_IC_DATA_IN_A +#define GPI_I2SRX0_BCLK_SLV \ + GPI_SYS_IOMUX_U0_SYS_CRG_I2SRX_BCLK_SLV +#define GPI_I2SRX0_EXT_SDIN0 \ + GPI_SYS_IOMUX_U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN0 +#define GPI_I2SRX0_EXT_SDIN1 \ + GPI_SYS_IOMUX_U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN1 +#define GPI_I2SRX0_EXT_SDIN2 \ + GPI_SYS_IOMUX_U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN2 +#define GPI_I2SRX0_LRCK_SLV \ + GPI_SYS_IOMUX_U0_SYS_CRG_I2SRX_LRCK_SLV +#define GPI_I2STX0_BCLK_SLV \ + GPI_SYS_IOMUX_U0_SYS_CRG_I2STX_BCLK_SLV +#define GPI_I2STX0_LRCK_SLV \ + GPI_SYS_IOMUX_U0_SYS_CRG_I2STX_LRCK_SLV +#define GPI_JTAG_CPU_CERTIFICATION_BYPASS_TRSTN \ + GPI_SYS_IOMUX_U0_CLKRST_SRC_BYPASS_JTAG_TRSTN +#define GPI_JTAG_CPU_CERTIFICATION_TCK \ + GPI_SYS_IOMUX_U0_SYS_CRG_CLK_JTAG_TCK +#define GPI_JTAG_CPU_CERTIFICATION_TDI \ + GPI_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDI +#define GPI_JTAG_CPU_CERTIFICATION_TMS \ + GPI_SYS_IOMUX_U0_JTAG_CERTIFICATION_TMS +#define GPI_JTAG_DSP_TCK \ + GPI_SYS_IOMUX_U0_HIFI4_JTCK +#define GPI_JTAG_DSP_TDI \ + GPI_SYS_IOMUX_U0_HIFI4_JTDI +#define GPI_JTAG_DSP_TMS \ + GPI_SYS_IOMUX_U0_HIFI4_JTMS +#define GPI_JTAG_DSP_TRST_N \ + GPI_SYS_IOMUX_U0_HIFI4_JTRSTN +#define GPI_PDM_4MIC0_DMIC0_DIN \ + GPI_SYS_IOMUX_U0_PDM_4MIC_DMIC0_DIN +#define GPI_PDM_4MIC0_DMIC1_DIN \ + GPI_SYS_IOMUX_U0_PDM_4MIC_DMIC1_DIN +#define GPI_SDIO0_CARD_DETECT_N \ + GPI_SYS_IOMUX_U0_DW_SDIO_CARD_DETECT_N +#define GPI_SDIO0_CARD_INT_N \ + GPI_SYS_IOMUX_U0_DW_SDIO_CARD_INT_N +#define GPI_SDIO0_CARD_WRITE_PRT \ + GPI_SYS_IOMUX_U0_DW_SDIO_CARD_WRITE_PRT +#define GPI_SDIO1_CARD_DETECT_N \ + GPI_SYS_IOMUX_U1_DW_SDIO_CARD_DETECT_N +#define GPI_SDIO1_CARD_INT_N \ + GPI_SYS_IOMUX_U1_DW_SDIO_CARD_INT_N +#define GPI_SDIO1_CARD_WRITE_PRT \ + GPI_SYS_IOMUX_U1_DW_SDIO_CARD_WRITE_PRT +#define GPI_SDIO1_CCMD_IN \ + GPI_SYS_IOMUX_U1_DW_SDIO_CCMD_IN +#define GPI_SDIO1_CDATA_IN_0 \ + GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_0 +#define GPI_SDIO1_CDATA_IN_1 \ + GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_1 +#define GPI_SDIO1_CDATA_IN_2 \ + GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_2 +#define GPI_SDIO1_CDATA_IN_3 \ + GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_3 +#define GPI_SDIO1_CDATA_IN_4 \ + GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_4 +#define GPI_SDIO1_CDATA_IN_5 \ + GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_5 +#define GPI_SDIO1_CDATA_IN_6 \ + GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_6 +#define GPI_SDIO1_CDATA_IN_7 \ + GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_7 +#define GPI_SDIO1_DATA_STROBE \ + GPI_SYS_IOMUX_U1_DW_SDIO_DATA_STROBE +#define GPI_SPDIF0_SPDIFI \ + GPI_SYS_IOMUX_U0_CDNS_SPDIF_SPDIFI +#define GPI_SPI0_SSPCLKIN \ + GPI_SYS_IOMUX_U0_SSP_SPI_SSPCLKIN +#define GPI_SPI0_SSPFSSIN \ + GPI_SYS_IOMUX_U0_SSP_SPI_SSPFSSIN +#define GPI_SPI0_SSPRXD \ + GPI_SYS_IOMUX_U0_SSP_SPI_SSPRXD +#define GPI_SPI1_SSPCLKIN \ + GPI_SYS_IOMUX_U1_SSP_SPI_SSPCLKIN +#define GPI_SPI1_SSPFSSIN \ + GPI_SYS_IOMUX_U1_SSP_SPI_SSPFSSIN +#define GPI_SPI1_SSPRXD \ + GPI_SYS_IOMUX_U1_SSP_SPI_SSPRXD +#define GPI_SPI2_SSPCLKIN \ + GPI_SYS_IOMUX_U2_SSP_SPI_SSPCLKIN +#define GPI_SPI2_SSPFSSIN \ + GPI_SYS_IOMUX_U2_SSP_SPI_SSPFSSIN +#define GPI_SPI2_SSPRXD \ + GPI_SYS_IOMUX_U2_SSP_SPI_SSPRXD +#define GPI_SPI3_SSPCLKIN \ + GPI_SYS_IOMUX_U3_SSP_SPI_SSPCLKIN +#define GPI_SPI3_SSPFSSIN \ + GPI_SYS_IOMUX_U3_SSP_SPI_SSPFSSIN +#define GPI_SPI3_SSPRXD \ + GPI_SYS_IOMUX_U3_SSP_SPI_SSPRXD +#define GPI_SPI4_SSPCLKIN \ + GPI_SYS_IOMUX_U4_SSP_SPI_SSPCLKIN +#define GPI_SPI4_SSPFSSIN \ + GPI_SYS_IOMUX_U4_SSP_SPI_SSPFSSIN +#define GPI_SPI4_SSPRXD \ + GPI_SYS_IOMUX_U4_SSP_SPI_SSPRXD +#define GPI_SPI5_SSPCLKIN \ + GPI_SYS_IOMUX_U5_SSP_SPI_SSPCLKIN +#define GPI_SPI5_SSPFSSIN \ + GPI_SYS_IOMUX_U5_SSP_SPI_SSPFSSIN +#define GPI_SPI5_SSPRXD \ + GPI_SYS_IOMUX_U5_SSP_SPI_SSPRXD +#define GPI_SPI6_SSPCLKIN \ + GPI_SYS_IOMUX_U6_SSP_SPI_SSPCLKIN +#define GPI_SPI6_SSPFSSIN \ + GPI_SYS_IOMUX_U6_SSP_SPI_SSPFSSIN +#define GPI_SPI6_SSPRXD \ + GPI_SYS_IOMUX_U6_SSP_SPI_SSPRXD +#define GPI_TDM0_CLK_SLV \ + GPI_SYS_IOMUX_U0_SYS_CRG_TDM_CLK_SLV +#define GPI_TDM0_PCM_RXD \ + GPI_SYS_IOMUX_U0_TDM16SLOT_PCM_RXD +#define GPI_TDM0_PCM_SYNCIN \ + GPI_SYS_IOMUX_U0_TDM16SLOT_PCM_SYNCIN +#define GPI_UART0_SIN \ + GPI_SYS_IOMUX_U0_DW_UART_SIN +#define GPI_UART1_CTS_N \ + GPI_SYS_IOMUX_U1_DW_UART_CTS_N +#define GPI_UART1_SIN \ + GPI_SYS_IOMUX_U1_DW_UART_SIN +#define GPI_UART2_CTS_N \ + GPI_SYS_IOMUX_U2_DW_UART_CTS_N +#define GPI_UART2_SIN \ + GPI_SYS_IOMUX_U2_DW_UART_SIN +#define GPI_UART3_SIN \ + GPI_SYS_IOMUX_U3_DW_UART_SIN +#define GPI_UART4_CTS_N \ + GPI_SYS_IOMUX_U4_DW_UART_CTS_N +#define GPI_UART4_SIN \ + GPI_SYS_IOMUX_U4_DW_UART_SIN +#define GPI_UART5_CTS_N \ + GPI_SYS_IOMUX_U5_DW_UART_CTS_N +#define GPI_UART5_SIN \ + GPI_SYS_IOMUX_U5_DW_UART_SIN +#define GPI_USB0_OVERCURRENT_N_IO \ + GPI_SYS_IOMUX_U0_CDN_USB_OVERCURRENT_N_IO +#define GPI_WAVE511_0_I_UART_RXSIN \ + GPI_SYS_IOMUX_U0_WAVE511_I_UART_RXSIN +#define GPI_NONE GPI_SYS_IOMUX_U6_SSP_SPI_SSPRXD + +// sys_iomux syscon +#define SYS_IOMUX_CFG__SAIF__SYSCFG_588_ADDR (0x24cU) +#define SYS_IOMUX_CFG__SAIF__SYSCFG_592_ADDR (0x250U) +#define SYS_IOMUX_CFG__SAIF__SYSCFG_596_ADDR (0x254U) +#define SYS_IOMUX_CFG__SAIF__SYSCFG_600_ADDR (0x258U) +#define SYS_IOMUX_CFG__SAIF__SYSCFG_604_ADDR (0x25cU) +#define SYS_IOMUX_CFG__SAIF__SYSCFG_608_ADDR (0x260U) +#define SYS_IOMUX_CFG__SAIF__SYSCFG_612_ADDR (0x264U) +#define SYS_IOMUX_CFG__SAIF__SYSCFG_616_ADDR (0x268U) +#define SYS_IOMUX_CFG__SAIF__SYSCFG_620_ADDR (0x26cU) +#define SYS_IOMUX_CFG__SAIF__SYSCFG_624_ADDR (0x270U) +#define SYS_IOMUX_CFG__SAIF__SYSCFG_628_ADDR (0x274U) +#define SYS_IOMUX_CFG__SAIF__SYSCFG_632_ADDR (0x278U) +#define SYS_IOMUX_CFG__SAIF__SYSCFG_636_ADDR (0x27cU) +#define SYS_IOMUX_CFG__SAIF__SYSCFG_640_ADDR (0x280U) + +#define PADCFG_PAD_GMAC1_MDC_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_588_ADDR +#define PADCFG_PAD_GMAC1_MDIO_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_592_ADDR +#define PADCFG_PAD_GMAC1_RXD0_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_596_ADDR +#define PADCFG_PAD_GMAC1_RXD1_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_600_ADDR +#define PADCFG_PAD_GMAC1_RXD2_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_604_ADDR +#define PADCFG_PAD_GMAC1_RXD3_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_608_ADDR +#define PADCFG_PAD_GMAC1_RXDV_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_612_ADDR +#define PADCFG_PAD_GMAC1_RXC_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_616_ADDR +#define PADCFG_PAD_GMAC1_TXD0_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_620_ADDR +#define PADCFG_PAD_GMAC1_TXD1_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_624_ADDR +#define PADCFG_PAD_GMAC1_TXD2_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_628_ADDR +#define PADCFG_PAD_GMAC1_TXD3_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_632_ADDR +#define PADCFG_PAD_GMAC1_TXEN_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_636_ADDR +#define PADCFG_PAD_GMAC1_TXC_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_640_ADDR + +// sys_iomux func sel setting +#define SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR (0x29cU) +#define PAD_GMAC1_RXC_FUNC_SEL_WIDTH 0x2U +#define PAD_GMAC1_RXC_FUNC_SEL_SHIFT 0x0U +#define PAD_GMAC1_RXC_FUNC_SEL_MASK 0x3U +#define PAD_GPIO10_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO10_FUNC_SEL_SHIFT 0x2U +#define PAD_GPIO10_FUNC_SEL_MASK 0x1CU +#define PAD_GPIO11_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO11_FUNC_SEL_SHIFT 0x5U +#define PAD_GPIO11_FUNC_SEL_MASK 0xE0U +#define PAD_GPIO12_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO12_FUNC_SEL_SHIFT 0x8U +#define PAD_GPIO12_FUNC_SEL_MASK 0x700U +#define PAD_GPIO13_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO13_FUNC_SEL_SHIFT 0xBU +#define PAD_GPIO13_FUNC_SEL_MASK 0x3800U +#define PAD_GPIO14_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO14_FUNC_SEL_SHIFT 0xEU +#define PAD_GPIO14_FUNC_SEL_MASK 0x1C000U +#define PAD_GPIO15_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO15_FUNC_SEL_SHIFT 0x11U +#define PAD_GPIO15_FUNC_SEL_MASK 0xE0000U +#define PAD_GPIO16_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO16_FUNC_SEL_SHIFT 0x14U +#define PAD_GPIO16_FUNC_SEL_MASK 0x700000U +#define PAD_GPIO17_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO17_FUNC_SEL_SHIFT 0x17U +#define PAD_GPIO17_FUNC_SEL_MASK 0x3800000U +#define PAD_GPIO18_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO18_FUNC_SEL_SHIFT 0x1AU +#define PAD_GPIO18_FUNC_SEL_MASK 0x1C000000U +#define PAD_GPIO19_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO19_FUNC_SEL_SHIFT 0x1DU +#define PAD_GPIO19_FUNC_SEL_MASK 0xE0000000U +#define SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR (0x2a0U) +#define PAD_GPIO20_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO20_FUNC_SEL_SHIFT 0x0U +#define PAD_GPIO20_FUNC_SEL_MASK 0x7U +#define PAD_GPIO21_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO21_FUNC_SEL_SHIFT 0x3U +#define PAD_GPIO21_FUNC_SEL_MASK 0x38U +#define PAD_GPIO22_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO22_FUNC_SEL_SHIFT 0x6U +#define PAD_GPIO22_FUNC_SEL_MASK 0x1C0U +#define PAD_GPIO23_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO23_FUNC_SEL_SHIFT 0x9U +#define PAD_GPIO23_FUNC_SEL_MASK 0xE00U +#define PAD_GPIO24_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO24_FUNC_SEL_SHIFT 0xCU +#define PAD_GPIO24_FUNC_SEL_MASK 0x7000U +#define PAD_GPIO25_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO25_FUNC_SEL_SHIFT 0xFU +#define PAD_GPIO25_FUNC_SEL_MASK 0x38000U +#define PAD_GPIO26_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO26_FUNC_SEL_SHIFT 0x12U +#define PAD_GPIO26_FUNC_SEL_MASK 0x1C0000U +#define PAD_GPIO27_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO27_FUNC_SEL_SHIFT 0x15U +#define PAD_GPIO27_FUNC_SEL_MASK 0xE00000U +#define PAD_GPIO28_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO28_FUNC_SEL_SHIFT 0x18U +#define PAD_GPIO28_FUNC_SEL_MASK 0x7000000U +#define PAD_GPIO29_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO29_FUNC_SEL_SHIFT 0x1BU +#define PAD_GPIO29_FUNC_SEL_MASK 0x38000000U +#define SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR (0x2a4U) +#define PAD_GPIO30_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO30_FUNC_SEL_SHIFT 0x0U +#define PAD_GPIO30_FUNC_SEL_MASK 0x7U +#define PAD_GPIO31_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO31_FUNC_SEL_SHIFT 0x3U +#define PAD_GPIO31_FUNC_SEL_MASK 0x38U +#define PAD_GPIO32_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO32_FUNC_SEL_SHIFT 0x6U +#define PAD_GPIO32_FUNC_SEL_MASK 0x1C0U +#define PAD_GPIO33_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO33_FUNC_SEL_SHIFT 0x9U +#define PAD_GPIO33_FUNC_SEL_MASK 0xE00U +#define PAD_GPIO34_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO34_FUNC_SEL_SHIFT 0xCU +#define PAD_GPIO34_FUNC_SEL_MASK 0x7000U +#define PAD_GPIO35_FUNC_SEL_WIDTH 0x2U +#define PAD_GPIO35_FUNC_SEL_SHIFT 0xFU +#define PAD_GPIO35_FUNC_SEL_MASK 0x18000U +#define PAD_GPIO36_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO36_FUNC_SEL_SHIFT 0x11U +#define PAD_GPIO36_FUNC_SEL_MASK 0xE0000U +#define PAD_GPIO37_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO37_FUNC_SEL_SHIFT 0x14U +#define PAD_GPIO37_FUNC_SEL_MASK 0x700000U +#define PAD_GPIO38_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO38_FUNC_SEL_SHIFT 0x17U +#define PAD_GPIO38_FUNC_SEL_MASK 0x3800000U +#define PAD_GPIO39_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO39_FUNC_SEL_SHIFT 0x1AU +#define PAD_GPIO39_FUNC_SEL_MASK 0x1C000000U +#define PAD_GPIO40_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO40_FUNC_SEL_SHIFT 0x1DU +#define PAD_GPIO40_FUNC_SEL_MASK 0xE0000000U +#define SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR (0x2a8U) +#define PAD_GPIO41_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO41_FUNC_SEL_SHIFT 0x0U +#define PAD_GPIO41_FUNC_SEL_MASK 0x7U +#define PAD_GPIO42_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO42_FUNC_SEL_SHIFT 0x3U +#define PAD_GPIO42_FUNC_SEL_MASK 0x38U +#define PAD_GPIO43_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO43_FUNC_SEL_SHIFT 0x6U +#define PAD_GPIO43_FUNC_SEL_MASK 0x1C0U +#define PAD_GPIO44_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO44_FUNC_SEL_SHIFT 0x9U +#define PAD_GPIO44_FUNC_SEL_MASK 0xE00U +#define PAD_GPIO45_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO45_FUNC_SEL_SHIFT 0xCU +#define PAD_GPIO45_FUNC_SEL_MASK 0x7000U +#define PAD_GPIO46_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO46_FUNC_SEL_SHIFT 0xFU +#define PAD_GPIO46_FUNC_SEL_MASK 0x38000U +#define PAD_GPIO47_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO47_FUNC_SEL_SHIFT 0x12U +#define PAD_GPIO47_FUNC_SEL_MASK 0x1C0000U +#define PAD_GPIO48_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO48_FUNC_SEL_SHIFT 0x15U +#define PAD_GPIO48_FUNC_SEL_MASK 0xE00000U +#define PAD_GPIO49_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO49_FUNC_SEL_SHIFT 0x18U +#define PAD_GPIO49_FUNC_SEL_MASK 0x7000000U +#define PAD_GPIO50_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO50_FUNC_SEL_SHIFT 0x1BU +#define PAD_GPIO50_FUNC_SEL_MASK 0x38000000U +#define PAD_GPIO51_FUNC_SEL_WIDTH 0x2U +#define PAD_GPIO51_FUNC_SEL_SHIFT 0x1EU +#define PAD_GPIO51_FUNC_SEL_MASK 0xC0000000U +#define SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR (0x2acU) +#define PAD_GPIO52_FUNC_SEL_WIDTH 0x2U +#define PAD_GPIO52_FUNC_SEL_SHIFT 0x0U +#define PAD_GPIO52_FUNC_SEL_MASK 0x3U +#define PAD_GPIO53_FUNC_SEL_WIDTH 0x2U +#define PAD_GPIO53_FUNC_SEL_SHIFT 0x2U +#define PAD_GPIO53_FUNC_SEL_MASK 0xCU +#define PAD_GPIO54_FUNC_SEL_WIDTH 0x2U +#define PAD_GPIO54_FUNC_SEL_SHIFT 0x4U +#define PAD_GPIO54_FUNC_SEL_MASK 0x30U +#define PAD_GPIO55_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO55_FUNC_SEL_SHIFT 0x6U +#define PAD_GPIO55_FUNC_SEL_MASK 0x1C0U +#define PAD_GPIO56_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO56_FUNC_SEL_SHIFT 0x9U +#define PAD_GPIO56_FUNC_SEL_MASK 0xE00U +#define PAD_GPIO57_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO57_FUNC_SEL_SHIFT 0xCU +#define PAD_GPIO57_FUNC_SEL_MASK 0x7000U +#define PAD_GPIO58_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO58_FUNC_SEL_SHIFT 0xFU +#define PAD_GPIO58_FUNC_SEL_MASK 0x38000U +#define PAD_GPIO59_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO59_FUNC_SEL_SHIFT 0x12U +#define PAD_GPIO59_FUNC_SEL_MASK 0x1C0000U +#define PAD_GPIO60_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO60_FUNC_SEL_SHIFT 0x15U +#define PAD_GPIO60_FUNC_SEL_MASK 0xE00000U +#define PAD_GPIO61_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO61_FUNC_SEL_SHIFT 0x18U +#define PAD_GPIO61_FUNC_SEL_MASK 0x7000000U +#define PAD_GPIO62_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO62_FUNC_SEL_SHIFT 0x1BU +#define PAD_GPIO62_FUNC_SEL_MASK 0x38000000U +#define PAD_GPIO63_FUNC_SEL_WIDTH 0x2U +#define PAD_GPIO63_FUNC_SEL_SHIFT 0x1EU +#define PAD_GPIO63_FUNC_SEL_MASK 0xC0000000U +#define SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR (0x2b0U) +#define PAD_GPIO6_FUNC_SEL_WIDTH 0x2U +#define PAD_GPIO6_FUNC_SEL_SHIFT 0x0U +#define PAD_GPIO6_FUNC_SEL_MASK 0x3U +#define PAD_GPIO7_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO7_FUNC_SEL_SHIFT 0x2U +#define PAD_GPIO7_FUNC_SEL_MASK 0x1CU +#define PAD_GPIO8_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO8_FUNC_SEL_SHIFT 0x5U +#define PAD_GPIO8_FUNC_SEL_MASK 0xE0U +#define PAD_GPIO9_FUNC_SEL_WIDTH 0x3U +#define PAD_GPIO9_FUNC_SEL_SHIFT 0x8U +#define PAD_GPIO9_FUNC_SEL_MASK 0x700U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_WIDTH 0x3U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_SHIFT 0xBU +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_MASK 0x3800U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_WIDTH 0x3U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_SHIFT 0xEU +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_MASK 0x1C000U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_WIDTH 0x3U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_SHIFT 0x11U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_MASK 0xE0000U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_WIDTH 0x3U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_SHIFT 0x14U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_MASK 0x700000U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_WIDTH 0x3U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_SHIFT 0x17U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_MASK 0x3800000U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_WIDTH 0x3U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_SHIFT 0x1AU +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_MASK 0x1C000000U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_WIDTH 0x3U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_SHIFT 0x1DU +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_MASK 0xE0000000U +#define SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR (0x2b4U) +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_WIDTH 0x3U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_SHIFT 0x0U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_MASK 0x7U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_WIDTH 0x3U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_SHIFT 0x3U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_MASK 0x38U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_WIDTH 0x3U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_SHIFT 0x6U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_MASK 0x1C0U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_WIDTH 0x3U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_SHIFT 0x9U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_MASK 0xE00U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_WIDTH 0x3U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_SHIFT 0xCU +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_MASK 0x7000U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_WIDTH 0x3U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_SHIFT 0xFU +#define U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_MASK 0x38000U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_WIDTH 0x3U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_SHIFT 0x12U +#define U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_MASK 0x1C0000U +#define U0_SYS_CRG_DVP_CLK_FUNC_SEL_WIDTH 0x3U +#define U0_SYS_CRG_DVP_CLK_FUNC_SEL_SHIFT 0x15U +#define U0_SYS_CRG_DVP_CLK_FUNC_SEL_MASK 0xE00000U + +#define PAD_GMAC1_RXC_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR \ + PAD_GMAC1_RXC_FUNC_SEL_SHIFT \ + PAD_GMAC1_RXC_FUNC_SEL_MASK +#define PAD_GPIO10_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR \ + PAD_GPIO10_FUNC_SEL_SHIFT \ + PAD_GPIO10_FUNC_SEL_MASK +#define PAD_GPIO11_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR \ + PAD_GPIO11_FUNC_SEL_SHIFT \ + PAD_GPIO11_FUNC_SEL_MASK +#define PAD_GPIO12_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR \ + PAD_GPIO12_FUNC_SEL_SHIFT \ + PAD_GPIO12_FUNC_SEL_MASK +#define PAD_GPIO13_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR \ + PAD_GPIO13_FUNC_SEL_SHIFT \ + PAD_GPIO13_FUNC_SEL_MASK +#define PAD_GPIO14_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR \ + PAD_GPIO14_FUNC_SEL_SHIFT \ + PAD_GPIO14_FUNC_SEL_MASK +#define PAD_GPIO15_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR \ + PAD_GPIO15_FUNC_SEL_SHIFT \ + PAD_GPIO15_FUNC_SEL_MASK +#define PAD_GPIO16_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR \ + PAD_GPIO16_FUNC_SEL_SHIFT \ + PAD_GPIO16_FUNC_SEL_MASK +#define PAD_GPIO17_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR \ + PAD_GPIO17_FUNC_SEL_SHIFT \ + PAD_GPIO17_FUNC_SEL_MASK +#define PAD_GPIO18_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR \ + PAD_GPIO18_FUNC_SEL_SHIFT \ + PAD_GPIO18_FUNC_SEL_MASK +#define PAD_GPIO19_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR \ + PAD_GPIO19_FUNC_SEL_SHIFT \ + PAD_GPIO19_FUNC_SEL_MASK +#define PAD_GPIO20_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR \ + PAD_GPIO20_FUNC_SEL_SHIFT \ + PAD_GPIO20_FUNC_SEL_MASK +#define PAD_GPIO21_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR \ + PAD_GPIO21_FUNC_SEL_SHIFT \ + PAD_GPIO21_FUNC_SEL_MASK +#define PAD_GPIO22_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR \ + PAD_GPIO22_FUNC_SEL_SHIFT \ + PAD_GPIO22_FUNC_SEL_MASK +#define PAD_GPIO23_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR \ + PAD_GPIO23_FUNC_SEL_SHIFT \ + PAD_GPIO23_FUNC_SEL_MASK +#define PAD_GPIO24_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR \ + PAD_GPIO24_FUNC_SEL_SHIFT \ + PAD_GPIO24_FUNC_SEL_MASK +#define PAD_GPIO25_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR \ + PAD_GPIO25_FUNC_SEL_SHIFT \ + PAD_GPIO25_FUNC_SEL_MASK +#define PAD_GPIO26_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR \ + PAD_GPIO26_FUNC_SEL_SHIFT \ + PAD_GPIO26_FUNC_SEL_MASK +#define PAD_GPIO27_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR \ + PAD_GPIO27_FUNC_SEL_SHIFT \ + PAD_GPIO27_FUNC_SEL_MASK +#define PAD_GPIO28_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR \ + PAD_GPIO28_FUNC_SEL_SHIFT \ + PAD_GPIO28_FUNC_SEL_MASK +#define PAD_GPIO29_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR \ + PAD_GPIO29_FUNC_SEL_SHIFT \ + PAD_GPIO29_FUNC_SEL_MASK +#define PAD_GPIO30_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR \ + PAD_GPIO30_FUNC_SEL_SHIFT \ + PAD_GPIO30_FUNC_SEL_MASK +#define PAD_GPIO31_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR \ + PAD_GPIO31_FUNC_SEL_SHIFT \ + PAD_GPIO31_FUNC_SEL_MASK +#define PAD_GPIO32_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR \ + PAD_GPIO32_FUNC_SEL_SHIFT \ + PAD_GPIO32_FUNC_SEL_MASK +#define PAD_GPIO33_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR \ + PAD_GPIO33_FUNC_SEL_SHIFT \ + PAD_GPIO33_FUNC_SEL_MASK +#define PAD_GPIO34_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR \ + PAD_GPIO34_FUNC_SEL_SHIFT \ + PAD_GPIO34_FUNC_SEL_MASK +#define PAD_GPIO35_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR \ + PAD_GPIO35_FUNC_SEL_SHIFT \ + PAD_GPIO35_FUNC_SEL_MASK +#define PAD_GPIO36_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR \ + PAD_GPIO36_FUNC_SEL_SHIFT \ + PAD_GPIO36_FUNC_SEL_MASK +#define PAD_GPIO37_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR \ + PAD_GPIO37_FUNC_SEL_SHIFT \ + PAD_GPIO37_FUNC_SEL_MASK +#define PAD_GPIO38_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR \ + PAD_GPIO38_FUNC_SEL_SHIFT \ + PAD_GPIO38_FUNC_SEL_MASK +#define PAD_GPIO39_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR \ + PAD_GPIO39_FUNC_SEL_SHIFT \ + PAD_GPIO39_FUNC_SEL_MASK +#define PAD_GPIO40_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR \ + PAD_GPIO40_FUNC_SEL_SHIFT \ + PAD_GPIO40_FUNC_SEL_MASK +#define PAD_GPIO41_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR \ + PAD_GPIO41_FUNC_SEL_SHIFT \ + PAD_GPIO41_FUNC_SEL_MASK +#define PAD_GPIO42_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR \ + PAD_GPIO42_FUNC_SEL_SHIFT \ + PAD_GPIO42_FUNC_SEL_MASK +#define PAD_GPIO43_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR \ + PAD_GPIO43_FUNC_SEL_SHIFT \ + PAD_GPIO43_FUNC_SEL_MASK +#define PAD_GPIO44_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR \ + PAD_GPIO44_FUNC_SEL_SHIFT \ + PAD_GPIO44_FUNC_SEL_MASK +#define PAD_GPIO45_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR \ + PAD_GPIO45_FUNC_SEL_SHIFT \ + PAD_GPIO45_FUNC_SEL_MASK +#define PAD_GPIO46_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR \ + PAD_GPIO46_FUNC_SEL_SHIFT \ + PAD_GPIO46_FUNC_SEL_MASK +#define PAD_GPIO47_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR \ + PAD_GPIO47_FUNC_SEL_SHIFT \ + PAD_GPIO47_FUNC_SEL_MASK +#define PAD_GPIO48_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR \ + PAD_GPIO48_FUNC_SEL_SHIFT \ + PAD_GPIO48_FUNC_SEL_MASK +#define PAD_GPIO49_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR \ + PAD_GPIO49_FUNC_SEL_SHIFT \ + PAD_GPIO49_FUNC_SEL_MASK +#define PAD_GPIO50_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR \ + PAD_GPIO50_FUNC_SEL_SHIFT \ + PAD_GPIO50_FUNC_SEL_MASK +#define PAD_GPIO51_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR \ + PAD_GPIO51_FUNC_SEL_SHIFT \ + PAD_GPIO51_FUNC_SEL_MASK +#define PAD_GPIO52_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR \ + PAD_GPIO52_FUNC_SEL_SHIFT \ + PAD_GPIO52_FUNC_SEL_MASK +#define PAD_GPIO53_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR \ + PAD_GPIO53_FUNC_SEL_SHIFT \ + PAD_GPIO53_FUNC_SEL_MASK +#define PAD_GPIO54_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR \ + PAD_GPIO54_FUNC_SEL_SHIFT \ + PAD_GPIO54_FUNC_SEL_MASK +#define PAD_GPIO55_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR \ + PAD_GPIO55_FUNC_SEL_SHIFT \ + PAD_GPIO55_FUNC_SEL_MASK +#define PAD_GPIO56_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR \ + PAD_GPIO56_FUNC_SEL_SHIFT \ + PAD_GPIO56_FUNC_SEL_MASK +#define PAD_GPIO57_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR \ + PAD_GPIO57_FUNC_SEL_SHIFT \ + PAD_GPIO57_FUNC_SEL_MASK +#define PAD_GPIO58_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR \ + PAD_GPIO58_FUNC_SEL_SHIFT \ + PAD_GPIO58_FUNC_SEL_MASK +#define PAD_GPIO59_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR \ + PAD_GPIO59_FUNC_SEL_SHIFT \ + PAD_GPIO59_FUNC_SEL_MASK +#define PAD_GPIO60_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR \ + PAD_GPIO60_FUNC_SEL_SHIFT \ + PAD_GPIO60_FUNC_SEL_MASK +#define PAD_GPIO61_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR \ + PAD_GPIO61_FUNC_SEL_SHIFT \ + PAD_GPIO61_FUNC_SEL_MASK +#define PAD_GPIO62_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR \ + PAD_GPIO62_FUNC_SEL_SHIFT \ + PAD_GPIO62_FUNC_SEL_MASK +#define PAD_GPIO63_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR \ + PAD_GPIO63_FUNC_SEL_SHIFT \ + PAD_GPIO63_FUNC_SEL_MASK +#define PAD_GPIO6_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR \ + PAD_GPIO6_FUNC_SEL_SHIFT \ + PAD_GPIO6_FUNC_SEL_MASK +#define PAD_GPIO7_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR \ + PAD_GPIO7_FUNC_SEL_SHIFT \ + PAD_GPIO7_FUNC_SEL_MASK +#define PAD_GPIO8_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR \ + PAD_GPIO8_FUNC_SEL_SHIFT \ + PAD_GPIO8_FUNC_SEL_MASK +#define PAD_GPIO9_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR \ + PAD_GPIO9_FUNC_SEL_SHIFT \ + PAD_GPIO9_FUNC_SEL_MASK +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR \ + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_SHIFT \ + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_MASK +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR \ + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_SHIFT \ + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_MASK +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR \ + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_SHIFT \ + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_MASK +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR \ + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_SHIFT \ + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_MASK +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR \ + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_SHIFT \ + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_MASK +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR \ + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_SHIFT \ + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_MASK +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR \ + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_SHIFT \ + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_MASK +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR \ + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_SHIFT \ + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_MASK +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR \ + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_SHIFT \ + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_MASK +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR \ + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_SHIFT \ + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_MASK +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR \ + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_SHIFT \ + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_MASK +#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR \ + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_SHIFT \ + U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_MASK +#define U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR \ + U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_SHIFT \ + U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_MASK +#define U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR \ + U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_SHIFT \ + U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_MASK +#define U0_SYS_CRG_DVP_CLK_FUNC_SEL \ + SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR \ + U0_SYS_CRG_DVP_CLK_FUNC_SEL_SHIFT \ + U0_SYS_CRG_DVP_CLK_FUNC_SEL_MASK +/************************sys_iomux***************************/ +// aon ioconfig + +// POS[0] +#define TESTEN_POS(data) ((data << 0x0U) & 0x1U) + +// SMT[0] POS[1] +#define RSTN_SMT(data) ((data << 0x0U) & 0x1U) +#define RSTN_POS(data) ((data << 0x1U) & 0x2U) + +// DS[1:0] +#define OSC_DS(data) ((data << 0x0U) & 0x3U) + +// sys ioconfig +// IE[0] DS[2:1] PU[3] PD[4] SLEW[5] SMT[6] POS[7] +#define GPIO_IE(data) ((data << 0x0U) & 0x1U) +#define GPIO_DS(data) ((data << 0x1U) & 0x6U) +#define GPIO_PU(data) ((data << 0x3U) & 0x8U) +#define GPIO_PD(data) ((data << 0x4U) & 0x10U) +#define GPIO_SLEW(data) ((data << 0x5U) & 0x20U) +#define GPIO_SMT(data) ((data << 0x6U) & 0x40U) +#define GPIO_POS(data) ((data << 0x7U) & 0x80U) + +#define IO(config) ((config) & 0xFF) +#define DOUT(dout) ((dout) & 0xFF) +#define DOEN(doen) ((doen) & 0xFF) +#define DIN(din_reg) ((din_reg) & 0xFF) + +// syscon value +#define IO_3_3V 0 /*00:3.3v*/ +#define IO_2_5V 1 /*01:2.5v*/ +#define IO_1_8V 2 /*10:1.8v*/ + +#endif /* __DT_BINDINGS_JH7110_PIN_CTRL_H__ */ diff --git a/Platform/StarFive/VisionFive2/DeviceTree/JH7110Power.h b/Platf= orm/StarFive/VisionFive2/DeviceTree/JH7110Power.h new file mode 100755 index 000000000000..4763c4de1f22 --- /dev/null +++ b/Platform/StarFive/VisionFive2/DeviceTree/JH7110Power.h @@ -0,0 +1,22 @@ +/** @file + This header provide all JH7110 power device tree bindings + + Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __DT_BINDINGS_JH7110_POWER_H__ +#define __DT_BINDINGS_JH7110_POWER_H__ + +#define JH7110_PD_SYSTOP 0 +#define JH7110_PD_CPU 1 +#define JH7110_PD_GPUA 2 +#define JH7110_PD_VDEC 3 +#define JH7110_PD_VOUT 4 +#define JH7110_PD_ISP 5 +#define JH7110_PD_VENC 6 +#define JH7110_PD_GPUB 7 + +#endif /* __DT_BINDINGS_JH7110_POWER_H__ */ diff --git a/Platform/StarFive/VisionFive2/DeviceTree/JH7110Rst.h b/Platfor= m/StarFive/VisionFive2/DeviceTree/JH7110Rst.h new file mode 100644 index 000000000000..fc9a2ff01a00 --- /dev/null +++ b/Platform/StarFive/VisionFive2/DeviceTree/JH7110Rst.h @@ -0,0 +1,228 @@ +/** @file + This header provide all JH7110 reset device tree bindings + + Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __DT_BINDINGS_JH7110_RESET_H__ +#define __DT_BINDINGS_JH7110_RESET_H__ + +/* + * group[0]: syscrg: assert0 + */ +#define RSTN_U0_JTAG2APB_PRESETN 0 +#define RSTN_U0_SYS_SYSCON_PRESETN 1 +#define RSTN_U0_SYS_IOMUX_PRESETN 2 +#define RSTN_U0_U7MC_RST_BUS 3 +#define RSTN_U0_U7MC_DEBUG 4 +#define RSTN_U0_U7MC_CORE0 5 +#define RSTN_U0_U7MC_CORE1 6 +#define RSTN_U0_U7MC_CORE2 7 +#define RSTN_U0_U7MC_CORE3 8 +#define RSTN_U0_U7MC_CORE4 9 +#define RSTN_U0_U7MC_CORE0_ST 10 +#define RSTN_U0_U7MC_CORE1_ST 11 +#define RSTN_U0_U7MC_CORE2_ST 12 +#define RSTN_U0_U7MC_CORE3_ST 13 +#define RSTN_U0_U7MC_CORE4_ST 14 +#define RSTN_U0_U7MC_TRACE_RST0 15 +#define RSTN_U0_U7MC_TRACE_RST1 16 +#define RSTN_U0_U7MC_TRACE_RST2 17 +#define RSTN_U0_U7MC_TRACE_RST3 18 +#define RSTN_U0_U7MC_TRACE_RST4 19 +#define RSTN_U0_U7MC_TRACE_COM 20 +#define RSTN_U0_IMG_GPU_APB 21 +#define RSTN_U0_IMG_GPU_DOMA 22 +#define RSTN_U0_NOC_BUS_APB_BUS_N 23 +#define RSTN_U0_NOC_BUS_AXICFG0_AXI_N 24 +#define RSTN_U0_NOC_BUS_CPU_AXI_N 25 +#define RSTN_U0_NOC_BUS_DISP_AXI_N 26 +#define RSTN_U0_NOC_BUS_GPU_AXI_N 27 +#define RSTN_U0_NOC_BUS_ISP_AXI_N 28 +#define RSTN_U0_NOC_BUS_DDRC_N 29 +#define RSTN_U0_NOC_BUS_STG_AXI_N 30 +#define RSTN_U0_NOC_BUS_VDEC_AXI_N 31 + +/* + * group[1]: syscrg: assert1 + */ +#define RSTN_U0_NOC_BUS_VENC_AXI_N 32 +#define RSTN_U0_AXI_CFG1_DEC_AHB 33 +#define RSTN_U0_AXI_CFG1_DEC_MAIN 34 +#define RSTN_U0_AXI_CFG0_DEC_MAIN 35 +#define RSTN_U0_AXI_CFG0_DEC_MAIN_DIV 36 +#define RSTN_U0_AXI_CFG0_DEC_HIFI4 37 +#define RSTN_U0_DDR_AXI 38 +#define RSTN_U0_DDR_OSC 39 +#define RSTN_U0_DDR_APB 40 +#define RSTN_U0_DOM_ISP_TOP_N 41 +#define RSTN_U0_DOM_ISP_TOP_AXI 42 +#define RSTN_U0_DOM_VOUT_TOP_SRC 43 +#define RSTN_U0_CODAJ12_AXI 44 +#define RSTN_U0_CODAJ12_CORE 45 +#define RSTN_U0_CODAJ12_APB 46 +#define RSTN_U0_WAVE511_AXI 47 +#define RSTN_U0_WAVE511_BPU 48 +#define RSTN_U0_WAVE511_VCE 49 +#define RSTN_U0_WAVE511_APB 50 +#define RSTN_U0_VDEC_JPG_ARB_JPG 51 +#define RSTN_U0_VDEC_JPG_ARB_MAIN 52 +#define RSTN_U0_AXIMEM_128B_AXI 53 +#define RSTN_U0_WAVE420L_AXI 54 +#define RSTN_U0_WAVE420L_BPU 55 +#define RSTN_U0_WAVE420L_VCE 56 +#define RSTN_U0_WAVE420L_APB 57 +#define RSTN_U1_AXIMEM_128B_AXI 58 +#define RSTN_U2_AXIMEM_128B_AXI 59 +#define RSTN_U0_INTMEM_ROM_SRAM_ROM 60 +#define RSTN_U0_CDNS_QSPI_AHB 61 +#define RSTN_U0_CDNS_QSPI_APB 62 +#define RSTN_U0_CDNS_QSPI_REF 63 + +/* + * group[2]: syscrg: assert2 + */ +#define RSTN_U0_DW_SDIO_AHB 64 +#define RSTN_U1_DW_SDIO_AHB 65 +#define RSTN_U1_DW_GMAC5_AXI64_A_I 66 +#define RSTN_U1_DW_GMAC5_AXI64_H_N 67 +#define RSTN_U0_MAILBOX_RRESETN 68 +#define RSTN_U0_SSP_SPI_APB 69 +#define RSTN_U1_SSP_SPI_APB 70 +#define RSTN_U2_SSP_SPI_APB 71 +#define RSTN_U3_SSP_SPI_APB 72 +#define RSTN_U4_SSP_SPI_APB 73 +#define RSTN_U5_SSP_SPI_APB 74 +#define RSTN_U6_SSP_SPI_APB 75 +#define RSTN_U0_DW_I2C_APB 76 +#define RSTN_U1_DW_I2C_APB 77 +#define RSTN_U2_DW_I2C_APB 78 +#define RSTN_U3_DW_I2C_APB 79 +#define RSTN_U4_DW_I2C_APB 80 +#define RSTN_U5_DW_I2C_APB 81 +#define RSTN_U6_DW_I2C_APB 82 +#define RSTN_U0_DW_UART_APB 83 +#define RSTN_U0_DW_UART_CORE 84 +#define RSTN_U1_DW_UART_APB 85 +#define RSTN_U1_DW_UART_CORE 86 +#define RSTN_U2_DW_UART_APB 87 +#define RSTN_U2_DW_UART_CORE 88 +#define RSTN_U3_DW_UART_APB 89 +#define RSTN_U3_DW_UART_CORE 90 +#define RSTN_U4_DW_UART_APB 91 +#define RSTN_U4_DW_UART_CORE 92 +#define RSTN_U5_DW_UART_APB 93 +#define RSTN_U5_DW_UART_CORE 94 +#define RSTN_U0_CDNS_SPDIF_APB 95 + +/* + * group[3]: syscrg: assert3 + */ +#define RSTN_U0_PWMDAC_APB 96 +#define RSTN_U0_PDM_4MIC_DMIC 97 +#define RSTN_U0_PDM_4MIC_APB 98 +#define RSTN_U0_I2SRX_3CH_APB 99 +#define RSTN_U0_I2SRX_3CH_BCLK 100 +#define RSTN_U0_I2STX_4CH_APB 101 +#define RSTN_U0_I2STX_4CH_BCLK 102 +#define RSTN_U1_I2STX_4CH_APB 103 +#define RSTN_U1_I2STX_4CH_BCLK 104 +#define RSTN_U0_TDM16SLOT_AHB 105 +#define RSTN_U0_TDM16SLOT_TDM 106 +#define RSTN_U0_TDM16SLOT_APB 107 +#define RSTN_U0_PWM_8CH_APB 108 +#define RSTN_U0_DSKIT_WDT_APB 109 +#define RSTN_U0_DSKIT_WDT_CORE 110 +#define RSTN_U0_CAN_CTRL_APB 111 +#define RSTN_U0_CAN_CTRL_CORE 112 +#define RSTN_U0_CAN_CTRL_TIMER 113 +#define RSTN_U1_CAN_CTRL_APB 114 +#define RSTN_U1_CAN_CTRL_CORE 115 +#define RSTN_U1_CAN_CTRL_TIMER 116 +#define RSTN_U0_TIMER_APB 117 +#define RSTN_U0_TIMER_TIMER0 118 +#define RSTN_U0_TIMER_TIMER1 119 +#define RSTN_U0_TIMER_TIMER2 120 +#define RSTN_U0_TIMER_TIMER3 121 +#define RSTN_U0_INT_CTRL_APB 122 +#define RSTN_U0_TEMP_SENSOR_APB 123 +#define RSTN_U0_TEMP_SENSOR_TEMP 124 +#define RSTN_U0_JTAG_CERTIFICATION_N 125 + +/* + * group[4]: stgcrg + */ +#define RSTN_U0_STG_SYSCON_PRESETN 128 +#define RSTN_U0_HIFI4_CORE 129 +#define RSTN_U0_HIFI4_AXI 130 +#define RSTN_U0_SEC_TOP_HRESETN 131 +#define RSTN_U0_E24_CORE 132 +#define RSTN_U0_DW_DMA1P_AXI 133 +#define RSTN_U0_DW_DMA1P_AHB 134 +#define RSTN_U0_CDN_USB_AXI 135 +#define RSTN_U0_CDN_USB_APB 136 +#define RSTN_U0_CDN_USB_UTMI_APB 137 +#define RSTN_U0_CDN_USB_PWRUP 138 +#define RSTN_U0_PLDA_PCIE_AXI_MST0 139 +#define RSTN_U0_PLDA_PCIE_AXI_SLV0 140 +#define RSTN_U0_PLDA_PCIE_AXI_SLV 141 +#define RSTN_U0_PLDA_PCIE_BRG 142 +#define RSTN_U0_PLDA_PCIE_CORE 143 +#define RSTN_U0_PLDA_PCIE_APB 144 +#define RSTN_U1_PLDA_PCIE_AXI_MST0 145 +#define RSTN_U1_PLDA_PCIE_AXI_SLV0 146 +#define RSTN_U1_PLDA_PCIE_AXI_SLV 147 +#define RSTN_U1_PLDA_PCIE_BRG 148 +#define RSTN_U1_PLDA_PCIE_CORE 149 +#define RSTN_U1_PLDA_PCIE_APB 150 + +/* + * group[5]: aoncrg + */ +#define RSTN_U0_DW_GMAC5_AXI64_AXI 160 +#define RSTN_U0_DW_GMAC5_AXI64_AHB 161 +#define RSTN_U0_AON_IOMUX_PRESETN 162 +#define RSTN_U0_PMU_APB 163 +#define RSTN_U0_PMU_WKUP 164 +#define RSTN_U0_RTC_HMS_APB 165 +#define RSTN_U0_RTC_HMS_CAL 166 +#define RSTN_U0_RTC_HMS_OSC32K 167 + +/* + * group[6]: ispcrg + */ +#define RSTN_U0_ISPV2_TOP_WRAPPER_P 192 +#define RSTN_U0_ISPV2_TOP_WRAPPER_C 193 +#define RSTN_U0_M31DPHY_HW 194 +#define RSTN_U0_M31DPHY_B09_ALWAYS_ON 195 +#define RSTN_U0_VIN_N_PCLK 196 +#define RSTN_U0_VIN_N_PIXEL_CLK_IF0 197 +#define RSTN_U0_VIN_N_PIXEL_CLK_IF1 198 +#define RSTN_U0_VIN_N_PIXEL_CLK_IF2 199 +#define RSTN_U0_VIN_N_PIXEL_CLK_IF3 200 +#define RSTN_U0_VIN_N_SYS_CLK 201 +#define RSTN_U0_VIN_P_AXIRD 202 +#define RSTN_U0_VIN_P_AXIWR 203 + +/* + * group[7]: voutcrg + */ +#define RSTN_U0_DC8200_AXI 224 +#define RSTN_U0_DC8200_AHB 225 +#define RSTN_U0_DC8200_CORE 226 +#define RSTN_U0_CDNS_DSITX_DPI 227 +#define RSTN_U0_CDNS_DSITX_APB 228 +#define RSTN_U0_CDNS_DSITX_RXESC 229 +#define RSTN_U0_CDNS_DSITX_SYS 230 +#define RSTN_U0_CDNS_DSITX_TXBYTEHS 231 +#define RSTN_U0_CDNS_DSITX_TXESC 232 +#define RSTN_U0_HDMI_TX_HDMI 233 +#define RSTN_U0_MIPITX_DPHY_SYS 234 +#define RSTN_U0_MIPITX_DPHY_TXBYTEHS 235 + +#define RSTN_JH7110_RESET_END 236 + +#endif /* __DT_BINDINGS_JH7110_RESET_H__ */ diff --git a/Platform/StarFive/VisionFive2/DeviceTree/Led.h b/Platform/Star= Five/VisionFive2/DeviceTree/Led.h new file mode 100644 index 000000000000..53d636e17215 --- /dev/null +++ b/Platform/StarFive/VisionFive2/DeviceTree/Led.h @@ -0,0 +1,90 @@ +/** @file + This header provide all the LEDs bindings + + Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __DT_BINDINGS_LEDS_H__ +#define __DT_BINDINGS_LEDS_H__ + +/* External trigger type */ +#define LEDS_TRIG_TYPE_EDGE 0 +#define LEDS_TRIG_TYPE_LEVEL 1 + +/* Boost modes */ +#define LEDS_BOOST_OFF 0 +#define LEDS_BOOST_ADAPTIVE 1 +#define LEDS_BOOST_FIXED 2 + +/* Standard LED colors */ +#define LED_COLOR_ID_WHITE 0 +#define LED_COLOR_ID_RED 1 +#define LED_COLOR_ID_GREEN 2 +#define LED_COLOR_ID_BLUE 3 +#define LED_COLOR_ID_AMBER 4 +#define LED_COLOR_ID_VIOLET 5 +#define LED_COLOR_ID_YELLOW 6 +#define LED_COLOR_ID_IR 7 +#define LED_COLOR_ID_MULTI 8 /* For multicolor LEDs */ +#define LED_COLOR_ID_RGB 9 /* For multicolor LEDs that can do arbitr= ary color, \ + so this would include RGBW and similar= */ +#define LED_COLOR_ID_MAX 10 + +/* Standard LED functions */ +/* Keyboard LEDs, usually it would be input4::capslock etc. */ +#define LED_FUNCTION_CAPSLOCK "capslock" +#define LED_FUNCTION_SCROLLLOCK "scrolllock" +#define LED_FUNCTION_NUMLOCK "numlock" +#define LED_FUNCTION_KBD_BACKLIGHT "kbd_backlight" + +/* System LEDs, usually found on system body. + platform:: mute (etc) is sometimes seen, : mute would be better */ +#define LED_FUNCTION_POWER "power" +#define LED_FUNCTION_DISK "disk" + +/* Obsolete: "platform:*:charging" (allwinner sun50i) */ +#define LED_FUNCTION_CHARGING "charging" + +/* Used RGB notification LEDs common on phones. + Obsolete equivalents: "status-led:{red,green,blue}" (Motorola Droid 4= ), + "lp5523:{r,g,b}" (Nokia N900) */ +#define LED_FUNCTION_STATUS "status" + +#define LED_FUNCTION_MICMUTE "micmute" +#define LED_FUNCTION_MUTE "mute" + +/* Miscelleaus functions. Use functions above if you can. */ +#define LED_FUNCTION_ACTIVITY "activity" +#define LED_FUNCTION_ALARM "alarm" +#define LED_FUNCTION_BACKLIGHT "backlight" +#define LED_FUNCTION_BLUETOOTH "bluetooth" +#define LED_FUNCTION_BOOT "boot" +#define LED_FUNCTION_CPU "cpu" +#define LED_FUNCTION_DEBUG "debug" +#define LED_FUNCTION_DISK_ACTIVITY "disk-activity" +#define LED_FUNCTION_DISK_ERR "disk-err" +#define LED_FUNCTION_DISK_READ "disk-read" +#define LED_FUNCTION_DISK_WRITE "disk-write" +#define LED_FUNCTION_FAULT "fault" +#define LED_FUNCTION_FLASH "flash" +#define LED_FUNCTION_HEARTBEAT "heartbeat" +#define LED_FUNCTION_INDICATOR "indicator" +#define LED_FUNCTION_LAN "lan" +#define LED_FUNCTION_MAIL "mail" +#define LED_FUNCTION_MTD "mtd" +#define LED_FUNCTION_PANIC "panic" +#define LED_FUNCTION_PROGRAMMING "programming" +#define LED_FUNCTION_RX "rx" +#define LED_FUNCTION_SD "sd" +#define LED_FUNCTION_STANDBY "standby" +#define LED_FUNCTION_TORCH "torch" +#define LED_FUNCTION_TX "tx" +#define LED_FUNCTION_USB "usb" +#define LED_FUNCTION_WAN "wan" +#define LED_FUNCTION_WLAN "wlan" +#define LED_FUNCTION_WPS "wps" + +#endif /* __DT_BINDINGS_LEDS_H__ */ diff --git a/Platform/StarFive/VisionFive2/DeviceTree/StarFiveClk.dtsi b/Pl= atform/StarFive/VisionFive2/DeviceTree/StarFiveClk.dtsi new file mode 100755 index 000000000000..be3bfe405d99 --- /dev/null +++ b/Platform/StarFive/VisionFive2/DeviceTree/StarFiveClk.dtsi @@ -0,0 +1,130 @@ +/** @file + Device tree defination for all JH7110 clocks used in StarFive VisionFive= 2 platform + + Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/ { + osc: osc { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + }; + + clk_ext_camera: clk-ext-camera { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + }; + + gmac1_rmii_refin: gmac1_rmii_refin { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <50000000>; + }; + + gmac1_rgmii_rxin: gmac1_rgmii_rxin { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <125000000>; + }; + + i2stx_bclk_ext: i2stx_bclk_ext { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <12288000>; + }; + + i2stx_lrck_ext: i2stx_lrck_ext { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <192000>; + }; + + i2srx_bclk_ext: i2srx_bclk_ext { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <12288000>; + }; + + i2srx_lrck_ext: i2srx_lrck_ext { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <192000>; + }; + + tdm_ext: tdm_ext { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <49152000>; + }; + + mclk_ext: mclk_ext { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <12288000>; + }; + + jtag_tck_inner: jtag_tck_inner { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <50000000>; + }; + + bist_apb: bist_apb { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <50000000>; + }; + + gmac0_rmii_refin: gmac0_rmii_refin { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <50000000>; + }; + + gmac0_rgmii_rxin: gmac0_rgmii_rxin { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <125000000>; + }; + + clk_rtc: clk_rtc { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32768>; + }; + + hdmitx0_pixelclk: hdmitx0_pixelclk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <297000000>; + }; + + mipitx_dphy_rxesc: mipitx_dphy_rxesc { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <10000000>; + }; + + mipitx_dphy_txbytehs: mipitx_dphy_txbytehs { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <297000000>; + }; + + wm8960_mclk: wm8960_mclk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24576000>; + }; + + ac108_mclk: ac108_mclk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + }; +}; diff --git a/Platform/StarFive/VisionFive2/DeviceTree/StarFiveHdmi.dtsi b/P= latform/StarFive/VisionFive2/DeviceTree/StarFiveHdmi.dtsi new file mode 100644 index 000000000000..ca96fa954ab4 --- /dev/null +++ b/Platform/StarFive/VisionFive2/DeviceTree/StarFiveHdmi.dtsi @@ -0,0 +1,28 @@ +/** @file + Device tree defination all JH7110 display audio for StarFive VisionFive = 2 platform + + Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +&sound1 { + /* i2s + hdmi */ + simple-audio-card,dai-link@0 { + reg =3D <0>; + format =3D "i2s"; + bitclock-master =3D <&sndi2s0>; + frame-master =3D <&sndi2s0>; + mclk-fs =3D <256>; + status =3D "okay"; + + sndi2s0: cpu { + sound-dai =3D <&i2stx_4ch0>; + }; + + sndhdmi0: codec { + sound-dai =3D <&hdmi>; + }; + }; +}; diff --git a/Platform/StarFive/VisionFive2/DeviceTree/StarFiveJH7110.dtsi b= /Platform/StarFive/VisionFive2/DeviceTree/StarFiveJH7110.dtsi new file mode 100644 index 000000000000..d216c0357a4b --- /dev/null +++ b/Platform/StarFive/VisionFive2/DeviceTree/StarFiveJH7110.dtsi @@ -0,0 +1,1812 @@ +/** @file + Device tree defination for JH7110 SoC + + Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/dts-v1/; +#include "StarFiveClk.dtsi" +#include "JH7110ClkGen.h" +#include "JH7110ClkVout.h" +#include "JH7110ClkIsp.h" +#include "JH7110Rst.h" +#include "JH7110Power.h" +#include "Thermal.h" +#include "Irq.h" + +/ { + compatible =3D "starfive,jh7110"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cluster0_opp: opp-table-0 { + compatible =3D "operating-points-v2"; + opp-shared; + opp-375000000 { + opp-hz =3D /bits/ 64 <375000000>; + opp-microvolt =3D <800000>; + }; + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + opp-microvolt =3D <800000>; + }; + opp-750000000 { + opp-hz =3D /bits/ 64 <750000000>; + opp-microvolt =3D <800000>; + opp-suspend; + }; + opp-1500000000 { + opp-hz =3D /bits/ 64 <1500000000>; + opp-microvolt =3D <1040000>; + }; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "sifive,u74-mc", "riscv"; + reg =3D <0>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <8192>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <40>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <16384>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <40>; + mmu-type =3D "riscv,sv39"; + next-level-cache =3D <&cachectrl>; + riscv,isa =3D "rv64imac"; + tlb-split; + #cooling-cells =3D <2>; + status =3D "disabled"; + + cpu0intctrl: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu1: cpu@1 { + compatible =3D "sifive,u74-mc", "riscv"; + reg =3D <1>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <40>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <40>; + mmu-type =3D "riscv,sv39"; + next-level-cache =3D <&cachectrl>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + #cooling-cells =3D <2>; + status =3D "okay"; + operating-points-v2 =3D <&cluster0_opp>; + + cpu1intctrl: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu2: cpu@2 { + compatible =3D "sifive,u74-mc", "riscv"; + reg =3D <2>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <40>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <40>; + mmu-type =3D "riscv,sv39"; + next-level-cache =3D <&cachectrl>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + #cooling-cells =3D <2>; + status =3D "okay"; + operating-points-v2 =3D <&cluster0_opp>; + + cpu2intctrl: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu3: cpu@3 { + compatible =3D "sifive,u74-mc", "riscv"; + reg =3D <3>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <40>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <40>; + mmu-type =3D "riscv,sv39"; + next-level-cache =3D <&cachectrl>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + #cooling-cells =3D <2>; + status =3D "okay"; + operating-points-v2 =3D <&cluster0_opp>; + + cpu3intctrl: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu4: cpu@4 { + compatible =3D "sifive,u74-mc", "riscv"; + reg =3D <4>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <40>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <40>; + mmu-type =3D "riscv,sv39"; + next-level-cache =3D <&cachectrl>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + #cooling-cells =3D <2>; + status =3D "okay"; + operating-points-v2 =3D <&cluster0_opp>; + + cpu4intctrl: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + + soc: soc { + compatible =3D "simple-bus"; + interrupt-parent =3D <&plic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + #clock-cells =3D <1>; + ranges; + + cachectrl: cache-controller@2010000 { + compatible =3D "sifive,fu740-c000-ccache", "cache"; + reg =3D <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>; + reg-names =3D "control", "sideband"; + interrupts =3D <1 3 4 2>; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <2048>; + cache-size =3D <2097152>; + cache-unified; + }; + + aon_syscon: aon_syscon@17010000 { + compatible =3D "syscon"; + reg =3D <0x0 0x17010000 0x0 0x1000>; + }; + + phyctrl0: multi-phyctrl@10210000 { + compatible =3D "starfive,phyctrl"; + reg =3D <0x0 0x10210000 0x0 0x10000>; + }; + + phyctrl1: pcie1-phyctrl@10220000 { + compatible =3D "starfive,phyctrl"; + reg =3D <0x0 0x10220000 0x0 0x10000>; + }; + + stg_syscon: stg_syscon@10240000 { + compatible =3D "syscon"; + reg =3D <0x0 0x10240000 0x0 0x1000>; + }; + + sys_syscon: sys_syscon@13030000 { + compatible =3D "syscon"; + reg =3D <0x0 0x13030000 0x0 0x1000>; + }; + + clint: clint@2000000 { + compatible =3D "riscv,clint0"; + reg =3D <0x0 0x2000000 0x0 0x10000>; + reg-names =3D "control"; + interrupts-extended =3D <&cpu0intctrl 3 &cpu0intctrl 7 + &cpu1intctrl 3 &cpu1intctrl 7 + &cpu2intctrl 3 &cpu2intctrl 7 + &cpu3intctrl 3 &cpu3intctrl 7 + &cpu4intctrl 3 &cpu4intctrl 7>; + #interrupt-cells =3D <1>; + }; + + plic: plic@c000000 { + compatible =3D "riscv,plic0"; + reg =3D <0x0 0xc000000 0x0 0x4000000>; + reg-names =3D "control"; + interrupts-extended =3D <&cpu0intctrl 11 + &cpu1intctrl 11 &cpu1intctrl 9 + &cpu2intctrl 11 &cpu2intctrl 9 + &cpu3intctrl 11 &cpu3intctrl 9 + &cpu4intctrl 11 &cpu4intctrl 9>; + interrupt-controller; + #interrupt-cells =3D <1>; + riscv,max-priority =3D <7>; + riscv,ndev =3D <136>; + }; + + clkgen: clock-controller { + compatible =3D "starfive,jh7110-clkgen"; + reg =3D <0x0 0x13020000 0x0 0x10000>, + <0x0 0x10230000 0x0 0x10000>, + <0x0 0x17000000 0x0 0x10000>; + reg-names =3D "sys", "stg", "aon"; + clocks =3D <&osc>, <&gmac1_rmii_refin>, + <&gmac1_rgmii_rxin>, + <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, + <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, + <&tdm_ext>, <&mclk_ext>, + <&jtag_tck_inner>, <&bist_apb>, + <&clk_rtc>, + <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>; + clock-names =3D "osc", "gmac1_rmii_refin", + "gmac1_rgmii_rxin", + "i2stx_bclk_ext", "i2stx_lrck_ext", + "i2srx_bclk_ext", "i2srx_lrck_ext", + "tdm_ext", "mclk_ext", + "jtag_tck_inner", "bist_apb", + "clk_rtc", + "gmac0_rmii_refin", "gmac0_rgmii_rxin"; + #clock-cells =3D <1>; + starfive,sys-syscon =3D <&sys_syscon 0x18 0x1c + 0x20 0x24 0x28 0x2c 0x30 0x34>; + status =3D "okay"; + }; + + clkvout: clock-controller@295C0000 { + compatible =3D "starfive,jh7110-clk-vout"; + reg =3D <0x0 0x295C0000 0x0 0x10000>; + reg-names =3D "vout"; + clocks =3D <&hdmitx0_pixelclk>, + <&mipitx_dphy_rxesc>, + <&mipitx_dphy_txbytehs>, + <&clkgen JH7110_VOUT_SRC>, + <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>; + clock-names =3D "hdmitx0_pixelclk", + "mipitx_dphy_rxesc", + "mipitx_dphy_txbytehs", + "vout_src", + "vout_top_ahb"; + resets =3D <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>; + reset-names =3D "vout_src"; + #clock-cells =3D <1>; + power-domains =3D <&pwrc JH7110_PD_VOUT>; + status =3D "okay"; + }; + + clkisp: clock-controller@19810000 { + compatible =3D "starfive,jh7110-clk-isp"; + reg =3D <0x0 0x19810000 0x0 0x10000>; + reg-names =3D "isp"; + #clock-cells =3D <1>; + clocks =3D <&clkgen JH7110_ISP_TOP_CLK_DVP>, + <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>, + <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>, + <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>; + clock-names =3D "u0_dom_isp_top_clk_dom_isp_top_clk_dvp", + "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x", + "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi", + "u0_sft7110_noc_bus_clk_isp_axi"; + resets =3D <&rstgen RSTN_U0_DOM_ISP_TOP_N>, + <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>, + <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>; + reset-names =3D "rst_isp_top_n", "rst_isp_top_axi", + "rst_isp_noc_bus_n"; + power-domains =3D <&pwrc JH7110_PD_ISP>; + status =3D "okay"; + }; + + qspi: spi@13010000 { + compatible =3D "cdns,qspi-nor"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0 0x13010000 0x0 0x10000 + 0x0 0x21000000 0x0 0x400000>; + interrupts =3D <25>; + clocks =3D <&clkgen JH7110_QSPI_CLK_REF>, + <&clkgen JH7110_QSPI_CLK_APB>, + <&clkgen JH7110_AHB1>, + <&clkgen JH7110_QSPI_CLK_AHB>; + clock-names =3D "clk_ref", + "clk_apb", + "ahb1", + "clk_ahb"; + resets =3D <&rstgen RSTN_U0_CDNS_QSPI_APB>, + <&rstgen RSTN_U0_CDNS_QSPI_AHB>, + <&rstgen RSTN_U0_CDNS_QSPI_REF>; + cdns,fifo-depth =3D <256>; + cdns,fifo-width =3D <4>; + cdns,trigger-address =3D <0x0>; + spi-max-frequency =3D <250000000>; + + nor_flash: nor-flash@0 { + compatible =3D "jedec,spi-nor"; + reg=3D<0>; + cdns,read-delay =3D <5>; + spi-max-frequency =3D <100000000>; + cdns,tshsl-ns =3D <1>; + cdns,tsd2d-ns =3D <1>; + cdns,tchsh-ns =3D <1>; + cdns,tslch-ns =3D <1>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + spl@0 { + reg =3D <0x0 0x40000>; + }; + uboot@100000 { + reg =3D <0x100000 0x300000>; + }; + data@f00000 { + reg =3D <0xf00000 0x100000>; + }; + }; + }; + }; + + otp: otp@17050000 { + compatible =3D "starfive,jh7110-otp"; + reg =3D <0x0 0x17050000 0x0 0x10000>; + clock-frequency =3D <4000000>; + clocks =3D <&clkgen JH7110_OTPC_CLK_APB>; + clock-names =3D "apb"; + }; + + usbdrd30: usbdrd{ + compatible =3D "starfive,jh7110-cdns3"; + reg =3D <0x0 0x10210000 0x0 0x1000>, + <0x0 0x10200000 0x0 0x1000>; + clocks =3D <&clkgen JH7110_USB_125M>, + <&clkgen JH7110_USB0_CLK_APP_125>, + <&clkgen JH7110_USB0_CLK_LPM>, + <&clkgen JH7110_USB0_CLK_STB>, + <&clkgen JH7110_USB0_CLK_USB_APB>, + <&clkgen JH7110_USB0_CLK_AXI>, + <&clkgen JH7110_USB0_CLK_UTMI_APB>, + <&clkgen JH7110_PCIE0_CLK_APB>; + clock-names =3D "125m","app","lpm","stb","apb","axi","utmi", "= phy"; + resets =3D <&rstgen RSTN_U0_CDN_USB_PWRUP>, + <&rstgen RSTN_U0_CDN_USB_APB>, + <&rstgen RSTN_U0_CDN_USB_AXI>, + <&rstgen RSTN_U0_CDN_USB_UTMI_APB>, + <&rstgen RSTN_U0_PLDA_PCIE_APB>; + reset-names =3D "pwrup","apb","axi","utmi", "phy"; + starfive,stg-syscon =3D <&stg_syscon 0x4 0xc4 0x148 0x1f4>; + starfive,sys-syscon =3D <&sys_syscon 0x18>; + status =3D "disabled"; + #address-cells =3D <2>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + ranges; + usbdrd_cdns3: usb@10100000 { + compatible =3D "cdns,usb3"; + reg =3D <0x0 0x10100000 0x0 0x10000>, + <0x0 0x10110000 0x0 0x10000>, + <0x0 0x10120000 0x0 0x10000>; + reg-names =3D "otg", "xhci", "dev"; + interrupts =3D <100>, <108>, <110>; + interrupt-names =3D "host", "peripheral", "otg"; + phy-names =3D "cdns3,usb3-phy", "cnds3,usb2-phy"; + maximum-speed =3D "super-speed"; + }; + }; + + timer: timer@13050000 { + compatible =3D "starfive,jh7110-timers"; + reg =3D <0x0 0x13050000 0x0 0x10000>; + interrupts =3D <69>, <70>, <71> ,<72>; + interrupt-names =3D "timer0", "timer1", + "timer2", "timer3"; + clocks =3D <&clkgen JH7110_TIMER_CLK_TIMER0>, + <&clkgen JH7110_TIMER_CLK_TIMER1>, + <&clkgen JH7110_TIMER_CLK_TIMER2>, + <&clkgen JH7110_TIMER_CLK_TIMER3>, + <&clkgen JH7110_TIMER_CLK_APB>; + clock-names =3D "timer0", "timer1", + "timer2", "timer3", "apb_clk"; + resets =3D <&rstgen RSTN_U0_TIMER_TIMER0>, + <&rstgen RSTN_U0_TIMER_TIMER1>, + <&rstgen RSTN_U0_TIMER_TIMER2>, + <&rstgen RSTN_U0_TIMER_TIMER3>, + <&rstgen RSTN_U0_TIMER_APB>; + reset-names =3D "timer0", "timer1", + "timer2", "timer3", "apb_rst"; + clock-frequency =3D <24000000>; + status =3D "okay"; + }; + + wdog: wdog@13070000 { + compatible =3D "starfive,jh7110-wdt"; + reg =3D <0x0 0x13070000 0x0 0x10000>; + interrupts =3D <68>; + interrupt-names =3D "wdog"; + clocks =3D <&clkgen JH7110_DSKIT_WDT_CLK_WDT>, + <&clkgen JH7110_DSKIT_WDT_CLK_APB>; + clock-names =3D "core_clk", "apb_clk"; + resets =3D <&rstgen RSTN_U0_DSKIT_WDT_APB>, + <&rstgen RSTN_U0_DSKIT_WDT_CORE>; + reset-names =3D "rst_apb", "rst_core"; + timeout-sec =3D <15>; + status =3D "okay"; + }; + + rtc: rtc@17040000 { + compatible =3D "starfive,jh7110-rtc"; + reg =3D <0x0 0x17040000 0x0 0x10000>; + interrupts =3D <10>, <11>, <12>; + interrupt-names =3D "rtc_ms_pulse", "rtc_sec_pulse", "rtc"; + clocks =3D <&clkgen JH7110_RTC_HMS_CLK_APB>, + <&clkgen JH7110_RTC_HMS_CLK_CAL>; + clock-names =3D "pclk", "cal_clk"; + resets =3D <&rstgen RSTN_U0_RTC_HMS_OSC32K>, + <&rstgen RSTN_U0_RTC_HMS_APB>, + <&rstgen RSTN_U0_RTC_HMS_CAL>; + reset-names =3D "rst_osc", "rst_apb", "rst_cal"; + rtc,cal-clock-freq =3D <1000000>; + status =3D "okay"; + }; + + pwrc: power-controller@17030000 { + compatible =3D "starfive,jh7110-pmu"; + reg =3D <0x0 0x17030000 0x0 0x10000>; + interrupts =3D <111>; + #power-domain-cells =3D <1>; + status =3D "okay"; + }; + + uart0: serial@10000000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x0 0x10000000 0x0 0x10000>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + clocks =3D <&clkgen JH7110_UART0_CLK_CORE>, + <&clkgen JH7110_UART0_CLK_APB>; + clock-names =3D "baudclk", "apb_pclk"; + resets =3D <&rstgen RSTN_U0_DW_UART_APB>, + <&rstgen RSTN_U0_DW_UART_CORE>; + interrupts =3D <32>; + status =3D "disabled"; + }; + + uart1: serial@10010000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x0 0x10010000 0x0 0x10000>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + clocks =3D <&clkgen JH7110_UART1_CLK_CORE>, + <&clkgen JH7110_UART1_CLK_APB>; + clock-names =3D "baudclk", "apb_pclk"; + resets =3D <&rstgen RSTN_U1_DW_UART_APB>, + <&rstgen RSTN_U1_DW_UART_CORE>; + interrupts =3D <33>; + status =3D "disabled"; + }; + + uart2: serial@10020000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x0 0x10020000 0x0 0x10000>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + clocks =3D <&clkgen JH7110_UART2_CLK_CORE>, + <&clkgen JH7110_UART2_CLK_APB>; + clock-names =3D "baudclk", "apb_pclk"; + resets =3D <&rstgen RSTN_U2_DW_UART_APB>, + <&rstgen RSTN_U2_DW_UART_CORE>; + interrupts =3D <34>; + status =3D "disabled"; + }; + + uart3: serial@12000000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x0 0x12000000 0x0 0x10000>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + clocks =3D <&clkgen JH7110_UART3_CLK_CORE>, + <&clkgen JH7110_UART3_CLK_APB>; + clock-names =3D "baudclk", "apb_pclk"; + resets =3D <&rstgen RSTN_U3_DW_UART_APB>, + <&rstgen RSTN_U3_DW_UART_CORE>; + interrupts =3D <45>; + status =3D "disabled"; + }; + + uart4: serial@12010000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x0 0x12010000 0x0 0x10000>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + clocks =3D <&clkgen JH7110_UART4_CLK_CORE>, + <&clkgen JH7110_UART4_CLK_APB>; + clock-names =3D "baudclk", "apb_pclk"; + resets =3D <&rstgen RSTN_U4_DW_UART_APB>, + <&rstgen RSTN_U4_DW_UART_CORE>; + interrupts =3D <46>; + status =3D "disabled"; + }; + + uart5: serial@12020000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x0 0x12020000 0x0 0x10000>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + clocks =3D <&clkgen JH7110_UART5_CLK_CORE>, + <&clkgen JH7110_UART5_CLK_APB>; + clock-names =3D "baudclk", "apb_pclk"; + resets =3D <&rstgen RSTN_U5_DW_UART_APB>, + <&rstgen RSTN_U5_DW_UART_CORE>; + interrupts =3D <47>; + status =3D "disabled"; + }; + + dma: dma-controller@16050000 { + compatible =3D "starfive,jh7110-dma", "snps,axi-dma-1.01a"; + reg =3D <0x0 0x16050000 0x0 0x10000>; + clocks =3D <&clkgen JH7110_DMA1P_CLK_AXI>, + <&clkgen JH7110_DMA1P_CLK_AHB>, + <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>; + clock-names =3D "core-clk", "cfgr-clk", "stg_clk"; + resets =3D <&rstgen RSTN_U0_DW_DMA1P_AXI>, + <&rstgen RSTN_U0_DW_DMA1P_AHB>, + <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>; + reset-names =3D "rst_axi", "rst_ahb", "rst_stg"; + interrupts =3D <73>; + #dma-cells =3D <2>; + dma-channels =3D <4>; + snps,dma-masters =3D <1>; + snps,data-width =3D <3>; + snps,num-hs-if =3D <56>; + snps,block-size =3D <65536 65536 65536 65536>; + snps,priority =3D <0 1 2 3>; + snps,axi-max-burst-len =3D <16>; + status =3D "disabled"; + }; + + gpio: gpio@13040000 { + compatible =3D "starfive,jh7110-sys-pinctrl"; + reg =3D <0x0 0x13040000 0x0 0x10000>; + reg-names =3D "control"; + clocks =3D <&clkgen JH7110_SYS_IOMUX_PCLK>; + resets =3D <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>; + interrupts =3D <86>; + interrupt-controller; + #gpio-cells =3D <2>; + ngpios =3D <64>; + status =3D "okay"; + }; + + gpioa: gpio@17020000 { + compatible =3D "starfive,jh7110-aon-pinctrl"; + reg =3D <0x0 0x17020000 0x0 0x10000>; + reg-names =3D "control"; + resets =3D <&rstgen RSTN_U0_AON_IOMUX_PRESETN>; + interrupts =3D <85>; + interrupt-controller; + #gpio-cells =3D <2>; + ngpios =3D <4>; + status =3D "okay"; + }; + + sfctemp: tmon@120e0000 { + compatible =3D "starfive,jh7110-temp"; + reg =3D <0x0 0x120e0000 0x0 0x10000>; + interrupts =3D <81>; + clocks =3D <&clkgen JH7110_TEMP_SENSOR_CLK_TEMP>, + <&clkgen JH7110_TEMP_SENSOR_CLK_APB>; + clock-names =3D "sense", "bus"; + resets =3D <&rstgen RSTN_U0_TEMP_SENSOR_TEMP>, + <&rstgen RSTN_U0_TEMP_SENSOR_APB>; + reset-names =3D "sense", "bus"; + #thermal-sensor-cells =3D <0>; + status =3D "disabled"; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <15000>; + + thermal-sensors =3D <&sfctemp>; + + trips { + cpu_alert0: cpu_alert0 { + /* milliCelsius */ + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu_crit: cpu_crit { + /* milliCelsius */ + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_alert0>; + cooling-device =3D + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + trng: trng@1600C000 { + compatible =3D "starfive,jh7110-trng"; + reg =3D <0x0 0x1600C000 0x0 0x4000>; + clocks =3D <&clkgen JH7110_SEC_HCLK>, + <&clkgen JH7110_SEC_MISCAHB_CLK>; + clock-names =3D "hclk", "ahb"; + resets =3D <&rstgen RSTN_U0_SEC_TOP_HRESETN>; + interrupts =3D <30>; + status =3D "disabled"; + }; + + sec_dma: sec_dma@16008000 { + compatible =3D "arm,pl080", "arm,primecell"; + arm,primecell-periphid =3D <0x00041080>; + reg =3D <0x0 0x16008000 0x0 0x4000>; + reg-names =3D "sec_dma"; + interrupts =3D <29>; + clocks =3D <&clkgen JH7110_SEC_HCLK>, + <&clkgen JH7110_SEC_MISCAHB_CLK>; + clock-names =3D "sec_hclk","apb_pclk"; + resets =3D <&rstgen RSTN_U0_SEC_TOP_HRESETN>; + reset-names =3D "sec_hre"; + lli-bus-interface-ahb1; + mem-bus-interface-ahb1; + memcpy-burst-size =3D <256>; + memcpy-bus-width =3D <32>; + #dma-cells =3D <2>; + status =3D "disabled"; + }; + + crypto: crypto@16000000 { + compatible =3D "starfive,jh7110-sec"; + reg =3D <0x0 0x16000000 0x0 0x4000>, + <0x0 0x16008000 0x0 0x4000>; + reg-names =3D "secreg","secdma"; + interrupts =3D <28>, <29>; + interrupt-names =3D "secirq", "dmairq"; + clocks =3D <&clkgen JH7110_SEC_HCLK>, + <&clkgen JH7110_SEC_MISCAHB_CLK>; + clock-names =3D "sec_hclk","sec_ahb"; + resets =3D <&rstgen RSTN_U0_SEC_TOP_HRESETN>; + reset-names =3D "sec_hre"; + enable-side-channel-mitigation =3D "true"; + enable-dma =3D "true"; + dmas =3D <&sec_dma 1 2>, + <&sec_dma 0 2>; + dma-names =3D "sec_m","sec_p"; + status =3D "disabled"; + }; + + i2c0: i2c@10030000 { + compatible =3D "snps,designware-i2c"; + reg =3D <0x0 0x10030000 0x0 0x10000>; + clocks =3D <&clkgen JH7110_I2C0_CLK_CORE>, + <&clkgen JH7110_I2C0_CLK_APB>; + clock-names =3D "ref", "pclk"; + resets =3D <&rstgen RSTN_U0_DW_I2C_APB>; + interrupts =3D <35>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c1: i2c@10040000 { + compatible =3D "snps,designware-i2c"; + reg =3D <0x0 0x10040000 0x0 0x10000>; + clocks =3D <&clkgen JH7110_I2C1_CLK_CORE>, + <&clkgen JH7110_I2C1_CLK_APB>; + clock-names =3D "ref", "pclk"; + resets =3D <&rstgen RSTN_U1_DW_I2C_APB>; + interrupts =3D <36>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c2: i2c@10050000 { + compatible =3D "snps,designware-i2c"; + reg =3D <0x0 0x10050000 0x0 0x10000>; + clocks =3D <&clkgen JH7110_I2C2_CLK_CORE>, + <&clkgen JH7110_I2C2_CLK_APB>; + clock-names =3D "ref", "pclk"; + resets =3D <&rstgen RSTN_U2_DW_I2C_APB>; + interrupts =3D <37>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c3: i2c@12030000 { + compatible =3D "snps,designware-i2c"; + reg =3D <0x0 0x12030000 0x0 0x10000>; + clocks =3D <&clkgen JH7110_I2C3_CLK_CORE>, + <&clkgen JH7110_I2C3_CLK_APB>; + clock-names =3D "ref", "pclk"; + resets =3D <&rstgen RSTN_U3_DW_I2C_APB>; + interrupts =3D <48>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c4: i2c@12040000 { + compatible =3D "snps,designware-i2c"; + reg =3D <0x0 0x12040000 0x0 0x10000>; + clocks =3D <&clkgen JH7110_I2C4_CLK_CORE>, + <&clkgen JH7110_I2C4_CLK_APB>; + clock-names =3D "ref", "pclk"; + resets =3D <&rstgen RSTN_U4_DW_I2C_APB>; + interrupts =3D <49>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c5: i2c@12050000 { + compatible =3D "snps,designware-i2c"; + reg =3D <0x0 0x12050000 0x0 0x10000>; + clocks =3D <&clkgen JH7110_I2C5_CLK_CORE>, + <&clkgen JH7110_I2C5_CLK_APB>; + clock-names =3D "ref", "pclk"; + resets =3D <&rstgen RSTN_U5_DW_I2C_APB>; + interrupts =3D <50>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c6: i2c@12060000 { + compatible =3D "snps,designware-i2c"; + reg =3D <0x0 0x12060000 0x0 0x10000>; + clocks =3D <&clkgen JH7110_I2C6_CLK_CORE>, + <&clkgen JH7110_I2C6_CLK_APB>; + clock-names =3D "ref", "pclk"; + resets =3D <&rstgen RSTN_U6_DW_I2C_APB>; + interrupts =3D <51>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + /* unremovable emmc as mmcblk0 */ + sdio0: sdio0@16010000 { + compatible =3D "starfive,jh7110-sdio"; + reg =3D <0x0 0x16010000 0x0 0x10000>; + clocks =3D <&clkgen JH7110_SDIO0_CLK_AHB>, + <&clkgen JH7110_SDIO0_CLK_SDCARD>; + clock-names =3D "biu","ciu"; + resets =3D <&rstgen RSTN_U0_DW_SDIO_AHB>; + reset-names =3D "reset"; + interrupts =3D <74>; + fifo-depth =3D <32>; + fifo-watermark-aligned; + data-addr =3D <0>; + starfive,sys-syscon =3D <&sys_syscon 0x14 0x1a 0x7c000000>; + status =3D "disabled"; + }; + + sdio1: sdio1@16020000 { + compatible =3D "starfive,jh7110-sdio"; + reg =3D <0x0 0x16020000 0x0 0x10000>; + clocks =3D <&clkgen JH7110_SDIO1_CLK_AHB>, + <&clkgen JH7110_SDIO1_CLK_SDCARD>; + clock-names =3D "biu","ciu"; + resets =3D <&rstgen RSTN_U1_DW_SDIO_AHB>; + reset-names =3D "reset"; + interrupts =3D <75>; + fifo-depth =3D <32>; + fifo-watermark-aligned; + data-addr =3D <0>; + starfive,sys-syscon =3D <&sys_syscon 0x9c 0x1 0x3e>; + status =3D "disabled"; + }; + + vin_sysctl: vin_sysctl@19800000 { + compatible =3D "starfive,jh7110-vin"; + reg =3D <0x0 0x19800000 0x0 0x10000>, + <0x0 0x19810000 0x0 0x10000>, + <0x0 0x19820000 0x0 0x10000>, + <0x0 0x19840000 0x0 0x10000>, + <0x0 0x19870000 0x0 0x30000>, + <0x0 0x11840000 0x0 0x10000>, + <0x0 0x17030000 0x0 0x10000>, + <0x0 0x13020000 0x0 0x10000>; + reg-names =3D "csi2rx", "vclk", "vrst", "sctrl", + "isp", "trst", "pmu", "syscrg"; + clocks =3D <&clkisp JH7110_DOM4_APB_FUNC>, + <&clkisp JH7110_U0_VIN_PCLK>, + <&clkisp JH7110_U0_VIN_SYS_CLK>, + <&clkisp JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C>, + <&clkisp JH7110_DVP_INV>, + <&clkisp JH7110_U0_VIN_CLK_P_AXIWR>, + <&clkisp JH7110_MIPI_RX0_PXL>, + <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF0>, + <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF1>, + <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF2>, + <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF3>, + <&clkisp JH7110_U0_M31DPHY_CFGCLK_IN>, + <&clkisp JH7110_U0_M31DPHY_REFCLK_IN>, + <&clkisp JH7110_U0_M31DPHY_TXCLKESC_LAN0>, + <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>, + <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>; + clock-names =3D "clk_apb_func", "clk_pclk", "clk_sys_clk", + "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr", + "clk_mipi_rx0_pxl", "clk_pixel_clk_if0", + "clk_pixel_clk_if1", "clk_pixel_clk_if2", + "clk_pixel_clk_if3", "clk_m31dphy_cfgclk_in", + "clk_m31dphy_refclk_in", "clk_m31dphy_txclkesc_lan0", + "clk_ispcore_2x", "clk_isp_axi"; + resets =3D <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>, + <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>, + <&rstgen RSTN_U0_VIN_N_PCLK>, + <&rstgen RSTN_U0_VIN_N_SYS_CLK>, + <&rstgen RSTN_U0_VIN_P_AXIRD>, + <&rstgen RSTN_U0_VIN_P_AXIWR>, + <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF0>, + <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF1>, + <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF2>, + <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF3>, + <&rstgen RSTN_U0_M31DPHY_HW>, + <&rstgen RSTN_U0_M31DPHY_B09_ALWAYS_ON>, + <&rstgen RSTN_U0_DOM_ISP_TOP_N>, + <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>; + reset-names =3D "rst_wrapper_p", "rst_wrapper_c", "rst_pclk", + "rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if= 0", + "rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_i= f3", + "rst_m31dphy_hw", "rst_m31dphy_b09_always_on", + "rst_isp_top_n", "rst_isp_top_axi"; + starfive,aon-syscon =3D <&aon_syscon 0x00>; + power-domains =3D <&pwrc JH7110_PD_ISP>; + /* irq nr: vin, isp, isp_csi, isp_scd, isp_csiline */ + interrupts =3D <92 87 88 89 90>; + status =3D "disabled"; + }; + + jpu: jpu@11900000 { + compatible =3D "starfive,jpu"; + reg =3D <0x0 0x13090000 0x0 0x300>; + interrupts =3D <14>; + clocks =3D <&clkgen JH7110_CODAJ12_CLK_AXI>, + <&clkgen JH7110_CODAJ12_CLK_CORE>, + <&clkgen JH7110_CODAJ12_CLK_APB>, + <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>; + clock-names =3D "axi_clk", "core_clk", + "apb_clk", "noc_bus"; + resets =3D <&rstgen RSTN_U0_CODAJ12_AXI>, + <&rstgen RSTN_U0_CODAJ12_CORE>, + <&rstgen RSTN_U0_CODAJ12_APB>; + reset-names =3D "rst_axi", "rst_core", "rst_apb"; + power-domains =3D <&pwrc JH7110_PD_VDEC>; + status =3D "disabled"; + }; + + vpu_dec: vpu_dec@130A0000 { + compatible =3D "starfive,vdec"; + reg =3D <0x0 0x130A0000 0x0 0x10000>; + interrupts =3D <13>; + clocks =3D <&clkgen JH7110_WAVE511_CLK_AXI>, + <&clkgen JH7110_WAVE511_CLK_BPU>, + <&clkgen JH7110_WAVE511_CLK_VCE>, + <&clkgen JH7110_WAVE511_CLK_APB>, + <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>; + clock-names =3D "axi_clk", "bpu_clk", "vce_clk", + "apb_clk", "noc_bus"; + resets =3D <&rstgen RSTN_U0_WAVE511_AXI>, + <&rstgen RSTN_U0_WAVE511_BPU>, + <&rstgen RSTN_U0_WAVE511_VCE>, + <&rstgen RSTN_U0_WAVE511_APB>, + <&rstgen RSTN_U0_AXIMEM_128B_AXI>; + reset-names =3D "rst_axi", "rst_bpu", "rst_vce", + "rst_apb", "rst_sram"; + starfive,vdec_noc_ctrl; + power-domains =3D <&pwrc JH7110_PD_VDEC>; + status =3D "disabled"; + }; + + vpu_enc: vpu_enc@130B0000 { + compatible =3D "starfive,venc"; + reg =3D <0x0 0x130B0000 0x0 0x10000>; + interrupts =3D <15>; + clocks =3D <&clkgen JH7110_WAVE420L_CLK_AXI>, + <&clkgen JH7110_WAVE420L_CLK_BPU>, + <&clkgen JH7110_WAVE420L_CLK_VCE>, + <&clkgen JH7110_WAVE420L_CLK_APB>, + <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>; + clock-names =3D "axi_clk", "bpu_clk", "vce_clk", + "apb_clk", "noc_bus"; + resets =3D <&rstgen RSTN_U0_WAVE420L_AXI>, + <&rstgen RSTN_U0_WAVE420L_BPU>, + <&rstgen RSTN_U0_WAVE420L_VCE>, + <&rstgen RSTN_U0_WAVE420L_APB>, + <&rstgen RSTN_U1_AXIMEM_128B_AXI>; + reset-names =3D "rst_axi", "rst_bpu", "rst_vce", + "rst_apb", "rst_sram"; + starfive,venc_noc_ctrl; + power-domains =3D <&pwrc JH7110_PD_VENC>; + status =3D "disabled"; + }; + + rstgen: reset-controller { + compatible =3D "starfive,jh7110-reset"; + reg =3D <0x0 0x13020000 0x0 0x10000>, + <0x0 0x10230000 0x0 0x10000>, + <0x0 0x17000000 0x0 0x10000>, + <0x0 0x19810000 0x0 0x10000>, + <0x0 0x295C0000 0x0 0x10000>; + reg-names =3D "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg= "; + #reset-cells =3D <1>; + status =3D "okay"; + }; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt =3D <0xf>; + snps,rd_osr_lmt =3D <0xf>; + snps,blen =3D <256 128 64 32 0 0 0>; + }; + + gmac0: ethernet@16030000 { + compatible =3D "starfive,dwmac","snps,dwmac-5.10a"; + reg =3D <0x0 0x16030000 0x0 0x10000>; + clock-names =3D "gtx", + "tx", + "ptp_ref", + "stmmaceth", + "pclk", + "gtxc", + "rmii_rtx"; + clocks =3D <&clkgen JH7110_GMAC0_GTXCLK>, + <&clkgen JH7110_U0_GMAC5_CLK_TX>, + <&clkgen JH7110_GMAC0_PTP>, + <&clkgen JH7110_U0_GMAC5_CLK_AHB>, + <&clkgen JH7110_U0_GMAC5_CLK_AXI>, + <&clkgen JH7110_GMAC0_GTXC>, + <&clkgen JH7110_GMAC0_RMII_RTX>; + resets =3D <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>, + <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>; + reset-names =3D "ahb", "stmmaceth"; + interrupts =3D <7>, <6>, <5> ; + interrupt-names =3D "macirq", "eth_wake_irq", "eth_lpi"; + max-frame-size =3D <9000>; + phy-mode =3D "rgmii-id"; + snps,multicast-filter-bins =3D <64>; + snps,perfect-filter-entries =3D <128>; + rx-fifo-depth =3D <2048>; + tx-fifo-depth =3D <2048>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config =3D <&stmmac_axi_setup>; + snps,tso; + snps,en-tx-lpi-clockgating; + snps,en-lpi; + snps,write-requests =3D <4>; + snps,read-requests =3D <4>; + snps,burst-map =3D <0x7>; + snps,txpbl =3D <16>; + snps,rxpbl =3D <16>; + status =3D "disabled"; + }; + + gmac1: ethernet@16040000 { + compatible =3D "starfive,dwmac","snps,dwmac-5.10a"; + reg =3D <0x0 0x16040000 0x0 0x10000>; + clock-names =3D "gtx", + "tx", + "ptp_ref", + "stmmaceth", + "pclk", + "gtxc", + "rmii_rtx"; + clocks =3D <&clkgen JH7110_GMAC1_GTXCLK>, + <&clkgen JH7110_GMAC5_CLK_TX>, + <&clkgen JH7110_GMAC5_CLK_PTP>, + <&clkgen JH7110_GMAC5_CLK_AHB>, + <&clkgen JH7110_GMAC5_CLK_AXI>, + <&clkgen JH7110_GMAC1_GTXC>, + <&clkgen JH7110_GMAC1_RMII_RTX>; + resets =3D <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>, + <&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>; + reset-names =3D "ahb", "stmmaceth"; + interrupts =3D <78>, <77>, <76> ; + interrupt-names =3D "macirq", "eth_wake_irq", "eth_lpi"; + max-frame-size =3D <9000>; + phy-mode =3D "rgmii-id"; + snps,multicast-filter-bins =3D <64>; + snps,perfect-filter-entries =3D <128>; + rx-fifo-depth =3D <2048>; + tx-fifo-depth =3D <2048>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config =3D <&stmmac_axi_setup>; + snps,tso; + snps,en-tx-lpi-clockgating; + snps,en-lpi; + snps,write-requests =3D <4>; + snps,read-requests =3D <4>; + snps,burst-map =3D <0x7>; + snps,txpbl =3D <16>; + snps,rxpbl =3D <16>; + status =3D "disabled"; + }; + + gpu: gpu@18000000 { + compatible =3D "img-gpu"; + reg =3D <0x0 0x18000000 0x0 0x100000>, + <0x0 0x130C000 0x0 0x10000>; + clocks =3D <&clkgen JH7110_GPU_CORE>, + <&clkgen JH7110_GPU_CLK_APB>, + <&clkgen JH7110_GPU_RTC_TOGGLE>, + <&clkgen JH7110_GPU_CORE_CLK>, + <&clkgen JH7110_GPU_SYS_CLK>, + <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>; + clock-names =3D "clk_bv", "clk_apb", "clk_rtc", + "clk_core", "clk_sys", "clk_axi"; + resets =3D <&rstgen RSTN_U0_IMG_GPU_APB>, + <&rstgen RSTN_U0_IMG_GPU_DOMA>; + reset-names =3D "rst_apb", "rst_doma"; + power-domains =3D <&pwrc JH7110_PD_GPUA>; + interrupts =3D <82>; + current-clock =3D <8000000>; + status =3D "disabled"; + }; + + can0: can@130d0000 { + compatible =3D "starfive,jh7110-can", "ipms,can"; + reg =3D <0x0 0x130d0000 0x0 0x1000>; + interrupts =3D <112>; + clocks =3D <&clkgen JH7110_CAN0_CTRL_CLK_APB>, + <&clkgen JH7110_CAN0_CTRL_CLK_CAN>, + <&clkgen JH7110_CAN0_CTRL_CLK_TIMER>; + clock-names =3D "apb_clk", "core_clk", "timer_clk"; + resets =3D <&rstgen RSTN_U0_CAN_CTRL_APB>, + <&rstgen RSTN_U0_CAN_CTRL_CORE>, + <&rstgen RSTN_U0_CAN_CTRL_TIMER>; + reset-names =3D "rst_apb", "rst_core", "rst_timer"; + frequency =3D <40000000>; + starfive,sys-syscon =3D <&sys_syscon 0x10 0x3 0x8>; + syscon,can_or_canfd =3D <0>; + status =3D "disabled"; + }; + + can1: can@130e0000 { + compatible =3D "starfive,jh7110-can", "ipms,can"; + reg =3D <0x0 0x130e0000 0x0 0x1000>; + interrupts =3D <113>; + clocks =3D <&clkgen JH7110_CAN1_CTRL_CLK_APB>, + <&clkgen JH7110_CAN1_CTRL_CLK_CAN>, + <&clkgen JH7110_CAN1_CTRL_CLK_TIMER>; + clock-names =3D "apb_clk", "core_clk", "timer_clk"; + resets =3D <&rstgen RSTN_U1_CAN_CTRL_APB>, + <&rstgen RSTN_U1_CAN_CTRL_CORE>, + <&rstgen RSTN_U1_CAN_CTRL_TIMER>; + reset-names =3D "rst_apb", "rst_core", "rst_timer"; + frequency =3D <40000000>; + starfive,sys-syscon =3D <&sys_syscon 0x88 0x12 0x40000>; + syscon,can_or_canfd =3D <1>; + status =3D "disabled"; + }; + + tdm: tdm@10090000 { + compatible =3D "starfive,jh7110-tdm"; + reg =3D <0x0 0x10090000 0x0 0x1000>; + reg-names =3D "tdm"; + clocks =3D <&clkgen JH7110_TDM_CLK_AHB>, + <&clkgen JH7110_TDM_CLK_APB>, + <&clkgen JH7110_TDM_INTERNAL>, + <&tdm_ext>, + <&clkgen JH7110_TDM_CLK_TDM>, + <&clkgen JH7110_MCLK_INNER>; + clock-names =3D "clk_tdm_ahb", "clk_tdm_apb", + "clk_tdm_internal", "clk_tdm_ext", + "clk_tdm", "mclk_inner"; + resets =3D <&rstgen RSTN_U0_TDM16SLOT_AHB>, + <&rstgen RSTN_U0_TDM16SLOT_APB>, + <&rstgen RSTN_U0_TDM16SLOT_TDM>; + reset-names =3D "tdm_ahb", "tdm_apb", "tdm_rst"; + dmas =3D <&dma 20 1>, <&dma 21 1>; + dma-names =3D "rx","tx"; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + + spdif0: spdif0@100a0000 { + compatible =3D "starfive,jh7110-spdif"; + reg =3D <0x0 0x100a0000 0x0 0x1000>; + clocks =3D <&clkgen JH7110_SPDIF_CLK_APB>, + <&clkgen JH7110_SPDIF_CLK_CORE>, + <&clkgen JH7110_AUDIO_ROOT>, + <&clkgen JH7110_MCLK_INNER>, + <&mclk_ext>, <&clkgen JH7110_MCLK>; + clock-names =3D "spdif-apb", "spdif-core", + "audroot", "mclk_inner", + "mclk_ext", "mclk"; + resets =3D <&rstgen RSTN_U0_CDNS_SPDIF_APB>; + reset-names =3D "rst_apb"; + interrupts =3D <84>; + interrupt-names =3D "tx"; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + + pwmdac: pwmdac@100b0000 { + compatible =3D "starfive,jh7110-pwmdac"; + reg =3D <0x0 0x100b0000 0x0 0x1000>; + clocks =3D <&clkgen JH7110_APB0>, + <&clkgen JH7110_PWMDAC_CLK_APB>, + <&clkgen JH7110_PWMDAC_CLK_CORE>; + clock-names =3D "apb0", "pwmdac-apb", "pwmdac-core"; + resets =3D <&rstgen RSTN_U0_PWMDAC_APB>; + reset-names =3D "rst-apb"; + dmas =3D <&dma 22 1>; + dma-names =3D "tx"; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + + i2stx: i2stx@100c0000 { + compatible =3D "snps,designware-i2stx"; + reg =3D <0x0 0x100c0000 0x0 0x1000>; + interrupt-names =3D "tx"; + #sound-dai-cells =3D <0>; + dmas =3D <&dma 28 1>; + dma-names =3D "rx"; + status =3D "disabled"; + }; + + pdm: pdm@100d0000 { + compatible =3D "starfive,jh7110-pdm"; + reg =3D <0x0 0x100d0000 0x0 0x1000>; + reg-names =3D "pdm"; + clocks =3D <&clkgen JH7110_PDM_CLK_DMIC>, + <&clkgen JH7110_PDM_CLK_APB>, + <&clkgen JH7110_MCLK>, + <&mclk_ext>; + clock-names =3D "pdm_mclk", + "pdm_apb", "clk_mclk", + "mclk_ext"; + resets =3D <&rstgen RSTN_U0_PDM_4MIC_DMIC>, + <&rstgen RSTN_U0_PDM_4MIC_APB>; + reset-names =3D "pdm_dmic", "pdm_apb"; + #sound-dai-cells =3D <0>; + }; + + i2srx_mst: i2srx_mst@100e0000 { + compatible =3D "starfive,jh7110-i2srx-master"; + reg =3D <0x0 0x100e0000 0x0 0x1000>; + clocks =3D <&clkgen JH7110_APB0>, + <&clkgen JH7110_I2SRX0_3CH_CLK_APB>, + <&clkgen JH7110_I2SRX_3CH_BCLK_MST>, + <&clkgen JH7110_I2SRX_3CH_LRCK_MST>, + <&clkgen JH7110_I2SRX0_3CH_BCLK>, + <&clkgen JH7110_I2SRX0_3CH_LRCK>, + <&clkgen JH7110_MCLK>, + <&mclk_ext>; + clock-names =3D "apb0", "i2srx_apb", + "i2srx_bclk_mst", "i2srx_lrck_mst", + "i2srx_bclk", "i2srx_lrck", + "mclk", "mclk_ext"; + resets =3D <&rstgen RSTN_U0_I2SRX_3CH_APB>, + <&rstgen RSTN_U0_I2SRX_3CH_BCLK>; + reset-names =3D "rst_apb_rx", "rst_bclk_rx"; + dmas =3D <&dma 24 1>; + dma-names =3D "rx"; + starfive,sys-syscon =3D <&sys_syscon 0x18 0x34>; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + + i2srx_3ch: i2srx_3ch@100e0000 { + compatible =3D "starfive,jh7110-i2srx", "snps,designware-i2s"; + reg =3D <0x0 0x100e0000 0x0 0x1000>; + clocks =3D <&clkgen JH7110_APB0>, + <&clkgen JH7110_I2SRX0_3CH_CLK_APB>, + <&clkgen JH7110_AUDIO_ROOT>, + <&clkgen JH7110_MCLK_INNER>, + <&clkgen JH7110_I2SRX_3CH_BCLK_MST>, + <&clkgen JH7110_I2SRX_3CH_LRCK_MST>, + <&clkgen JH7110_I2SRX0_3CH_BCLK>, + <&clkgen JH7110_I2SRX0_3CH_LRCK>, + <&clkgen JH7110_MCLK>, + <&mclk_ext>, + <&i2srx_bclk_ext>, + <&i2srx_lrck_ext>; + clock-names =3D "apb0", "3ch-apb", + "audioroot", "mclk-inner", + "bclk_mst", "3ch-lrck", + "rx-bclk", "rx-lrck", + "mclk", "mclk_ext", + "bclk-ext", "lrck-ext"; + resets =3D <&rstgen RSTN_U0_I2SRX_3CH_APB>, + <&rstgen RSTN_U0_I2SRX_3CH_BCLK>; + dmas =3D <&dma 24 1>; + dma-names =3D "rx"; + starfive,sys-syscon =3D <&sys_syscon 0x18 0x34>; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + + i2stx_4ch0: i2stx_4ch0@120b0000 { + compatible =3D "starfive,jh7110-i2stx-4ch0", "snps,designware-= i2s"; + reg =3D <0x0 0x120b0000 0x0 0x1000>; + clocks =3D <&clkgen JH7110_MCLK_INNER>, + <&clkgen JH7110_I2STX_4CH0_BCLK_MST>, + <&clkgen JH7110_I2STX_4CH0_LRCK_MST>, + <&clkgen JH7110_MCLK>, + <&clkgen JH7110_I2STX0_4CHBCLK>, + <&clkgen JH7110_I2STX0_4CHLRCK>, + <&clkgen JH7110_I2STX0_4CHCLK_APB>, + <&mclk_ext>; + clock-names =3D "inner", "bclk-mst", + "lrck-mst", "mclk", + "bclk0", "lrck0", + "i2s_apb", "mclk_ext"; + resets =3D <&rstgen RSTN_U0_I2STX_4CH_APB>, + <&rstgen RSTN_U0_I2STX_4CH_BCLK>; + reset-names =3D "rst_apb", "rst_bclk"; + dmas =3D <&dma 47 1>; + dma-names =3D "tx"; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + + i2stx_4ch1: i2stx_4ch1@120c0000 { + compatible =3D "starfive,jh7110-i2stx-4ch1", "snps,designware-= i2s"; + reg =3D <0x0 0x120c0000 0x0 0x1000>; + clocks =3D <&clkgen JH7110_AUDIO_ROOT>, + <&clkgen JH7110_MCLK_INNER>, + <&clkgen JH7110_I2STX_4CH1_BCLK_MST>, + <&clkgen JH7110_I2STX_4CH1_LRCK_MST>, + <&clkgen JH7110_MCLK>, + <&clkgen JH7110_I2STX1_4CHBCLK>, + <&clkgen JH7110_I2STX1_4CHLRCK>, + <&clkgen JH7110_MCLK_OUT>, + <&clkgen JH7110_APB0>, + <&clkgen JH7110_I2STX1_4CHCLK_APB>, + <&mclk_ext>, + <&i2stx_bclk_ext>, + <&i2stx_lrck_ext>; + clock-names =3D "audroot", "mclk_inner", "bclk_mst", + "lrck_mst", "mclk", "4chbclk", + "4chlrck", "mclk_out", + "apb0", "clk_apb", + "mclk_ext", "bclk_ext", "lrck_ext"; + resets =3D <&rstgen RSTN_U1_I2STX_4CH_APB>, + <&rstgen RSTN_U1_I2STX_4CH_BCLK>; + dmas =3D <&dma 48 1>; + dma-names =3D "tx"; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + + ptc: pwm@120d0000 { + compatible =3D "starfive,jh7110-pwm"; + reg =3D <0x0 0x120d0000 0x0 0x10000>; + reg-names =3D "control"; + clocks =3D <&clkgen JH7110_PWM_CLK_APB>; + resets =3D <&rstgen RSTN_U0_PWM_8CH_APB>; + starfive,approx-freq =3D <2000000>; + #pwm-cells=3D<3>; + starfive,npwm =3D <8>; + status =3D "disabled"; + }; + + spdif_transmitter: spdif_transmitter { + compatible =3D "linux,spdif-dit"; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + + pwmdac_codec: pwmdac-transmitter { + compatible =3D "starfive,jh7110-pwmdac-dit"; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + + dmic_codec: dmic_codec { + compatible =3D "dmic-codec"; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + + spi0: spi@10060000 { + compatible =3D "arm,pl022", "arm,primecell"; + reg =3D <0x0 0x10060000 0x0 0x10000>; + clocks =3D <&clkgen JH7110_SPI0_CLK_APB>; + clock-names =3D "apb_pclk"; + resets =3D <&rstgen RSTN_U0_SSP_SPI_APB>; + reset-names =3D "rst_apb"; + interrupts =3D <38>; + /* shortage of dma channel that not be used */ + /*dmas =3D <&dma 14 1>, <&dma 15 1>;*/ + /*dma-names =3D "rx","tx";*/ + arm,primecell-periphid =3D <0x00041022>; + num-cs =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi1: spi@10070000 { + compatible =3D "arm,pl022", "arm,primecell"; + reg =3D <0x0 0x10070000 0x0 0x10000>; + clocks =3D <&clkgen JH7110_SPI1_CLK_APB>; + clock-names =3D "apb_pclk"; + resets =3D <&rstgen RSTN_U1_SSP_SPI_APB>; + reset-names =3D "rst_apb"; + interrupts =3D <39>; + /* shortage of dma channel that not be used */ + /*dmas =3D <&dma 16 1>, <&dma 17 1>;*/ + /*dma-names =3D "rx","tx";*/ + arm,primecell-periphid =3D <0x00041022>; + num-cs =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi2: spi@10080000 { + compatible =3D "arm,pl022", "arm,primecell"; + reg =3D <0x0 0x10080000 0x0 0x10000>; + clocks =3D <&clkgen JH7110_SPI2_CLK_APB>; + clock-names =3D "apb_pclk"; + resets =3D <&rstgen RSTN_U2_SSP_SPI_APB>; + reset-names =3D "rst_apb"; + interrupts =3D <40>; + /* shortage of dma channel that not be used */ + /*dmas =3D <&dma 18 1>, <&dma 19 1>;*/ + /*dma-names =3D "rx","tx";*/ + arm,primecell-periphid =3D <0x00041022>; + num-cs =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi3: spi@12070000 { + compatible =3D "arm,pl022", "arm,primecell"; + reg =3D <0x0 0x12070000 0x0 0x10000>; + clocks =3D <&clkgen JH7110_SPI3_CLK_APB>; + clock-names =3D "apb_pclk"; + resets =3D <&rstgen RSTN_U3_SSP_SPI_APB>; + reset-names =3D "rst_apb"; + interrupts =3D <52>; + /* shortage of dma channel that not be used */ + /*dmas =3D <&dma 39 1>, <&dma 40 1>;*/ + /*dma-names =3D "rx","tx";*/ + arm,primecell-periphid =3D <0x00041022>; + num-cs =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi4: spi@12080000 { + compatible =3D "arm,pl022", "arm,primecell"; + reg =3D <0x0 0x12080000 0x0 0x10000>; + clocks =3D <&clkgen JH7110_SPI4_CLK_APB>; + clock-names =3D "apb_pclk"; + resets =3D <&rstgen RSTN_U4_SSP_SPI_APB>; + reset-names =3D "rst_apb"; + interrupts =3D <53>; + /* shortage of dma channel that not be used */ + /*dmas =3D <&dma 41 1>, <&dma 42 1>;*/ + /*dma-names =3D "rx","tx";*/ + arm,primecell-periphid =3D <0x00041022>; + num-cs =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi5: spi@12090000 { + compatible =3D "arm,pl022", "arm,primecell"; + reg =3D <0x0 0x12090000 0x0 0x10000>; + clocks =3D <&clkgen JH7110_SPI5_CLK_APB>; + clock-names =3D "apb_pclk"; + resets =3D <&rstgen RSTN_U5_SSP_SPI_APB>; + reset-names =3D "rst_apb"; + interrupts =3D <54>; + /* shortage of dma channel that not be used */ + /*dmas =3D <&dma 43 1>, <&dma 44 1>;*/ + /*dma-names =3D "rx","tx";*/ + arm,primecell-periphid =3D <0x00041022>; + num-cs =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi6: spi@120A0000 { + compatible =3D "arm,pl022", "arm,primecell"; + reg =3D <0x0 0x120A0000 0x0 0x10000>; + clocks =3D <&clkgen JH7110_SPI6_CLK_APB>; + clock-names =3D "apb_pclk"; + resets =3D <&rstgen RSTN_U6_SSP_SPI_APB>; + reset-names =3D "rst_apb"; + interrupts =3D <55>; + /* shortage of dma channel that not be used */ + /*dmas =3D <&dma 45 1>, <&dma 46 1>;*/ + /*dma-names =3D "rx","tx";*/ + arm,primecell-periphid =3D <0x00041022>; + num-cs =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + pcie0: pcie@2B000000 { + compatible =3D "starfive,jh7110-pcie","plda,pci-xpressrich3-ax= i"; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + reg =3D <0x0 0x2B000000 0x0 0x1000000 + 0x9 0x40000000 0x0 0x10000000>; + reg-names =3D "reg", "config"; + device_type =3D "pci"; + starfive,stg-syscon =3D <&stg_syscon 0xc0 0xc4 0x130 0x1b8>; + starfive,phyctrl =3D <&phyctrl0 0x28 0x80>; + bus-range =3D <0x0 0xff>; + ranges =3D <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x0= 8000000>, + <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x4000000= 0>; + msi-parent =3D <&plic>; + interrupts =3D <56>; + interrupt-controller; + interrupt-names =3D "msi"; + interrupt-parent =3D <&plic>; + interrupt-map-mask =3D <0x0 0x0 0x0 0x7>; + interrupt-map =3D <0x0 0x0 0x0 0x1 &plic 0x1>, + <0x0 0x0 0x0 0x2 &plic 0x2>, + <0x0 0x0 0x0 0x3 &plic 0x3>, + <0x0 0x0 0x0 0x4 &plic 0x4>; + resets =3D <&rstgen RSTN_U0_PLDA_PCIE_AXI_MST0>, + <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV0>, + <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV>, + <&rstgen RSTN_U0_PLDA_PCIE_BRG>, + <&rstgen RSTN_U0_PLDA_PCIE_CORE>, + <&rstgen RSTN_U0_PLDA_PCIE_APB>; + reset-names =3D "rst_mst0", "rst_slv0", "rst_slv", + "rst_brg", "rst_core", "rst_apb"; + clocks =3D <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>, + <&clkgen JH7110_PCIE0_CLK_TL>, + <&clkgen JH7110_PCIE0_CLK_AXI_MST0>, + <&clkgen JH7110_PCIE0_CLK_APB>; + clock-names =3D "noc", "tl", "axi_mst0", "apb"; + status =3D "disabled"; + }; + + pcie1: pcie@2C000000 { + compatible =3D "starfive,jh7110-pcie","plda,pci-xpressrich3-ax= i"; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + reg =3D <0x0 0x2C000000 0x0 0x1000000 + 0x9 0xc0000000 0x0 0x10000000>; + reg-names =3D "reg", "config"; + device_type =3D "pci"; + starfive,stg-syscon =3D <&stg_syscon 0x270 0x274 0x2e0 0x368>; + starfive,phyctrl =3D <&phyctrl1 0x28 0x80>; + bus-range =3D <0x0 0xff>; + ranges =3D <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x0= 8000000>, + <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x4000000= 0>; + msi-parent =3D <&plic>; + interrupts =3D <57>; + interrupt-controller; + interrupt-names =3D "msi"; + interrupt-parent =3D <&plic>; + interrupt-map-mask =3D <0x0 0x0 0x0 0x7>; + interrupt-map =3D <0x0 0x0 0x0 0x1 &plic 0x1>, + <0x0 0x0 0x0 0x2 &plic 0x2>, + <0x0 0x0 0x0 0x3 &plic 0x3>, + <0x0 0x0 0x0 0x4 &plic 0x4>; + resets =3D <&rstgen RSTN_U1_PLDA_PCIE_AXI_MST0>, + <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV0>, + <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV>, + <&rstgen RSTN_U1_PLDA_PCIE_BRG>, + <&rstgen RSTN_U1_PLDA_PCIE_CORE>, + <&rstgen RSTN_U1_PLDA_PCIE_APB>; + reset-names =3D "rst_mst0", "rst_slv0", "rst_slv", + "rst_brg", "rst_core", "rst_apb"; + clocks =3D <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>, + <&clkgen JH7110_PCIE1_CLK_TL>, + <&clkgen JH7110_PCIE1_CLK_AXI_MST0>, + <&clkgen JH7110_PCIE1_CLK_APB>; + clock-names =3D "noc", "tl", "axi_mst0", "apb"; + status =3D "disabled"; + }; + + mailbox_contrl0: mailbox@0 { + compatible =3D "starfive,mail_box"; + reg =3D <0x0 0x13060000 0x0 0x0001000>; + clocks =3D <&clkgen JH7110_MAILBOX_CLK_APB>; + clock-names =3D "clk_apb"; + resets =3D <&rstgen RSTN_U0_MAILBOX_RRESETN>; + reset-names =3D "mbx_rre"; + interrupts =3D <26 27>; + #mbox-cells =3D <2>; + status =3D "disabled"; + }; + + mailbox_client0: mailbox_client@0 { + compatible =3D "starfive,mailbox-test"; + mbox-names =3D "rx", "tx"; + mboxes =3D <&mailbox_contrl0 0 1>,<&mailbox_contrl0 1 0>; + status =3D "disabled"; + }; + + display: display-subsystem { + compatible =3D "starfive,jh7110-display","verisilicon,display-= subsystem"; + ports =3D <&dc_out_dpi0>; + status =3D "disabled"; + }; + + dssctrl: dssctrl@295B0000 { + compatible =3D "starfive,jh7110-dssctrl","verisilicon,dss-ctrl= ", "syscon"; + reg =3D <0 0x295B0000 0 0x90>; + }; + + tda988x_pin: tda988x_pin { + compatible =3D "starfive,tda998x_rgb_pin"; + status =3D "disabled"; + }; + + rgb_output: rgb-output { + compatible =3D "starfive,jh7110-rgb_output","verisilicon,rgb-e= ncoder"; + //verisilicon,dss-syscon =3D <&dssctrl>; + //verisilicon,mux-mask =3D <0x70 0x380>; + //verisilicon,mux-val =3D <0x40 0x280>; + status =3D "disabled"; + }; + + dc8200: dc8200@29400000 { + compatible =3D "starfive,jh7110-dc8200","verisilicon,dc8200"; + verisilicon,dss-syscon =3D <&dssctrl>;//20220624 panel syscon + reg =3D <0x0 0x29400000 0x0 0x100>, + <0x0 0x29400800 0x0 0x2000>, + <0x0 0x17030000 0x0 0x1000>; + interrupts =3D <95>; + status =3D "disabled"; + clocks =3D <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>, + <&clkgen JH7110_VOUT_SRC>, + <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>, + <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>, + <&clkvout JH7110_U0_DC8200_CLK_PIX0>, + <&clkvout JH7110_U0_DC8200_CLK_PIX1>, + <&clkvout JH7110_U0_DC8200_CLK_AXI>, + <&clkvout JH7110_U0_DC8200_CLK_CORE>, + <&clkvout JH7110_U0_DC8200_CLK_AHB>, + <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>, + <&clkvout JH7110_DOM_VOUT_TOP_LCD_CLK>, + <&hdmitx0_pixelclk>, + <&clkvout JH7110_DC8200_PIX0>, + <&clkvout JH7110_U0_DC8200_CLK_PIX0_OUT>, + <&clkvout JH7110_U0_DC8200_CLK_PIX1_OUT>; + clock-names =3D "noc_disp","vout_src", + "top_vout_axi","top_vout_ahb", + "pix_clk","vout_pix1", + "axi_clk","core_clk","vout_ahb", + "vout_top_axi","vout_top_lcd","hdmitx0_pixelclk","dc8200_pi= x0", + "dc8200_pix0_out","dc8200_pix1_out"; + resets =3D <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>, + <&rstgen RSTN_U0_DC8200_AXI>, + <&rstgen RSTN_U0_DC8200_AHB>, + <&rstgen RSTN_U0_DC8200_CORE>, + <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>; + reset-names =3D "rst_vout_src","rst_axi","rst_ahb","rst_core", + "rst_noc_disp"; + }; + + dsi_output: dsi-output { + compatible =3D "starfive,jh7110-display-encoder","verisilicon,= dsi-encoder"; + status =3D "disabled"; + }; + + mipi_dphy: mipi-dphy@295e0000{ + compatible =3D "starfive,jh7110-mipi-dphy-tx","m31,mipi-dphy-t= x"; + reg =3D <0x0 0x295e0000 0x0 0x10000>; + clocks =3D <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>; + clock-names =3D "dphy_txesc"; + resets =3D <&rstgen RSTN_U0_MIPITX_DPHY_SYS>, + <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>; + reset-names =3D "dphy_sys", "dphy_txbytehs"; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + + mipi_dsi: mipi@295d0000 { + compatible =3D "starfive,jh7110-mipi_dsi","cdns,dsi"; + reg =3D <0x0 0x295d0000 0x0 0x10000>; + interrupts =3D <98>; + reg-names =3D "dsi"; + clocks =3D <&clkvout JH7110_U0_CDNS_DSITX_CLK_SYS>, + <&clkvout JH7110_U0_CDNS_DSITX_CLK_APB>, + <&clkvout JH7110_U0_CDNS_DSITX_CLK_TXESC>, + <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>; + clock-names =3D "sys", "apb", "txesc", "dpi"; + resets =3D <&rstgen RSTN_U0_CDNS_DSITX_DPI>, + <&rstgen RSTN_U0_CDNS_DSITX_APB>, + <&rstgen RSTN_U0_CDNS_DSITX_RXESC>, + <&rstgen RSTN_U0_CDNS_DSITX_SYS>, + <&rstgen RSTN_U0_CDNS_DSITX_TXBYTEHS>, + <&rstgen RSTN_U0_CDNS_DSITX_TXESC>; + reset-names =3D "dsi_dpi", "dsi_apb", "dsi_rxesc", + "dsi_sys", "dsi_txbytehs", "dsi_txesc"; + phys =3D <&mipi_dphy>; + phy-names =3D "dphy"; + status =3D "disabled"; + + }; + + hdmi: hdmi@29590000 { + compatible =3D "starfive,jh7110-hdmi","inno,hdmi"; + reg =3D <0x0 0x29590000 0x0 0x4000>; + interrupts =3D <99>; + /*interrupts =3D ;*/ + /*clocks =3D <&cru PCLK_HDMI>;*/ + /*clock-names =3D "pclk";*/ + /*pinctrl-names =3D "default";*/ + /*pinctrl-0 =3D <&hdmi_ctl>;*/ + status =3D "disabled"; + clocks =3D <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>, + <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>, + <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>, + <&hdmitx0_pixelclk>; + clock-names =3D "sysclk", "mclk","bclk","pclk"; + resets =3D <&rstgen RSTN_U0_HDMI_TX_HDMI>; + reset-names =3D "hdmi_tx"; + #sound-dai-cells =3D <0>; + }; + + sound0: snd-card0 { + compatible =3D "simple-audio-card"; + simple-audio-card,name =3D "Starfive-AC108-Sound-Card"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + sound1: snd-card1 { + compatible =3D "simple-audio-card"; + simple-audio-card,name =3D "Starfive-HDMI-Sound-Card"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + sound2: snd-card2 { + compatible =3D "simple-audio-card"; + simple-audio-card,name =3D "Starfive-PDM-Sound-Card"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + sound3: snd-card3 { + compatible =3D "simple-audio-card"; + simple-audio-card,name =3D "Starfive-PWMDAC-Sound-Card"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + sound4: snd-card4 { + compatible =3D "simple-audio-card"; + simple-audio-card,name =3D "Starfive-SPDIF-Sound-Card"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + sound5: snd-card5 { + compatible =3D "simple-audio-card"; + simple-audio-card,name =3D "Starfive-TDM-Sound-Card"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + sound6: snd-card6 { + compatible =3D "simple-audio-card"; + simple-audio-card,name =3D "Starfive-WM8960-Sound-Card"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + co_process: e24@0 { + compatible =3D "starfive,e24"; + reg =3D <0x0 0xc0110000 0x0 0x00001000>, + <0x0 0xc0111000 0x0 0x0001f000>; + reg-names =3D "ecmd", "espace"; + clocks =3D <&clkgen JH7110_E2_RTC_CLK>, + <&clkgen JH7110_E2_CLK_CORE>, + <&clkgen JH7110_E2_CLK_DBG>; + clock-names =3D "clk_rtc", "clk_core", "clk_dbg"; + resets =3D <&rstgen RSTN_U0_E24_CORE>; + reset-names =3D "e24_core"; + starfive,stg-syscon =3D <&stg_syscon>; + interrupt-parent =3D <&plic>; + firmware-name =3D "e24_elf"; + irq-mode =3D <1>; + mbox-names =3D "tx", "rx"; + mboxes =3D <&mailbox_contrl0 0 2>,<&mailbox_contrl0 2 0>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0xc0000000 0x0 0xc0000000 0x200000>; + status =3D "disabled"; + dsp@0 {}; + }; + + xrp: xrp@0 { + compatible =3D "cdns,xrp"; + reg =3D <0x0 0x10230000 0x0 0x00010000 + 0x0 0x10240000 0x0 0x00010000>; + memory-region =3D <&xrp_reserved>; + clocks =3D <&clkgen JH7110_HIFI4_CLK_CORE>; + clock-names =3D "core_clk"; + resets =3D <&rstgen RSTN_U0_HIFI4_CORE>, + <&rstgen RSTN_U0_HIFI4_AXI>; + reset-names =3D "rst_core","rst_axi"; + starfive,stg-syscon =3D <&stg_syscon>; + firmware-name =3D "hifi4_elf"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x40000000 0x0 0x20000000 0x040000 + 0xf0000000 0x0 0xf0000000 0x03000000>; + status =3D "disabled"; + dsp@0 { + }; + }; + + starfive_cpufreq: starfive,jh7110-cpufreq { + compatible =3D "starfive,jh7110-cpufreq"; + clocks =3D <&clkgen JH7110_CPU_CORE>; + clock-names =3D "cpu_clk"; + }; + }; +}; diff --git a/Platform/StarFive/VisionFive2/DeviceTree/StarFivePwmDac.dtsi b= /Platform/StarFive/VisionFive2/DeviceTree/StarFivePwmDac.dtsi new file mode 100644 index 000000000000..ed2883b5d02f --- /dev/null +++ b/Platform/StarFive/VisionFive2/DeviceTree/StarFivePwmDac.dtsi @@ -0,0 +1,26 @@ +/** @file + Device tree defination all JH7110 pwmdac audio for StarFive VisionFive 2= platform + + Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +&sound3 { + simple-audio-card,dai-link@0 { + reg =3D <0>; + format =3D "left_j"; + bitclock-master =3D <&sndcpu0>; + frame-master =3D <&sndcpu0>; + status =3D "okay"; + + sndcpu0: cpu { + sound-dai =3D <&pwmdac>; + }; + + codec { + sound-dai =3D <&pwmdac_codec>; + }; + }; +}; diff --git a/Platform/StarFive/VisionFive2/DeviceTree/StarFiveVisionFive2.d= ts b/Platform/StarFive/VisionFive2/DeviceTree/StarFiveVisionFive2.dts new file mode 100644 index 000000000000..6649c5b9dc00 --- /dev/null +++ b/Platform/StarFive/VisionFive2/DeviceTree/StarFiveVisionFive2.dts @@ -0,0 +1,211 @@ +/** @file + Device tree defination for StarFive VisionFive 2 platform + + Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/dts-v1/; +#include "StarFiveVisionFive2.dtsi" +#include "StarFiveHdmi.dtsi" + +/ { + model =3D "StarFive VisionFive V2"; + compatible =3D "starfive,visionfive-v2", "starfive,jh7110"; + + gpio-restart { + compatible =3D "gpio-restart"; + gpios =3D <&gpio 35 GPIO_ACTIVE_HIGH>; + priority =3D <160>; + }; + +}; + +&gpio { + uart0_pins: uart0-pins { + uart0-pins-tx { + starfive,pins =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + }; + + uart0-pins-rx { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-doen =3D ; + starfive,pin-gpio-din =3D ; + }; + }; + + i2c2_pins: i2c2-pins { + i2c2-pins-scl { + starfive,pins =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + starfive,pin-gpio-din =3D ; + }; + + i2c2-pins-sda { + starfive,pins =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + starfive,pin-gpio-din =3D ; + }; + }; + + mmc0_pins: mmc0-pins { + mmc0-pins-rest { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + }; + }; + + sdcard1_pins: sdcard1-pins { + sdcard1-pins0 { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + }; + + sdcard1-pins1 { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + starfive,pin-gpio-din =3D ; + }; + + sdcard1-pins2 { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + starfive,pin-gpio-din =3D ; + }; + + sdcard1-pins3 { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + starfive,pin-gpio-din =3D ; + }; + + sdcard1-pins4 { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + starfive,pin-gpio-din =3D ; + }; + + sdcard1-pins5 { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + starfive,pin-gpio-din =3D ; + }; + }; + + inno_hdmi_pins: inno_hdmi-pins { + inno_hdmi-scl { + starfive,pins =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + starfive,pin-gpio-din =3D ; + }; + + inno_hdmi-sda { + starfive,pins =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + starfive,pin-gpio-din =3D ; + }; + inno_hdmi-cec-pins { + starfive,pins =3D ; + //starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-doen =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-din =3D ; + }; + inno_hdmi-hpd-pins { + starfive,pins =3D ; + //starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-doen =3D ; + starfive,pin-gpio-din =3D ; + }; + }; + + mclk_ext_pins: mclk_ext_pins { + mclk_ext_pins { + starfive,pins =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-din =3D ; + starfive,pin-gpio-doen =3D ; + }; + }; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_pins>; + status =3D "okay"; +}; + +&i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2_pins>; + status =3D "okay"; +}; + +&sdio0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mmc0_pins>; + status =3D "okay"; +}; + +&sdio1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdcard1_pins>; + //cd-gpios =3D <&gpio 41 0>; + status =3D "okay"; +}; + +&hdmi { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&inno_hdmi_pins>; +}; + +&i2stx_4ch0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mclk_ext_pins>; + status =3D "okay"; +}; + +&cpu1 { + cpu-supply =3D <&cpu_vdd>; + clocks =3D <&clkgen JH7110_CPU_CORE>; + clock-names =3D "cpu"; +}; diff --git a/Platform/StarFive/VisionFive2/DeviceTree/StarFiveVisionFive2.d= tsi b/Platform/StarFive/VisionFive2/DeviceTree/StarFiveVisionFive2.dtsi new file mode 100755 index 000000000000..f56307568874 --- /dev/null +++ b/Platform/StarFive/VisionFive2/DeviceTree/StarFiveVisionFive2.dtsi @@ -0,0 +1,838 @@ +/** @file + Device tree defination for StarFive VisionFive 2 platform + + Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/dts-v1/; +#include "StarFiveJH7110.dtsi" +#include "StarFivePwmDac.dtsi" +#include "JH7110PinCtrl.h" +#include "Gpio.h" +#include "Led.h" + +/ { + model =3D "StarFive VisionFive V2"; + compatible =3D "starfive,visionfive-v2", "starfive,jh7110"; + + aliases { + spi0 =3D &qspi; + gpio0 =3D &gpio; + ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; + mmc0 =3D &sdio0; + mmc1 =3D &sdio1; + serial0 =3D &uart0; + serial3 =3D &uart3; + i2c0 =3D &i2c0; + i2c1 =3D &i2c1; + i2c2 =3D &i2c2; + i2c3 =3D &i2c3; + i2c4 =3D &i2c4; + i2c5 =3D &i2c5; + i2c6 =3D &i2c6; + }; + + chosen { + linux,initrd-start =3D <0x0 0x46100000>; + linux,initrd-end =3D <0x0 0x4c000000>; + stdout-path =3D "serial0:115200"; + #bootargs =3D "debug console=3DttyS0 rootwait"; + }; + + cpus { + timebase-frequency =3D <4000000>; + }; + + memory@40000000 { + device_type =3D "memory"; + reg =3D <0x0 0x40000000 0x1 0x0>; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + linux,cma { + compatible =3D "shared-dma-pool"; + reusable; + size =3D <0x0 0x20000000>; + alignment =3D <0x0 0x1000>; + alloc-ranges =3D <0x0 0x80000000 0x0 0x20000000>; + linux,cma-default; + }; + + e24_mem: e24@c0000000 { + no-map; + reg =3D <0x0 0xc0110000 0x0 0xf0000>; + }; + + xrp_reserved: xrpbuffer@f0000000 { + reg =3D <0x0 0xf0000000 0x0 0x01ffffff + 0x0 0xf2000000 0x0 0x00001000 + 0x0 0xf2001000 0x0 0x00fff000 + 0x0 0xf3000000 0x0 0x00001000>; + }; + + }; + + leds { + compatible =3D "gpio-leds"; + + led-ack { + gpios =3D <&gpioa 3 GPIO_ACTIVE_HIGH>; + color =3D ; + function =3D LED_FUNCTION_HEARTBEAT; + linux,default-trigger =3D "heartbeat"; + label =3D "ack"; + }; + }; +}; + +&gpio { + i2c0_pins: i2c0-pins { + i2c0-pins-scl { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + starfive,pin-gpio-din =3D ; + }; + + i2c0-pins-sda { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + starfive,pin-gpio-din =3D ; + }; + }; + + i2c5_pins: i2c5-pins { + i2c5-pins-scl { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + starfive,pin-gpio-din =3D ; + }; + + i2c5-pins-sda { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + starfive,pin-gpio-din =3D ; + }; + }; + + i2c6_pins: i2c6-pins { + i2c6-pins-scl { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + starfive,pin-gpio-din =3D ; + }; + + i2c6-pins-sda { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + starfive,pin-gpio-din =3D ; + }; + }; + + csi_pins: csi-pins { + csi-pins-pwdn { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + }; + }; + + pwmdac0_pins: pwmdac0-pins { + pwmdac0-pins-left { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + }; + + pwmdac0-pins-right { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + }; + }; + + pwm_pins: pwm-pins { + pwm_ch0-pins { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + }; + + pwm_ch1-pins { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + }; + }; + + ssp0_pins: ssp0-pins { + ssp0-pins_tx { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + }; + + ssp0-pins_rx { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-doen =3D ; + starfive,pin-gpio-din =3D ; + }; + + ssp0-pins_clk { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + }; + + ssp0-pins_cs { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + }; + }; + + pcie0_perst_default: pcie0_perst_default { + perst-pins { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + }; + }; + + pcie0_perst_active: pcie0_perst_active { + perst-pins { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + }; + }; + + pcie0_wake_default: pcie0_wake_default { + wake-pins { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-doen =3D ; + }; + }; + + pcie0_clkreq_default: pcie0_clkreq_default { + clkreq-pins { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-doen =3D ; + }; + }; + + pcie1_perst_default: pcie1_perst_default { + perst-pins { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + }; + }; + + pcie1_perst_active: pcie1_perst_active { + perst-pins { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + }; + }; + + pcie1_wake_default: pcie1_wake_default { + wake-pins { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-doen =3D ; + }; + }; + + pcie1_clkreq_default: pcie1_clkreq_default { + clkreq-pins { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-doen =3D ; + }; + }; + + usb_pins: usb-pins { + drive-vbus-pin { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + }; + }; + + i2srx_pins: i2srx-pins { + i2srx-pins0 { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-doen =3D ; + starfive,pin-gpio-din =3D ; + }; + }; + + i2s_clk_pins: i2s-clk0 { + i2s-clk0_bclk { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-din =3D ; + starfive,pin-gpio-doen =3D ; + }; + + i2s-clk0_lrclk { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-din =3D ; + starfive,pin-gpio-doen =3D ; + }; + }; + + i2stx_pins: i2stx-pins { + i2stx-pins0 { + starfive,pins =3D ; + starfive,pinmux =3D ; + starfive,pin-ioconfig =3D ; + starfive,pin-gpio-dout =3D ; + starfive,pin-gpio-doen =3D ; + }; + }; +}; + +&uart0 { + status =3D "okay"; +}; + +&dma { + status =3D "okay"; +}; + +&trng { + status =3D "okay"; +}; + +&crypto { + status =3D "okay"; +}; + +&sec_dma { + status =3D "okay"; +}; + +&i2c0 { + clock-frequency =3D <100000>; + i2c-sda-hold-time-ns =3D <300>; + i2c-sda-falling-time-ns =3D <510>; + i2c-scl-falling-time-ns =3D <510>; + auto_calc_scl_lhcnt; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_pins>; + status =3D "okay"; +}; + +&i2c2 { + clock-frequency =3D <100000>; + i2c-sda-hold-time-ns =3D <300>; + i2c-sda-falling-time-ns =3D <510>; + i2c-scl-falling-time-ns =3D <510>; + auto_calc_scl_lhcnt; + status =3D "okay"; + + seeed_plane_i2c@45 { + compatible =3D "seeed_panel"; + reg =3D <0x45>; + + port { + panel_out0: endpoint { + remote-endpoint =3D <&dsi0_output>; + }; + }; + }; + + tinker_ft5406: tinker_ft5406@38 { + compatible =3D "tinker_ft5406"; + reg =3D <0x38>; + }; + + panel_radxa@19 { + compatible =3D"starfive_jadard"; + reg =3D <0x19>; + reset-gpio =3D <&gpio 23 0>; + enable-gpio =3D <&gpio 22 0>; + + port { + panel_out1: endpoint { + remote-endpoint =3D <&dsi1_output>; + }; + }; + }; + + touchscreen@14 { + compatible =3D "goodix,gt911"; + reg =3D <0x14>; + irq-gpios =3D <&gpio 30 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&gpio 31 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c5 { + clock-frequency =3D <100000>; + i2c-sda-hold-time-ns =3D <300>; + i2c-sda-falling-time-ns =3D <510>; + i2c-scl-falling-time-ns =3D <510>; + auto_calc_scl_lhcnt; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c5_pins>; + status =3D "okay"; + + eeprom@50 { + compatible =3D "atmel,24c04"; + reg =3D <0x50>; + pagesize =3D <16>; + }; + + pmic: axp15060_reg@36 { + compatible =3D "stf,axp15060-regulator"; + reg =3D <0x36>; + + regulators { + mipi_0p9: ALDO1 { + regulator-boot-on; + regulator-compatible =3D "mipi_0p9"; + regulator-name =3D "mipi_0p9"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + }; + hdmi_0p9: ALDO5 { + regulator-boot-on; + regulator-compatible =3D "hdmi_0p9"; + regulator-name =3D "hdmi_0p9"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + }; + hdmi_1p8: ALDO3 { + regulator-boot-on; + regulator-compatible =3D "hdmi_1p8"; + regulator-name =3D "hdmi_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + cpu_vdd: DCDC2 { + regulator-boot-on; + regulator-always-on; + regulator-compatible =3D "cpu_vdd"; + regulator-name =3D "cpu_vdd"; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1540000>; + }; + }; + }; +}; + +&i2c6 { + clock-frequency =3D <100000>; + i2c-sda-hold-time-ns =3D <300>; + i2c-sda-falling-time-ns =3D <510>; + i2c-scl-falling-time-ns =3D <510>; + auto_calc_scl_lhcnt; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c6_pins>; + status =3D "okay"; + + imx219: imx219@10 { + compatible =3D "sony,imx219"; + reg =3D <0x10>; + clocks =3D <&clk_ext_camera>; + clock-names =3D "xclk"; + //reset-gpio =3D <&gpio 18 0>; + //DOVDD-supply =3D <&v2v8>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&csi_pins>; + rotation =3D <0>; + orientation =3D <1>; //CAMERA_ORIENTATION_BACK + + port { + /* CSI2 bus endpoint */ + imx219_to_csi2rx0: endpoint { + remote-endpoint =3D <&csi2rx0_from_imx219>; + bus-type =3D <4>; /* MIPI CSI-2 D-PHY */ + clock-lanes =3D <4>; + data-lanes =3D <0 1>; + lane-polarities =3D <0 0 0>; + link-frequencies =3D /bits/ 64 <456000000>; + }; + }; + }; +}; + +&sdio0 { + max-frequency =3D <100000000>; + card-detect-delay =3D <300>; + bus-width =3D <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + cap-mmc-hw-reset; + post-power-on-delay-ms =3D <200>; + status =3D "okay"; +}; + +&sdio1 { + max-frequency =3D <100000000>; + card-detect-delay =3D <300>; + bus-width =3D <4>; + no-sdio; + no-mmc; + broken-cd; + cap-sd-highspeed; + post-power-on-delay-ms =3D <200>; + status =3D "okay"; +}; + +&vin_sysctl { + /* when use dvp open this pinctrl*/ + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* CSI2 bus endpoint */ + csi2rx0_from_imx219: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&imx219_to_csi2rx0>; + bus-type =3D <4>; /* MIPI CSI-2 D-PHY */ + clock-lanes =3D <4>; + data-lanes =3D <0 1>; + lane-polarities =3D <0 0 0>; + status =3D "okay"; + }; + }; + }; +}; + +&sfctemp { + status =3D "okay"; +}; + +&jpu { + status =3D "okay"; +}; + +&vpu_dec { + status =3D "okay"; +}; + +&vpu_enc { + status =3D "okay"; +}; + +&gmac0 { + status =3D "okay"; + #address-cells =3D <1>; + #size-cells =3D <0>; + phy0: ethernet-phy@0 { + rxc_dly_en =3D <1>; + tx_delay_sel_fe =3D <5>; + tx_delay_sel =3D <0xa>; + tx_inverted_10 =3D <0x1>; + tx_inverted_100 =3D <0x1>; + tx_inverted_1000 =3D <0x1>; + }; +}; + +&gmac1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + phy1: ethernet-phy@1 { + tx_delay_sel_fe =3D <5>; + tx_delay_sel =3D <0>; + rxc_dly_en =3D <0>; + tx_inverted_10 =3D <0x1>; + tx_inverted_100 =3D <0x1>; + tx_inverted_1000 =3D <0x0>; + }; +}; + +&gpu { + status =3D "okay"; +}; + +&pwmdac { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwmdac0_pins>; + status =3D "okay"; +}; + +&i2srx_3ch { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2s_clk_pins &i2srx_pins>; + status =3D "disabled"; +}; + +&i2stx_4ch1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2stx_pins>; + status =3D "disabled"; +}; + +&pwmdac_codec { + status =3D "okay"; +}; + +&spi0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ssp0_pins>; + status =3D "okay"; + + spi_dev0: spi@0 { + compatible =3D "rohm,dh2228fv"; + pl022,com-mode =3D <1>; + spi-max-frequency =3D <10000000>; + reg =3D <0>; + status =3D "okay"; + }; +}; + +&pcie0 { + pinctrl-names =3D "default", "perst-default", "perst-active"; + pinctrl-0 =3D <&pcie0_wake_default>, + <&pcie0_clkreq_default>; + pinctrl-1 =3D <&pcie0_perst_default>; + pinctrl-2 =3D <&pcie0_perst_active>; + status =3D "okay"; +}; + +&pcie1 { + pinctrl-names =3D "default", "perst-default", "perst-active"; + pinctrl-0 =3D <&pcie1_wake_default>, + <&pcie1_clkreq_default>; + pinctrl-1 =3D <&pcie1_perst_default>; + pinctrl-2 =3D <&pcie1_perst_active>; + status =3D "okay"; +}; + +&mailbox_contrl0 { + status =3D "okay"; +}; + +&mailbox_client0 { + status =3D "okay"; +}; + +&display { + status =3D "okay"; +}; + +&hdmi { + status =3D "okay"; + + hdmi_in: port { + #address-cells =3D <1>; + #size-cells =3D <0>; + hdmi_in_lcdc: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&dc_out_dpi1>; + }; + }; +}; + +&dc8200 { + status =3D "okay"; + + dc_out: port { + #address-cells =3D <1>; + #size-cells =3D <0>; + dc_out_dpi0: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&hdmi_input0>; + }; + dc_out_dpi1: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&hdmi_in_lcdc>; + }; + + dc_out_dpi2: endpoint@2 { + reg =3D <2>; + remote-endpoint =3D <&mipi_in>; + }; + }; +}; + +&rgb_output { + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + hdmi_input0:endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&dc_out_dpi0>; + }; + }; + }; +}; + +&dsi_output { + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mipi_in: endpoint { + remote-endpoint =3D <&dc_out_dpi2>; + }; + }; + + port@1 { + reg =3D <1>; + sf_dpi_output: endpoint { + remote-endpoint =3D <&dsi_in_port>; + }; + }; + }; +}; + +&mipi_dsi { + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + dsi0_output: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&panel_out0>; + }; + + dsi1_output: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&panel_out1>; + }; + }; + + port@1{ + reg =3D <1>; + dsi_in_port: endpoint { + remote-endpoint =3D <&sf_dpi_output>; + }; + }; + + }; +}; + +&mipi_dphy { + status =3D "okay"; +}; + +&co_process { + status =3D "okay"; +}; + +&usbdrd30 { + clocks =3D <&clkgen JH7110_USB_125M>, + <&clkgen JH7110_USB0_CLK_APP_125>, + <&clkgen JH7110_USB0_CLK_LPM>, + <&clkgen JH7110_USB0_CLK_STB>, + <&clkgen JH7110_USB0_CLK_USB_APB>, + <&clkgen JH7110_USB0_CLK_AXI>, + <&clkgen JH7110_USB0_CLK_UTMI_APB>; + clock-names =3D "125m","app","lpm","stb","apb","axi","utmi"; + resets =3D <&rstgen RSTN_U0_CDN_USB_PWRUP>, + <&rstgen RSTN_U0_CDN_USB_APB>, + <&rstgen RSTN_U0_CDN_USB_AXI>, + <&rstgen RSTN_U0_CDN_USB_UTMI_APB>; + reset-names =3D "pwrup","apb","axi","utmi"; + starfive,usb2-only; + dr_mode =3D "peripheral"; /*host or peripheral*/ + status =3D "okay"; +}; + +&xrp { + status =3D "okay"; +}; + +&ptc { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm_pins>; + status =3D "okay"; +}; diff --git a/Platform/StarFive/VisionFive2/DeviceTree/Thermal.h b/Platform/= StarFive/VisionFive2/DeviceTree/Thermal.h new file mode 100644 index 000000000000..48af62f5722e --- /dev/null +++ b/Platform/StarFive/VisionFive2/DeviceTree/Thermal.h @@ -0,0 +1,16 @@ +/** @file + This header provide all the thermal bindings + + Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __DT_BINDINGS_THERMAL_H__ +#define __DT_BINDINGS_THERMAL_H__ + +/* On cooling devices upper and lower limits */ +#define THERMAL_NO_LIMIT (~0) + +#endif /* __DT_BINDINGS_THERMAL_H__ */ diff --git a/Platform/StarFive/VisionFive2/DeviceTree/VisionFive2DeviceTree= .inf b/Platform/StarFive/VisionFive2/DeviceTree/VisionFive2DeviceTree.inf new file mode 100644 index 000000000000..75256cbf6406 --- /dev/null +++ b/Platform/StarFive/VisionFive2/DeviceTree/VisionFive2DeviceTree.inf @@ -0,0 +1,36 @@ +## @file +# Device tree description of the StarFive VisionFive 2 platform +# +# Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<= BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D VisionFive2DeviceTree + FILE_GUID =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 #gDtPlatformDefa= ultDtbFileGuid + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + StarFiveClk.dtsi + StarFiveHdmi.dtsi + StarFiveVisionFive2.dtsi + StarFivePwmDac.dtsi + StarFiveVisionFive2.dts + StarFiveVisionFive2.dtsi + JH7110Rst.h + JH7110Power.h + JH7110ClkGen.h + JH7110ClkIsp.h + JH7110ClkVout.h + JH7110PinCtrl.h + Led.h + Irq.h + Gpio.h + Thermal.h + +[Packages] + MdePkg/MdePkg.dec diff --git a/Platform/StarFive/VisionFive2/VarStore.fdf.inc b/Platform/Star= Five/VisionFive2/VarStore.fdf.inc new file mode 100644 index 000000000000..62b4baa43e98 --- /dev/null +++ b/Platform/StarFive/VisionFive2/VarStore.fdf.inc @@ -0,0 +1,77 @@ +## @file +# FDF include file with Layout Regions that define an empty variable stor= e. +# +# Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<= BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +$(VARS_OFFSET)|$(VARS_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +# +# NV_VARIABLE_STORE +# +DATA =3D { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid =3D + # { 0xFFF12B8D, 0x7696, 0x4C8B, + # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }} + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0xC0000 + 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, + # Signature "_FVH" # Attributes + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, + # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0x28, 0x09, 0x00, 0x00, 0x00, 0x02, + # Blockmap[0]: 0x3 Blocks * 0x40000 Bytes / Block + 0x3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, + # Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + # Signature: gEfiAuthenticatedVariableGuid =3D + # { 0xaaf32c78, 0x947b, 0x439a, + # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, +!else + # Signature: gEfiVariableGuid =3D + # { 0xddcf3616, 0x3275, 0x4164, + # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, +!endif + # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariabl= eSize) - + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) =3D 0x3FFB8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0xFF, 0x03, 0x00, + # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +$(VARS_FTW_WORKING_OFFSET)|$(VARS_FTW_WORKING_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +# +# NV_FTW_WORKING +# +DATA =3D { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =3D gEdkiiWorkingBl= ockSignatureGuid =3D + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0= x1b, 0x95 }} + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Res= erved + 0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 + 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +$(VARS_FTW_SPARE_OFFSET)|$(VARS_FTW_SPARE_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize +# +# NV_FTW_SPARE +# diff --git a/Platform/StarFive/VisionFive2/VisionFive2.dsc b/Platform/StarF= ive/VisionFive2/VisionFive2.dsc new file mode 100644 index 000000000000..d8dd16867c20 --- /dev/null +++ b/Platform/StarFive/VisionFive2/VisionFive2.dsc @@ -0,0 +1,596 @@ +## @file +# RISC-V EFI on StarFive VisionFive 2 platform +# +# Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<= BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + PLATFORM_NAME =3D VisionFive2 + PLATFORM_GUID =3D 8317E90F-428B-403F-9057-112B0C19008E + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x0001001c + OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES =3D RISCV64 + BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D Platform/StarFive/VisionFive2/VisionF= ive2.fdf + + # + # Enable below options may cause build error or may not work on + # the initial version of RISC-V package + # Defines for default states. These can be changed on the command line. + # -D FLAG=3DVALUE + # + DEFINE SECURE_BOOT_ENABLE =3D FALSE + DEFINE DEBUG_ON_SERIAL_PORT =3D FALSE + + # + # Network definition + # + DEFINE NETWORK_SNP_ENABLE =3D FALSE + DEFINE NETWORK_IP6_ENABLE =3D FALSE + DEFINE NETWORK_TLS_ENABLE =3D FALSE + DEFINE NETWORK_HTTP_BOOT_ENABLE =3D FALSE + DEFINE NETWORK_ISCSI_ENABLE =3D FALSE + +[BuildOptions] + GCC:RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG +!ifdef $(SOURCE_DEBUG_ENABLE) + GCC:*_*_RISCV64_GENFW_FLAGS =3D --keepexceptiontable +!endif + +##########################################################################= ###### +# +# SKU Identification section - list of all SKU IDs supported by this Platf= orm. +# +##########################################################################= ###### +[SkuIds] + 0|DEFAULT + +##########################################################################= ###### +# +# Library Class section - list of all Library Classes needed by this Platf= orm. +# +##########################################################################= ###### + +!include MdePkg/MdeLibs.dsc.inc + +[LibraryClasses] + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchroniza= tionLib.inf + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibN= ull.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMain= tenanceLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServic= esLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableL= ib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf + PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf + PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf + SerialPortLib|MdePkg/Library/BaseSerialPortLibRiscVSbiLib/BaseSerialPort= LibRiscVSbiLibRam.inf + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDev= icePathLibDevicePathProtocol.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeS= ecurityManagementLib.inf + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf + SortLib|MdeModulePkg/Library/BaseSortLib/BaseSortLib.inf + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + VariableFlashInfoLib|MdeModulePkg/Library/BaseVariableFlashInfoLib/BaseV= ariableFlashInfoLib.inf + VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/Var= iablePolicyHelperLib.inf + NorFlashInfoLib|EmbeddedPkg/Library/NorFlashInfoLib/NorFlashInfoLib.inf + +# RISC-V Platform Library + TimeBaseLib|EmbeddedPkg//Library/TimeBaseLib/TimeBaseLib.inf + RealTimeClockLib|EmbeddedPkg//Library/VirtualRealTimeClockLib/VirtualRea= lTimeClockLib.inf + +# RISC-V Core Library + RiscVOpensbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/Risc= VOpensbiLib.inf + +!ifdef $(SOURCE_DEBUG_ENABLE) + PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDeb= ug/PeCoffExtraActionLibDebug.inf + DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibS= erialPort/DebugCommunicationLibSerialPort.inf +!else + PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeC= offExtraActionLibNull.inf + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.i= nf +!endif + + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseD= ebugPrintErrorLevelLib.inf + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf + TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasure= mentLib.inf + AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf + SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBo= otVariableLib.inf + SecureBootVariableProvisionLib|SecurityPkg/Library/SecureBootVariablePro= visionLib/SecureBootVariableProvisionLib.inf + PlatformPKProtectionLib|SecurityPkg/Library/PlatformPKProtectionLibVarPo= licy/PlatformPKProtectionLibVarPolicy.inf +!else + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem= entLibNull.inf + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLib= Null.inf +!endif + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf + +!if $(HTTP_BOOT_ENABLE) =3D=3D TRUE + HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf +!endif + + # ACPI not supported yet. + #S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScri= ptLib.inf + SmbusLib|MdePkg/Library/BaseSmbusLibNull/BaseSmbusLibNull.inf + OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib= /BaseOrderedCollectionRedBlackTreeLib.inf + +[LibraryClasses.common] +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf +!endif + RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.= inf + RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf + RiscVMmuLib|UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf + MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachine= ModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf + CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandler= Lib/BaseRiscV64CpuExceptionHandlerLib.inf + # Pci dependencies + PciHostBridgeLib|Silicon/StarFive/JH7110Pkg/Library/PciHostBridgeLib/Pci= HostBridgeLib.inf + PciSegmentLib|Silicon/StarFive/JH7110Pkg/Library/PciSegmentLib/PciSegmen= tLib.inf + TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLi= b.inf + + # Flattened Device Tree (FDT) access library + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + +[LibraryClasses.common.SEC] +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + + ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseE= xtractGuidedSectionLib.inf + +[LibraryClasses.common.DXE_CORE] + TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLi= b.inf + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeC= oreMemoryAllocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExt= ractGuidedSectionLib.inf +!ifdef $(SOURCE_DEBUG_ENABLE) + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf +!endif + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLi= b.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/R= untimeDxeReportStatusCodeLib.inf + ResetSystemLib|Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetS= ystemLib.inf + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf +!endif + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyL= ibRuntimeDxe.inf + +[LibraryClasses.common.UEFI_DRIVER] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLi= b.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyL= ib.inf + +[LibraryClasses.common.DXE_DRIVER] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLi= b.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif +!ifdef $(SOURCE_DEBUG_ENABLE) + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf +!endif + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf + PlatformBootManagerLib|Platform/RISC-V/PlatformPkg/Library/PlatformBootM= anagerLib/PlatformBootManagerLib.inf + PlatformBmPrintScLib|OvmfPkg/Library/PlatformBmPrintScLib/PlatformBmPrin= tScLib.inf + PlatformMemoryTestLib|Platform/RISC-V/PlatformPkg/Library/PlatformMemory= TestLibNull/PlatformMemoryTestLibNull.inf + PlatformUpdateProgressLib|Platform/RISC-V/PlatformPkg/Library/PlatformUp= dateProgressLibNull/PlatformUpdateProgressLibNull.inf + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf + +[LibraryClasses.common.UEFI_APPLICATION] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLi= b.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +##########################################################################= ###### +[PcdsFeatureFlag] + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE + +[PcdsFixedAtBuild] + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1 + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FAL= SE + gEfiMdePkgTokenSpaceGuid.PcdMaximumGuidedExtractHandler|0x10 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x8000 + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0xe000 + gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 + gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|0 + + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F +!ifdef $(SOURCE_DEBUG_ENABLE) + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F +!endif + +!ifdef $(SOURCE_DEBUG_ENABLE) + gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 +!endif + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + # override the default values from SecurityPkg to ensure images from all= sources are verified in secure boot + gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0= x04 +!endif + + # F2 for UI APP + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c= , 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0= x31 } + + # PCIE + gJH7110TokenSpaceGuid.PcdPciBusMin|0x00 + gJH7110TokenSpaceGuid.PcdPciBusMax|0xFF + gJH7110TokenSpaceGuid.PcdPciIoBase|0x01 + gJH7110TokenSpaceGuid.PcdPciIoSize|0x00 #Disable PIO + gJH7110TokenSpaceGuid.PcdPciIoOffset|0x00 + gJH7110TokenSpaceGuid.PcdPci0Mmio32Base|0x30000000 + gJH7110TokenSpaceGuid.PcdPci0Mmio32Size|0x8000000 + gJH7110TokenSpaceGuid.PcdPci0Mmio64Base|0x900000000 + gJH7110TokenSpaceGuid.PcdPci0Mmio64Size|0x40000000 + gJH7110TokenSpaceGuid.PcdPci1Mmio32Base|0x38000000 + gJH7110TokenSpaceGuid.PcdPci1Mmio32Size|0x8000000 + gJH7110TokenSpaceGuid.PcdPci1Mmio64Base|0x980000000 + gJH7110TokenSpaceGuid.PcdPci1Mmio64Size|0x40000000 + + # DW MMC/SD card controller + gDesignWareTokenSpaceGuid.PcdDwEmmcDxeBaseAddress|0x16010000 + gDesignWareTokenSpaceGuid.PcdDwSdDxeBaseAddress|0x16020000 + gDesignWareTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz|198000000 + gDesignWareTokenSpaceGuid.PcdDwEmmcDxeMaxClockFreqInHz|198000000 + gDesignWareTokenSpaceGuid.PcdDwPermitObsoleteDrivers|TRUE + gDesignWareTokenSpaceGuid.PcdDwEmmcDxeFifoDepth|32 + gDesignWareTokenSpaceGuid.PcdDwEmmcDxeUHSEn|FALSE + gDesignWareTokenSpaceGuid.PcdDwEmmcDxeCPULittleEndian|TRUE + + # SPI + gJH7110TokenSpaceGuid.PcdSpiFlashRegBase|0x13010000 + gJH7110TokenSpaceGuid.PcdSpiFlashAhbBase|0x21000000 + gJH7110TokenSpaceGuid.PcdSpiFlashFifoWidth|4 + gJH7110TokenSpaceGuid.PcdSpiFlashRefClkHz|100000000 + gJH7110TokenSpaceGuid.PcdSpiFlashTshslNs|1 + gJH7110TokenSpaceGuid.PcdSpiFlashTsd2dNs|1 + gJH7110TokenSpaceGuid.PcdSpiFlashTchshNs|1 + gJH7110TokenSpaceGuid.PcdSpiFlashTslchNs|1 + +##########################################################################= ###### +# +# Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Pla= tform +# +##########################################################################= ###### + +[PcdsDynamicDefault] + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0 + + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600 + + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|0 + + # + # Set video resolution for boot options and for text setup. + # PlatformDxe can set the former at runtime. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1280 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|800 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480 + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0 + + # Set video resolution for text setup. + # gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480 + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +##########################################################################= ###### +[Components] + + # + # SEC Phase modules + # + OvmfPkg/RiscVVirt/Sec/SecMain.inf { + + ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectio= nLib/PrePiExtractGuidedSectionLib.inf + LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaC= ustomDecompressLib.inf + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf + PrePiHobListPointerLib|OvmfPkg/RiscVVirt/Library/PrePiHobListPointer= Lib/PrePiHobListPointerLib.inf + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/Pre= PiMemoryAllocationLib.inf + } + + # + # DXE Phase modules + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + + NULL|MdeModulePkg//Library/LzmaCustomDecompressLib/LzmaCustomDecompr= essLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + } + + MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCod= eRouterRuntimeDxe.inf + MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRun= timeDxe.inf + + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + } + + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf { + + NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificatio= nLib.inf + } +!else + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf +!endif + + UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf + MdeModulePkg/Universal/Metronome/Metronome.inf + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf { + + ResetSystemLib|MdeModulePkg/Library/BaseResetSystemLibNull/BaseReset= SystemLibNull.inf + } + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + # MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.i= nf + # MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + # MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + # + # RISC-V Platform module + # + UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf + + # + # RISC-V Core module + # + UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib= /VariablePolicyHelperLib.inf + } + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntim= eDxe.inf + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + + # + # Emulator for x64 OpRoms, etc. + # + #MultiArchUefiPkg/Drivers/Emulator/Emulator.inf { + # + # UnicornEngineLib|unicorn/efi/UnicornEngineLib.inf + # UnicornStubLib|unicorn/efi/UnicornStubLib.inf + # UnicornX86Lib|unicorn/efi/UnicornX86Lib.inf + #} + + # No graphic console supported yet. + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf= { + + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + } + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf { + + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + MdeModulePkg/Universal/PrintDxe/PrintDxe.inf + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + # + # Network Support + # + !include NetworkPkg/Network.dsc.inc + + # + # sdio/mmc support + # + EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf + Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf { + + GCC:*_*_*_CC_FLAGS =3D -DCONFIG_DWEMMC + } + Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwSdmmcDxe.inf { + + GCC:*_*_*_CC_FLAGS =3D -DCONFIG_DWSDMMC + } + + # + # PCIe support + # + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf { + + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + } + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + + # + # NVMe boot devices + # + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + + # + # Usb Support + # + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + UDF filesystem + # + FatPkg/EnhancedFatDxe/Fat.inf + MdeModulePkg/Universal/Disk/UdfDxe/UdfDxe.inf + + # + # QSPI Flash Support + # + Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiDxe/SpiDxe.inf + Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiFlashDxe/SpiFlash= Dxe.inf + Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/FvbDxe/FvbDxe.inf + + OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand.in= f { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + } + + ShellPkg/Application/Shell/Shell.inf { + + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComman= dLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Co= mmandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1= CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1= CommandsLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandlePar= singLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcf= gCommandLib.inf + + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 + } + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDx= e.inf +!endif + + MdeModulePkg/Logo/LogoDxe.inf + MdeModulePkg/Application/UiApp/UiApp.inf { + + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanc= eManagerUiLib.inf + } + + # + # Device Tree Binary + # - Compile by EDK2, and will embed into OpenSBI .rodata section using F= W_FDT_PATH + # when compiling OpenSBI. EDK2 will get the start address of the devic= e tree from + # register 'a1' + # + Platform/StarFive/VisionFive2/DeviceTree/VisionFive2DeviceTree.inf diff --git a/Platform/StarFive/VisionFive2/VisionFive2.fdf b/Platform/StarF= ive/VisionFive2/VisionFive2.fdf new file mode 100644 index 000000000000..4007258ea588 --- /dev/null +++ b/Platform/StarFive/VisionFive2/VisionFive2.fdf @@ -0,0 +1,284 @@ +# @file +# Flash definition file on StarFive VisionFive 2 platform +# +# Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<= BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +!include VisionFive2.fdf.inc + +# +# Build the variable store and the firmware code as one unified flash devi= ce +# image. +# +[FD.VisionFive2] +BaseAddress =3D $(FW_BASE_OFFSET) +Size =3D $(FW_SIZE) +ErasePolarity =3D 1 +BlockSize =3D $(BLOCK_SIZE) +NumBlocks =3D $(BLOCK_NUM) + + +$(FVMAIN_OFFSET)|$(FVMAIN_SIZE) +gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase|gUefiOvmfPkgTokenSpaceGuid.= PcdOvmfDxeMemFvSize +FV =3D FVMAIN_COMPACT + +!include VarStore.fdf.inc + +##########################################################################= ###### + +[FV.DXEFV] +BlockSize =3D 0x10000 +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D 27A72E80-3118-4c0c-8673-AA5B4EFA9613 + +APRIORI DXE { + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiDxe/SpiDxe.i= nf + INF Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiFlashDxe/Spi= FlashDxe.inf + INF Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/FvbDxe/FvbDxe.i= nf +} + +# +# DXE Phase modules +# +INF MdeModulePkg/Core/Dxe/DxeMain.inf + +INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatus= CodeRouterRuntimeDxe.inf +INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandler= RuntimeDxe.inf +INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + +# +# Emulator for x64 OpRoms, etc. +# +#INF MultiArchUefiPkg/Drivers/Emulator/Emulator.inf + +INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf +INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf +INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf +INF MdeModulePkg/Universal/Metronome/Metronome.inf +INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + +# RISC-V Core Drivers +INF UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf +INF UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf + +INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + +INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootCon= figDxe.inf +!endif + +INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf +INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf +INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRun= timeDxe.inf +INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf +# +# Multiple Console IO support +# +INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf +INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf +INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.= inf +INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf +INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf +INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf +INF MdeModulePkg/Universal/PrintDxe/PrintDxe.inf +INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf +INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf +INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf +INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf +INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf +INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf +# INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf +# INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf +INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe= .inf +INF FatPkg/EnhancedFatDxe/Fat.inf +INF MdeModulePkg/Universal/Disk/UdfDxe/UdfDxe.inf + +# !ifndef $(SOURCE_DEBUG_ENABLE) +# INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf +# !endif + +INF OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand= .inf +INF ShellPkg/Application/Shell/Shell.inf + +# +# Bds +# +INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf +INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf +INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.= inf +INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf +INF MdeModulePkg/Application/UiApp/UiApp.inf + +# +# Network modules +# +!if $(E1000_ENABLE) + FILE DRIVER =3D 5D695E11-9B3F-4b83-B25F-4A8D5D69BE07 { + SECTION PE32 =3D Intel3.5/EFIX64/E3507X2.EFI + } +!endif + +!include NetworkPkg/Network.fdf.inc + +# +# SDIO/MMC support +# +INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf +INF Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf +INF Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwSdmmcDxe.inf + +# +# PCIe support +# +INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf +INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + +# NVMe boot devices +INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + +# +# Usb Support +# +INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf +INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf +INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf +INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf +INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf +INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf +INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + +# +# TianoCore logo (splash screen) +# +INF MdeModulePkg/Logo/LogoDxe.inf + +# +# QSPI Flash Support +# +INF Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiDxe/SpiDxe.inf +INF Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiFlashDxe/SpiFl= ashDxe.inf +INF Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/FvbDxe/FvbDxe.inf +##########################################################################= ###### + +[FV.FVMAIN_COMPACT] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + +INF OvmfPkg/RiscVVirt/Sec/SecMain.inf + +FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED= =3D TRUE { + # + # These firmware volumes will have files placed in them uncompressed, + # and then both firmware volumes will be compressed in a single + # compression operation in order to achieve better overall compressio= n. + # + SECTION FV_IMAGE =3D DXEFV + } + } + +[Rule.Common.SEC] + FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED FIXED{ + PE32 PE32 Align=3DAuto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING =3D"$(MODULE_NAME)" Optional + VERSION STRING =3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE =3D $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION =3D $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION =3D $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM =3D $(NAMED_GUID) { + RAW ACPI |.acpi + RAW ASL |.aml + } + +[Rule.Common.USER_DEFINED.DTB] + FILE FREEFORM =3D $(NAMED_GUID) { + RAW BIN |.dtb + } diff --git a/Platform/StarFive/VisionFive2/VisionFive2.fdf.inc b/Platform/S= tarFive/VisionFive2/VisionFive2.fdf.inc new file mode 100644 index 000000000000..98beda0de77c --- /dev/null +++ b/Platform/StarFive/VisionFive2/VisionFive2.fdf.inc @@ -0,0 +1,48 @@ +## @file +# Definitions of Flash definition file on StarFive VisionFive 2 platform +# +# Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<= BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +# +# OpenSBI: 0x4000_0000 ~ 0x401F_FFFF +# EDK2 : 0x4020_0000 ~ 0x40A0_0000 +# +DEFINE FSBL_SIZE =3D 0x00100000 #100MB +DEFINE OPENSBI_SIZE =3D 0x00200000 +DEFINE FW_BASE_OFFSET =3D 0x40200000 +DEFINE FW_SIZE =3D 0x00800000 # (BLOCK_NUM x BLOCK_SIZE) + +DEFINE BLOCK_NUM =3D 0x800 +DEFINE BLOCK_SIZE =3D 0x1000 + +DEFINE FVMAIN_OFFSET =3D 0x00000000 # Offset from FW_BASE end +DEFINE FVMAIN_SIZE =3D 0x00740000 + +# +# EFI Variables memory region in Flash. +# +DEFINE VARS_OFFSET =3D 0x00740000 # Offset from FW_BASE end +DEFINE VARS_SIZE =3D 0x00040000 +DEFINE VARS_FTW_WORKING_OFFSET =3D $(VARS_OFFSET) + $(VARS_SIZE) +DEFINE VARS_FTW_WORKING_SIZE =3D 0x00040000 +DEFINE VARS_FTW_SPARE_OFFSET =3D $(VARS_FTW_WORKING_OFFSET) + $(VARS_FTW= _WORKING_SIZE) +DEFINE VARS_FTW_SPARE_SIZE =3D 0x00040000 + +# +# Memory map use for non-volatile variable offset in flash +# | FSBL | OPENSBI | EDK2 | EFI VARS | ... | +# +SET gJH7110TokenSpaceGuid.PcdJH7110FlashVarOffset =3D $(FSBL_SIZE) + $(OPE= NSBI_SIZE) + $(VARS_OFFSET) + +# +# Temporary RAM region use for sec startup before memory is discovered +# +SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase =3D 0x43FF0000 +SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize =3D 0x00010000 + +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency =3D 24000000= # 24Mhz --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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