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([2401:4900:1c80:4a26:3248:430a:4718:b9e6]) by smtp.gmail.com with ESMTPSA id jc15-20020a17090325cf00b001c746b986e5sm3433158plb.45.2023.10.21.10.33.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Oct 2023 10:33:35 -0700 (PDT) From: "Dhaval Sharma" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Laszlo Ersek Subject: [edk2-devel] [PATCH v6 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V Date: Sat, 21 Oct 2023 23:03:13 +0530 Message-Id: <20231021173314.19363-5-dhaval@rivosinc.com> In-Reply-To: <20231021173314.19363-1-dhaval@rivosinc.com> References: <20231021173314.19363-1-dhaval@rivosinc.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dhaval@rivosinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1697909618175100009 Content-Type: text/plain; charset="utf-8" Use newly defined cache management operations for RISC-V where possible It builds up on the support added for RISC-V cache management instructions in BaseLib. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Laszlo Ersek Signed-off-by: Dhaval Sharma Acked-by: Laszlo Ersek --- Notes: V1: - Utilize cache management instructions if HW supports it This patch is part of restructuring on top of v5 MdePkg/MdePkg.dec | 8 + MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf | 2 + MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 159 += ++++++++++++++++--- MdePkg/MdePkg.uni | 4 + 4 files changed, 154 insertions(+), 19 deletions(-) diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index ac54338089e8..fa92673ff633 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -2399,6 +2399,14 @@ [PcdsFixedAtBuild.AARCH64, PcdsPatchableInModule.AAR= CH64] # @Prompt CPU Rng algorithm's GUID. gEfiMdePkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x00,0x0= 0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID*|0x0000= 0037 =20 +[PcdsFixedAtBuild.RISCV64, PcdsPatchableInModule.RISCV64] + # + # Configurability to override RISC-V CPU Features + # BIT 0 =3D Cache Management Operations. This bit is relevant only if + # previous stage has feature enabled and user wants to disable it. + # + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFF|UINT= 64|0x69 + [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] ## This value is used to set the base address of PCI express hierarchy. # @Prompt PCI Express Base Address. diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib= .inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf index 6fd9cbe5f6c9..39a7fb963b49 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf @@ -56,3 +56,5 @@ [LibraryClasses] BaseLib DebugLib =20 +[Pcd.RISCV64] + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride ## CONSUMES diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/L= ibrary/BaseCacheMaintenanceLib/RiscVCache.c index 4eb18edb9aa7..6851970c9e16 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c @@ -1,7 +1,8 @@ /** @file - RISC-V specific functionality for cache. + Implement Risc-V Cache Management Operations =20 Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2023, Rivos Inc. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -9,10 +10,111 @@ #include #include #include +#include + +// TODO: This will be removed once RISC-V CPU HOB is available +#define RISCV_CACHE_BLOCK_SIZE 64 +#define RISCV_CPU_FEATURE_CMO_BITMASK 0x1 + +typedef enum { + Clean, + Flush, + Invld, +} CACHE_OP; + +/** +Verify CBOs are supported by this HW +TODO: Use RISC-V CPU HOB once available. + +**/ +STATIC +BOOLEAN +RiscVIsCMOEnabled ( + VOID + ) +{ + // TODO: Add check for CMO from CPU HOB. + // If CMO is disabled in HW, skip Override check + // Otherwise this PCD can override settings + return ((PcdGet64 (PcdRiscVFeatureOverride) & RISCV_CPU_FEATURE_CMO_BITM= ASK) !=3D 0); +} + +/** + Performs required opeartion on cache lines in the cache coherency domain + of the calling CPU. If Address is not aligned on a cache line boundary, + then entire cache line containing Address is operated. If Address + Leng= th + is not aligned on a cache line boundary, then the entire cache line + containing Address + Length -1 is operated. + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + @param Address The base address of the cache lines to + invalidate. + @param Length The number of bytes to invalidate from the instruction + cache. + @param Op Type of CMO operation to be performed + @return Address. + +**/ +STATIC +VOID +CacheOpCacheRange ( + IN VOID *Address, + IN UINTN Length, + IN CACHE_OP Op + ) +{ + UINTN CacheLineSize; + UINTN Start; + UINTN End; + + if (Length =3D=3D 0) { + return; + } + + if ((Op !=3D Invld) && (Op !=3D Flush) && (Op !=3D Clean)) { + return; + } + + ASSERT ((Length - 1) <=3D (MAX_ADDRESS - (UINTN)Address)); + + CacheLineSize =3D RISCV_CACHE_BLOCK_SIZE; + + Start =3D (UINTN)Address; + // + // Calculate the cache line alignment + // + End =3D (Start + Length + (CacheLineSize - 1)) & ~(CacheLineSize - 1); + Start &=3D ~((UINTN)CacheLineSize - 1); + + DEBUG ( + (DEBUG_INFO, + "%a Performing Cache Management Operation %d \n", __func__, Op) + ); + + do { + switch (Op) { + case Invld: + RiscVCpuCacheInvalAsmCbo (Start); + break; + case Flush: + RiscVCpuCacheFlushAsmCbo (Start); + break; + case Clean: + RiscVCpuCacheCleanAsmCbo (Start); + break; + default: + break; + } + + Start =3D Start + CacheLineSize; + } while (Start !=3D End); +} =20 /** Invalidates the entire instruction cache in cache coherency domain of the - calling CPU. + calling CPU. Risc-V does not have currently an CBO implementation which = can + invalidate entire I-cache. Hence using Fence instruction for now. P.S. F= ence + instruction may or may not implement full I-cache invd functionality on = all + implementations. =20 **/ VOID @@ -56,12 +158,17 @@ InvalidateInstructionCacheRange ( IN UINTN Length ) { - DEBUG ( - (DEBUG_WARN, - "%a:RISC-V unsupported function.\n" - "Invalidating the whole instruction cache instead.\n", __func__) - ); - InvalidateInstructionCache (); + if (RiscVIsCMOEnabled ()) { + CacheOpCacheRange (Address, Length, Invld); + } else { + DEBUG ( + (DEBUG_WARN, + "%a:RISC-V unsupported function.\n" + "Invalidating the whole instruction cache instead.\n", __func__) + ); + InvalidateInstructionCache (); + } + return Address; } =20 @@ -117,7 +224,12 @@ WriteBackInvalidateDataCacheRange ( IN UINTN Length ) { - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__)); + if (RiscVIsCMOEnabled ()) { + CacheOpCacheRange (Address, Length, Flush); + } else { + DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__)); + } + return Address; } =20 @@ -156,10 +268,7 @@ WriteBackDataCache ( =20 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). =20 - @param Address The base address of the data cache lines to write back. = If - the CPU is in a physical addressing mode, then Address i= s a - physical address. If the CPU is in a virtual addressing - mode, then Address is a virtual address. + @param Address The base address of the data cache lines to write back. @param Length The number of bytes to write back from the data cache. =20 @return Address of cache written in main memory. @@ -172,7 +281,12 @@ WriteBackDataCacheRange ( IN UINTN Length ) { - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__)); + if (RiscVIsCMOEnabled ()) { + CacheOpCacheRange (Address, Length, Clean); + } else { + DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__)); + } + return Address; } =20 @@ -214,10 +328,7 @@ InvalidateDataCache ( =20 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). =20 - @param Address The base address of the data cache lines to invalidate. = If - the CPU is in a physical addressing mode, then Address i= s a - physical address. If the CPU is in a virtual addressing = mode, - then Address is a virtual address. + @param Address The base address of the data cache lines to invalidate. @param Length The number of bytes to invalidate from the data cache. =20 @return Address. @@ -230,6 +341,16 @@ InvalidateDataCacheRange ( IN UINTN Length ) { - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__)); + if (RiscVIsCMOEnabled ()) { + CacheOpCacheRange (Address, Length, Invld); + } else { + DEBUG ( + (DEBUG_WARN, + "%a:RISC-V unsupported function.\n" + "Invalidating the whole Data cache instead.\n", __func__) + ); + InvalidateDataCache (); + } + return Address; } diff --git a/MdePkg/MdePkg.uni b/MdePkg/MdePkg.uni index 5c1fa24065c7..f49c33191054 100644 --- a/MdePkg/MdePkg.uni +++ b/MdePkg/MdePkg.uni @@ -287,6 +287,10 @@ =20 #string STR_gEfiMdePkgTokenSpaceGuid_PcdGuidedExtractHandlerTableAddress_H= ELP #language en-US "This value is used to set the available memory addres= s to store Guided Extract Handlers. The required memory space is decided by= the value of PcdMaximumGuidedExtractHandler." =20 +#string STR_gEfiMdePkgTokenSpaceGuid_PcdRiscVFeatureOverride_PROMPT #lang= uage en-US "RISC-V Feature Override" + +#string STR_gEfiMdePkgTokenSpaceGuid_PcdRiscVFeatureOverride_HELP #langua= ge en-US "This value is used to Override Any RISC-V specific features suppo= rted by this PCD" + #string STR_gEfiMdePkgTokenSpaceGuid_PcdPciExpressBaseAddress_PROMPT #lan= guage en-US "PCI Express Base Address" =20 #string STR_gEfiMdePkgTokenSpaceGuid_PcdPciExpressBaseAddress_HELP #langu= age en-US "This value is used to set the base address of PCI express hierar= chy." --=20 2.39.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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