From nobody Tue Feb 10 04:15:36 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+109530+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+109530+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=marvell.com ARC-Seal: i=1; a=rsa-sha256; t=1697047736; cv=none; d=zohomail.com; s=zohoarc; b=nFZohulfuIyHRPVl8uOVWPzSFfrbli0wi6V3i89+XG8irxdT8rS8WL/Vd1Xh14h9M+nsp+6gO9YGA5jpvELHh8uHmTJevL5rkexNUFyj05If5OinrSXSlLrN2FI61xoKfA4WNgxihEAudsiWlFNz0rKMn3vRqIFJLeWwLef11HE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697047736; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=JS+eNT7wdLa6MUuJ5cflDnNuzOCIBX4PA3eM7jl8vyI=; b=IFx1NSbi9Dq628QzsIYrBq+BitDPX6p9jB0YzrZSvvUB0DPm9BrQDjMDB+AFZ71Bsl1ZwOT2cHGTFccm8QdcKuBZEf1NxwUz+z5Y2B/n9fJUnm/2nkhgJklgYiLVoukESMGyxrh+G8vbNbdKxyKpqbrMd+nSCep8cHEMnKh9tDI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+109530+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1697047736199455.433075068216; Wed, 11 Oct 2023 11:08:56 -0700 (PDT) Return-Path: DKIM-Signature: a=rsa-sha256; bh=ZiwuEvaiHwdaJ2G6qQnJ+3c9q9lsMoeytemzCD6muCs=; c=relaxed/simple; d=groups.io; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding:Content-Type; s=20140610; t=1697047735; v=1; b=axP3OZ2y44OtSvL7nKLB+2qh66JTrrHvtsukLT56T2OA08UbOjIbVP5XHoLvmzdNqwWM99oW a2lOi9j9PNAre5v4evPQtfpP1lsEfpcuPz1G3BLJczxcBcv012qCIpZruLrR0TyqBe2BC9op4jw 080BNWCnOl6qbxm9nIeVdndU= X-Received: by 127.0.0.2 with SMTP id cqjdYY1788612xs1YjWMdMyC; Wed, 11 Oct 2023 11:08:55 -0700 X-Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.148.174]) by mx.groups.io with SMTP id smtpd.web10.23391.1697046833638835781 for ; Wed, 11 Oct 2023 10:53:53 -0700 X-Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39BFwr8C008613; Wed, 11 Oct 2023 10:53:53 -0700 X-Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3tnxtggg90-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 11 Oct 2023 10:53:53 -0700 X-Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 11 Oct 2023 10:53:51 -0700 X-Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 11 Oct 2023 10:53:51 -0700 X-Received: from MRVL-5Lp9he46Ey.marvell.com (unknown [10.193.12.187]) by maili.marvell.com (Postfix) with ESMTP id 17BA75B6935; Wed, 11 Oct 2023 10:53:51 -0700 (PDT) From: "Narinder Dhillon" To: CC: , , Narinder Dhillon Subject: [edk2-devel] [edk2-platforms PATCH v1 3/4] Platform/Marvell: Use new package name and path Date: Wed, 11 Oct 2023 10:53:22 -0700 Message-ID: <20231011175323.14450-4-ndhillon@marvell.com> In-Reply-To: <20231011175323.14450-1-ndhillon@marvell.com> References: <20231011175323.14450-1-ndhillon@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: dAjq0IJgbuzh51bZML_gfNAWNFIUiYGx X-Proofpoint-GUID: dAjq0IJgbuzh51bZML_gfNAWNFIUiYGx Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ndhillon@marvell.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: VLBjDWtZVtuHTWiv6z4xNvy5x1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1697047738368100019 Content-Type: text/plain; charset="utf-8" From: Narinder Dhillon New Marvell package name, path, and token space needs to be propagated to all dependent files. Signed-off-by: Narinder Dhillon --- .../Marvell/Armada70x0Db/Armada70x0Db.dsc | 108 +++++++------- .../Armada70x0DbBoardDescLib.inf | 2 +- .../NonDiscoverableInitLib.inf | 2 +- .../Marvell/Armada80x0Db/Armada80x0Db.dsc | 133 +++++++++--------- .../Armada80x0DbBoardDescLib.inf | 2 +- .../NonDiscoverableInitLib.inf | 2 +- .../Cn9130DbABoardDescLib.inf | 2 +- .../Cn9132DbABoardDescLib.inf | 2 +- Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc | 100 ++++++------- Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc | 66 ++++----- Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc | 66 ++++----- Platform/Marvell/Cn913xDb/Cn913xDbA.dsc | 8 +- .../NonDiscoverableInitLib.inf | 2 +- 13 files changed, 246 insertions(+), 249 deletions(-) diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marv= ell/Armada70x0Db/Armada70x0Db.dsc index 5df7498f71..362175f59e 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc @@ -48,54 +48,54 @@ ##########################################################################= ###### [PcdsFixedAtBuild.common] #Platform description - gMarvellTokenSpaceGuid.PcdProductPlatformName|"Armada 7040 DB" - gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.5" + gMarvellSiliconTokenSpaceGuid.PcdProductPlatformName|"Armada 7040 DB" + gMarvellSiliconTokenSpaceGuid.PcdProductVersion|"Rev. 1.5" =20 #CP110 count - gMarvellTokenSpaceGuid.PcdMaxCpCount|1 + gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount|1 =20 #MPP - gMarvellTokenSpaceGuid.PcdMppChipCount|2 + gMarvellSiliconTokenSpaceGuid.PcdMppChipCount|2 =20 # APN806-A0 MPP SET - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 - gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20 - gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x3 } + gMarvellSiliconTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE + gMarvellSiliconTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppPinCount|20 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1,= 0x1, 0x1, 0x1, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x3 } =20 # CP110 MPP SET - Router configuration - gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 - gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64 - gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0= x4, 0x4, 0x4, 0x4 } - gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x4, 0x4, 0x0, 0x3, 0x3, 0x3, 0= x3, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x9, 0xA } - gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xA, 0x0, 0x7, 0x0, 0x7, 0x7, 0= x7, 0x2, 0x2, 0x0 } - gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x1, 0x1, 0= x1, 0x1, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= xE, 0xE, 0xE, 0xE } - gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE + gMarvellSiliconTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppPinCount|64 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4,= 0x4, 0x4, 0x4, 0x4, 0x4 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel1|{ 0x4, 0x4, 0x0, 0x3, 0x3,= 0x3, 0x3, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x9, 0xA } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel3|{ 0xA, 0x0, 0x7, 0x0, 0x7,= 0x7, 0x7, 0x2, 0x2, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x1,= 0x1, 0x1, 0x1, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1,= 0x1, 0xE, 0xE, 0xE, 0xE } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0 } =20 # I2C - gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57, 0x60, 0x21 } - gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x50, 0x57 } - gMarvellTokenSpaceGuid.PcdEepromI2cBuses|{ 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000 - gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000 - gMarvellTokenSpaceGuid.PcdI2cBusCount|2 + gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57, 0x60, 0= x21 } + gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x50, 0x57 } + gMarvellSiliconTokenSpaceGuid.PcdEepromI2cBuses|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdI2cClockFrequency|250000000 + gMarvellSiliconTokenSpaceGuid.PcdI2cBaudRate|100000 + gMarvellSiliconTokenSpaceGuid.PcdI2cBusCount|2 =20 #SPI - gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF2700680 - gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000 - gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000 + gMarvellSiliconTokenSpaceGuid.PcdSpiRegBase|0xF2700680 + gMarvellSiliconTokenSpaceGuid.PcdSpiMaxFrequency|10000000 + gMarvellSiliconTokenSpaceGuid.PcdSpiClockFrequency|200000000 =20 - gMarvellTokenSpaceGuid.PcdSpiFlashMode|3 - gMarvellTokenSpaceGuid.PcdSpiFlashCs|0 + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashMode|3 + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashCs|0 =20 #ComPhy - gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } # ComPhy0 # 0: SGMII1 1.25 Gbps # 1: USB3_HOST0 5 Gbps @@ -103,36 +103,36 @@ # 3: SATA1 5 Gbps # 4: USB3_HOST1 5 Gbps # 5: PCIE2 5 Gbps - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_SGMII1), $(CP_USB3_HOS= T0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) } - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(C= P_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) } + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_SGMII1), $(CP_U= SB3_HOST0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) } + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_1_25G), $(CP_5= G), $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) } =20 #UtmiPhy - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1) } + gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTM= I_USB_HOST1) } =20 #MDIO - gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } =20 #PHY - gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + gMarvellSiliconTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE =20 #NET - gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 } - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_1000), $(PHY_SPEED_1000) } - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_SGMI= I), $(PHY_RGMII) } - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 } - gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 } + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000),= $(PHY_SPEED_1000), $(PHY_SPEED_1000) } + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(P= HY_SGMII), $(PHY_RGMII) } + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 } + gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers|{ 0x1 } =20 #PciEmulation - gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1 } - gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciEAhci|{ 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } =20 #RTC - gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000 + gMarvellSiliconTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000 diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada7= 0x0DbBoardDescLib.inf b/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDesc= Lib/Armada70x0DbBoardDescLib.inf index 20294ab43b..75331ae8e4 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBo= ardDescLib.inf +++ b/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBo= ardDescLib.inf @@ -22,7 +22,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib diff --git a/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscov= erableInitLib.inf b/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/No= nDiscoverableInitLib.inf index 946b9fd6d0..64623e33f8 100644 --- a/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscoverableI= nitLib.inf +++ b/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscoverableI= nitLib.inf @@ -29,7 +29,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc b/Platform/Marv= ell/Armada80x0Db/Armada80x0Db.dsc index 2698bd6573..22a0040265 100644 --- a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc +++ b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc @@ -31,9 +31,6 @@ =20 !include MdePkg/MdeLibs.dsc.inc =20 -[Components.common] - Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf - [Components.AARCH64] Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf =20 @@ -48,63 +45,63 @@ ##########################################################################= ###### [PcdsFixedAtBuild.common] #Platform description - gMarvellTokenSpaceGuid.PcdProductPlatformName|"Armada 8040 DB" - gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.4" + gMarvellSiliconTokenSpaceGuid.PcdProductPlatformName|"Armada 8040 DB" + gMarvellSiliconTokenSpaceGuid.PcdProductVersion|"Rev. 1.4" =20 #MPP - gMarvellTokenSpaceGuid.PcdMppChipCount|3 + gMarvellSiliconTokenSpaceGuid.PcdMppChipCount|3 =20 # APN806-A0 MPP SET - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 - gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20 - gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x3 } + gMarvellSiliconTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE + gMarvellSiliconTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppPinCount|20 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1,= 0x1, 0x1, 0x1, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x3 } =20 # CP110 MPP SET - master - gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 - gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64 - gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } - gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } - gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } - gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0xFF, 0x7, 0x0, 0x7, 0= xA, 0xA, 0x2, 0x2, 0x5 } - gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x9, 0x9, 0x8, 0x8, 0x1, 0= x1, 0x1, 0x1, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0xE, 0xE, 0xE, 0xE } - gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE + gMarvellSiliconTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppPinCount|64 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0xFF, 0x7, 0x0, = 0x7, 0xA, 0xA, 0x2, 0x2, 0x5 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel4|{ 0x9, 0x9, 0x8, 0x8, = 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, = 0x1, 0x1, 0xE, 0xE, 0xE, 0xE } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, = 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } =20 # CP110 MPP SET - slave - gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000 - gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64 - gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0= x3, 0x3, 0x3, 0x3, 0x3 } - gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0= x3, 0x3, 0xFF, 0xFF, 0xFF } - gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0x8, 0x9, 0xA } - gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0xA, 0x8, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } - gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } - gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } - gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE + gMarvellSiliconTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppPinCount|64 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel0|{ 0x3, 0x3, 0x3, 0x3, = 0x3, 0x3, 0x3, 0x3, 0x3, 0x3 } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel1|{ 0x3, 0x3, 0x3, 0x3, = 0x3, 0x3, 0x3, 0xFF, 0xFF, 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, = 0xFF, 0xFF, 0xFF, 0x8, 0x9, 0xA } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel3|{ 0xA, 0x8, 0xFF, 0xFF, = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, = 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } =20 # I2C - gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57, 0x50, 0x57, 0x= 21, 0x25 } - gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x1, 0x1, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1, 0x0, 0x0, 0x= 1 } - gMarvellTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x50, 0x57, 0x50, 0x57 } - gMarvellTokenSpaceGuid.PcdEepromI2cBuses|{ 0x0, 0x0, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000 - gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000 - gMarvellTokenSpaceGuid.PcdI2cBusCount|2 + gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57, 0x50, 0= x57, 0x21, 0x25 } + gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x1, 0x1, 0x0= , 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1, 0x0, = 0x0, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x50, 0x57, 0x50, = 0x57 } + gMarvellSiliconTokenSpaceGuid.PcdEepromI2cBuses|{ 0x0, 0x0, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdI2cClockFrequency|250000000 + gMarvellSiliconTokenSpaceGuid.PcdI2cBaudRate|100000 + gMarvellSiliconTokenSpaceGuid.PcdI2cBusCount|2 =20 #SPI - gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF4700680 - gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000 - gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000 + gMarvellSiliconTokenSpaceGuid.PcdSpiRegBase|0xF4700680 + gMarvellSiliconTokenSpaceGuid.PcdSpiMaxFrequency|10000000 + gMarvellSiliconTokenSpaceGuid.PcdSpiClockFrequency|200000000 =20 - gMarvellTokenSpaceGuid.PcdSpiFlashMode|3 - gMarvellTokenSpaceGuid.PcdSpiFlashCs|0 + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashMode|3 + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashCs|0 =20 #ComPhy - gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 } # ComPhy0 # 0: PCIE0 5 Gbps # 1: SATA0 5 Gbps @@ -112,8 +109,8 @@ # 3: SATA1 5 Gbps # 4: USB_HOST1 5 Gbps # 5: PCIE2 5 Gbps - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_SATA0), $= (CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) } - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_1= 0_3125G), $(CP_5G), $(CP_5G), $(CP_5G) } + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_SA= TA0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) } + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G),= $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) } # ComPhy1 # 0: PCIE0 5 Gbps # 1: SATA0 5 Gbps @@ -121,36 +118,36 @@ # 3: SATA1 5 Gbps # 4: PCIE1 5 Gbps # 5: PCIE2 5 Gbps - gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_SATA2), $= (CP_SFI), $(CP_SATA3), $(CP_PCIE1), $(CP_PCIE2) } - gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_1= 0_3125G), $(CP_5G), $(CP_5G), $(CP_5G) } + gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_SA= TA2), $(CP_SFI), $(CP_SATA3), $(CP_PCIE1), $(CP_PCIE2) } + gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G),= $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) } =20 #UtmiPhy - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1, 0x0 } - gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) } + gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1,= 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTM= I_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) } =20 #MDIO - gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x1 } =20 #PHY - gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x1, 0x0 } - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + gMarvellSiliconTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPhySmiAddresses|{ 0x1, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE =20 #NET - gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x3, 0x0, 0x2 } - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_1000), $(PHY_SPEED_10000), $(PHY_SPEED_1000) } - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMI= I), $(PHY_SFI), $(PHY_RGMII) } - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0x1 } - gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x2, 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x3, 0x0, 0x2 } + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0= x0 } + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000),= $(PHY_SPEED_1000), $(PHY_SPEED_10000), $(PHY_SPEED_1000) } + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(P= HY_RGMII), $(PHY_SFI), $(PHY_RGMII) } + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x1, 0x1= } + gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x2, 0x0, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 } =20 #PciEmulation - gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 } - gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } =20 #RTC - gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF4284000 + gMarvellSiliconTokenSpaceGuid.PcdRtcBaseAddress|0xF4284000 diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada8= 0x0DbBoardDescLib.inf b/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDesc= Lib/Armada80x0DbBoardDescLib.inf index 07ee65dfa4..302e0f832f 100644 --- a/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBo= ardDescLib.inf +++ b/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBo= ardDescLib.inf @@ -22,7 +22,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib diff --git a/Platform/Marvell/Armada80x0Db/NonDiscoverableInitLib/NonDiscov= erableInitLib.inf b/Platform/Marvell/Armada80x0Db/NonDiscoverableInitLib/No= nDiscoverableInitLib.inf index fb303f3d89..261f2114c4 100644 --- a/Platform/Marvell/Armada80x0Db/NonDiscoverableInitLib/NonDiscoverableI= nitLib.inf +++ b/Platform/Marvell/Armada80x0Db/NonDiscoverableInitLib/NonDiscoverableI= nitLib.inf @@ -30,7 +30,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDe= scLib.inf b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDes= cLib.inf index dfbdc84448..c93b3077c7 100644 --- a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.i= nf +++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.i= nf @@ -22,7 +22,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDe= scLib.inf b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDes= cLib.inf index 27a0214622..e0c84138b7 100644 --- a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.i= nf +++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.i= nf @@ -22,7 +22,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib diff --git a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc b/Platform/Marvell= /Cn913xDb/Cn9130DbA.dsc.inc index e4d4c8e073..61bfdc8eb6 100644 --- a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc +++ b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc @@ -14,47 +14,47 @@ ##########################################################################= ###### [PcdsFixedAtBuild.common] # CP115 count - gMarvellTokenSpaceGuid.PcdMaxCpCount|1 + gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount|1 =20 # MPP - gMarvellTokenSpaceGuid.PcdMppChipCount|2 + gMarvellSiliconTokenSpaceGuid.PcdMppChipCount|2 =20 # APN807 MPP - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 - gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20 - gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x1, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x3 } + gMarvellSiliconTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE + gMarvellSiliconTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppPinCount|20 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1,= 0x1, 0x1, 0x1, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x1, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x3 } =20 # CP115 #0 MPP - gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 - gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64 - gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0= x3, 0x3, 0x3, 0x3 } - gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x0, 0x3, 0x3, 0x3, 0= x3, 0x1, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x3, 0xA } - gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xA, 0x3, 0x7, 0x6, 0x7, 0x2, 0= x2, 0x2, 0x2, 0x1 } - gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= xE, 0xE, 0xE, 0xE } - gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE + gMarvellSiliconTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppPinCount|64 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3,= 0x3, 0x3, 0x3, 0x3, 0x3 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x0, 0x3, 0x3,= 0x3, 0x3, 0x1, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel2|{ 0x1, 0x1, 0x1, 0x1, 0x1,= 0x1, 0x1, 0x1, 0x3, 0xA } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel3|{ 0xA, 0x3, 0x7, 0x6, 0x7,= 0x2, 0x2, 0x2, 0x2, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel4|{ 0x1, 0x1, 0x1, 0x1, 0x1,= 0x1, 0x1, 0x1, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1,= 0x1, 0xE, 0xE, 0xE, 0xE } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0 } =20 # I2C - gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x21 } - gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 } - gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000 - gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000 + gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x21 } + gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdI2cClockFrequency|250000000 + gMarvellSiliconTokenSpaceGuid.PcdI2cBaudRate|100000 =20 # SPI - gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF2700680 - gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000 - gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000 + gMarvellSiliconTokenSpaceGuid.PcdSpiRegBase|0xF2700680 + gMarvellSiliconTokenSpaceGuid.PcdSpiMaxFrequency|10000000 + gMarvellSiliconTokenSpaceGuid.PcdSpiClockFrequency|200000000 =20 - gMarvellTokenSpaceGuid.PcdSpiFlashMode|3 - gMarvellTokenSpaceGuid.PcdSpiFlashCs|0 + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashMode|3 + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashCs|0 =20 # ComPhy - gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } # ComPhy0 # 0: PCIE0 5 Gbps # 1: PCIE0 5 Gbps @@ -62,39 +62,39 @@ # 3: PCIE0 5 Gbps # 4: SFI 10.31 Gbps # 5: SATA1 5 Gbps - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $= (CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)} - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5= G), $(CP_5G), $(CP_10_3125G), $(CP_5G) } + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PC= IE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)} + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G),= $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) } =20 # UtmiPhy - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1) } + gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTM= I_USB_HOST1) } =20 # MDIO - gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } =20 # PHY - gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + gMarvellSiliconTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE =20 # NET - gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 } - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_1000), $(PHY_SPEED_1000) } - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMI= I), $(PHY_RGMII) } - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 } - gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 } + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000),= $(PHY_SPEED_1000), $(PHY_SPEED_1000) } + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(P= HY_RGMII), $(PHY_RGMII) } + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 } + gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers|{ 0x1 } =20 # NonDiscoverableDevices - gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1 } - gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciEAhci|{ 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } =20 # RTC - gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000 + gMarvellSiliconTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000 =20 # Variable store - gMarvellTokenSpaceGuid.PcdSpiMemoryMapped|FALSE + gMarvellSiliconTokenSpaceGuid.PcdSpiMemoryMapped|FALSE diff --git a/Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc b/Platform/Marvell= /Cn913xDb/Cn9131DbA.dsc.inc index 7235b9f86e..8166f441b7 100644 --- a/Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc +++ b/Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc @@ -14,25 +14,25 @@ ##########################################################################= ###### [PcdsFixedAtBuild.common] # CP115 count - gMarvellTokenSpaceGuid.PcdMaxCpCount|2 + gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount|2 =20 # MPP - gMarvellTokenSpaceGuid.PcdMppChipCount|3 + gMarvellSiliconTokenSpaceGuid.PcdMppChipCount|3 =20 # CP115 #1 MPP - gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000 - gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64 - gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x0, 0x3, 0x3, 0x3, 0= x3, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x9, 0x0 } - gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0= x7, 0x2, 0x2, 0x0 } - gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE + gMarvellSiliconTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppPinCount|64 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x0, 0x3, 0x3,= 0x3, 0x3, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x9, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0x0, 0x0, 0x0,= 0x7, 0x7, 0x2, 0x2, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel5|{ 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel6|{ 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0 } =20 # ComPhy - gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 } # ComPhy1 # 0: PCIE0 5 Gbps # 1: PCIE0 5 Gbps @@ -40,33 +40,33 @@ # 3: USB3_HOST1 5 Gbps # 4: SFI 10.31 Gbps # 5: SATA1 5 Gbps - gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $= (CP_UNCONNECTED), $(CP_USB3_HOST1), $(CP_SFI), $(CP_SATA1)} - gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_D= EFAULT), $(CP_5G), $(CP_10_3125G), $(CP_5G) } + gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_PC= IE0), $(CP_UNCONNECTED), $(CP_USB3_HOST1), $(CP_SFI), $(CP_SATA1)} + gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G),= $(CP_DEFAULT), $(CP_5G), $(CP_10_3125G), $(CP_5G) } =20 # UtmiPhy - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) } + gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0,= 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTM= I_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) } =20 # MDIO - gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } =20 # PHY - gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + gMarvellSiliconTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE =20 # NET - gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0 } - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_1000), $(PHY_SPEED_1000), $(PHY_SPEED_10000) } - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMI= I), $(PHY_RGMII), $(PHY_SFI) } - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1, 0xFF } - gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0 } - gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0= x0 } + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000),= $(PHY_SPEED_1000), $(PHY_SPEED_1000), $(PHY_SPEED_10000) } + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(P= HY_RGMII), $(PHY_RGMII), $(PHY_SFI) } + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1, 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1= } + gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 } =20 # NonDiscoverableDevices - gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } diff --git a/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc b/Platform/Marvell= /Cn913xDb/Cn9132DbA.dsc.inc index a0b90fac1c..909f0fbc78 100644 --- a/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc +++ b/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc @@ -14,25 +14,25 @@ ##########################################################################= ###### [PcdsFixedAtBuild.common] # CP115 count - gMarvellTokenSpaceGuid.PcdMaxCpCount|3 + gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount|3 =20 # MPP - gMarvellTokenSpaceGuid.PcdMppChipCount|4 + gMarvellSiliconTokenSpaceGuid.PcdMppChipCount|4 =20 # CP115 #2 MPP - gMarvellTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip3MppBaseAddress|0xF6440000 - gMarvellTokenSpaceGuid.PcdChip3MppPinCount|64 - gMarvellTokenSpaceGuid.PcdChip3MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdChip3MppSel1|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdChip3MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x9, 0x9, 0x0 } - gMarvellTokenSpaceGuid.PcdChip3MppSel3|{ 0x0, 0x0, 0x8, 0x0, 0x8, 0x0, 0= x0, 0x2, 0x2, 0x0 } - gMarvellTokenSpaceGuid.PcdChip3MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdChip3MppSel5|{ 0x0, 0x0, 0x0, 0x0, 0xA, 0xB, 0= xE, 0xE, 0xE, 0xE } - gMarvellTokenSpaceGuid.PcdChip3MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE + gMarvellSiliconTokenSpaceGuid.PcdChip3MppBaseAddress|0xF6440000 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppPinCount|64 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel1|{ 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x9, 0x9, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel3|{ 0x0, 0x0, 0x8, 0x0, 0x8,= 0x0, 0x0, 0x2, 0x2, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel5|{ 0x0, 0x0, 0x0, 0x0, 0xA,= 0xB, 0xE, 0xE, 0xE, 0xE } + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0 } =20 # ComPhy - gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1, 0x1 } # ComPhy1 # 0: PCIE0 5 Gbps # 1: PCIE0 5 Gbps @@ -40,33 +40,33 @@ # 3: USB3_HOST1 5 Gbps # 4: SFI 10.31 Gbps # 5: PCIE2 5 Gbps - gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $= (CP_SATA0), $(CP_USB3_HOST1), $(CP_SFI), $(CP_PCIE2)} - gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5= G), $(CP_5G), $(CP_10_3125G), $(CP_5G) } + gMarvellSiliconTokenSpaceGuid.PcdChip2ComPhyTypes|{ $(CP_PCIE0), $(CP_PC= IE0), $(CP_SATA0), $(CP_USB3_HOST1), $(CP_SFI), $(CP_PCIE2)} + gMarvellSiliconTokenSpaceGuid.PcdChip2ComPhySpeeds|{ $(CP_5G), $(CP_5G),= $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) } =20 # UtmiPhy - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1, 0= x1, 0x1 } - gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_= HOST1) } + gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0,= 0x1, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTM= I_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UT= MI_USB_HOST1) } =20 # MDIO - gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } =20 # PHY - gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + gMarvellSiliconTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE =20 # NET - gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0, 0x0= } - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_1000), $(PHY_SPEED_1000), $(PHY_SPEED_10000), $(PHY_SPEED_10000) } - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMI= I), $(PHY_RGMII), $(PHY_SFI), $(PHY_SFI) } - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1, 0xFF, 0xFF } - gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1, 0x2 } - gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0, 0x0= } + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0= x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000),= $(PHY_SPEED_1000), $(PHY_SPEED_1000), $(PHY_SPEED_10000), $(PHY_SPEED_1000= 0) } + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(P= HY_RGMII), $(PHY_RGMII), $(PHY_SFI), $(PHY_SFI) } + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1, 0xFF, 0= xFF } + gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1= , 0x2 } + gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1, 0x1 } =20 # NonDiscoverableDevices - gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1, 0x0, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1= } + gMarvellSiliconTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1, 0x0, 0x1 } diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc b/Platform/Marvell/Cn9= 13xDb/Cn913xDbA.dsc index ff91d10142..dc18e94dbc 100644 --- a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc +++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc @@ -69,10 +69,10 @@ [PcdsFixedAtBuild.common] #Platform description !if $(CN9130) - gMarvellTokenSpaceGuid.PcdProductPlatformName|"CN9130 DB-A" + gMarvellSiliconTokenSpaceGuid.PcdProductPlatformName|"CN9130 DB-A" !elseif $(CN9131) - gMarvellTokenSpaceGuid.PcdProductPlatformName|"CN9131 DB-A" + gMarvellSiliconTokenSpaceGuid.PcdProductPlatformName|"CN9131 DB-A" !elseif $(CN9132) - gMarvellTokenSpaceGuid.PcdProductPlatformName|"CN9132 DB-A" + gMarvellSiliconTokenSpaceGuid.PcdProductPlatformName|"CN9132 DB-A" !endif - gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.1" + gMarvellSiliconTokenSpaceGuid.PcdProductVersion|"Rev. 1.1" diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverab= leInitLib.inf b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscove= rableInitLib.inf index f7cfb3684d..e4f0cf6bd6 100644 --- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.inf +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.inf @@ -23,7 +23,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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