From nobody Tue Feb 10 20:28:24 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+109529+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+109529+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=marvell.com ARC-Seal: i=1; a=rsa-sha256; t=1697047734; cv=none; d=zohomail.com; s=zohoarc; b=hrQI2s/nEO+gaTunnWUX77UkjBSUErWdkYBfD0PRHT25tRixYRo8D0Xt+XcxQP51zrxJjNZnWbsLV+8G9HOkRevGhX47RiFigAGa8qn/B0mgqvSNgf2FtE8uJWLaYtX8nWHt1oxKwvLg80R4lsY49wp/tsk7jOelbtDMFpt2+Cw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697047734; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=4Pudz1aKkyQOWMv+iU63iOD7powJ9XUHgIXqHlXNwAo=; b=SZ6ABJ6Q3qaOqztb7zCJmJi2oHNGItj1XY/t0d8N+LKzaz6phB6aF6r+wwGO1E/o7UBIzh5ElwfTmrl2bnG8BXInPlmKUsnik6LQW0g+p5+ZqPBOHhnxVx6mLXhxVrRVUHZkQfe+KX9yVoJ8jTcXDGkBRNw4s8Owc47qAnkf7a4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+109529+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 169704773479262.58401618628318; Wed, 11 Oct 2023 11:08:54 -0700 (PDT) Return-Path: DKIM-Signature: a=rsa-sha256; bh=DY32fvcx2k3cz35cgxiFyjzZkfl3UXsfDvrun6Dug4Y=; c=relaxed/simple; d=groups.io; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding:Content-Type; s=20140610; t=1697047734; v=1; b=rjJ11H1VYUhxAAkcMkh+VDmXmbsINpwJfDpjInQe/OzyrUxE1uxze/LTgu5tEzJ+cTMJcpHn MNIqe50QDS4GI5pk36uAX6S8uf+wteQovVVJCiNnjmQxUGD2wdyp2SLZtRcaBvuCpQQIBQJ7ps+ N8u8FJxujvs3OrmIb7t24D5k= X-Received: by 127.0.0.2 with SMTP id FICFYY1788612xYFN20JkhTm; Wed, 11 Oct 2023 11:08:54 -0700 X-Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.148.174]) by mx.groups.io with SMTP id smtpd.web11.23483.1697046832439508827 for ; Wed, 11 Oct 2023 10:53:52 -0700 X-Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39BFwr8B008613; Wed, 11 Oct 2023 10:53:52 -0700 X-Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3tnxtggg8r-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 11 Oct 2023 10:53:51 -0700 X-Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 11 Oct 2023 10:53:50 -0700 X-Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 11 Oct 2023 10:53:50 -0700 X-Received: from MRVL-5Lp9he46Ey.marvell.com (unknown [10.193.12.187]) by maili.marvell.com (Postfix) with ESMTP id CE5AB5B6934; Wed, 11 Oct 2023 10:53:49 -0700 (PDT) From: "Narinder Dhillon" To: CC: , , Narinder Dhillon Subject: [edk2-devel] [edk2-platforms PATCH v1 2/4] Silicon/Marvell: Use new package name and path Date: Wed, 11 Oct 2023 10:53:21 -0700 Message-ID: <20231011175323.14450-3-ndhillon@marvell.com> In-Reply-To: <20231011175323.14450-1-ndhillon@marvell.com> References: <20231011175323.14450-1-ndhillon@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: vm5wfK9VUakzt7jAHOGl1lsSDC3fq31j X-Proofpoint-GUID: vm5wfK9VUakzt7jAHOGl1lsSDC3fq31j Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ndhillon@marvell.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: lzaGOqUejVgbz15TEQqTNgaGx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1697047736381100010 Content-Type: text/plain; charset="utf-8" From: Narinder Dhillon New Marvell package name, path, and token space needs to be propagated to all dependent files. Signed-off-by: Narinder Dhillon --- .../Applications/EepromCmd/EepromCmd.inf | 2 +- .../Applications/FirmwareUpdate/FUpdate.inf | 6 +- .../Applications/SpiTool/SpiFlashCmd.inf | 6 +- .../Armada7k8k/AcpiTables/Armada70x0Db.inf | 2 +- .../Armada7k8k/AcpiTables/Armada80x0Db.inf | 2 +- .../Armada7k8k/AcpiTables/Armada80x0McBin.inf | 2 +- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 22 ++-- .../Armada7k8kRngDxe/Armada7k8kRngDxe.inf | 4 +- .../Drivers/PlatInitDxe/PlatInitDxe.inf | 6 +- .../PlatformFlashAccessLib.inf | 6 +- .../Library/Armada7k8kLib/Armada7k8kLib.inf | 4 +- .../Armada7k8kMemoryInitPeiLib.inf | 14 +-- .../PciHostBridgeLib.inf | 2 +- .../Armada7k8kPciSegmentLib/PciSegmentLib.inf | 2 +- .../Armada7k8kSampleAtResetLib.inf | 2 +- .../Armada7k8kSoCDescLib.inf | 4 +- .../RealTimeClockLib/RealTimeClockLib.inf | 4 +- .../Marvell/Documentation/PortingGuide.txt | 114 +++++++++--------- .../Drivers/BoardDesc/MvBoardDescDxe.inf | 18 +-- .../Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf | 2 +- .../Gpio/MvPca95xxDxe/MvPca95xxDxe.inf | 2 +- .../Drivers/I2c/MvEepromDxe/MvEepromDxe.inf | 6 +- .../Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf | 14 +-- .../Drivers/Net/MvMdioDxe/MvMdioDxe.inf | 2 +- .../Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.inf | 12 +- Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf | 16 +-- .../NonDiscoverableDxe/NonDiscoverableDxe.inf | 2 +- .../Drivers/SdMmc/XenonDxe/XenonDxe.inf | 2 +- .../SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 14 +-- .../Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf | 8 +- .../Spi/MvSpiFlashDxe/MvSpiFlashDxe.inf | 2 +- .../Spi/MvSpiOrionDxe/MvSpiOrionDxe.inf | 8 +- .../Marvell/Library/ComPhyLib/ComPhyLib.inf | 28 ++--- Silicon/Marvell/Library/IcuLib/IcuLib.inf | 4 +- Silicon/Marvell/Library/MppLib/MppLib.inf | 94 +++++++-------- .../Marvell/Library/MvGpioLib/MvGpioLib.inf | 2 +- .../Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf | 2 +- .../OcteonTx/AcpiTables/T91/Cn9130DbA.inf | 2 +- .../OcteonTx/AcpiTables/T91/Cn9131DbA.inf | 2 +- .../AcpiTables/T91/Cn913xCEx7Eval.inf | 2 +- 40 files changed, 224 insertions(+), 224 deletions(-) diff --git a/Silicon/Marvell/Applications/EepromCmd/EepromCmd.inf b/Silicon= /Marvell/Applications/EepromCmd/EepromCmd.inf index 1880416e42..8f71612e54 100644 --- a/Silicon/Marvell/Applications/EepromCmd/EepromCmd.inf +++ b/Silicon/Marvell/Applications/EepromCmd/EepromCmd.inf @@ -20,7 +20,7 @@ MdePkg/MdePkg.dec ShellPkg/ShellPkg.dec MdeModulePkg/MdeModulePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] UefiLib diff --git a/Silicon/Marvell/Applications/FirmwareUpdate/FUpdate.inf b/Sili= con/Marvell/Applications/FirmwareUpdate/FUpdate.inf index ee03d450d5..41e1d26140 100644 --- a/Silicon/Marvell/Applications/FirmwareUpdate/FUpdate.inf +++ b/Silicon/Marvell/Applications/FirmwareUpdate/FUpdate.inf @@ -20,7 +20,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec ShellPkg/ShellPkg.dec =20 [LibraryClasses] @@ -39,8 +39,8 @@ UefiRuntimeServicesTableLib =20 [Pcd] - gMarvellTokenSpaceGuid.PcdSpiFlashCs - gMarvellTokenSpaceGuid.PcdSpiFlashMode + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashCs + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashMode =20 [Protocols] gEfiBlockIoProtocolGuid diff --git a/Silicon/Marvell/Applications/SpiTool/SpiFlashCmd.inf b/Silicon= /Marvell/Applications/SpiTool/SpiFlashCmd.inf index 3a6a2115f8..8340e43723 100644 --- a/Silicon/Marvell/Applications/SpiTool/SpiFlashCmd.inf +++ b/Silicon/Marvell/Applications/SpiTool/SpiFlashCmd.inf @@ -21,7 +21,7 @@ MdePkg/MdePkg.dec ShellPkg/ShellPkg.dec MdeModulePkg/MdeModulePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] UefiLib @@ -39,8 +39,8 @@ FileHandleLib =20 [Pcd] - gMarvellTokenSpaceGuid.PcdSpiFlashCs - gMarvellTokenSpaceGuid.PcdSpiFlashMode + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashCs + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashMode =20 [Protocols] gMarvellSpiFlashProtocolGuid diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf b/Silic= on/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf index f3cce52e96..416b4cd63e 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf @@ -32,7 +32,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [FixedPcd] gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf b/Silic= on/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf index 7750817e1b..f7ed7f2350 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf @@ -32,7 +32,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [FixedPcd] gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf b/Si= licon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf index 98e5cc8b6e..c8cdea2b7d 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf @@ -33,7 +33,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [FixedPcd] gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel= l/Armada7k8k/Armada7k8k.dsc.inc index a135cb88b8..9711a8d6a7 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -373,31 +373,31 @@ gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000 =20 # ARM-TF region reservation - gMarvellTokenSpaceGuid.PcdArmTFRegionBase|0x4000000 - gMarvellTokenSpaceGuid.PcdArmTFRegionSize|0x200000 + gMarvellSiliconTokenSpaceGuid.PcdArmTFRegionBase|0x4000000 + gMarvellSiliconTokenSpaceGuid.PcdArmTFRegionSize|0x200000 =20 # Additional region reservation (e.g. for PEI stack base) - gMarvellTokenSpaceGuid.PcdAuxiliaryReservedRegionBase|0x4200000 - gMarvellTokenSpaceGuid.PcdAuxiliaryReservedRegionSize|0x200000 + gMarvellSiliconTokenSpaceGuid.PcdAuxiliaryReservedRegionBase|0x4200000 + gMarvellSiliconTokenSpaceGuid.PcdAuxiliaryReservedRegionSize|0x200000 =20 # OP-TEE region reservation - gMarvellTokenSpaceGuid.PcdOpTeeRegionBase|0x4400000 - gMarvellTokenSpaceGuid.PcdOpTeeRegionSize|0x1000000 + gMarvellSiliconTokenSpaceGuid.PcdOpTeeRegionBase|0x4400000 + gMarvellSiliconTokenSpaceGuid.PcdOpTeeRegionSize|0x1000000 =20 # SMBIOS/DMI gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev|0x0 gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2 - gMarvellTokenSpaceGuid.PcdFirmwareVersion|"EDK2 SH 1.1" + gMarvellSiliconTokenSpaceGuid.PcdFirmwareVersion|"EDK2 SH 1.1" =20 # TRNG - gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0xF2760000 + gMarvellSiliconTokenSpaceGuid.PcdEip76TrngBaseAddress|0xF2760000 =20 # # Variable store - default values # - gMarvellTokenSpaceGuid.PcdSpiMemoryBase|0xF9000000 - gMarvellTokenSpaceGuid.PcdSpiMemoryMapped|TRUE - gMarvellTokenSpaceGuid.PcdSpiVariableOffset|0x3C0000 + gMarvellSiliconTokenSpaceGuid.PcdSpiMemoryBase|0xF9000000 + gMarvellSiliconTokenSpaceGuid.PcdSpiMemoryMapped|TRUE + gMarvellSiliconTokenSpaceGuid.PcdSpiVariableOffset|0x3C0000 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000 diff --git a/Silicon/Marvell/Armada7k8k/Drivers/Armada7k8kRngDxe/Armada7k8k= RngDxe.inf b/Silicon/Marvell/Armada7k8k/Drivers/Armada7k8kRngDxe/Armada7k8k= RngDxe.inf index 4c766eeff8..7ba9ec9d26 100644 --- a/Silicon/Marvell/Armada7k8k/Drivers/Armada7k8kRngDxe/Armada7k8kRngDxe.= inf +++ b/Silicon/Marvell/Armada7k8k/Drivers/Armada7k8kRngDxe/Armada7k8kRngDxe.= inf @@ -20,7 +20,7 @@ =20 [Packages] MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] BaseMemoryLib @@ -29,7 +29,7 @@ UefiDriverEntryPoint =20 [Pcd] - gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress + gMarvellSiliconTokenSpaceGuid.PcdEip76TrngBaseAddress =20 [Protocols] gEfiRngProtocolGuid ## PRODUCES diff --git a/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf= b/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf index 398baebcf5..93f1f5c822 100644 --- a/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf +++ b/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf @@ -23,7 +23,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] ArmadaBoardDescLib @@ -42,8 +42,8 @@ gEfiEventReadyToBootGuid =20 [FixedPcd] - gMarvellTokenSpaceGuid.PcdProductManufacturer - gMarvellTokenSpaceGuid.PcdProductPlatformName + gMarvellSiliconTokenSpaceGuid.PcdProductManufacturer + gMarvellSiliconTokenSpaceGuid.PcdProductPlatformName =20 [Protocols] gMarvellPlatformInitCompleteProtocolGuid ## PRODUCES diff --git a/Silicon/Marvell/Armada7k8k/Feature/Capsule/PlatformFlashAccess= Lib/PlatformFlashAccessLib.inf b/Silicon/Marvell/Armada7k8k/Feature/Capsule= /PlatformFlashAccessLib/PlatformFlashAccessLib.inf index 69a7b71c51..b678a24028 100644 --- a/Silicon/Marvell/Armada7k8k/Feature/Capsule/PlatformFlashAccessLib/Pla= tformFlashAccessLib.inf +++ b/Silicon/Marvell/Armada7k8k/Feature/Capsule/PlatformFlashAccessLib/Pla= tformFlashAccessLib.inf @@ -24,7 +24,7 @@ MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec SignedCapsulePkg/SignedCapsulePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] BaseLib @@ -38,8 +38,8 @@ UefiRuntimeServicesTableLib =20 [Pcd] - gMarvellTokenSpaceGuid.PcdSpiFlashCs - gMarvellTokenSpaceGuid.PcdSpiFlashMode + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashCs + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashMode =20 [Protocols] gMarvellSpiFlashProtocolGuid diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib= .inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf index 8b77a07ab3..51127cfbd9 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf @@ -17,7 +17,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] ArmadaBoardDescLib @@ -45,7 +45,7 @@ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask gArmTokenSpaceGuid.PcdArmPrimaryCore =20 - gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress + gMarvellSiliconTokenSpaceGuid.PcdConfigSpaceBaseAddress =20 [Ppis] gArmMpCoreInfoPpiGuid diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/= Armada7k8kMemoryInitPeiLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7= k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.inf index f0b469ee55..e48ab5857d 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7= k8kMemoryInitPeiLib.inf +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7= k8kMemoryInitPeiLib.inf @@ -24,7 +24,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] ArmPlatformLib @@ -36,9 +36,9 @@ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob =20 [FixedPcd] - gMarvellTokenSpaceGuid.PcdArmTFRegionBase - gMarvellTokenSpaceGuid.PcdArmTFRegionSize - gMarvellTokenSpaceGuid.PcdAuxiliaryReservedRegionBase - gMarvellTokenSpaceGuid.PcdAuxiliaryReservedRegionSize - gMarvellTokenSpaceGuid.PcdOpTeeRegionBase - gMarvellTokenSpaceGuid.PcdOpTeeRegionSize + gMarvellSiliconTokenSpaceGuid.PcdArmTFRegionBase + gMarvellSiliconTokenSpaceGuid.PcdArmTFRegionSize + gMarvellSiliconTokenSpaceGuid.PcdAuxiliaryReservedRegionBase + gMarvellSiliconTokenSpaceGuid.PcdAuxiliaryReservedRegionSize + gMarvellSiliconTokenSpaceGuid.PcdOpTeeRegionBase + gMarvellSiliconTokenSpaceGuid.PcdOpTeeRegionSize diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/= PciHostBridgeLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHost= BridgeLib/PciHostBridgeLib.inf index 8fcb133e99..5877cb345e 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHost= BridgeLib.inf +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHost= BridgeLib.inf @@ -27,7 +27,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] ArmLib diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/Pci= SegmentLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib= /PciSegmentLib.inf index d3876791e9..40e74be6bf 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegment= Lib.inf +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegment= Lib.inf @@ -25,7 +25,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] ArmadaBoardDescLib diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/= Armada7k8kSampleAtResetLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7= k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.inf index 512cbf5f7e..09986828ec 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7= k8kSampleAtResetLib.inf +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7= k8kSampleAtResetLib.inf @@ -17,7 +17,7 @@ [Packages] MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLi= b/Armada7k8kSoCDescLib.inf index d5809c6789..15a7a505d8 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.inf +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.inf @@ -21,7 +21,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib @@ -29,4 +29,4 @@ PcdLib =20 [FixedPcd] - gMarvellTokenSpaceGuid.PcdMaxCpCount + gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount diff --git a/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeCl= ockLib.inf b/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeCl= ockLib.inf index 733827e61a..7dfa109e56 100644 --- a/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.= inf +++ b/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.= inf @@ -29,7 +29,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib @@ -44,7 +44,7 @@ gEfiEventVirtualAddressChangeGuid =20 [Pcd] - gMarvellTokenSpaceGuid.PcdRtcBaseAddress + gMarvellSiliconTokenSpaceGuid.PcdRtcBaseAddress =20 [Depex.common.DXE_RUNTIME_DRIVER] gEfiCpuArchProtocolGuid diff --git a/Silicon/Marvell/Documentation/PortingGuide.txt b/Silicon/Marve= ll/Documentation/PortingGuide.txt index 9dee5c89fa..24cf5cff0a 100644 --- a/Silicon/Marvell/Documentation/PortingGuide.txt +++ b/Silicon/Marvell/Documentation/PortingGuide.txt @@ -70,7 +70,7 @@ COMPHY configuration =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D In order to configure ComPhy library, following PCDs are available: =20 - - gMarvellTokenSpaceGuid.PcdComPhyDevices + - gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices =20 This array indicates, which ones of the ComPhy chips defined in MVHW_COMPHY_DESC template will be configured. @@ -84,7 +84,7 @@ defined numbers for SPEED/TYPE/INVERT, whose description = can be found in: =20 OpenPlatformPkg/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h =20 - - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes + - gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyTypes (Array of types - currently supported are: =20 CP_UNCONNECTED 0x0 @@ -112,7 +112,7 @@ defined numbers for SPEED/TYPE/INVERT, whose descriptio= n can be found in: CP_RXAUI1 0x16 CP_SFI 0x17 ) =20 - - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds + - gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhySpeeds (Array of speeds - currently supported are: =20 CP_1_25G 0x1 @@ -126,7 +126,7 @@ defined numbers for SPEED/TYPE/INVERT, whose descriptio= n can be found in: CP_6_25G 0x9 CP_10_3125G 0xA ) =20 - - gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags + - gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyInvFlags (Array of lane inversion types - currently supported are: =20 CP_NO_INVERT 0x0 @@ -138,9 +138,9 @@ Example ------- =20 #ComPhy - gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_SGMII1= ), $(CP_USB3_HOST0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) } - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_1_25G= ), $(CP_5G), $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) } + gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP= _SGMII1), $(CP_USB3_HOST0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_= PCIE2) } + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(C= P_1_25G), $(CP_5G), $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) } =20 =20 PHY Driver configuration @@ -148,13 +148,13 @@ PHY Driver configuration MvPhyDxe provides basic initialization and status routines for Marvell PHY= s. Currently only 1512 and 1112 series PHYs are supported. Following PCDs are= required: =20 - - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg + - gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg (boolean - if true, driver waits for autonegotiation on startup) - - gMarvellTokenSpaceGuid.PcdPhyDeviceIds + - gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds (list of values corresponding to MV_PHY_DEVICE_ID enum) - - gMarvellTokenSpaceGuid.PcdPhySmiAddresses + - gMarvellSiliconTokenSpaceGuid.PcdPhySmiAddresses (addresses of PHY devices) - - gMarvellTokenSpaceGuid.PcdPhy2MdioController + - gMarvellSiliconTokenSpaceGuid.PcdPhy2MdioController (Array specifying, which Mdio controller the PHY is attached to) =20 =20 @@ -169,11 +169,11 @@ It should be extended when adding support for other P= HY models. =20 Disable autonegotiation: =20 - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE =20 assuming, that PHY models are 1512 and 1112 for two consecutive ports: =20 - gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x1 } =20 =20 MDIO configuration @@ -181,7 +181,7 @@ MDIO configuration MDIO driver provides access to network PHYs' registers via EFI_MDIO_READ a= nd EFI_MDIO_WRITE functions (EFI_MDIO_PROTOCOL). Following PCD is required: =20 - - gMarvellTokenSpaceGuid.PcdMdioControllers + - gMarvellSiliconTokenSpaceGuid.PcdMdioControllers (Array with used controllers Set to 0x1 for enabled, 0x0 for disabled) =20 @@ -194,17 +194,17 @@ In order to enable driver on a new platform, followin= g steps need to be taken: - add following line to .fdf file: INF edk2-platforms/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf - add PCDs with relevant values to .dsc file: - - gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57 } + - gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57 } (addresses of I2C slave devices on bus) - - gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0 } + - gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0 } (buses to which accoring slaves are attached) - - gMarvellTokenSpaceGuid.PcdI2cBusCount|2 + - gMarvellSiliconTokenSpaceGuid.PcdI2cBusCount|2 (number of SoC's I2C buses) - - gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x1, 0x1 } + - gMarvellSiliconTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x1, 0x= 1 } (array with used controllers) - - gMarvellTokenSpaceGuid.PcdI2cClockFrequency|200000000 + - gMarvellSiliconTokenSpaceGuid.PcdI2cClockFrequency|200000000 (I2C host controller clock frequency) - - gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000 + - gMarvellSiliconTokenSpaceGuid.PcdI2cBaudRate|100000 (baud rate used in I2C transmission) =20 =20 @@ -213,13 +213,13 @@ PciEmulation configuration Installation of various NonDiscoverable devices via PciEmulation driver is= performed via set of PCDs. Following are available: =20 - - gMarvellTokenSpaceGuid.PcdPciEXhci + - gMarvellSiliconTokenSpaceGuid.PcdPciEXhci (Indicates, which Xhci devices are used) =20 - - gMarvellTokenSpaceGuid.PcdPciEAhci + - gMarvellSiliconTokenSpaceGuid.PcdPciEAhci (Indicates, which Ahci devices are used) =20 - - gMarvellTokenSpaceGuid.PcdPciESdhci + - gMarvellSiliconTokenSpaceGuid.PcdPciESdhci (Indicates, which Sdhci devices are used) =20 All above PCD's correspond to hardware description in a dedicated structur= e: @@ -235,15 +235,15 @@ Example Assuming we want to enable second XHCI port and one SDHCI port on Armada 70x0 board, following needs to be declared: =20 - gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x0 0x1 } - gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x0 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1 } =20 =20 SATA configuration =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D There is one additional PCD for AHCI: =20 - - gMarvellTokenSpaceGuid.PcdSataBaseAddress + - gMarvellSiliconTokenSpaceGuid.PcdSataBaseAddress (Base address of SATA controller register space - used in SATA Com= Phy init sequence) =20 @@ -253,14 +253,14 @@ Pp2Dxe configuration Pp2Dxe is driver supporting PP2 NIC on Marvell platforms. Following PCDs are required to operate: =20 - - gMarvellTokenSpaceGuid.PcdPp2Controllers + - gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers (Array with used controllers Set to 0x1 for enabled, 0x0 for disabled) =20 - - gMarvellTokenSpaceGuid.PcdPp2Port2Controller + - gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller (Array specifying, to which controller the port belongs to) =20 - - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes + - gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes (Indicates speed of the network interface: =20 PHY_RGMII 0x0 @@ -273,22 +273,22 @@ are required to operate: PHY_RXAUI 0x7 PHY_SFI 0x8 ) =20 - - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes + - gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes (Array specifying, to which PHY from - gMarvellTokenSpaceGuid.PcdPhyDeviceIds is used. If none, + gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds is used. If none, e.g. in 10G SFI in-band link detection, 0xFF value must be specified) =20 - - gMarvellTokenSpaceGuid.PcdPp2PortIds + - gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds (Identificators of PP2 ports) =20 - - gMarvellTokenSpaceGuid.PcdPp2GopIndexes + - gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes (Indexes used in GOP operation) =20 - - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp + - gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp (Set to 0x1 for always-up interface, 0x0 otherwise) =20 - - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed + - gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed (Indicates speed of the network interface: =20 PHY_SPEED_10 0x1 @@ -302,11 +302,11 @@ UTMI PHY configuration =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D In order to configure UTMI, following PCDs are available: =20 - - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled + - gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled (Array with used controllers Set to 0x1 for enabled, 0x0 for disabled) =20 - - gMarvellTokenSpaceGuid.PcdUtmiPortType + - gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType (Indicates type of the connected USB port: =20 UTMI_USB_HOST0 0x0 @@ -317,29 +317,29 @@ Example ------- =20 # UtmiPhy - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, = 0x1 } - gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST= 0), $(UTMI_USB_HOST1) } + gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|= { 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_U= SB_HOST0), $(UTMI_USB_HOST1) } =20 =20 SPI driver configuration =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Following PCDs are available for configuration of spi driver: =20 - - gMarvellTokenSpaceGuid.PcdSpiClockFrequency + - gMarvellSiliconTokenSpaceGuid.PcdSpiClockFrequency (Frequency (in Hz) of SPI clock) =20 - - gMarvellTokenSpaceGuid.PcdSpiMaxFrequency + - gMarvellSiliconTokenSpaceGuid.PcdSpiMaxFrequency (Max SCLK line frequency (in Hz) (max transfer frequency) ) =20 SpiFlash configuration =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Folowing PCDs for spi flash driver configuration must be set properly: =20 - - gMarvellTokenSpaceGuid.PcdSpiFlashMode + - gMarvellSiliconTokenSpaceGuid.PcdSpiFlashMode (Default SCLK mode (see SPI_MODE enum in file edk2-platforms/Platform/Marvell/Drivers/Spi/MvSpi.h)) =20 - - gMarvellTokenSpaceGuid.PcdSpiFlashCs + - gMarvellSiliconTokenSpaceGuid.PcdSpiFlashCs (Chip select used for communication with the Flash) =20 MPP configuration @@ -350,7 +350,7 @@ In order to set desired pin multiplexing, .dsc file nee= ds to be modified. Documentation/Build.txt for currently supported {platftorm_name} ) Following PCDs are available: =20 - - gMarvellTokenSpaceGuid.PcdMppChipCount + - gMarvellSiliconTokenSpaceGuid.PcdMppChipCount (Indicates how many different chips are placed on board. So far up= to 4 chips are supported) =20 @@ -360,37 +360,37 @@ Every MPP PCD has part where =20 Below is example for the first chip (Chip0). =20 - - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag + - gMarvellSiliconTokenSpaceGuid.PcdChip0MppReverseFlag (Indicates that register order is reversed. (Needs to be used only= for AP806-Z1) ) =20 - - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress + - gMarvellSiliconTokenSpaceGuid.PcdChip0MppBaseAddress (This is base address for MPP configuration register) =20 - - gMarvellTokenSpaceGuid.PcdChip0MppPinCount + - gMarvellSiliconTokenSpaceGuid.PcdChip0MppPinCount (Defines how many MPP pins are available) =20 - - gMarvellTokenSpaceGuid.PcdChip0MppSel0 - - gMarvellTokenSpaceGuid.PcdChip0MppSel1 - - gMarvellTokenSpaceGuid.PcdChip0MppSel2 + - gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel0 + - gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel1 + - gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel2 (This registers defines functions of 10 pins in ascending order) =20 Examples -------- =20 # APN806-A0 MPP SET - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 - gMarvellTokenSpaceGuid.PcdChip0MppRegCount|3 - gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0= x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x0 } - gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x0, 0x0, 0x0, 0= x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE + gMarvellSiliconTokenSpaceGuid.PcdChip0MppBaseAddress|0xF0= 6F4000 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppRegCount|3 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1,= 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel1|{ 0x0, 0x0,= 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } =20 Set pin 6 and 7 to 0xa function: - gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0xa, 0xa, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel0|{ 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0xa, 0xa, 0x0, 0x0 } =20 =20 Ramdisk configuration =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D There is one PCD available for Ramdisk configuration =20 - - gMarvellTokenSpaceGuid.PcdRamDiskSize + - gMarvellSiliconTokenSpaceGuid.PcdRamDiskSize (Defines size of Ramdisk) diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf b/Silicon= /Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf index 75ecae1b98..0dd17f7b56 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf @@ -18,7 +18,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] ArmadaBoardDescLib @@ -32,14 +32,14 @@ gMarvellBoardDescProtocolGuid =20 [Pcd] - gMarvellTokenSpaceGuid.PcdComPhyDevices - gMarvellTokenSpaceGuid.PcdI2cControllersEnabled - gMarvellTokenSpaceGuid.PcdPciEAhci - gMarvellTokenSpaceGuid.PcdPciESdhci - gMarvellTokenSpaceGuid.PcdPciEXhci - gMarvellTokenSpaceGuid.PcdPp2Controllers - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled - gMarvellTokenSpaceGuid.PcdUtmiPortType + gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices + gMarvellSiliconTokenSpaceGuid.PcdI2cControllersEnabled + gMarvellSiliconTokenSpaceGuid.PcdPciEAhci + gMarvellSiliconTokenSpaceGuid.PcdPciESdhci + gMarvellSiliconTokenSpaceGuid.PcdPciEXhci + gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers + gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled + gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType =20 [Depex] TRUE diff --git a/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf b/Silicon= /Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf index 6f36c2db2e..db111a2c57 100644 --- a/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf +++ b/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf @@ -21,7 +21,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] ArmadaSoCDescLib diff --git a/Silicon/Marvell/Drivers/Gpio/MvPca95xxDxe/MvPca95xxDxe.inf b/S= ilicon/Marvell/Drivers/Gpio/MvPca95xxDxe/MvPca95xxDxe.inf index c202d811f2..0f00698c55 100644 --- a/Silicon/Marvell/Drivers/Gpio/MvPca95xxDxe/MvPca95xxDxe.inf +++ b/Silicon/Marvell/Drivers/Gpio/MvPca95xxDxe/MvPca95xxDxe.inf @@ -21,7 +21,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib diff --git a/Silicon/Marvell/Drivers/I2c/MvEepromDxe/MvEepromDxe.inf b/Sili= con/Marvell/Drivers/I2c/MvEepromDxe/MvEepromDxe.inf index cfe9db9c1c..c5f6aa7833 100644 --- a/Silicon/Marvell/Drivers/I2c/MvEepromDxe/MvEepromDxe.inf +++ b/Silicon/Marvell/Drivers/I2c/MvEepromDxe/MvEepromDxe.inf @@ -18,7 +18,7 @@ ArmPlatformPkg/ArmPlatformPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] BaseLib @@ -36,8 +36,8 @@ gMarvellEepromProtocolGuid =20 [Pcd] - gMarvellTokenSpaceGuid.PcdEepromI2cAddresses - gMarvellTokenSpaceGuid.PcdEepromI2cBuses + gMarvellSiliconTokenSpaceGuid.PcdEepromI2cAddresses + gMarvellSiliconTokenSpaceGuid.PcdEepromI2cBuses =20 [Depex] TRUE diff --git a/Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf b/Silicon/Ma= rvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf index f631fbe797..d73f2433fc 100755 --- a/Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf +++ b/Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf @@ -19,7 +19,7 @@ MdeModulePkg/MdeModulePkg.dec ArmPlatformPkg/ArmPlatformPkg.dec ArmPkg/ArmPkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] IoLib @@ -38,12 +38,12 @@ gMarvellBoardDescProtocolGuid =20 [Pcd] - gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses - gMarvellTokenSpaceGuid.PcdI2cSlaveBuses - gMarvellTokenSpaceGuid.PcdI2cControllersEnabled - gMarvellTokenSpaceGuid.PcdI2cClockFrequency - gMarvellTokenSpaceGuid.PcdI2cBaudRate - gMarvellTokenSpaceGuid.PcdI2cBusCount + gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveAddresses + gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveBuses + gMarvellSiliconTokenSpaceGuid.PcdI2cControllersEnabled + gMarvellSiliconTokenSpaceGuid.PcdI2cClockFrequency + gMarvellSiliconTokenSpaceGuid.PcdI2cBaudRate + gMarvellSiliconTokenSpaceGuid.PcdI2cBusCount =20 [Guids] gEfiEndOfDxeEventGroupGuid diff --git a/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf b/Silicon/= Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf index f4511a9288..196d119586 100644 --- a/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf +++ b/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf @@ -21,7 +21,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] BaseLib diff --git a/Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.inf b/Silicon/Ma= rvell/Drivers/Net/MvPhyDxe/MvPhyDxe.inf index abf84af612..b8e5d30fc3 100644 --- a/Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.inf +++ b/Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.inf @@ -19,7 +19,7 @@ ArmPlatformPkg/ArmPlatformPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] BaseLib @@ -36,11 +36,11 @@ gMarvellPhyProtocolGuid =20 [Pcd] - gMarvellTokenSpaceGuid.PcdMdioControllersEnabled - gMarvellTokenSpaceGuid.PcdPhy2MdioController - gMarvellTokenSpaceGuid.PcdPhyDeviceIds - gMarvellTokenSpaceGuid.PcdPhySmiAddresses - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg + gMarvellSiliconTokenSpaceGuid.PcdMdioControllersEnabled + gMarvellSiliconTokenSpaceGuid.PcdPhy2MdioController + gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds + gMarvellSiliconTokenSpaceGuid.PcdPhySmiAddresses + gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg =20 [Depex] TRUE diff --git a/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf b/Silicon/Marvel= l/Drivers/Net/Pp2Dxe/Pp2Dxe.inf index 17a2a88d62..bd8b557c1a 100644 --- a/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf +++ b/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf @@ -21,7 +21,7 @@ MdeModulePkg/MdeModulePkg.dec NetworkPkg/NetworkPkg.dec ArmPkg/ArmPkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DmaLib @@ -47,13 +47,13 @@ gMarvellPhyProtocolGuid =20 [Pcd] - gMarvellTokenSpaceGuid.PcdPp2GopIndexes - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes - gMarvellTokenSpaceGuid.PcdPp2Port2Controller - gMarvellTokenSpaceGuid.PcdPp2PortIds + gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes + gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller + gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds =20 [Depex] TRUE diff --git a/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.= inf b/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.inf index af266ee083..88fc3f17bb 100644 --- a/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.inf +++ b/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.inf @@ -19,7 +19,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] NonDiscoverableDeviceRegistrationLib diff --git a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonDxe.inf b/Silicon/= Marvell/Drivers/SdMmc/XenonDxe/XenonDxe.inf index 18f1b164fd..4bf8718c36 100644 --- a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonDxe.inf +++ b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonDxe.inf @@ -33,7 +33,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] BaseLib diff --git a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.in= f b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf index 582c0faf25..682de9aeec 100644 --- a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf +++ b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf @@ -22,7 +22,7 @@ [Packages] MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] BaseLib @@ -36,12 +36,12 @@ =20 [FixedPcd] gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision - gMarvellTokenSpaceGuid.PcdProductManufacturer - gMarvellTokenSpaceGuid.PcdProductPlatformName - gMarvellTokenSpaceGuid.PcdProductSerial - gMarvellTokenSpaceGuid.PcdProductVersion - gMarvellTokenSpaceGuid.PcdFirmwareVendor - gMarvellTokenSpaceGuid.PcdFirmwareVersion + gMarvellSiliconTokenSpaceGuid.PcdProductManufacturer + gMarvellSiliconTokenSpaceGuid.PcdProductPlatformName + gMarvellSiliconTokenSpaceGuid.PcdProductSerial + gMarvellSiliconTokenSpaceGuid.PcdProductVersion + gMarvellSiliconTokenSpaceGuid.PcdFirmwareVendor + gMarvellSiliconTokenSpaceGuid.PcdFirmwareVersion =20 [Protocols] gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED diff --git a/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf b/Silicon/Ma= rvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf index b5d38da11b..902a3f4fff 100644 --- a/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf +++ b/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf @@ -18,7 +18,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] BaseLib @@ -52,9 +52,9 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize - gMarvellTokenSpaceGuid.PcdSpiMemoryBase - gMarvellTokenSpaceGuid.PcdSpiMemoryMapped - gMarvellTokenSpaceGuid.PcdSpiVariableOffset + gMarvellSiliconTokenSpaceGuid.PcdSpiMemoryBase + gMarvellSiliconTokenSpaceGuid.PcdSpiMemoryMapped + gMarvellSiliconTokenSpaceGuid.PcdSpiVariableOffset =20 [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64 diff --git a/Silicon/Marvell/Drivers/Spi/MvSpiFlashDxe/MvSpiFlashDxe.inf b/= Silicon/Marvell/Drivers/Spi/MvSpiFlashDxe/MvSpiFlashDxe.inf index c6e93b82a1..ecaf5ad05f 100644 --- a/Silicon/Marvell/Drivers/Spi/MvSpiFlashDxe/MvSpiFlashDxe.inf +++ b/Silicon/Marvell/Drivers/Spi/MvSpiFlashDxe/MvSpiFlashDxe.inf @@ -17,7 +17,7 @@ [Packages] EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib diff --git a/Silicon/Marvell/Drivers/Spi/MvSpiOrionDxe/MvSpiOrionDxe.inf b/= Silicon/Marvell/Drivers/Spi/MvSpiOrionDxe/MvSpiOrionDxe.inf index 36697d4fa4..10142105f8 100644 --- a/Silicon/Marvell/Drivers/Spi/MvSpiOrionDxe/MvSpiOrionDxe.inf +++ b/Silicon/Marvell/Drivers/Spi/MvSpiOrionDxe/MvSpiOrionDxe.inf @@ -17,7 +17,7 @@ [Packages] EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib @@ -32,9 +32,9 @@ UefiRuntimeLib =20 [FixedPcd] - gMarvellTokenSpaceGuid.PcdSpiClockFrequency - gMarvellTokenSpaceGuid.PcdSpiMaxFrequency - gMarvellTokenSpaceGuid.PcdSpiRegBase + gMarvellSiliconTokenSpaceGuid.PcdSpiClockFrequency + gMarvellSiliconTokenSpaceGuid.PcdSpiMaxFrequency + gMarvellSiliconTokenSpaceGuid.PcdSpiRegBase =20 [Protocols] gMarvellSpiMasterProtocolGuid diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf b/Silicon/Marv= ell/Library/ComPhyLib/ComPhyLib.inf index c9a00d79d7..13944a865d 100644 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf @@ -17,7 +17,7 @@ EmbeddedPkg/EmbeddedPkg.dec ArmPkg/ArmPkg.dec ArmPlatformPkg/ArmPlatformPkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] ArmLib @@ -37,24 +37,24 @@ gMarvellBoardDescProtocolGuid ## CONSUMES =20 [FixedPcd] - gMarvellTokenSpaceGuid.PcdComPhyDevices + gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices =20 #Chip0 - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds - gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyTypes + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhySpeeds + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyInvFlags =20 #Chip1 - gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes - gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds - gMarvellTokenSpaceGuid.PcdChip1ComPhyInvFlags + gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhyTypes + gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhySpeeds + gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhyInvFlags =20 #Chip2 - gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes - gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds - gMarvellTokenSpaceGuid.PcdChip2ComPhyInvFlags + gMarvellSiliconTokenSpaceGuid.PcdChip2ComPhyTypes + gMarvellSiliconTokenSpaceGuid.PcdChip2ComPhySpeeds + gMarvellSiliconTokenSpaceGuid.PcdChip2ComPhyInvFlags =20 #Chip3 - gMarvellTokenSpaceGuid.PcdChip3ComPhyTypes - gMarvellTokenSpaceGuid.PcdChip3ComPhySpeeds - gMarvellTokenSpaceGuid.PcdChip3ComPhyInvFlags + gMarvellSiliconTokenSpaceGuid.PcdChip3ComPhyTypes + gMarvellSiliconTokenSpaceGuid.PcdChip3ComPhySpeeds + gMarvellSiliconTokenSpaceGuid.PcdChip3ComPhyInvFlags diff --git a/Silicon/Marvell/Library/IcuLib/IcuLib.inf b/Silicon/Marvell/Li= brary/IcuLib/IcuLib.inf index a2adf412a7..d0817b4fb3 100644 --- a/Silicon/Marvell/Library/IcuLib/IcuLib.inf +++ b/Silicon/Marvell/Library/IcuLib/IcuLib.inf @@ -21,7 +21,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] ArmadaSoCDescLib @@ -30,4 +30,4 @@ PcdLib =20 [FixedPcd] - gMarvellTokenSpaceGuid.PcdMaxCpCount + gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount diff --git a/Silicon/Marvell/Library/MppLib/MppLib.inf b/Silicon/Marvell/Li= brary/MppLib/MppLib.inf index 4c1887a472..7bfbfee825 100644 --- a/Silicon/Marvell/Library/MppLib/MppLib.inf +++ b/Silicon/Marvell/Library/MppLib/MppLib.inf @@ -15,7 +15,7 @@ MdeModulePkg/MdeModulePkg.dec ArmPkg/ArmPkg.dec ArmPlatformPkg/ArmPlatformPkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] ArmLib @@ -28,57 +28,57 @@ MppLib.c =20 [FixedPcd] - gMarvellTokenSpaceGuid.PcdMppChipCount + gMarvellSiliconTokenSpaceGuid.PcdMppChipCount =20 - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress - gMarvellTokenSpaceGuid.PcdChip0MppPinCount - gMarvellTokenSpaceGuid.PcdChip0MppSel0 - gMarvellTokenSpaceGuid.PcdChip0MppSel1 - gMarvellTokenSpaceGuid.PcdChip0MppSel2 - gMarvellTokenSpaceGuid.PcdChip0MppSel3 - gMarvellTokenSpaceGuid.PcdChip0MppSel4 - gMarvellTokenSpaceGuid.PcdChip0MppSel5 - gMarvellTokenSpaceGuid.PcdChip0MppSel6 - gMarvellTokenSpaceGuid.PcdChip0MppSel7 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppReverseFlag + gMarvellSiliconTokenSpaceGuid.PcdChip0MppBaseAddress + gMarvellSiliconTokenSpaceGuid.PcdChip0MppPinCount + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel0 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel1 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel2 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel3 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel4 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel5 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel6 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel7 =20 - gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag - gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress - gMarvellTokenSpaceGuid.PcdChip1MppPinCount - gMarvellTokenSpaceGuid.PcdChip1MppSel0 - gMarvellTokenSpaceGuid.PcdChip1MppSel1 - gMarvellTokenSpaceGuid.PcdChip1MppSel2 - gMarvellTokenSpaceGuid.PcdChip1MppSel3 - gMarvellTokenSpaceGuid.PcdChip1MppSel4 - gMarvellTokenSpaceGuid.PcdChip1MppSel5 - gMarvellTokenSpaceGuid.PcdChip1MppSel6 - gMarvellTokenSpaceGuid.PcdChip1MppSel7 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppReverseFlag + gMarvellSiliconTokenSpaceGuid.PcdChip1MppBaseAddress + gMarvellSiliconTokenSpaceGuid.PcdChip1MppPinCount + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel0 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel1 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel2 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel3 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel4 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel5 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel6 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel7 =20 - gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag - gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress - gMarvellTokenSpaceGuid.PcdChip2MppPinCount - gMarvellTokenSpaceGuid.PcdChip2MppSel0 - gMarvellTokenSpaceGuid.PcdChip2MppSel1 - gMarvellTokenSpaceGuid.PcdChip2MppSel2 - gMarvellTokenSpaceGuid.PcdChip2MppSel3 - gMarvellTokenSpaceGuid.PcdChip2MppSel4 - gMarvellTokenSpaceGuid.PcdChip2MppSel5 - gMarvellTokenSpaceGuid.PcdChip2MppSel6 - gMarvellTokenSpaceGuid.PcdChip2MppSel7 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppReverseFlag + gMarvellSiliconTokenSpaceGuid.PcdChip2MppBaseAddress + gMarvellSiliconTokenSpaceGuid.PcdChip2MppPinCount + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel0 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel1 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel2 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel3 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel4 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel5 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel6 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel7 =20 - gMarvellTokenSpaceGuid.PcdChip3MppReverseFlag - gMarvellTokenSpaceGuid.PcdChip3MppBaseAddress - gMarvellTokenSpaceGuid.PcdChip3MppPinCount - gMarvellTokenSpaceGuid.PcdChip3MppSel0 - gMarvellTokenSpaceGuid.PcdChip3MppSel1 - gMarvellTokenSpaceGuid.PcdChip3MppSel2 - gMarvellTokenSpaceGuid.PcdChip3MppSel3 - gMarvellTokenSpaceGuid.PcdChip3MppSel4 - gMarvellTokenSpaceGuid.PcdChip3MppSel5 - gMarvellTokenSpaceGuid.PcdChip3MppSel6 - gMarvellTokenSpaceGuid.PcdChip3MppSel7 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppReverseFlag + gMarvellSiliconTokenSpaceGuid.PcdChip3MppBaseAddress + gMarvellSiliconTokenSpaceGuid.PcdChip3MppPinCount + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel0 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel1 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel2 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel3 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel4 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel5 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel6 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel7 =20 - gMarvellTokenSpaceGuid.PcdPciESdhci + gMarvellSiliconTokenSpaceGuid.PcdPciESdhci =20 [BuildOptions] *_*_*_CC_FLAGS =3D -fno-stack-protector diff --git a/Silicon/Marvell/Library/MvGpioLib/MvGpioLib.inf b/Silicon/Marv= ell/Library/MvGpioLib/MvGpioLib.inf index 24db268bc7..0fefbc0156 100644 --- a/Silicon/Marvell/Library/MvGpioLib/MvGpioLib.inf +++ b/Silicon/Marvell/Library/MvGpioLib/MvGpioLib.inf @@ -20,7 +20,7 @@ [Packages] EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf b/Silicon/Ma= rvell/Library/UtmiPhyLib/UtmiPhyLib.inf index f0051f47e1..26fbdf4438 100644 --- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf +++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf @@ -17,7 +17,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] ArmLib diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf b/Silico= n/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf index 2cd13aa2b6..d1e44beecc 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf @@ -33,7 +33,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [FixedPcd] gArmPlatformTokenSpaceGuid.PcdCoreCount diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf b/Silico= n/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf index 0c9fb82682..bc118b9fb3 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf @@ -34,7 +34,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [FixedPcd] gArmPlatformTokenSpaceGuid.PcdCoreCount diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf b/S= ilicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf index 27e7294014..7b040ce7e8 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf @@ -37,7 +37,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [FixedPcd] gArmPlatformTokenSpaceGuid.PcdCoreCount --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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