From nobody Sat May 18 14:01:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+109528+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+109528+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=marvell.com ARC-Seal: i=1; a=rsa-sha256; t=1697047735; cv=none; d=zohomail.com; s=zohoarc; b=HZJxNhH0rvu7786/DLg6Hs4pOAZiLhc9x2GJ4/+hrgMqbq5atVkYyttdlFrHGzooV/IHnq8jq/xqdTBdji1bVrO98hWycxWLUuJya0RYizg0ISNDsFk7Ns2K2MT+F+woGlkWvN5Nd9SlBhRHD3ppVmyREYUDe6aujRVeruOtS5Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697047735; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=Vg7vHeh5g0q32M3K11gPLYg3shKj6k2e3EaKjNp3HbA=; b=npiDXtmOnSrcS2cGgZT5lYXfTwDcMoT1fJjWIQZdfO6aT/yFJa8Yk2DsEnip5/P2AsWZgeFCjX1YlH6xjLhzQCcI4RJ//ZS7Lwo/v/+/EqYcoKXqLJ+0NAh5TasAO5smgxJWgFeevQvhN/0ZGX2057X6pW6EmEO4DNjKQ4WyFjs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+109528+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1697047735294143.81612685009884; Wed, 11 Oct 2023 11:08:55 -0700 (PDT) Return-Path: DKIM-Signature: a=rsa-sha256; bh=GK5GrRj/FFT30lnDRaz7UJvNijaUsU/xflzHgJc3BH8=; c=relaxed/simple; d=groups.io; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding:Content-Type; s=20140610; t=1697047734; v=1; b=gIK/kKkjiPGZU+qX9/oqet+Sh81wheuHb/iEjXpHyjZiqd+OJqONLqkIdkcciJyCHdk8ayZw ySWRuT8fxcVsmuNvyznAiuzj4FL4zHJThTR/PkU/9IWnUD31jKymKxUHqeUe1Mbwtnf6vQetloh UdJ3U542jiytYYIyq3c6YEPM= X-Received: by 127.0.0.2 with SMTP id lFjMYY1788612x6oeKUhce9Q; Wed, 11 Oct 2023 11:08:54 -0700 X-Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.148.174]) by mx.groups.io with SMTP id smtpd.web11.23479.1697046830915964028 for ; Wed, 11 Oct 2023 10:53:50 -0700 X-Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39BFvwpW006320; Wed, 11 Oct 2023 10:53:50 -0700 X-Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3tnxtggg8n-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 11 Oct 2023 10:53:50 -0700 X-Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 11 Oct 2023 10:53:48 -0700 X-Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 11 Oct 2023 10:53:48 -0700 X-Received: from MRVL-5Lp9he46Ey.marvell.com (unknown [10.193.12.187]) by maili.marvell.com (Postfix) with ESMTP id 5BA5B5B6934; Wed, 11 Oct 2023 10:53:48 -0700 (PDT) From: "Narinder Dhillon" To: CC: , , Narinder Dhillon Subject: [edk2-devel] [edk2-platforms PATCH v1 1/4] Silicon/Marvell: Retructure package Date: Wed, 11 Oct 2023 10:53:20 -0700 Message-ID: <20231011175323.14450-2-ndhillon@marvell.com> In-Reply-To: <20231011175323.14450-1-ndhillon@marvell.com> References: <20231011175323.14450-1-ndhillon@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: xUqEtKjadLEhhXDIVoyJlRiUmJ3-NInx X-Proofpoint-GUID: xUqEtKjadLEhhXDIVoyJlRiUmJ3-NInx Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ndhillon@marvell.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: ZPCuVbalvAwUGOtPyi2n45Ixx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1697047736360100009 Content-Type: text/plain; charset="utf-8" From: Narinder Dhillon Current Marvell package structure makes it difficult to add new silicon packages that reuse common elements without creating nested DEC files. This patch creates a new MarvellSiliconPkg folder and moves the current common elements inside it. Also gMarvellTokenSpaceGuid has been renamed to gMarvellSiliconTokenSpaceGuid to align with new package name. Signed-off-by: Narinder Dhillon --- Silicon/Marvell/Marvell.dec | 208 ----------------- .../Include/IndustryStandard/MvSmc.h | 0 .../Include/Library/ArmadaBoardDescLib.h | 0 .../Include/Library/ArmadaIcuLib.h | 0 .../Include/Library/ArmadaSoCDescLib.h | 0 .../Include/Library/MppLib.h | 0 .../Include/Library/MvComPhyLib.h | 0 .../Include/Library/MvGpioLib.h | 0 .../Include/Library/NonDiscoverableInitLib.h | 0 .../Include/Library/SampleAtResetLib.h | 0 .../Include/Library/UtmiPhyLib.h | 0 .../Include/Protocol/BoardDesc.h | 0 .../Include/Protocol/Eeprom.h | 0 .../Include/Protocol/Mdio.h | 0 .../Include/Protocol/MvI2c.h | 0 .../Include/Protocol/MvPhy.h | 0 .../Include/Protocol/Spi.h | 0 .../Include/Protocol/SpiFlash.h | 0 .../MarvellSiliconPkg/MarvellSiliconPkg.dec | 211 ++++++++++++++++++ 19 files changed, 211 insertions(+), 208 deletions(-) delete mode 100644 Silicon/Marvell/Marvell.dec rename Silicon/Marvell/{ =3D> MarvellSiliconPkg}/Include/IndustryStandard/= MvSmc.h (100%) rename Silicon/Marvell/{ =3D> MarvellSiliconPkg}/Include/Library/ArmadaBoa= rdDescLib.h (100%) rename Silicon/Marvell/{ =3D> MarvellSiliconPkg}/Include/Library/ArmadaIcu= Lib.h (100%) rename Silicon/Marvell/{ =3D> MarvellSiliconPkg}/Include/Library/ArmadaSoC= DescLib.h (100%) rename Silicon/Marvell/{ =3D> MarvellSiliconPkg}/Include/Library/MppLib.h = (100%) rename Silicon/Marvell/{ =3D> MarvellSiliconPkg}/Include/Library/MvComPhyL= ib.h (100%) rename Silicon/Marvell/{ =3D> MarvellSiliconPkg}/Include/Library/MvGpioLib= .h (100%) rename Silicon/Marvell/{ =3D> MarvellSiliconPkg}/Include/Library/NonDiscov= erableInitLib.h (100%) rename Silicon/Marvell/{ =3D> MarvellSiliconPkg}/Include/Library/SampleAtR= esetLib.h (100%) rename Silicon/Marvell/{ =3D> MarvellSiliconPkg}/Include/Library/UtmiPhyLi= b.h (100%) rename Silicon/Marvell/{ =3D> MarvellSiliconPkg}/Include/Protocol/BoardDes= c.h (100%) rename Silicon/Marvell/{ =3D> MarvellSiliconPkg}/Include/Protocol/Eeprom.h= (100%) rename Silicon/Marvell/{ =3D> MarvellSiliconPkg}/Include/Protocol/Mdio.h (= 100%) rename Silicon/Marvell/{ =3D> MarvellSiliconPkg}/Include/Protocol/MvI2c.h = (100%) rename Silicon/Marvell/{ =3D> MarvellSiliconPkg}/Include/Protocol/MvPhy.h = (100%) rename Silicon/Marvell/{ =3D> MarvellSiliconPkg}/Include/Protocol/Spi.h (1= 00%) rename Silicon/Marvell/{ =3D> MarvellSiliconPkg}/Include/Protocol/SpiFlash= .h (100%) create mode 100644 Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec deleted file mode 100644 index 482a90da25..0000000000 --- a/Silicon/Marvell/Marvell.dec +++ /dev/null @@ -1,208 +0,0 @@ -# Copyright (C) 2016 Marvell International Ltd. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# - -[Defines] - DEC_SPECIFICATION =3D 0x00010005 - PACKAGE_NAME =3D OpenPlatformMarvellPkg - PACKAGE_GUID =3D c372916e-83ad-4b2a-8410-bbc31bd9e68f - PACKAGE_VERSION =3D 0.1 - -##########################################################################= ###### -# -# Include Section - list of Include Paths that are provided by this packag= e. -# Comments are used for Keywords and Module Types. -# -# Supported Module Types: -# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_D= RIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION -# -##########################################################################= ###### - -[Includes] - Include - -[Guids.common] - gMarvellTokenSpaceGuid =3D { 0xf995c6c8, 0xbc9b, 0x4e93, { 0xbd, 0xcf, 0= x49, 0x90, 0xc6, 0xe7, 0x8c, 0x7f } } - - gShellEepromHiiGuid =3D { 0xb2f4c714, 0x147f, 0x4ff7, { 0x82, 0x1b, 0xce= , 0x7b, 0x91, 0x7f, 0x5f, 0x2f } } - gShellFUpdateHiiGuid =3D { 0x9b5d2176, 0x590a, 0x49db, { 0x89, 0x5d, 0x4= a, 0x70, 0xfe, 0xad, 0xbe, 0x24 } } - gShellSfHiiGuid =3D { 0x03a67756, 0x8cde, 0x4638, { 0x82, 0x34, 0x4a, 0x= 0f, 0x6d, 0x58, 0x81, 0x39 } } - -[LibraryClasses] - ArmadaBoardDescLib|Include/Library/ArmadaBoardDescLib.h - ArmadaIcuLib|Include/Library/ArmadaIcuLib.h - ArmadaSoCDescLib|Include/Library/ArmadaSoCDescLib.h - MvGpioLib|Include/Library/MvGpioLib.h - NonDiscoverableInitLib|Include/Library/NonDiscoverableInitLib.h - SampleAtResetLib|Include/Library/SampleAtResetLib.h - -[Protocols] - # installed as a protocol by PlatInitDxe to force ordering between DXE d= rivers - # that depend on the lowlevel platform initialization having been comple= ted - gMarvellPlatformInitCompleteProtocolGuid =3D { 0x465b8cf7, 0x016f, 0x4ba= 6, { 0xbe, 0x6b, 0x28, 0x0e, 0x3a, 0x7d, 0x38, 0x6f } } - -[PcdsFixedAtBuild.common] -#Board description - gMarvellTokenSpaceGuid.PcdMaxCpCount|0x2|UINT8|0x30000072 - -#MPP - gMarvellTokenSpaceGuid.PcdMppChipCount|0|UINT32|0x30000001 - - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE|BOOLEAN|0x30000002 - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0|UINT64|0x30000003 - gMarvellTokenSpaceGuid.PcdChip0MppPinCount|0|UINT32|0x30000004 - gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x0 }|VOID*|0x30000005 - gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x0 }|VOID*|0x30000006 - gMarvellTokenSpaceGuid.PcdChip0MppSel2|{ 0x0 }|VOID*|0x30000007 - gMarvellTokenSpaceGuid.PcdChip0MppSel3|{ 0x0 }|VOID*|0x30000008 - gMarvellTokenSpaceGuid.PcdChip0MppSel4|{ 0x0 }|VOID*|0x30000009 - gMarvellTokenSpaceGuid.PcdChip0MppSel5|{ 0x0 }|VOID*|0x30000010 - gMarvellTokenSpaceGuid.PcdChip0MppSel6|{ 0x0 }|VOID*|0x30000011 - gMarvellTokenSpaceGuid.PcdChip0MppSel7|{ 0x0 }|VOID*|0x30000012 - - gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE|BOOLEAN|0x30000013 - gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0|UINT64|0x30000014 - gMarvellTokenSpaceGuid.PcdChip1MppPinCount|0|UINT32|0x30000015 - gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x0 }|VOID*|0x30000016 - gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x0 }|VOID*|0x30000017 - gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x0 }|VOID*|0x30000018 - gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0x0 }|VOID*|0x30000019 - gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x0 }|VOID*|0x30000020 - gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x0 }|VOID*|0x30000021 - gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0x0 }|VOID*|0x30000022 - gMarvellTokenSpaceGuid.PcdChip1MppSel7|{ 0x0 }|VOID*|0x30000023 - - gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE|BOOLEAN|0x30000024 - gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0|UINT64|0x30000025 - gMarvellTokenSpaceGuid.PcdChip2MppPinCount|0|UINT32|0x30000026 - gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x0 }|VOID*|0x30000027 - gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0 }|VOID*|0x30000028 - gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0x0 }|VOID*|0x30000029 - gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0 }|VOID*|0x30000030 - gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0x0 }|VOID*|0x30000031 - gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0x0 }|VOID*|0x30000032 - gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0x0 }|VOID*|0x30000033 - gMarvellTokenSpaceGuid.PcdChip2MppSel7|{ 0x0 }|VOID*|0x30000034 - - gMarvellTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE|BOOLEAN|0x30000035 - gMarvellTokenSpaceGuid.PcdChip3MppBaseAddress|0|UINT64|0x30000036 - gMarvellTokenSpaceGuid.PcdChip3MppPinCount|0|UINT32|0x30000037 - gMarvellTokenSpaceGuid.PcdChip3MppSel0|{ 0x0 }|VOID*|0x30000038 - gMarvellTokenSpaceGuid.PcdChip3MppSel1|{ 0x0 }|VOID*|0x30000039 - gMarvellTokenSpaceGuid.PcdChip3MppSel2|{ 0x0 }|VOID*|0x30000040 - gMarvellTokenSpaceGuid.PcdChip3MppSel3|{ 0x0 }|VOID*|0x30000041 - gMarvellTokenSpaceGuid.PcdChip3MppSel4|{ 0x0 }|VOID*|0x30000042 - gMarvellTokenSpaceGuid.PcdChip3MppSel5|{ 0x0 }|VOID*|0x30000043 - gMarvellTokenSpaceGuid.PcdChip3MppSel6|{ 0x0 }|VOID*|0x30000044 - gMarvellTokenSpaceGuid.PcdChip3MppSel7|{ 0x0 }|VOID*|0x30000045 - -#I2C - gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x0 }|VOID*|0x3000046 - gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 }|VOID*|0x3000184 - gMarvellTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x0 }|VOID*|0x3000050 - gMarvellTokenSpaceGuid.PcdEepromI2cBuses|{ 0x0 }|VOID*|0x3000185 - gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0 }|VOID*|0x3000047 - gMarvellTokenSpaceGuid.PcdI2cClockFrequency|0|UINT32|0x3000048 - gMarvellTokenSpaceGuid.PcdI2cBaudRate|0|UINT32|0x3000049 - gMarvellTokenSpaceGuid.PcdI2cBusCount|0|UINT32|0x3000183 - -#SPI - gMarvellTokenSpaceGuid.PcdSpiRegBase|0|UINT32|0x3000051 - gMarvellTokenSpaceGuid.PcdSpiMemoryBase|0|UINT64|0x3000059 - gMarvellTokenSpaceGuid.PcdSpiMemoryMapped|TRUE|BOOLEAN|0x3000060 - gMarvellTokenSpaceGuid.PcdSpiVariableOffset|0|UINT32|0x3000061 - gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|0|UINT32|0x30000052 - gMarvellTokenSpaceGuid.PcdSpiClockFrequency|0|UINT32|0x30000053 - - gMarvellTokenSpaceGuid.PcdSpiFlashCs|0|UINT32|0x3000057 - gMarvellTokenSpaceGuid.PcdSpiFlashMode|0|UINT32|0x3000058 - -#ComPhy - gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x0 }|VOID*|0x30000098 - - #Chip0 - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ 0x0 }|VOID*|0x30000068 - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ 0x0 }|VOID*|0x30000069 - gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags|{ 0x0 }|VOID*|0x30000070 - - #Chip1 - gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ 0x0 }|VOID*|0x30000105 - gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ 0x0 }|VOID*|0x30000106 - gMarvellTokenSpaceGuid.PcdChip1ComPhyInvFlags|{ 0x0 }|VOID*|0x30000107 - - #Chip2 - gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes|{ 0x0 }|VOID*|0x30000140 - gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds|{ 0x0 }|VOID*|0x30000141 - gMarvellTokenSpaceGuid.PcdChip2ComPhyInvFlags|{ 0x0 }|VOID*|0x30000142 - - #Chip3 - gMarvellTokenSpaceGuid.PcdChip3ComPhyTypes|{ 0x0 }|VOID*|0x30000175 - gMarvellTokenSpaceGuid.PcdChip3ComPhySpeeds|{ 0x0 }|VOID*|0x30000176 - gMarvellTokenSpaceGuid.PcdChip3ComPhyInvFlags|{ 0x0 }|VOID*|0x30000177 - -#UtmiPhy - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x0 }|VOID*|0x30000206 - gMarvellTokenSpaceGuid.PcdUtmiPortType|{ 0x0 }|VOID*|0x30000207 - -#MDIO - gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x0 }|VOID*|0x3000043 - -#PHY - gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 }|VOID*|0x3000027 - gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 }|VOID*|0x3000095 - gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }|VOID*|0x3000024 - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE|BOOLEAN|0x3000070 - -#NET - gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x0 }|VOID*|0x3000028 - gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0 }|VOID*|0x3000029 - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0 }|VOID*|0x300002A - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x0 }|VOID*|0x300002B - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ 0x0 }|VOID*|0x3000044 - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0x0 }|VOID*|0x3000045 - gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0 }|VOID*|0x300002D - gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0 }|VOID*|0x300002C - -#PciEmulation - gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x0 }|VOID*|0x3000033 - gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x0 }|VOID*|0x3000034 - gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x0 }|VOID*|0x3000035 - -#Platform description - gMarvellTokenSpaceGuid.PcdFirmwareVendor|"EFI Development Kit II / Semih= alf"|VOID*|0x50000104 - gMarvellTokenSpaceGuid.PcdFirmwareVersion|"EDK II"|VOID*|0x50000105 - gMarvellTokenSpaceGuid.PcdProductManufacturer|"Marvell"|VOID*|0x50000100 - gMarvellTokenSpaceGuid.PcdProductPlatformName|"Marvell Development Board= "|VOID*|0x50000101 - gMarvellTokenSpaceGuid.PcdProductSerial|"Serial Not Set"|VOID*|0x50000103 - gMarvellTokenSpaceGuid.PcdProductVersion|"Revision unknown"|VOID*|0x5000= 0102 - -#RTC - gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0x0|UINT64|0x40000052 - -#TRNG - gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0x0|UINT64|0x50000053 - -#Configuration space - gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xF0000000|UINT64|0x500= 00054 - - # - # The secure firmware may occupy a DRAM region that is accessible by the - # normal world. These PCDs describe such a region, which will be convert= ed - # to 'reserved' memory before DXE is entered. - # - gMarvellTokenSpaceGuid.PcdArmTFRegionBase|0x0|UINT64|0x50000000 - gMarvellTokenSpaceGuid.PcdArmTFRegionSize|0x0|UINT32|0x50000001 - gMarvellTokenSpaceGuid.PcdAuxiliaryReservedRegionBase|0x0|UINT64|0x50000= 002 - gMarvellTokenSpaceGuid.PcdAuxiliaryReservedRegionSize|0x0|UINT32|0x50000= 003 - gMarvellTokenSpaceGuid.PcdOpTeeRegionBase|0x0|UINT64|0x50000004 - gMarvellTokenSpaceGuid.PcdOpTeeRegionSize|0x0|UINT32|0x50000005 - -[Protocols] - gMarvellBoardDescProtocolGuid =3D { 0xebed8738, 0xd4a6, 0x400= 1, { 0xa9, 0xc9, 0x52, 0xb0, 0xcb, 0x7d, 0xdb, 0xf9 }} - gMarvellEepromProtocolGuid =3D { 0x71954bda, 0x60d3, 0x4ef= 8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }} - gMarvellMdioProtocolGuid =3D { 0x40010b03, 0x5f08, 0x496= a, { 0xa2, 0x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }} - gMarvellPhyProtocolGuid =3D { 0x32f48a43, 0x37e3, 0x4ac= f, { 0x93, 0xc4, 0x3e, 0x57, 0xa7, 0xb0, 0xfb, 0xdc }} - gMarvellSpiMasterProtocolGuid =3D { 0x23de66a3, 0xf666, 0x4b3= e, { 0xaa, 0xa2, 0x68, 0x9b, 0x18, 0xae, 0x2e, 0x19 }} - gMarvellSpiFlashProtocolGuid =3D { 0x9accb423, 0x5bd2, 0x4fc= a, { 0x9b, 0x4c, 0x2e, 0x65, 0xfc, 0x25, 0xdf, 0x21 }} - diff --git a/Silicon/Marvell/Include/IndustryStandard/MvSmc.h b/Silicon/Mar= vell/MarvellSiliconPkg/Include/IndustryStandard/MvSmc.h similarity index 100% rename from Silicon/Marvell/Include/IndustryStandard/MvSmc.h rename to Silicon/Marvell/MarvellSiliconPkg/Include/IndustryStandard/MvSmc.h diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon= /Marvell/MarvellSiliconPkg/Include/Library/ArmadaBoardDescLib.h similarity index 100% rename from Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h rename to Silicon/Marvell/MarvellSiliconPkg/Include/Library/ArmadaBoardDesc= Lib.h diff --git a/Silicon/Marvell/Include/Library/ArmadaIcuLib.h b/Silicon/Marve= ll/MarvellSiliconPkg/Include/Library/ArmadaIcuLib.h similarity index 100% rename from Silicon/Marvell/Include/Library/ArmadaIcuLib.h rename to Silicon/Marvell/MarvellSiliconPkg/Include/Library/ArmadaIcuLib.h diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/M= arvell/MarvellSiliconPkg/Include/Library/ArmadaSoCDescLib.h similarity index 100% rename from Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h rename to Silicon/Marvell/MarvellSiliconPkg/Include/Library/ArmadaSoCDescLi= b.h diff --git a/Silicon/Marvell/Include/Library/MppLib.h b/Silicon/Marvell/Mar= vellSiliconPkg/Include/Library/MppLib.h similarity index 100% rename from Silicon/Marvell/Include/Library/MppLib.h rename to Silicon/Marvell/MarvellSiliconPkg/Include/Library/MppLib.h diff --git a/Silicon/Marvell/Include/Library/MvComPhyLib.h b/Silicon/Marvel= l/MarvellSiliconPkg/Include/Library/MvComPhyLib.h similarity index 100% rename from Silicon/Marvell/Include/Library/MvComPhyLib.h rename to Silicon/Marvell/MarvellSiliconPkg/Include/Library/MvComPhyLib.h diff --git a/Silicon/Marvell/Include/Library/MvGpioLib.h b/Silicon/Marvell/= MarvellSiliconPkg/Include/Library/MvGpioLib.h similarity index 100% rename from Silicon/Marvell/Include/Library/MvGpioLib.h rename to Silicon/Marvell/MarvellSiliconPkg/Include/Library/MvGpioLib.h diff --git a/Silicon/Marvell/Include/Library/NonDiscoverableInitLib.h b/Sil= icon/Marvell/MarvellSiliconPkg/Include/Library/NonDiscoverableInitLib.h similarity index 100% rename from Silicon/Marvell/Include/Library/NonDiscoverableInitLib.h rename to Silicon/Marvell/MarvellSiliconPkg/Include/Library/NonDiscoverable= InitLib.h diff --git a/Silicon/Marvell/Include/Library/SampleAtResetLib.h b/Silicon/M= arvell/MarvellSiliconPkg/Include/Library/SampleAtResetLib.h similarity index 100% rename from Silicon/Marvell/Include/Library/SampleAtResetLib.h rename to Silicon/Marvell/MarvellSiliconPkg/Include/Library/SampleAtResetLi= b.h diff --git a/Silicon/Marvell/Include/Library/UtmiPhyLib.h b/Silicon/Marvell= /MarvellSiliconPkg/Include/Library/UtmiPhyLib.h similarity index 100% rename from Silicon/Marvell/Include/Library/UtmiPhyLib.h rename to Silicon/Marvell/MarvellSiliconPkg/Include/Library/UtmiPhyLib.h diff --git a/Silicon/Marvell/Include/Protocol/BoardDesc.h b/Silicon/Marvell= /MarvellSiliconPkg/Include/Protocol/BoardDesc.h similarity index 100% rename from Silicon/Marvell/Include/Protocol/BoardDesc.h rename to Silicon/Marvell/MarvellSiliconPkg/Include/Protocol/BoardDesc.h diff --git a/Silicon/Marvell/Include/Protocol/Eeprom.h b/Silicon/Marvell/Ma= rvellSiliconPkg/Include/Protocol/Eeprom.h similarity index 100% rename from Silicon/Marvell/Include/Protocol/Eeprom.h rename to Silicon/Marvell/MarvellSiliconPkg/Include/Protocol/Eeprom.h diff --git a/Silicon/Marvell/Include/Protocol/Mdio.h b/Silicon/Marvell/Marv= ellSiliconPkg/Include/Protocol/Mdio.h similarity index 100% rename from Silicon/Marvell/Include/Protocol/Mdio.h rename to Silicon/Marvell/MarvellSiliconPkg/Include/Protocol/Mdio.h diff --git a/Silicon/Marvell/Include/Protocol/MvI2c.h b/Silicon/Marvell/Mar= vellSiliconPkg/Include/Protocol/MvI2c.h similarity index 100% rename from Silicon/Marvell/Include/Protocol/MvI2c.h rename to Silicon/Marvell/MarvellSiliconPkg/Include/Protocol/MvI2c.h diff --git a/Silicon/Marvell/Include/Protocol/MvPhy.h b/Silicon/Marvell/Mar= vellSiliconPkg/Include/Protocol/MvPhy.h similarity index 100% rename from Silicon/Marvell/Include/Protocol/MvPhy.h rename to Silicon/Marvell/MarvellSiliconPkg/Include/Protocol/MvPhy.h diff --git a/Silicon/Marvell/Include/Protocol/Spi.h b/Silicon/Marvell/Marve= llSiliconPkg/Include/Protocol/Spi.h similarity index 100% rename from Silicon/Marvell/Include/Protocol/Spi.h rename to Silicon/Marvell/MarvellSiliconPkg/Include/Protocol/Spi.h diff --git a/Silicon/Marvell/Include/Protocol/SpiFlash.h b/Silicon/Marvell/= MarvellSiliconPkg/Include/Protocol/SpiFlash.h similarity index 100% rename from Silicon/Marvell/Include/Protocol/SpiFlash.h rename to Silicon/Marvell/MarvellSiliconPkg/Include/Protocol/SpiFlash.h diff --git a/Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec b/Sili= con/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec new file mode 100644 index 0000000000..02ba7e449a --- /dev/null +++ b/Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec @@ -0,0 +1,211 @@ +# Copyright (C) 2016 Marvell International Ltd. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + DEC_SPECIFICATION =3D 0x00010005 + PACKAGE_NAME =3D MarvellSiliconPkg + PACKAGE_GUID =3D c372916e-83ad-4b2a-8410-bbc31bd9e68f + PACKAGE_VERSION =3D 0.1 + +##########################################################################= ###### +# +# Include Section - list of Include Paths that are provided by this packag= e. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_D= RIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +##########################################################################= ###### + +[Includes] + Include + +[Guids.common] + gMarvellSiliconTokenSpaceGuid =3D { 0xf995c6c8, 0xbc9b, 0x4e93, { 0xbd, = 0xcf, 0x49, 0x90, 0xc6, 0xe7, 0x8c, 0x7f } } + + gShellEepromHiiGuid =3D { 0xb2f4c714, 0x147f, 0x4ff7, { 0x82, 0x1b, 0xce= , 0x7b, 0x91, 0x7f, 0x5f, 0x2f } } + gShellFUpdateHiiGuid =3D { 0x9b5d2176, 0x590a, 0x49db, { 0x89, 0x5d, 0x4= a, 0x70, 0xfe, 0xad, 0xbe, 0x24 } } + gShellSfHiiGuid =3D { 0x03a67756, 0x8cde, 0x4638, { 0x82, 0x34, 0x4a, 0x= 0f, 0x6d, 0x58, 0x81, 0x39 } } + +[LibraryClasses] + ArmadaBoardDescLib|Include/Library/ArmadaBoardDescLib.h + ArmadaIcuLib|Include/Library/ArmadaIcuLib.h + ArmadaSoCDescLib|Include/Library/ArmadaSoCDescLib.h + MvGpioLib|Include/Library/MvGpioLib.h + NonDiscoverableInitLib|Include/Library/NonDiscoverableInitLib.h + SampleAtResetLib|Include/Library/SampleAtResetLib.h + UtmiPhyLib|Include/Library/UtmiPhyLib.h + MppLib|Include/Library/MppLib.h + MvComPhyLib|Include/Library/MvComPhyLib.h + +[Protocols] + # installed as a protocol by PlatInitDxe to force ordering between DXE d= rivers + # that depend on the lowlevel platform initialization having been comple= ted + gMarvellPlatformInitCompleteProtocolGuid =3D { 0x465b8cf7, 0x016f, 0x4ba= 6, { 0xbe, 0x6b, 0x28, 0x0e, 0x3a, 0x7d, 0x38, 0x6f } } + +[PcdsFixedAtBuild.common] +#Board description + gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount|0x2|UINT8|0x30000072 + +#MPP + gMarvellSiliconTokenSpaceGuid.PcdMppChipCount|0|UINT32|0x30000001 + + gMarvellSiliconTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE|BOOLEAN|0x300= 00002 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppBaseAddress|0|UINT64|0x30000003 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppPinCount|0|UINT32|0x30000004 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel0|{ 0x0 }|VOID*|0x30000005 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel1|{ 0x0 }|VOID*|0x30000006 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel2|{ 0x0 }|VOID*|0x30000007 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel3|{ 0x0 }|VOID*|0x30000008 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel4|{ 0x0 }|VOID*|0x30000009 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel5|{ 0x0 }|VOID*|0x30000010 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel6|{ 0x0 }|VOID*|0x30000011 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel7|{ 0x0 }|VOID*|0x30000012 + + gMarvellSiliconTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE|BOOLEAN|0x300= 00013 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppBaseAddress|0|UINT64|0x30000014 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppPinCount|0|UINT32|0x30000015 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel0|{ 0x0 }|VOID*|0x30000016 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel1|{ 0x0 }|VOID*|0x30000017 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel2|{ 0x0 }|VOID*|0x30000018 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel3|{ 0x0 }|VOID*|0x30000019 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel4|{ 0x0 }|VOID*|0x30000020 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel5|{ 0x0 }|VOID*|0x30000021 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel6|{ 0x0 }|VOID*|0x30000022 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel7|{ 0x0 }|VOID*|0x30000023 + + gMarvellSiliconTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE|BOOLEAN|0x300= 00024 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppBaseAddress|0|UINT64|0x30000025 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppPinCount|0|UINT32|0x30000026 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel0|{ 0x0 }|VOID*|0x30000027 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel1|{ 0x0 }|VOID*|0x30000028 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel2|{ 0x0 }|VOID*|0x30000029 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel3|{ 0x0 }|VOID*|0x30000030 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel4|{ 0x0 }|VOID*|0x30000031 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel5|{ 0x0 }|VOID*|0x30000032 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel6|{ 0x0 }|VOID*|0x30000033 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel7|{ 0x0 }|VOID*|0x30000034 + + gMarvellSiliconTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE|BOOLEAN|0x300= 00035 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppBaseAddress|0|UINT64|0x30000036 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppPinCount|0|UINT32|0x30000037 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel0|{ 0x0 }|VOID*|0x30000038 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel1|{ 0x0 }|VOID*|0x30000039 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel2|{ 0x0 }|VOID*|0x30000040 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel3|{ 0x0 }|VOID*|0x30000041 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel4|{ 0x0 }|VOID*|0x30000042 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel5|{ 0x0 }|VOID*|0x30000043 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel6|{ 0x0 }|VOID*|0x30000044 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel7|{ 0x0 }|VOID*|0x30000045 + +#I2C + gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x0 }|VOID*|0x30000= 46 + gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 }|VOID*|0x3000184 + gMarvellSiliconTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x0 }|VOID*|0x3000= 050 + gMarvellSiliconTokenSpaceGuid.PcdEepromI2cBuses|{ 0x0 }|VOID*|0x3000185 + gMarvellSiliconTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0 }|VOID*|0x3= 000047 + gMarvellSiliconTokenSpaceGuid.PcdI2cClockFrequency|0|UINT32|0x3000048 + gMarvellSiliconTokenSpaceGuid.PcdI2cBaudRate|0|UINT32|0x3000049 + gMarvellSiliconTokenSpaceGuid.PcdI2cBusCount|0|UINT32|0x3000183 + +#SPI + gMarvellSiliconTokenSpaceGuid.PcdSpiRegBase|0|UINT32|0x3000051 + gMarvellSiliconTokenSpaceGuid.PcdSpiMemoryBase|0|UINT64|0x3000059 + gMarvellSiliconTokenSpaceGuid.PcdSpiMemoryMapped|TRUE|BOOLEAN|0x3000060 + gMarvellSiliconTokenSpaceGuid.PcdSpiVariableOffset|0|UINT32|0x3000061 + gMarvellSiliconTokenSpaceGuid.PcdSpiMaxFrequency|0|UINT32|0x30000052 + gMarvellSiliconTokenSpaceGuid.PcdSpiClockFrequency|0|UINT32|0x30000053 + + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashCs|0|UINT32|0x3000057 + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashMode|0|UINT32|0x3000058 + +#ComPhy + gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x0 }|VOID*|0x30000098 + + #Chip0 + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyTypes|{ 0x0 }|VOID*|0x300000= 68 + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhySpeeds|{ 0x0 }|VOID*|0x30000= 069 + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyInvFlags|{ 0x0 }|VOID*|0x300= 00070 + + #Chip1 + gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhyTypes|{ 0x0 }|VOID*|0x300001= 05 + gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhySpeeds|{ 0x0 }|VOID*|0x30000= 106 + gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhyInvFlags|{ 0x0 }|VOID*|0x300= 00107 + + #Chip2 + gMarvellSiliconTokenSpaceGuid.PcdChip2ComPhyTypes|{ 0x0 }|VOID*|0x300001= 40 + gMarvellSiliconTokenSpaceGuid.PcdChip2ComPhySpeeds|{ 0x0 }|VOID*|0x30000= 141 + gMarvellSiliconTokenSpaceGuid.PcdChip2ComPhyInvFlags|{ 0x0 }|VOID*|0x300= 00142 + + #Chip3 + gMarvellSiliconTokenSpaceGuid.PcdChip3ComPhyTypes|{ 0x0 }|VOID*|0x300001= 75 + gMarvellSiliconTokenSpaceGuid.PcdChip3ComPhySpeeds|{ 0x0 }|VOID*|0x30000= 176 + gMarvellSiliconTokenSpaceGuid.PcdChip3ComPhyInvFlags|{ 0x0 }|VOID*|0x300= 00177 + +#UtmiPhy + gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x0 }|VOID*|0x= 30000206 + gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ 0x0 }|VOID*|0x30000207 + +#MDIO + gMarvellSiliconTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x0 }|VOID*|0x= 3000043 + +#PHY + gMarvellSiliconTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 }|VOID*|0x3000= 027 + gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 }|VOID*|0x3000095 + gMarvellSiliconTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }|VOID*|0x3000024 + gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE|BOOLEAN|0x30000= 70 + +#NET + gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers|{ 0x0 }|VOID*|0x3000028 + gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0 }|VOID*|0x3000029 + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0 }|VOID*|0x30= 0002A + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x0 }|VOID*|0x30000= 2B + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ 0x0 }|VOID*|0x3= 000044 + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes|{ 0x0 }|VOID*|0x3000045 + gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0 }|VOID*|0x3000= 02D + gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds|{ 0x0 }|VOID*|0x300002C + +#PciEmulation + gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x0 }|VOID*|0x3000033 + gMarvellSiliconTokenSpaceGuid.PcdPciEAhci|{ 0x0 }|VOID*|0x3000034 + gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x0 }|VOID*|0x3000035 + +#Platform description + gMarvellSiliconTokenSpaceGuid.PcdFirmwareVendor|"EFI Development Kit II = / Semihalf"|VOID*|0x50000104 + gMarvellSiliconTokenSpaceGuid.PcdFirmwareVersion|"EDK II"|VOID*|0x500001= 05 + gMarvellSiliconTokenSpaceGuid.PcdProductManufacturer|"Marvell"|VOID*|0x5= 0000100 + gMarvellSiliconTokenSpaceGuid.PcdProductPlatformName|"Marvell Developmen= t Board"|VOID*|0x50000101 + gMarvellSiliconTokenSpaceGuid.PcdProductSerial|"Serial Not Set"|VOID*|0x= 50000103 + gMarvellSiliconTokenSpaceGuid.PcdProductVersion|"Revision unknown"|VOID*= |0x50000102 + +#RTC + gMarvellSiliconTokenSpaceGuid.PcdRtcBaseAddress|0x0|UINT64|0x40000052 + +#TRNG + gMarvellSiliconTokenSpaceGuid.PcdEip76TrngBaseAddress|0x0|UINT64|0x50000= 053 + +#Configuration space + gMarvellSiliconTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xF0000000|UINT6= 4|0x50000054 + + # + # The secure firmware may occupy a DRAM region that is accessible by the + # normal world. These PCDs describe such a region, which will be convert= ed + # to 'reserved' memory before DXE is entered. + # + gMarvellSiliconTokenSpaceGuid.PcdArmTFRegionBase|0x0|UINT64|0x50000000 + gMarvellSiliconTokenSpaceGuid.PcdArmTFRegionSize|0x0|UINT32|0x50000001 + gMarvellSiliconTokenSpaceGuid.PcdAuxiliaryReservedRegionBase|0x0|UINT64|= 0x50000002 + gMarvellSiliconTokenSpaceGuid.PcdAuxiliaryReservedRegionSize|0x0|UINT32|= 0x50000003 + gMarvellSiliconTokenSpaceGuid.PcdOpTeeRegionBase|0x0|UINT64|0x50000004 + gMarvellSiliconTokenSpaceGuid.PcdOpTeeRegionSize|0x0|UINT32|0x50000005 + +[Protocols] + gMarvellBoardDescProtocolGuid =3D { 0xebed8738, 0xd4a6, 0x400= 1, { 0xa9, 0xc9, 0x52, 0xb0, 0xcb, 0x7d, 0xdb, 0xf9 }} + gMarvellEepromProtocolGuid =3D { 0x71954bda, 0x60d3, 0x4ef= 8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }} + gMarvellMdioProtocolGuid =3D { 0x40010b03, 0x5f08, 0x496= a, { 0xa2, 0x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }} + gMarvellPhyProtocolGuid =3D { 0x32f48a43, 0x37e3, 0x4ac= f, { 0x93, 0xc4, 0x3e, 0x57, 0xa7, 0xb0, 0xfb, 0xdc }} + gMarvellSpiMasterProtocolGuid =3D { 0x23de66a3, 0xf666, 0x4b3= e, { 0xaa, 0xa2, 0x68, 0x9b, 0x18, 0xae, 0x2e, 0x19 }} + gMarvellSpiFlashProtocolGuid =3D { 0x9accb423, 0x5bd2, 0x4fc= a, { 0x9b, 0x4c, 0x2e, 0x65, 0xfc, 0x25, 0xdf, 0x21 }} + --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#109528): https://edk2.groups.io/g/devel/message/109528 Mute This Topic: https://groups.io/mt/101902577/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 18 14:01:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+109529+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+109529+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=marvell.com ARC-Seal: i=1; a=rsa-sha256; t=1697047734; cv=none; d=zohomail.com; s=zohoarc; b=hrQI2s/nEO+gaTunnWUX77UkjBSUErWdkYBfD0PRHT25tRixYRo8D0Xt+XcxQP51zrxJjNZnWbsLV+8G9HOkRevGhX47RiFigAGa8qn/B0mgqvSNgf2FtE8uJWLaYtX8nWHt1oxKwvLg80R4lsY49wp/tsk7jOelbtDMFpt2+Cw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697047734; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=4Pudz1aKkyQOWMv+iU63iOD7powJ9XUHgIXqHlXNwAo=; b=SZ6ABJ6Q3qaOqztb7zCJmJi2oHNGItj1XY/t0d8N+LKzaz6phB6aF6r+wwGO1E/o7UBIzh5ElwfTmrl2bnG8BXInPlmKUsnik6LQW0g+p5+ZqPBOHhnxVx6mLXhxVrRVUHZkQfe+KX9yVoJ8jTcXDGkBRNw4s8Owc47qAnkf7a4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+109529+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 169704773479262.58401618628318; Wed, 11 Oct 2023 11:08:54 -0700 (PDT) Return-Path: DKIM-Signature: a=rsa-sha256; bh=DY32fvcx2k3cz35cgxiFyjzZkfl3UXsfDvrun6Dug4Y=; c=relaxed/simple; d=groups.io; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding:Content-Type; s=20140610; t=1697047734; v=1; b=rjJ11H1VYUhxAAkcMkh+VDmXmbsINpwJfDpjInQe/OzyrUxE1uxze/LTgu5tEzJ+cTMJcpHn MNIqe50QDS4GI5pk36uAX6S8uf+wteQovVVJCiNnjmQxUGD2wdyp2SLZtRcaBvuCpQQIBQJ7ps+ N8u8FJxujvs3OrmIb7t24D5k= X-Received: by 127.0.0.2 with SMTP id FICFYY1788612xYFN20JkhTm; Wed, 11 Oct 2023 11:08:54 -0700 X-Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.148.174]) by mx.groups.io with SMTP id smtpd.web11.23483.1697046832439508827 for ; Wed, 11 Oct 2023 10:53:52 -0700 X-Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39BFwr8B008613; Wed, 11 Oct 2023 10:53:52 -0700 X-Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3tnxtggg8r-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 11 Oct 2023 10:53:51 -0700 X-Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 11 Oct 2023 10:53:50 -0700 X-Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 11 Oct 2023 10:53:50 -0700 X-Received: from MRVL-5Lp9he46Ey.marvell.com (unknown [10.193.12.187]) by maili.marvell.com (Postfix) with ESMTP id CE5AB5B6934; Wed, 11 Oct 2023 10:53:49 -0700 (PDT) From: "Narinder Dhillon" To: CC: , , Narinder Dhillon Subject: [edk2-devel] [edk2-platforms PATCH v1 2/4] Silicon/Marvell: Use new package name and path Date: Wed, 11 Oct 2023 10:53:21 -0700 Message-ID: <20231011175323.14450-3-ndhillon@marvell.com> In-Reply-To: <20231011175323.14450-1-ndhillon@marvell.com> References: <20231011175323.14450-1-ndhillon@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: vm5wfK9VUakzt7jAHOGl1lsSDC3fq31j X-Proofpoint-GUID: vm5wfK9VUakzt7jAHOGl1lsSDC3fq31j Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ndhillon@marvell.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: lzaGOqUejVgbz15TEQqTNgaGx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1697047736381100010 Content-Type: text/plain; charset="utf-8" From: Narinder Dhillon New Marvell package name, path, and token space needs to be propagated to all dependent files. Signed-off-by: Narinder Dhillon --- .../Applications/EepromCmd/EepromCmd.inf | 2 +- .../Applications/FirmwareUpdate/FUpdate.inf | 6 +- .../Applications/SpiTool/SpiFlashCmd.inf | 6 +- .../Armada7k8k/AcpiTables/Armada70x0Db.inf | 2 +- .../Armada7k8k/AcpiTables/Armada80x0Db.inf | 2 +- .../Armada7k8k/AcpiTables/Armada80x0McBin.inf | 2 +- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 22 ++-- .../Armada7k8kRngDxe/Armada7k8kRngDxe.inf | 4 +- .../Drivers/PlatInitDxe/PlatInitDxe.inf | 6 +- .../PlatformFlashAccessLib.inf | 6 +- .../Library/Armada7k8kLib/Armada7k8kLib.inf | 4 +- .../Armada7k8kMemoryInitPeiLib.inf | 14 +-- .../PciHostBridgeLib.inf | 2 +- .../Armada7k8kPciSegmentLib/PciSegmentLib.inf | 2 +- .../Armada7k8kSampleAtResetLib.inf | 2 +- .../Armada7k8kSoCDescLib.inf | 4 +- .../RealTimeClockLib/RealTimeClockLib.inf | 4 +- .../Marvell/Documentation/PortingGuide.txt | 114 +++++++++--------- .../Drivers/BoardDesc/MvBoardDescDxe.inf | 18 +-- .../Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf | 2 +- .../Gpio/MvPca95xxDxe/MvPca95xxDxe.inf | 2 +- .../Drivers/I2c/MvEepromDxe/MvEepromDxe.inf | 6 +- .../Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf | 14 +-- .../Drivers/Net/MvMdioDxe/MvMdioDxe.inf | 2 +- .../Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.inf | 12 +- Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf | 16 +-- .../NonDiscoverableDxe/NonDiscoverableDxe.inf | 2 +- .../Drivers/SdMmc/XenonDxe/XenonDxe.inf | 2 +- .../SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 14 +-- .../Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf | 8 +- .../Spi/MvSpiFlashDxe/MvSpiFlashDxe.inf | 2 +- .../Spi/MvSpiOrionDxe/MvSpiOrionDxe.inf | 8 +- .../Marvell/Library/ComPhyLib/ComPhyLib.inf | 28 ++--- Silicon/Marvell/Library/IcuLib/IcuLib.inf | 4 +- Silicon/Marvell/Library/MppLib/MppLib.inf | 94 +++++++-------- .../Marvell/Library/MvGpioLib/MvGpioLib.inf | 2 +- .../Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf | 2 +- .../OcteonTx/AcpiTables/T91/Cn9130DbA.inf | 2 +- .../OcteonTx/AcpiTables/T91/Cn9131DbA.inf | 2 +- .../AcpiTables/T91/Cn913xCEx7Eval.inf | 2 +- 40 files changed, 224 insertions(+), 224 deletions(-) diff --git a/Silicon/Marvell/Applications/EepromCmd/EepromCmd.inf b/Silicon= /Marvell/Applications/EepromCmd/EepromCmd.inf index 1880416e42..8f71612e54 100644 --- a/Silicon/Marvell/Applications/EepromCmd/EepromCmd.inf +++ b/Silicon/Marvell/Applications/EepromCmd/EepromCmd.inf @@ -20,7 +20,7 @@ MdePkg/MdePkg.dec ShellPkg/ShellPkg.dec MdeModulePkg/MdeModulePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] UefiLib diff --git a/Silicon/Marvell/Applications/FirmwareUpdate/FUpdate.inf b/Sili= con/Marvell/Applications/FirmwareUpdate/FUpdate.inf index ee03d450d5..41e1d26140 100644 --- a/Silicon/Marvell/Applications/FirmwareUpdate/FUpdate.inf +++ b/Silicon/Marvell/Applications/FirmwareUpdate/FUpdate.inf @@ -20,7 +20,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec ShellPkg/ShellPkg.dec =20 [LibraryClasses] @@ -39,8 +39,8 @@ UefiRuntimeServicesTableLib =20 [Pcd] - gMarvellTokenSpaceGuid.PcdSpiFlashCs - gMarvellTokenSpaceGuid.PcdSpiFlashMode + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashCs + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashMode =20 [Protocols] gEfiBlockIoProtocolGuid diff --git a/Silicon/Marvell/Applications/SpiTool/SpiFlashCmd.inf b/Silicon= /Marvell/Applications/SpiTool/SpiFlashCmd.inf index 3a6a2115f8..8340e43723 100644 --- a/Silicon/Marvell/Applications/SpiTool/SpiFlashCmd.inf +++ b/Silicon/Marvell/Applications/SpiTool/SpiFlashCmd.inf @@ -21,7 +21,7 @@ MdePkg/MdePkg.dec ShellPkg/ShellPkg.dec MdeModulePkg/MdeModulePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] UefiLib @@ -39,8 +39,8 @@ FileHandleLib =20 [Pcd] - gMarvellTokenSpaceGuid.PcdSpiFlashCs - gMarvellTokenSpaceGuid.PcdSpiFlashMode + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashCs + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashMode =20 [Protocols] gMarvellSpiFlashProtocolGuid diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf b/Silic= on/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf index f3cce52e96..416b4cd63e 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf @@ -32,7 +32,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [FixedPcd] gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf b/Silic= on/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf index 7750817e1b..f7ed7f2350 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf @@ -32,7 +32,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [FixedPcd] gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf b/Si= licon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf index 98e5cc8b6e..c8cdea2b7d 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf @@ -33,7 +33,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [FixedPcd] gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel= l/Armada7k8k/Armada7k8k.dsc.inc index a135cb88b8..9711a8d6a7 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -373,31 +373,31 @@ gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000 =20 # ARM-TF region reservation - gMarvellTokenSpaceGuid.PcdArmTFRegionBase|0x4000000 - gMarvellTokenSpaceGuid.PcdArmTFRegionSize|0x200000 + gMarvellSiliconTokenSpaceGuid.PcdArmTFRegionBase|0x4000000 + gMarvellSiliconTokenSpaceGuid.PcdArmTFRegionSize|0x200000 =20 # Additional region reservation (e.g. for PEI stack base) - gMarvellTokenSpaceGuid.PcdAuxiliaryReservedRegionBase|0x4200000 - gMarvellTokenSpaceGuid.PcdAuxiliaryReservedRegionSize|0x200000 + gMarvellSiliconTokenSpaceGuid.PcdAuxiliaryReservedRegionBase|0x4200000 + gMarvellSiliconTokenSpaceGuid.PcdAuxiliaryReservedRegionSize|0x200000 =20 # OP-TEE region reservation - gMarvellTokenSpaceGuid.PcdOpTeeRegionBase|0x4400000 - gMarvellTokenSpaceGuid.PcdOpTeeRegionSize|0x1000000 + gMarvellSiliconTokenSpaceGuid.PcdOpTeeRegionBase|0x4400000 + gMarvellSiliconTokenSpaceGuid.PcdOpTeeRegionSize|0x1000000 =20 # SMBIOS/DMI gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev|0x0 gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2 - gMarvellTokenSpaceGuid.PcdFirmwareVersion|"EDK2 SH 1.1" + gMarvellSiliconTokenSpaceGuid.PcdFirmwareVersion|"EDK2 SH 1.1" =20 # TRNG - gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0xF2760000 + gMarvellSiliconTokenSpaceGuid.PcdEip76TrngBaseAddress|0xF2760000 =20 # # Variable store - default values # - gMarvellTokenSpaceGuid.PcdSpiMemoryBase|0xF9000000 - gMarvellTokenSpaceGuid.PcdSpiMemoryMapped|TRUE - gMarvellTokenSpaceGuid.PcdSpiVariableOffset|0x3C0000 + gMarvellSiliconTokenSpaceGuid.PcdSpiMemoryBase|0xF9000000 + gMarvellSiliconTokenSpaceGuid.PcdSpiMemoryMapped|TRUE + gMarvellSiliconTokenSpaceGuid.PcdSpiVariableOffset|0x3C0000 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000 diff --git a/Silicon/Marvell/Armada7k8k/Drivers/Armada7k8kRngDxe/Armada7k8k= RngDxe.inf b/Silicon/Marvell/Armada7k8k/Drivers/Armada7k8kRngDxe/Armada7k8k= RngDxe.inf index 4c766eeff8..7ba9ec9d26 100644 --- a/Silicon/Marvell/Armada7k8k/Drivers/Armada7k8kRngDxe/Armada7k8kRngDxe.= inf +++ b/Silicon/Marvell/Armada7k8k/Drivers/Armada7k8kRngDxe/Armada7k8kRngDxe.= inf @@ -20,7 +20,7 @@ =20 [Packages] MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] BaseMemoryLib @@ -29,7 +29,7 @@ UefiDriverEntryPoint =20 [Pcd] - gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress + gMarvellSiliconTokenSpaceGuid.PcdEip76TrngBaseAddress =20 [Protocols] gEfiRngProtocolGuid ## PRODUCES diff --git a/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf= b/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf index 398baebcf5..93f1f5c822 100644 --- a/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf +++ b/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf @@ -23,7 +23,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] ArmadaBoardDescLib @@ -42,8 +42,8 @@ gEfiEventReadyToBootGuid =20 [FixedPcd] - gMarvellTokenSpaceGuid.PcdProductManufacturer - gMarvellTokenSpaceGuid.PcdProductPlatformName + gMarvellSiliconTokenSpaceGuid.PcdProductManufacturer + gMarvellSiliconTokenSpaceGuid.PcdProductPlatformName =20 [Protocols] gMarvellPlatformInitCompleteProtocolGuid ## PRODUCES diff --git a/Silicon/Marvell/Armada7k8k/Feature/Capsule/PlatformFlashAccess= Lib/PlatformFlashAccessLib.inf b/Silicon/Marvell/Armada7k8k/Feature/Capsule= /PlatformFlashAccessLib/PlatformFlashAccessLib.inf index 69a7b71c51..b678a24028 100644 --- a/Silicon/Marvell/Armada7k8k/Feature/Capsule/PlatformFlashAccessLib/Pla= tformFlashAccessLib.inf +++ b/Silicon/Marvell/Armada7k8k/Feature/Capsule/PlatformFlashAccessLib/Pla= tformFlashAccessLib.inf @@ -24,7 +24,7 @@ MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec SignedCapsulePkg/SignedCapsulePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] BaseLib @@ -38,8 +38,8 @@ UefiRuntimeServicesTableLib =20 [Pcd] - gMarvellTokenSpaceGuid.PcdSpiFlashCs - gMarvellTokenSpaceGuid.PcdSpiFlashMode + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashCs + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashMode =20 [Protocols] gMarvellSpiFlashProtocolGuid diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib= .inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf index 8b77a07ab3..51127cfbd9 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf @@ -17,7 +17,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] ArmadaBoardDescLib @@ -45,7 +45,7 @@ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask gArmTokenSpaceGuid.PcdArmPrimaryCore =20 - gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress + gMarvellSiliconTokenSpaceGuid.PcdConfigSpaceBaseAddress =20 [Ppis] gArmMpCoreInfoPpiGuid diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/= Armada7k8kMemoryInitPeiLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7= k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.inf index f0b469ee55..e48ab5857d 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7= k8kMemoryInitPeiLib.inf +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7= k8kMemoryInitPeiLib.inf @@ -24,7 +24,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] ArmPlatformLib @@ -36,9 +36,9 @@ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob =20 [FixedPcd] - gMarvellTokenSpaceGuid.PcdArmTFRegionBase - gMarvellTokenSpaceGuid.PcdArmTFRegionSize - gMarvellTokenSpaceGuid.PcdAuxiliaryReservedRegionBase - gMarvellTokenSpaceGuid.PcdAuxiliaryReservedRegionSize - gMarvellTokenSpaceGuid.PcdOpTeeRegionBase - gMarvellTokenSpaceGuid.PcdOpTeeRegionSize + gMarvellSiliconTokenSpaceGuid.PcdArmTFRegionBase + gMarvellSiliconTokenSpaceGuid.PcdArmTFRegionSize + gMarvellSiliconTokenSpaceGuid.PcdAuxiliaryReservedRegionBase + gMarvellSiliconTokenSpaceGuid.PcdAuxiliaryReservedRegionSize + gMarvellSiliconTokenSpaceGuid.PcdOpTeeRegionBase + gMarvellSiliconTokenSpaceGuid.PcdOpTeeRegionSize diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/= PciHostBridgeLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHost= BridgeLib/PciHostBridgeLib.inf index 8fcb133e99..5877cb345e 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHost= BridgeLib.inf +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHost= BridgeLib.inf @@ -27,7 +27,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] ArmLib diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/Pci= SegmentLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib= /PciSegmentLib.inf index d3876791e9..40e74be6bf 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegment= Lib.inf +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegment= Lib.inf @@ -25,7 +25,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] ArmadaBoardDescLib diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/= Armada7k8kSampleAtResetLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7= k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.inf index 512cbf5f7e..09986828ec 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7= k8kSampleAtResetLib.inf +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7= k8kSampleAtResetLib.inf @@ -17,7 +17,7 @@ [Packages] MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLi= b/Armada7k8kSoCDescLib.inf index d5809c6789..15a7a505d8 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.inf +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.inf @@ -21,7 +21,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib @@ -29,4 +29,4 @@ PcdLib =20 [FixedPcd] - gMarvellTokenSpaceGuid.PcdMaxCpCount + gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount diff --git a/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeCl= ockLib.inf b/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeCl= ockLib.inf index 733827e61a..7dfa109e56 100644 --- a/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.= inf +++ b/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.= inf @@ -29,7 +29,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib @@ -44,7 +44,7 @@ gEfiEventVirtualAddressChangeGuid =20 [Pcd] - gMarvellTokenSpaceGuid.PcdRtcBaseAddress + gMarvellSiliconTokenSpaceGuid.PcdRtcBaseAddress =20 [Depex.common.DXE_RUNTIME_DRIVER] gEfiCpuArchProtocolGuid diff --git a/Silicon/Marvell/Documentation/PortingGuide.txt b/Silicon/Marve= ll/Documentation/PortingGuide.txt index 9dee5c89fa..24cf5cff0a 100644 --- a/Silicon/Marvell/Documentation/PortingGuide.txt +++ b/Silicon/Marvell/Documentation/PortingGuide.txt @@ -70,7 +70,7 @@ COMPHY configuration =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D In order to configure ComPhy library, following PCDs are available: =20 - - gMarvellTokenSpaceGuid.PcdComPhyDevices + - gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices =20 This array indicates, which ones of the ComPhy chips defined in MVHW_COMPHY_DESC template will be configured. @@ -84,7 +84,7 @@ defined numbers for SPEED/TYPE/INVERT, whose description = can be found in: =20 OpenPlatformPkg/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h =20 - - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes + - gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyTypes (Array of types - currently supported are: =20 CP_UNCONNECTED 0x0 @@ -112,7 +112,7 @@ defined numbers for SPEED/TYPE/INVERT, whose descriptio= n can be found in: CP_RXAUI1 0x16 CP_SFI 0x17 ) =20 - - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds + - gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhySpeeds (Array of speeds - currently supported are: =20 CP_1_25G 0x1 @@ -126,7 +126,7 @@ defined numbers for SPEED/TYPE/INVERT, whose descriptio= n can be found in: CP_6_25G 0x9 CP_10_3125G 0xA ) =20 - - gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags + - gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyInvFlags (Array of lane inversion types - currently supported are: =20 CP_NO_INVERT 0x0 @@ -138,9 +138,9 @@ Example ------- =20 #ComPhy - gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_SGMII1= ), $(CP_USB3_HOST0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) } - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_1_25G= ), $(CP_5G), $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) } + gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP= _SGMII1), $(CP_USB3_HOST0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_= PCIE2) } + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(C= P_1_25G), $(CP_5G), $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) } =20 =20 PHY Driver configuration @@ -148,13 +148,13 @@ PHY Driver configuration MvPhyDxe provides basic initialization and status routines for Marvell PHY= s. Currently only 1512 and 1112 series PHYs are supported. Following PCDs are= required: =20 - - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg + - gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg (boolean - if true, driver waits for autonegotiation on startup) - - gMarvellTokenSpaceGuid.PcdPhyDeviceIds + - gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds (list of values corresponding to MV_PHY_DEVICE_ID enum) - - gMarvellTokenSpaceGuid.PcdPhySmiAddresses + - gMarvellSiliconTokenSpaceGuid.PcdPhySmiAddresses (addresses of PHY devices) - - gMarvellTokenSpaceGuid.PcdPhy2MdioController + - gMarvellSiliconTokenSpaceGuid.PcdPhy2MdioController (Array specifying, which Mdio controller the PHY is attached to) =20 =20 @@ -169,11 +169,11 @@ It should be extended when adding support for other P= HY models. =20 Disable autonegotiation: =20 - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE =20 assuming, that PHY models are 1512 and 1112 for two consecutive ports: =20 - gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x1 } =20 =20 MDIO configuration @@ -181,7 +181,7 @@ MDIO configuration MDIO driver provides access to network PHYs' registers via EFI_MDIO_READ a= nd EFI_MDIO_WRITE functions (EFI_MDIO_PROTOCOL). Following PCD is required: =20 - - gMarvellTokenSpaceGuid.PcdMdioControllers + - gMarvellSiliconTokenSpaceGuid.PcdMdioControllers (Array with used controllers Set to 0x1 for enabled, 0x0 for disabled) =20 @@ -194,17 +194,17 @@ In order to enable driver on a new platform, followin= g steps need to be taken: - add following line to .fdf file: INF edk2-platforms/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf - add PCDs with relevant values to .dsc file: - - gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57 } + - gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57 } (addresses of I2C slave devices on bus) - - gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0 } + - gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0 } (buses to which accoring slaves are attached) - - gMarvellTokenSpaceGuid.PcdI2cBusCount|2 + - gMarvellSiliconTokenSpaceGuid.PcdI2cBusCount|2 (number of SoC's I2C buses) - - gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x1, 0x1 } + - gMarvellSiliconTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x1, 0x= 1 } (array with used controllers) - - gMarvellTokenSpaceGuid.PcdI2cClockFrequency|200000000 + - gMarvellSiliconTokenSpaceGuid.PcdI2cClockFrequency|200000000 (I2C host controller clock frequency) - - gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000 + - gMarvellSiliconTokenSpaceGuid.PcdI2cBaudRate|100000 (baud rate used in I2C transmission) =20 =20 @@ -213,13 +213,13 @@ PciEmulation configuration Installation of various NonDiscoverable devices via PciEmulation driver is= performed via set of PCDs. Following are available: =20 - - gMarvellTokenSpaceGuid.PcdPciEXhci + - gMarvellSiliconTokenSpaceGuid.PcdPciEXhci (Indicates, which Xhci devices are used) =20 - - gMarvellTokenSpaceGuid.PcdPciEAhci + - gMarvellSiliconTokenSpaceGuid.PcdPciEAhci (Indicates, which Ahci devices are used) =20 - - gMarvellTokenSpaceGuid.PcdPciESdhci + - gMarvellSiliconTokenSpaceGuid.PcdPciESdhci (Indicates, which Sdhci devices are used) =20 All above PCD's correspond to hardware description in a dedicated structur= e: @@ -235,15 +235,15 @@ Example Assuming we want to enable second XHCI port and one SDHCI port on Armada 70x0 board, following needs to be declared: =20 - gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x0 0x1 } - gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x0 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1 } =20 =20 SATA configuration =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D There is one additional PCD for AHCI: =20 - - gMarvellTokenSpaceGuid.PcdSataBaseAddress + - gMarvellSiliconTokenSpaceGuid.PcdSataBaseAddress (Base address of SATA controller register space - used in SATA Com= Phy init sequence) =20 @@ -253,14 +253,14 @@ Pp2Dxe configuration Pp2Dxe is driver supporting PP2 NIC on Marvell platforms. Following PCDs are required to operate: =20 - - gMarvellTokenSpaceGuid.PcdPp2Controllers + - gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers (Array with used controllers Set to 0x1 for enabled, 0x0 for disabled) =20 - - gMarvellTokenSpaceGuid.PcdPp2Port2Controller + - gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller (Array specifying, to which controller the port belongs to) =20 - - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes + - gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes (Indicates speed of the network interface: =20 PHY_RGMII 0x0 @@ -273,22 +273,22 @@ are required to operate: PHY_RXAUI 0x7 PHY_SFI 0x8 ) =20 - - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes + - gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes (Array specifying, to which PHY from - gMarvellTokenSpaceGuid.PcdPhyDeviceIds is used. If none, + gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds is used. If none, e.g. in 10G SFI in-band link detection, 0xFF value must be specified) =20 - - gMarvellTokenSpaceGuid.PcdPp2PortIds + - gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds (Identificators of PP2 ports) =20 - - gMarvellTokenSpaceGuid.PcdPp2GopIndexes + - gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes (Indexes used in GOP operation) =20 - - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp + - gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp (Set to 0x1 for always-up interface, 0x0 otherwise) =20 - - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed + - gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed (Indicates speed of the network interface: =20 PHY_SPEED_10 0x1 @@ -302,11 +302,11 @@ UTMI PHY configuration =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D In order to configure UTMI, following PCDs are available: =20 - - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled + - gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled (Array with used controllers Set to 0x1 for enabled, 0x0 for disabled) =20 - - gMarvellTokenSpaceGuid.PcdUtmiPortType + - gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType (Indicates type of the connected USB port: =20 UTMI_USB_HOST0 0x0 @@ -317,29 +317,29 @@ Example ------- =20 # UtmiPhy - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, = 0x1 } - gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST= 0), $(UTMI_USB_HOST1) } + gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|= { 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_U= SB_HOST0), $(UTMI_USB_HOST1) } =20 =20 SPI driver configuration =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Following PCDs are available for configuration of spi driver: =20 - - gMarvellTokenSpaceGuid.PcdSpiClockFrequency + - gMarvellSiliconTokenSpaceGuid.PcdSpiClockFrequency (Frequency (in Hz) of SPI clock) =20 - - gMarvellTokenSpaceGuid.PcdSpiMaxFrequency + - gMarvellSiliconTokenSpaceGuid.PcdSpiMaxFrequency (Max SCLK line frequency (in Hz) (max transfer frequency) ) =20 SpiFlash configuration =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Folowing PCDs for spi flash driver configuration must be set properly: =20 - - gMarvellTokenSpaceGuid.PcdSpiFlashMode + - gMarvellSiliconTokenSpaceGuid.PcdSpiFlashMode (Default SCLK mode (see SPI_MODE enum in file edk2-platforms/Platform/Marvell/Drivers/Spi/MvSpi.h)) =20 - - gMarvellTokenSpaceGuid.PcdSpiFlashCs + - gMarvellSiliconTokenSpaceGuid.PcdSpiFlashCs (Chip select used for communication with the Flash) =20 MPP configuration @@ -350,7 +350,7 @@ In order to set desired pin multiplexing, .dsc file nee= ds to be modified. Documentation/Build.txt for currently supported {platftorm_name} ) Following PCDs are available: =20 - - gMarvellTokenSpaceGuid.PcdMppChipCount + - gMarvellSiliconTokenSpaceGuid.PcdMppChipCount (Indicates how many different chips are placed on board. So far up= to 4 chips are supported) =20 @@ -360,37 +360,37 @@ Every MPP PCD has part where =20 Below is example for the first chip (Chip0). =20 - - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag + - gMarvellSiliconTokenSpaceGuid.PcdChip0MppReverseFlag (Indicates that register order is reversed. (Needs to be used only= for AP806-Z1) ) =20 - - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress + - gMarvellSiliconTokenSpaceGuid.PcdChip0MppBaseAddress (This is base address for MPP configuration register) =20 - - gMarvellTokenSpaceGuid.PcdChip0MppPinCount + - gMarvellSiliconTokenSpaceGuid.PcdChip0MppPinCount (Defines how many MPP pins are available) =20 - - gMarvellTokenSpaceGuid.PcdChip0MppSel0 - - gMarvellTokenSpaceGuid.PcdChip0MppSel1 - - gMarvellTokenSpaceGuid.PcdChip0MppSel2 + - gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel0 + - gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel1 + - gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel2 (This registers defines functions of 10 pins in ascending order) =20 Examples -------- =20 # APN806-A0 MPP SET - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 - gMarvellTokenSpaceGuid.PcdChip0MppRegCount|3 - gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0= x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x0 } - gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x0, 0x0, 0x0, 0= x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE + gMarvellSiliconTokenSpaceGuid.PcdChip0MppBaseAddress|0xF0= 6F4000 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppRegCount|3 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1,= 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel1|{ 0x0, 0x0,= 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } =20 Set pin 6 and 7 to 0xa function: - gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0xa, 0xa, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel0|{ 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0xa, 0xa, 0x0, 0x0 } =20 =20 Ramdisk configuration =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D There is one PCD available for Ramdisk configuration =20 - - gMarvellTokenSpaceGuid.PcdRamDiskSize + - gMarvellSiliconTokenSpaceGuid.PcdRamDiskSize (Defines size of Ramdisk) diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf b/Silicon= /Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf index 75ecae1b98..0dd17f7b56 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf @@ -18,7 +18,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] ArmadaBoardDescLib @@ -32,14 +32,14 @@ gMarvellBoardDescProtocolGuid =20 [Pcd] - gMarvellTokenSpaceGuid.PcdComPhyDevices - gMarvellTokenSpaceGuid.PcdI2cControllersEnabled - gMarvellTokenSpaceGuid.PcdPciEAhci - gMarvellTokenSpaceGuid.PcdPciESdhci - gMarvellTokenSpaceGuid.PcdPciEXhci - gMarvellTokenSpaceGuid.PcdPp2Controllers - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled - gMarvellTokenSpaceGuid.PcdUtmiPortType + gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices + gMarvellSiliconTokenSpaceGuid.PcdI2cControllersEnabled + gMarvellSiliconTokenSpaceGuid.PcdPciEAhci + gMarvellSiliconTokenSpaceGuid.PcdPciESdhci + gMarvellSiliconTokenSpaceGuid.PcdPciEXhci + gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers + gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled + gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType =20 [Depex] TRUE diff --git a/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf b/Silicon= /Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf index 6f36c2db2e..db111a2c57 100644 --- a/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf +++ b/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf @@ -21,7 +21,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] ArmadaSoCDescLib diff --git a/Silicon/Marvell/Drivers/Gpio/MvPca95xxDxe/MvPca95xxDxe.inf b/S= ilicon/Marvell/Drivers/Gpio/MvPca95xxDxe/MvPca95xxDxe.inf index c202d811f2..0f00698c55 100644 --- a/Silicon/Marvell/Drivers/Gpio/MvPca95xxDxe/MvPca95xxDxe.inf +++ b/Silicon/Marvell/Drivers/Gpio/MvPca95xxDxe/MvPca95xxDxe.inf @@ -21,7 +21,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib diff --git a/Silicon/Marvell/Drivers/I2c/MvEepromDxe/MvEepromDxe.inf b/Sili= con/Marvell/Drivers/I2c/MvEepromDxe/MvEepromDxe.inf index cfe9db9c1c..c5f6aa7833 100644 --- a/Silicon/Marvell/Drivers/I2c/MvEepromDxe/MvEepromDxe.inf +++ b/Silicon/Marvell/Drivers/I2c/MvEepromDxe/MvEepromDxe.inf @@ -18,7 +18,7 @@ ArmPlatformPkg/ArmPlatformPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] BaseLib @@ -36,8 +36,8 @@ gMarvellEepromProtocolGuid =20 [Pcd] - gMarvellTokenSpaceGuid.PcdEepromI2cAddresses - gMarvellTokenSpaceGuid.PcdEepromI2cBuses + gMarvellSiliconTokenSpaceGuid.PcdEepromI2cAddresses + gMarvellSiliconTokenSpaceGuid.PcdEepromI2cBuses =20 [Depex] TRUE diff --git a/Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf b/Silicon/Ma= rvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf index f631fbe797..d73f2433fc 100755 --- a/Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf +++ b/Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf @@ -19,7 +19,7 @@ MdeModulePkg/MdeModulePkg.dec ArmPlatformPkg/ArmPlatformPkg.dec ArmPkg/ArmPkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] IoLib @@ -38,12 +38,12 @@ gMarvellBoardDescProtocolGuid =20 [Pcd] - gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses - gMarvellTokenSpaceGuid.PcdI2cSlaveBuses - gMarvellTokenSpaceGuid.PcdI2cControllersEnabled - gMarvellTokenSpaceGuid.PcdI2cClockFrequency - gMarvellTokenSpaceGuid.PcdI2cBaudRate - gMarvellTokenSpaceGuid.PcdI2cBusCount + gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveAddresses + gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveBuses + gMarvellSiliconTokenSpaceGuid.PcdI2cControllersEnabled + gMarvellSiliconTokenSpaceGuid.PcdI2cClockFrequency + gMarvellSiliconTokenSpaceGuid.PcdI2cBaudRate + gMarvellSiliconTokenSpaceGuid.PcdI2cBusCount =20 [Guids] gEfiEndOfDxeEventGroupGuid diff --git a/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf b/Silicon/= Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf index f4511a9288..196d119586 100644 --- a/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf +++ b/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf @@ -21,7 +21,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] BaseLib diff --git a/Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.inf b/Silicon/Ma= rvell/Drivers/Net/MvPhyDxe/MvPhyDxe.inf index abf84af612..b8e5d30fc3 100644 --- a/Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.inf +++ b/Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.inf @@ -19,7 +19,7 @@ ArmPlatformPkg/ArmPlatformPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] BaseLib @@ -36,11 +36,11 @@ gMarvellPhyProtocolGuid =20 [Pcd] - gMarvellTokenSpaceGuid.PcdMdioControllersEnabled - gMarvellTokenSpaceGuid.PcdPhy2MdioController - gMarvellTokenSpaceGuid.PcdPhyDeviceIds - gMarvellTokenSpaceGuid.PcdPhySmiAddresses - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg + gMarvellSiliconTokenSpaceGuid.PcdMdioControllersEnabled + gMarvellSiliconTokenSpaceGuid.PcdPhy2MdioController + gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds + gMarvellSiliconTokenSpaceGuid.PcdPhySmiAddresses + gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg =20 [Depex] TRUE diff --git a/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf b/Silicon/Marvel= l/Drivers/Net/Pp2Dxe/Pp2Dxe.inf index 17a2a88d62..bd8b557c1a 100644 --- a/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf +++ b/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf @@ -21,7 +21,7 @@ MdeModulePkg/MdeModulePkg.dec NetworkPkg/NetworkPkg.dec ArmPkg/ArmPkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DmaLib @@ -47,13 +47,13 @@ gMarvellPhyProtocolGuid =20 [Pcd] - gMarvellTokenSpaceGuid.PcdPp2GopIndexes - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes - gMarvellTokenSpaceGuid.PcdPp2Port2Controller - gMarvellTokenSpaceGuid.PcdPp2PortIds + gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes + gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller + gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds =20 [Depex] TRUE diff --git a/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.= inf b/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.inf index af266ee083..88fc3f17bb 100644 --- a/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.inf +++ b/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.inf @@ -19,7 +19,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] NonDiscoverableDeviceRegistrationLib diff --git a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonDxe.inf b/Silicon/= Marvell/Drivers/SdMmc/XenonDxe/XenonDxe.inf index 18f1b164fd..4bf8718c36 100644 --- a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonDxe.inf +++ b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonDxe.inf @@ -33,7 +33,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] BaseLib diff --git a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.in= f b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf index 582c0faf25..682de9aeec 100644 --- a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf +++ b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf @@ -22,7 +22,7 @@ [Packages] MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] BaseLib @@ -36,12 +36,12 @@ =20 [FixedPcd] gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision - gMarvellTokenSpaceGuid.PcdProductManufacturer - gMarvellTokenSpaceGuid.PcdProductPlatformName - gMarvellTokenSpaceGuid.PcdProductSerial - gMarvellTokenSpaceGuid.PcdProductVersion - gMarvellTokenSpaceGuid.PcdFirmwareVendor - gMarvellTokenSpaceGuid.PcdFirmwareVersion + gMarvellSiliconTokenSpaceGuid.PcdProductManufacturer + gMarvellSiliconTokenSpaceGuid.PcdProductPlatformName + gMarvellSiliconTokenSpaceGuid.PcdProductSerial + gMarvellSiliconTokenSpaceGuid.PcdProductVersion + gMarvellSiliconTokenSpaceGuid.PcdFirmwareVendor + gMarvellSiliconTokenSpaceGuid.PcdFirmwareVersion =20 [Protocols] gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED diff --git a/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf b/Silicon/Ma= rvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf index b5d38da11b..902a3f4fff 100644 --- a/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf +++ b/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf @@ -18,7 +18,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] BaseLib @@ -52,9 +52,9 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize - gMarvellTokenSpaceGuid.PcdSpiMemoryBase - gMarvellTokenSpaceGuid.PcdSpiMemoryMapped - gMarvellTokenSpaceGuid.PcdSpiVariableOffset + gMarvellSiliconTokenSpaceGuid.PcdSpiMemoryBase + gMarvellSiliconTokenSpaceGuid.PcdSpiMemoryMapped + gMarvellSiliconTokenSpaceGuid.PcdSpiVariableOffset =20 [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64 diff --git a/Silicon/Marvell/Drivers/Spi/MvSpiFlashDxe/MvSpiFlashDxe.inf b/= Silicon/Marvell/Drivers/Spi/MvSpiFlashDxe/MvSpiFlashDxe.inf index c6e93b82a1..ecaf5ad05f 100644 --- a/Silicon/Marvell/Drivers/Spi/MvSpiFlashDxe/MvSpiFlashDxe.inf +++ b/Silicon/Marvell/Drivers/Spi/MvSpiFlashDxe/MvSpiFlashDxe.inf @@ -17,7 +17,7 @@ [Packages] EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib diff --git a/Silicon/Marvell/Drivers/Spi/MvSpiOrionDxe/MvSpiOrionDxe.inf b/= Silicon/Marvell/Drivers/Spi/MvSpiOrionDxe/MvSpiOrionDxe.inf index 36697d4fa4..10142105f8 100644 --- a/Silicon/Marvell/Drivers/Spi/MvSpiOrionDxe/MvSpiOrionDxe.inf +++ b/Silicon/Marvell/Drivers/Spi/MvSpiOrionDxe/MvSpiOrionDxe.inf @@ -17,7 +17,7 @@ [Packages] EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib @@ -32,9 +32,9 @@ UefiRuntimeLib =20 [FixedPcd] - gMarvellTokenSpaceGuid.PcdSpiClockFrequency - gMarvellTokenSpaceGuid.PcdSpiMaxFrequency - gMarvellTokenSpaceGuid.PcdSpiRegBase + gMarvellSiliconTokenSpaceGuid.PcdSpiClockFrequency + gMarvellSiliconTokenSpaceGuid.PcdSpiMaxFrequency + gMarvellSiliconTokenSpaceGuid.PcdSpiRegBase =20 [Protocols] gMarvellSpiMasterProtocolGuid diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf b/Silicon/Marv= ell/Library/ComPhyLib/ComPhyLib.inf index c9a00d79d7..13944a865d 100644 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf @@ -17,7 +17,7 @@ EmbeddedPkg/EmbeddedPkg.dec ArmPkg/ArmPkg.dec ArmPlatformPkg/ArmPlatformPkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] ArmLib @@ -37,24 +37,24 @@ gMarvellBoardDescProtocolGuid ## CONSUMES =20 [FixedPcd] - gMarvellTokenSpaceGuid.PcdComPhyDevices + gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices =20 #Chip0 - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds - gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyTypes + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhySpeeds + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyInvFlags =20 #Chip1 - gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes - gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds - gMarvellTokenSpaceGuid.PcdChip1ComPhyInvFlags + gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhyTypes + gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhySpeeds + gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhyInvFlags =20 #Chip2 - gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes - gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds - gMarvellTokenSpaceGuid.PcdChip2ComPhyInvFlags + gMarvellSiliconTokenSpaceGuid.PcdChip2ComPhyTypes + gMarvellSiliconTokenSpaceGuid.PcdChip2ComPhySpeeds + gMarvellSiliconTokenSpaceGuid.PcdChip2ComPhyInvFlags =20 #Chip3 - gMarvellTokenSpaceGuid.PcdChip3ComPhyTypes - gMarvellTokenSpaceGuid.PcdChip3ComPhySpeeds - gMarvellTokenSpaceGuid.PcdChip3ComPhyInvFlags + gMarvellSiliconTokenSpaceGuid.PcdChip3ComPhyTypes + gMarvellSiliconTokenSpaceGuid.PcdChip3ComPhySpeeds + gMarvellSiliconTokenSpaceGuid.PcdChip3ComPhyInvFlags diff --git a/Silicon/Marvell/Library/IcuLib/IcuLib.inf b/Silicon/Marvell/Li= brary/IcuLib/IcuLib.inf index a2adf412a7..d0817b4fb3 100644 --- a/Silicon/Marvell/Library/IcuLib/IcuLib.inf +++ b/Silicon/Marvell/Library/IcuLib/IcuLib.inf @@ -21,7 +21,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] ArmadaSoCDescLib @@ -30,4 +30,4 @@ PcdLib =20 [FixedPcd] - gMarvellTokenSpaceGuid.PcdMaxCpCount + gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount diff --git a/Silicon/Marvell/Library/MppLib/MppLib.inf b/Silicon/Marvell/Li= brary/MppLib/MppLib.inf index 4c1887a472..7bfbfee825 100644 --- a/Silicon/Marvell/Library/MppLib/MppLib.inf +++ b/Silicon/Marvell/Library/MppLib/MppLib.inf @@ -15,7 +15,7 @@ MdeModulePkg/MdeModulePkg.dec ArmPkg/ArmPkg.dec ArmPlatformPkg/ArmPlatformPkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] ArmLib @@ -28,57 +28,57 @@ MppLib.c =20 [FixedPcd] - gMarvellTokenSpaceGuid.PcdMppChipCount + gMarvellSiliconTokenSpaceGuid.PcdMppChipCount =20 - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress - gMarvellTokenSpaceGuid.PcdChip0MppPinCount - gMarvellTokenSpaceGuid.PcdChip0MppSel0 - gMarvellTokenSpaceGuid.PcdChip0MppSel1 - gMarvellTokenSpaceGuid.PcdChip0MppSel2 - gMarvellTokenSpaceGuid.PcdChip0MppSel3 - gMarvellTokenSpaceGuid.PcdChip0MppSel4 - gMarvellTokenSpaceGuid.PcdChip0MppSel5 - gMarvellTokenSpaceGuid.PcdChip0MppSel6 - gMarvellTokenSpaceGuid.PcdChip0MppSel7 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppReverseFlag + gMarvellSiliconTokenSpaceGuid.PcdChip0MppBaseAddress + gMarvellSiliconTokenSpaceGuid.PcdChip0MppPinCount + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel0 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel1 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel2 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel3 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel4 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel5 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel6 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel7 =20 - gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag - gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress - gMarvellTokenSpaceGuid.PcdChip1MppPinCount - gMarvellTokenSpaceGuid.PcdChip1MppSel0 - gMarvellTokenSpaceGuid.PcdChip1MppSel1 - gMarvellTokenSpaceGuid.PcdChip1MppSel2 - gMarvellTokenSpaceGuid.PcdChip1MppSel3 - gMarvellTokenSpaceGuid.PcdChip1MppSel4 - gMarvellTokenSpaceGuid.PcdChip1MppSel5 - gMarvellTokenSpaceGuid.PcdChip1MppSel6 - gMarvellTokenSpaceGuid.PcdChip1MppSel7 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppReverseFlag + gMarvellSiliconTokenSpaceGuid.PcdChip1MppBaseAddress + gMarvellSiliconTokenSpaceGuid.PcdChip1MppPinCount + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel0 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel1 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel2 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel3 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel4 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel5 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel6 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel7 =20 - gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag - gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress - gMarvellTokenSpaceGuid.PcdChip2MppPinCount - gMarvellTokenSpaceGuid.PcdChip2MppSel0 - gMarvellTokenSpaceGuid.PcdChip2MppSel1 - gMarvellTokenSpaceGuid.PcdChip2MppSel2 - gMarvellTokenSpaceGuid.PcdChip2MppSel3 - gMarvellTokenSpaceGuid.PcdChip2MppSel4 - gMarvellTokenSpaceGuid.PcdChip2MppSel5 - gMarvellTokenSpaceGuid.PcdChip2MppSel6 - gMarvellTokenSpaceGuid.PcdChip2MppSel7 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppReverseFlag + gMarvellSiliconTokenSpaceGuid.PcdChip2MppBaseAddress + gMarvellSiliconTokenSpaceGuid.PcdChip2MppPinCount + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel0 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel1 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel2 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel3 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel4 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel5 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel6 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel7 =20 - gMarvellTokenSpaceGuid.PcdChip3MppReverseFlag - gMarvellTokenSpaceGuid.PcdChip3MppBaseAddress - gMarvellTokenSpaceGuid.PcdChip3MppPinCount - gMarvellTokenSpaceGuid.PcdChip3MppSel0 - gMarvellTokenSpaceGuid.PcdChip3MppSel1 - gMarvellTokenSpaceGuid.PcdChip3MppSel2 - gMarvellTokenSpaceGuid.PcdChip3MppSel3 - gMarvellTokenSpaceGuid.PcdChip3MppSel4 - gMarvellTokenSpaceGuid.PcdChip3MppSel5 - gMarvellTokenSpaceGuid.PcdChip3MppSel6 - gMarvellTokenSpaceGuid.PcdChip3MppSel7 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppReverseFlag + gMarvellSiliconTokenSpaceGuid.PcdChip3MppBaseAddress + gMarvellSiliconTokenSpaceGuid.PcdChip3MppPinCount + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel0 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel1 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel2 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel3 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel4 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel5 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel6 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel7 =20 - gMarvellTokenSpaceGuid.PcdPciESdhci + gMarvellSiliconTokenSpaceGuid.PcdPciESdhci =20 [BuildOptions] *_*_*_CC_FLAGS =3D -fno-stack-protector diff --git a/Silicon/Marvell/Library/MvGpioLib/MvGpioLib.inf b/Silicon/Marv= ell/Library/MvGpioLib/MvGpioLib.inf index 24db268bc7..0fefbc0156 100644 --- a/Silicon/Marvell/Library/MvGpioLib/MvGpioLib.inf +++ b/Silicon/Marvell/Library/MvGpioLib/MvGpioLib.inf @@ -20,7 +20,7 @@ [Packages] EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf b/Silicon/Ma= rvell/Library/UtmiPhyLib/UtmiPhyLib.inf index f0051f47e1..26fbdf4438 100644 --- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf +++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf @@ -17,7 +17,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] ArmLib diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf b/Silico= n/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf index 2cd13aa2b6..d1e44beecc 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf @@ -33,7 +33,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [FixedPcd] gArmPlatformTokenSpaceGuid.PcdCoreCount diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf b/Silico= n/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf index 0c9fb82682..bc118b9fb3 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf @@ -34,7 +34,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [FixedPcd] gArmPlatformTokenSpaceGuid.PcdCoreCount diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf b/S= ilicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf index 27e7294014..7b040ce7e8 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf @@ -37,7 +37,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [FixedPcd] gArmPlatformTokenSpaceGuid.PcdCoreCount --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#109529): https://edk2.groups.io/g/devel/message/109529 Mute This Topic: https://groups.io/mt/101902578/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 18 14:01:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+109530+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+109530+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=marvell.com ARC-Seal: i=1; a=rsa-sha256; t=1697047736; cv=none; d=zohomail.com; s=zohoarc; b=nFZohulfuIyHRPVl8uOVWPzSFfrbli0wi6V3i89+XG8irxdT8rS8WL/Vd1Xh14h9M+nsp+6gO9YGA5jpvELHh8uHmTJevL5rkexNUFyj05If5OinrSXSlLrN2FI61xoKfA4WNgxihEAudsiWlFNz0rKMn3vRqIFJLeWwLef11HE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697047736; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=JS+eNT7wdLa6MUuJ5cflDnNuzOCIBX4PA3eM7jl8vyI=; b=IFx1NSbi9Dq628QzsIYrBq+BitDPX6p9jB0YzrZSvvUB0DPm9BrQDjMDB+AFZ71Bsl1ZwOT2cHGTFccm8QdcKuBZEf1NxwUz+z5Y2B/n9fJUnm/2nkhgJklgYiLVoukESMGyxrh+G8vbNbdKxyKpqbrMd+nSCep8cHEMnKh9tDI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+109530+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1697047736199455.433075068216; Wed, 11 Oct 2023 11:08:56 -0700 (PDT) Return-Path: DKIM-Signature: a=rsa-sha256; bh=ZiwuEvaiHwdaJ2G6qQnJ+3c9q9lsMoeytemzCD6muCs=; c=relaxed/simple; d=groups.io; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding:Content-Type; s=20140610; t=1697047735; v=1; b=axP3OZ2y44OtSvL7nKLB+2qh66JTrrHvtsukLT56T2OA08UbOjIbVP5XHoLvmzdNqwWM99oW a2lOi9j9PNAre5v4evPQtfpP1lsEfpcuPz1G3BLJczxcBcv012qCIpZruLrR0TyqBe2BC9op4jw 080BNWCnOl6qbxm9nIeVdndU= X-Received: by 127.0.0.2 with SMTP id cqjdYY1788612xs1YjWMdMyC; Wed, 11 Oct 2023 11:08:55 -0700 X-Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.148.174]) by mx.groups.io with SMTP id smtpd.web10.23391.1697046833638835781 for ; Wed, 11 Oct 2023 10:53:53 -0700 X-Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39BFwr8C008613; Wed, 11 Oct 2023 10:53:53 -0700 X-Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3tnxtggg90-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 11 Oct 2023 10:53:53 -0700 X-Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 11 Oct 2023 10:53:51 -0700 X-Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 11 Oct 2023 10:53:51 -0700 X-Received: from MRVL-5Lp9he46Ey.marvell.com (unknown [10.193.12.187]) by maili.marvell.com (Postfix) with ESMTP id 17BA75B6935; Wed, 11 Oct 2023 10:53:51 -0700 (PDT) From: "Narinder Dhillon" To: CC: , , Narinder Dhillon Subject: [edk2-devel] [edk2-platforms PATCH v1 3/4] Platform/Marvell: Use new package name and path Date: Wed, 11 Oct 2023 10:53:22 -0700 Message-ID: <20231011175323.14450-4-ndhillon@marvell.com> In-Reply-To: <20231011175323.14450-1-ndhillon@marvell.com> References: <20231011175323.14450-1-ndhillon@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: dAjq0IJgbuzh51bZML_gfNAWNFIUiYGx X-Proofpoint-GUID: dAjq0IJgbuzh51bZML_gfNAWNFIUiYGx Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ndhillon@marvell.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: VLBjDWtZVtuHTWiv6z4xNvy5x1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1697047738368100019 Content-Type: text/plain; charset="utf-8" From: Narinder Dhillon New Marvell package name, path, and token space needs to be propagated to all dependent files. Signed-off-by: Narinder Dhillon --- .../Marvell/Armada70x0Db/Armada70x0Db.dsc | 108 +++++++------- .../Armada70x0DbBoardDescLib.inf | 2 +- .../NonDiscoverableInitLib.inf | 2 +- .../Marvell/Armada80x0Db/Armada80x0Db.dsc | 133 +++++++++--------- .../Armada80x0DbBoardDescLib.inf | 2 +- .../NonDiscoverableInitLib.inf | 2 +- .../Cn9130DbABoardDescLib.inf | 2 +- .../Cn9132DbABoardDescLib.inf | 2 +- Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc | 100 ++++++------- Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc | 66 ++++----- Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc | 66 ++++----- Platform/Marvell/Cn913xDb/Cn913xDbA.dsc | 8 +- .../NonDiscoverableInitLib.inf | 2 +- 13 files changed, 246 insertions(+), 249 deletions(-) diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marv= ell/Armada70x0Db/Armada70x0Db.dsc index 5df7498f71..362175f59e 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc @@ -48,54 +48,54 @@ ##########################################################################= ###### [PcdsFixedAtBuild.common] #Platform description - gMarvellTokenSpaceGuid.PcdProductPlatformName|"Armada 7040 DB" - gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.5" + gMarvellSiliconTokenSpaceGuid.PcdProductPlatformName|"Armada 7040 DB" + gMarvellSiliconTokenSpaceGuid.PcdProductVersion|"Rev. 1.5" =20 #CP110 count - gMarvellTokenSpaceGuid.PcdMaxCpCount|1 + gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount|1 =20 #MPP - gMarvellTokenSpaceGuid.PcdMppChipCount|2 + gMarvellSiliconTokenSpaceGuid.PcdMppChipCount|2 =20 # APN806-A0 MPP SET - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 - gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20 - gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x3 } + gMarvellSiliconTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE + gMarvellSiliconTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppPinCount|20 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1,= 0x1, 0x1, 0x1, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x3 } =20 # CP110 MPP SET - Router configuration - gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 - gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64 - gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0= x4, 0x4, 0x4, 0x4 } - gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x4, 0x4, 0x0, 0x3, 0x3, 0x3, 0= x3, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x9, 0xA } - gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xA, 0x0, 0x7, 0x0, 0x7, 0x7, 0= x7, 0x2, 0x2, 0x0 } - gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x1, 0x1, 0= x1, 0x1, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= xE, 0xE, 0xE, 0xE } - gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE + gMarvellSiliconTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppPinCount|64 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4,= 0x4, 0x4, 0x4, 0x4, 0x4 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel1|{ 0x4, 0x4, 0x0, 0x3, 0x3,= 0x3, 0x3, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x9, 0xA } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel3|{ 0xA, 0x0, 0x7, 0x0, 0x7,= 0x7, 0x7, 0x2, 0x2, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x1,= 0x1, 0x1, 0x1, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1,= 0x1, 0xE, 0xE, 0xE, 0xE } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0 } =20 # I2C - gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57, 0x60, 0x21 } - gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x50, 0x57 } - gMarvellTokenSpaceGuid.PcdEepromI2cBuses|{ 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000 - gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000 - gMarvellTokenSpaceGuid.PcdI2cBusCount|2 + gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57, 0x60, 0= x21 } + gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x50, 0x57 } + gMarvellSiliconTokenSpaceGuid.PcdEepromI2cBuses|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdI2cClockFrequency|250000000 + gMarvellSiliconTokenSpaceGuid.PcdI2cBaudRate|100000 + gMarvellSiliconTokenSpaceGuid.PcdI2cBusCount|2 =20 #SPI - gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF2700680 - gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000 - gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000 + gMarvellSiliconTokenSpaceGuid.PcdSpiRegBase|0xF2700680 + gMarvellSiliconTokenSpaceGuid.PcdSpiMaxFrequency|10000000 + gMarvellSiliconTokenSpaceGuid.PcdSpiClockFrequency|200000000 =20 - gMarvellTokenSpaceGuid.PcdSpiFlashMode|3 - gMarvellTokenSpaceGuid.PcdSpiFlashCs|0 + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashMode|3 + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashCs|0 =20 #ComPhy - gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } # ComPhy0 # 0: SGMII1 1.25 Gbps # 1: USB3_HOST0 5 Gbps @@ -103,36 +103,36 @@ # 3: SATA1 5 Gbps # 4: USB3_HOST1 5 Gbps # 5: PCIE2 5 Gbps - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_SGMII1), $(CP_USB3_HOS= T0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) } - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(C= P_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) } + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_SGMII1), $(CP_U= SB3_HOST0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) } + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_1_25G), $(CP_5= G), $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) } =20 #UtmiPhy - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1) } + gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTM= I_USB_HOST1) } =20 #MDIO - gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } =20 #PHY - gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + gMarvellSiliconTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE =20 #NET - gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 } - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_1000), $(PHY_SPEED_1000) } - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_SGMI= I), $(PHY_RGMII) } - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 } - gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 } + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000),= $(PHY_SPEED_1000), $(PHY_SPEED_1000) } + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(P= HY_SGMII), $(PHY_RGMII) } + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 } + gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers|{ 0x1 } =20 #PciEmulation - gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1 } - gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciEAhci|{ 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } =20 #RTC - gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000 + gMarvellSiliconTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000 diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada7= 0x0DbBoardDescLib.inf b/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDesc= Lib/Armada70x0DbBoardDescLib.inf index 20294ab43b..75331ae8e4 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBo= ardDescLib.inf +++ b/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBo= ardDescLib.inf @@ -22,7 +22,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib diff --git a/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscov= erableInitLib.inf b/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/No= nDiscoverableInitLib.inf index 946b9fd6d0..64623e33f8 100644 --- a/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscoverableI= nitLib.inf +++ b/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscoverableI= nitLib.inf @@ -29,7 +29,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc b/Platform/Marv= ell/Armada80x0Db/Armada80x0Db.dsc index 2698bd6573..22a0040265 100644 --- a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc +++ b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc @@ -31,9 +31,6 @@ =20 !include MdePkg/MdeLibs.dsc.inc =20 -[Components.common] - Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf - [Components.AARCH64] Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf =20 @@ -48,63 +45,63 @@ ##########################################################################= ###### [PcdsFixedAtBuild.common] #Platform description - gMarvellTokenSpaceGuid.PcdProductPlatformName|"Armada 8040 DB" - gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.4" + gMarvellSiliconTokenSpaceGuid.PcdProductPlatformName|"Armada 8040 DB" + gMarvellSiliconTokenSpaceGuid.PcdProductVersion|"Rev. 1.4" =20 #MPP - gMarvellTokenSpaceGuid.PcdMppChipCount|3 + gMarvellSiliconTokenSpaceGuid.PcdMppChipCount|3 =20 # APN806-A0 MPP SET - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 - gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20 - gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x3 } + gMarvellSiliconTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE + gMarvellSiliconTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppPinCount|20 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1,= 0x1, 0x1, 0x1, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x3 } =20 # CP110 MPP SET - master - gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 - gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64 - gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } - gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } - gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } - gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0xFF, 0x7, 0x0, 0x7, 0= xA, 0xA, 0x2, 0x2, 0x5 } - gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x9, 0x9, 0x8, 0x8, 0x1, 0= x1, 0x1, 0x1, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0xE, 0xE, 0xE, 0xE } - gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE + gMarvellSiliconTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppPinCount|64 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0xFF, 0x7, 0x0, = 0x7, 0xA, 0xA, 0x2, 0x2, 0x5 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel4|{ 0x9, 0x9, 0x8, 0x8, = 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, = 0x1, 0x1, 0xE, 0xE, 0xE, 0xE } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, = 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } =20 # CP110 MPP SET - slave - gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000 - gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64 - gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0= x3, 0x3, 0x3, 0x3, 0x3 } - gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0= x3, 0x3, 0xFF, 0xFF, 0xFF } - gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0x8, 0x9, 0xA } - gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0xA, 0x8, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } - gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } - gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } - gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE + gMarvellSiliconTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppPinCount|64 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel0|{ 0x3, 0x3, 0x3, 0x3, = 0x3, 0x3, 0x3, 0x3, 0x3, 0x3 } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel1|{ 0x3, 0x3, 0x3, 0x3, = 0x3, 0x3, 0x3, 0xFF, 0xFF, 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, = 0xFF, 0xFF, 0xFF, 0x8, 0x9, 0xA } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel3|{ 0xA, 0x8, 0xFF, 0xFF, = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, = 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } =20 # I2C - gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57, 0x50, 0x57, 0x= 21, 0x25 } - gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x1, 0x1, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1, 0x0, 0x0, 0x= 1 } - gMarvellTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x50, 0x57, 0x50, 0x57 } - gMarvellTokenSpaceGuid.PcdEepromI2cBuses|{ 0x0, 0x0, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000 - gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000 - gMarvellTokenSpaceGuid.PcdI2cBusCount|2 + gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57, 0x50, 0= x57, 0x21, 0x25 } + gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x1, 0x1, 0x0= , 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1, 0x0, = 0x0, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x50, 0x57, 0x50, = 0x57 } + gMarvellSiliconTokenSpaceGuid.PcdEepromI2cBuses|{ 0x0, 0x0, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdI2cClockFrequency|250000000 + gMarvellSiliconTokenSpaceGuid.PcdI2cBaudRate|100000 + gMarvellSiliconTokenSpaceGuid.PcdI2cBusCount|2 =20 #SPI - gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF4700680 - gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000 - gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000 + gMarvellSiliconTokenSpaceGuid.PcdSpiRegBase|0xF4700680 + gMarvellSiliconTokenSpaceGuid.PcdSpiMaxFrequency|10000000 + gMarvellSiliconTokenSpaceGuid.PcdSpiClockFrequency|200000000 =20 - gMarvellTokenSpaceGuid.PcdSpiFlashMode|3 - gMarvellTokenSpaceGuid.PcdSpiFlashCs|0 + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashMode|3 + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashCs|0 =20 #ComPhy - gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 } # ComPhy0 # 0: PCIE0 5 Gbps # 1: SATA0 5 Gbps @@ -112,8 +109,8 @@ # 3: SATA1 5 Gbps # 4: USB_HOST1 5 Gbps # 5: PCIE2 5 Gbps - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_SATA0), $= (CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) } - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_1= 0_3125G), $(CP_5G), $(CP_5G), $(CP_5G) } + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_SA= TA0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) } + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G),= $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) } # ComPhy1 # 0: PCIE0 5 Gbps # 1: SATA0 5 Gbps @@ -121,36 +118,36 @@ # 3: SATA1 5 Gbps # 4: PCIE1 5 Gbps # 5: PCIE2 5 Gbps - gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_SATA2), $= (CP_SFI), $(CP_SATA3), $(CP_PCIE1), $(CP_PCIE2) } - gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_1= 0_3125G), $(CP_5G), $(CP_5G), $(CP_5G) } + gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_SA= TA2), $(CP_SFI), $(CP_SATA3), $(CP_PCIE1), $(CP_PCIE2) } + gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G),= $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) } =20 #UtmiPhy - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1, 0x0 } - gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) } + gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1,= 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTM= I_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) } =20 #MDIO - gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x1 } =20 #PHY - gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x1, 0x0 } - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + gMarvellSiliconTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPhySmiAddresses|{ 0x1, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE =20 #NET - gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x3, 0x0, 0x2 } - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_1000), $(PHY_SPEED_10000), $(PHY_SPEED_1000) } - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMI= I), $(PHY_SFI), $(PHY_RGMII) } - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0x1 } - gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x2, 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x3, 0x0, 0x2 } + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0= x0 } + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000),= $(PHY_SPEED_1000), $(PHY_SPEED_10000), $(PHY_SPEED_1000) } + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(P= HY_RGMII), $(PHY_SFI), $(PHY_RGMII) } + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x1, 0x1= } + gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x2, 0x0, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 } =20 #PciEmulation - gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 } - gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } =20 #RTC - gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF4284000 + gMarvellSiliconTokenSpaceGuid.PcdRtcBaseAddress|0xF4284000 diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada8= 0x0DbBoardDescLib.inf b/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDesc= Lib/Armada80x0DbBoardDescLib.inf index 07ee65dfa4..302e0f832f 100644 --- a/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBo= ardDescLib.inf +++ b/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBo= ardDescLib.inf @@ -22,7 +22,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib diff --git a/Platform/Marvell/Armada80x0Db/NonDiscoverableInitLib/NonDiscov= erableInitLib.inf b/Platform/Marvell/Armada80x0Db/NonDiscoverableInitLib/No= nDiscoverableInitLib.inf index fb303f3d89..261f2114c4 100644 --- a/Platform/Marvell/Armada80x0Db/NonDiscoverableInitLib/NonDiscoverableI= nitLib.inf +++ b/Platform/Marvell/Armada80x0Db/NonDiscoverableInitLib/NonDiscoverableI= nitLib.inf @@ -30,7 +30,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDe= scLib.inf b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDes= cLib.inf index dfbdc84448..c93b3077c7 100644 --- a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.i= nf +++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.i= nf @@ -22,7 +22,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDe= scLib.inf b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDes= cLib.inf index 27a0214622..e0c84138b7 100644 --- a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.i= nf +++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.i= nf @@ -22,7 +22,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib diff --git a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc b/Platform/Marvell= /Cn913xDb/Cn9130DbA.dsc.inc index e4d4c8e073..61bfdc8eb6 100644 --- a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc +++ b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc @@ -14,47 +14,47 @@ ##########################################################################= ###### [PcdsFixedAtBuild.common] # CP115 count - gMarvellTokenSpaceGuid.PcdMaxCpCount|1 + gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount|1 =20 # MPP - gMarvellTokenSpaceGuid.PcdMppChipCount|2 + gMarvellSiliconTokenSpaceGuid.PcdMppChipCount|2 =20 # APN807 MPP - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 - gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20 - gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x1, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x3 } + gMarvellSiliconTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE + gMarvellSiliconTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppPinCount|20 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1,= 0x1, 0x1, 0x1, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x1, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x3 } =20 # CP115 #0 MPP - gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 - gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64 - gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0= x3, 0x3, 0x3, 0x3 } - gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x0, 0x3, 0x3, 0x3, 0= x3, 0x1, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x3, 0xA } - gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xA, 0x3, 0x7, 0x6, 0x7, 0x2, 0= x2, 0x2, 0x2, 0x1 } - gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= xE, 0xE, 0xE, 0xE } - gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE + gMarvellSiliconTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppPinCount|64 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3,= 0x3, 0x3, 0x3, 0x3, 0x3 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x0, 0x3, 0x3,= 0x3, 0x3, 0x1, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel2|{ 0x1, 0x1, 0x1, 0x1, 0x1,= 0x1, 0x1, 0x1, 0x3, 0xA } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel3|{ 0xA, 0x3, 0x7, 0x6, 0x7,= 0x2, 0x2, 0x2, 0x2, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel4|{ 0x1, 0x1, 0x1, 0x1, 0x1,= 0x1, 0x1, 0x1, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1,= 0x1, 0xE, 0xE, 0xE, 0xE } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0 } =20 # I2C - gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x21 } - gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 } - gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000 - gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000 + gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x21 } + gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdI2cClockFrequency|250000000 + gMarvellSiliconTokenSpaceGuid.PcdI2cBaudRate|100000 =20 # SPI - gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF2700680 - gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000 - gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000 + gMarvellSiliconTokenSpaceGuid.PcdSpiRegBase|0xF2700680 + gMarvellSiliconTokenSpaceGuid.PcdSpiMaxFrequency|10000000 + gMarvellSiliconTokenSpaceGuid.PcdSpiClockFrequency|200000000 =20 - gMarvellTokenSpaceGuid.PcdSpiFlashMode|3 - gMarvellTokenSpaceGuid.PcdSpiFlashCs|0 + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashMode|3 + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashCs|0 =20 # ComPhy - gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } # ComPhy0 # 0: PCIE0 5 Gbps # 1: PCIE0 5 Gbps @@ -62,39 +62,39 @@ # 3: PCIE0 5 Gbps # 4: SFI 10.31 Gbps # 5: SATA1 5 Gbps - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $= (CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)} - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5= G), $(CP_5G), $(CP_10_3125G), $(CP_5G) } + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PC= IE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)} + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G),= $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) } =20 # UtmiPhy - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1) } + gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTM= I_USB_HOST1) } =20 # MDIO - gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } =20 # PHY - gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + gMarvellSiliconTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE =20 # NET - gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 } - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_1000), $(PHY_SPEED_1000) } - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMI= I), $(PHY_RGMII) } - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 } - gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 } + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000),= $(PHY_SPEED_1000), $(PHY_SPEED_1000) } + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(P= HY_RGMII), $(PHY_RGMII) } + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 } + gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers|{ 0x1 } =20 # NonDiscoverableDevices - gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1 } - gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciEAhci|{ 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } =20 # RTC - gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000 + gMarvellSiliconTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000 =20 # Variable store - gMarvellTokenSpaceGuid.PcdSpiMemoryMapped|FALSE + gMarvellSiliconTokenSpaceGuid.PcdSpiMemoryMapped|FALSE diff --git a/Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc b/Platform/Marvell= /Cn913xDb/Cn9131DbA.dsc.inc index 7235b9f86e..8166f441b7 100644 --- a/Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc +++ b/Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc @@ -14,25 +14,25 @@ ##########################################################################= ###### [PcdsFixedAtBuild.common] # CP115 count - gMarvellTokenSpaceGuid.PcdMaxCpCount|2 + gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount|2 =20 # MPP - gMarvellTokenSpaceGuid.PcdMppChipCount|3 + gMarvellSiliconTokenSpaceGuid.PcdMppChipCount|3 =20 # CP115 #1 MPP - gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000 - gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64 - gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x0, 0x3, 0x3, 0x3, 0= x3, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x9, 0x0 } - gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0= x7, 0x2, 0x2, 0x0 } - gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE + gMarvellSiliconTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppPinCount|64 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x0, 0x3, 0x3,= 0x3, 0x3, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x9, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0x0, 0x0, 0x0,= 0x7, 0x7, 0x2, 0x2, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel5|{ 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel6|{ 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0 } =20 # ComPhy - gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 } # ComPhy1 # 0: PCIE0 5 Gbps # 1: PCIE0 5 Gbps @@ -40,33 +40,33 @@ # 3: USB3_HOST1 5 Gbps # 4: SFI 10.31 Gbps # 5: SATA1 5 Gbps - gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $= (CP_UNCONNECTED), $(CP_USB3_HOST1), $(CP_SFI), $(CP_SATA1)} - gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_D= EFAULT), $(CP_5G), $(CP_10_3125G), $(CP_5G) } + gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_PC= IE0), $(CP_UNCONNECTED), $(CP_USB3_HOST1), $(CP_SFI), $(CP_SATA1)} + gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G),= $(CP_DEFAULT), $(CP_5G), $(CP_10_3125G), $(CP_5G) } =20 # UtmiPhy - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) } + gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0,= 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTM= I_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) } =20 # MDIO - gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } =20 # PHY - gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + gMarvellSiliconTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE =20 # NET - gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0 } - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_1000), $(PHY_SPEED_1000), $(PHY_SPEED_10000) } - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMI= I), $(PHY_RGMII), $(PHY_SFI) } - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1, 0xFF } - gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0 } - gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0= x0 } + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000),= $(PHY_SPEED_1000), $(PHY_SPEED_1000), $(PHY_SPEED_10000) } + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(P= HY_RGMII), $(PHY_RGMII), $(PHY_SFI) } + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1, 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1= } + gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 } =20 # NonDiscoverableDevices - gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } diff --git a/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc b/Platform/Marvell= /Cn913xDb/Cn9132DbA.dsc.inc index a0b90fac1c..909f0fbc78 100644 --- a/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc +++ b/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc @@ -14,25 +14,25 @@ ##########################################################################= ###### [PcdsFixedAtBuild.common] # CP115 count - gMarvellTokenSpaceGuid.PcdMaxCpCount|3 + gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount|3 =20 # MPP - gMarvellTokenSpaceGuid.PcdMppChipCount|4 + gMarvellSiliconTokenSpaceGuid.PcdMppChipCount|4 =20 # CP115 #2 MPP - gMarvellTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip3MppBaseAddress|0xF6440000 - gMarvellTokenSpaceGuid.PcdChip3MppPinCount|64 - gMarvellTokenSpaceGuid.PcdChip3MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdChip3MppSel1|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdChip3MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x9, 0x9, 0x0 } - gMarvellTokenSpaceGuid.PcdChip3MppSel3|{ 0x0, 0x0, 0x8, 0x0, 0x8, 0x0, 0= x0, 0x2, 0x2, 0x0 } - gMarvellTokenSpaceGuid.PcdChip3MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdChip3MppSel5|{ 0x0, 0x0, 0x0, 0x0, 0xA, 0xB, 0= xE, 0xE, 0xE, 0xE } - gMarvellTokenSpaceGuid.PcdChip3MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE + gMarvellSiliconTokenSpaceGuid.PcdChip3MppBaseAddress|0xF6440000 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppPinCount|64 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel1|{ 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x9, 0x9, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel3|{ 0x0, 0x0, 0x8, 0x0, 0x8,= 0x0, 0x0, 0x2, 0x2, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel5|{ 0x0, 0x0, 0x0, 0x0, 0xA,= 0xB, 0xE, 0xE, 0xE, 0xE } + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0 } =20 # ComPhy - gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1, 0x1 } # ComPhy1 # 0: PCIE0 5 Gbps # 1: PCIE0 5 Gbps @@ -40,33 +40,33 @@ # 3: USB3_HOST1 5 Gbps # 4: SFI 10.31 Gbps # 5: PCIE2 5 Gbps - gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $= (CP_SATA0), $(CP_USB3_HOST1), $(CP_SFI), $(CP_PCIE2)} - gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5= G), $(CP_5G), $(CP_10_3125G), $(CP_5G) } + gMarvellSiliconTokenSpaceGuid.PcdChip2ComPhyTypes|{ $(CP_PCIE0), $(CP_PC= IE0), $(CP_SATA0), $(CP_USB3_HOST1), $(CP_SFI), $(CP_PCIE2)} + gMarvellSiliconTokenSpaceGuid.PcdChip2ComPhySpeeds|{ $(CP_5G), $(CP_5G),= $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) } =20 # UtmiPhy - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1, 0= x1, 0x1 } - gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_= HOST1) } + gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0,= 0x1, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTM= I_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UT= MI_USB_HOST1) } =20 # MDIO - gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } =20 # PHY - gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + gMarvellSiliconTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE =20 # NET - gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0, 0x0= } - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_1000), $(PHY_SPEED_1000), $(PHY_SPEED_10000), $(PHY_SPEED_10000) } - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMI= I), $(PHY_RGMII), $(PHY_SFI), $(PHY_SFI) } - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1, 0xFF, 0xFF } - gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1, 0x2 } - gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0, 0x0= } + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0= x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000),= $(PHY_SPEED_1000), $(PHY_SPEED_1000), $(PHY_SPEED_10000), $(PHY_SPEED_1000= 0) } + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(P= HY_RGMII), $(PHY_RGMII), $(PHY_SFI), $(PHY_SFI) } + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1, 0xFF, 0= xFF } + gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1= , 0x2 } + gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1, 0x1 } =20 # NonDiscoverableDevices - gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1, 0x0, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1= } + gMarvellSiliconTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1, 0x0, 0x1 } diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc b/Platform/Marvell/Cn9= 13xDb/Cn913xDbA.dsc index ff91d10142..dc18e94dbc 100644 --- a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc +++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc @@ -69,10 +69,10 @@ [PcdsFixedAtBuild.common] #Platform description !if $(CN9130) - gMarvellTokenSpaceGuid.PcdProductPlatformName|"CN9130 DB-A" + gMarvellSiliconTokenSpaceGuid.PcdProductPlatformName|"CN9130 DB-A" !elseif $(CN9131) - gMarvellTokenSpaceGuid.PcdProductPlatformName|"CN9131 DB-A" + gMarvellSiliconTokenSpaceGuid.PcdProductPlatformName|"CN9131 DB-A" !elseif $(CN9132) - gMarvellTokenSpaceGuid.PcdProductPlatformName|"CN9132 DB-A" + gMarvellSiliconTokenSpaceGuid.PcdProductPlatformName|"CN9132 DB-A" !endif - gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.1" + gMarvellSiliconTokenSpaceGuid.PcdProductVersion|"Rev. 1.1" diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverab= leInitLib.inf b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscove= rableInitLib.inf index f7cfb3684d..e4f0cf6bd6 100644 --- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.inf +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitL= ib.inf @@ -23,7 +23,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#109530): https://edk2.groups.io/g/devel/message/109530 Mute This Topic: https://groups.io/mt/101902579/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 18 14:01:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+109531+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+109531+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=marvell.com ARC-Seal: i=1; a=rsa-sha256; t=1697047735; cv=none; d=zohomail.com; s=zohoarc; b=ictc6gM+zNIXyIwBSggBzfEYdNo2c21SrvqP8PzTFLMqaSKzuQIn6bhM9yBI/Er2UWzSOwi/FlBQJXgl96ymk/ddZ4FTqkO0Zj9BKKg8AL0nhcFT5YW8LiTr5m0BwVU9Evgrs4L72ozpD5Bq7WfvwgJEfY4RiqR0MIBZlbAT4l0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697047735; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=aDZvhFogxf7+5DhOZ38EbhdY+RHmlwpYiHcC7awUs/c=; b=AYSqhVaTzBk7WRJW5O3PvAGh2DFHL45BnsLNBJvl8eQbNQVBfWoVWZJW8PZCPHTuIu112D+nzia/Z7jgZQDiL2j2Hew66ystCPHUo8PoUuwi2obDCPMdGDh/zoZWHPvv3sv/7IPkyCEvu79mAjX+L7h6rjUW0RyVFDXVLGxAb8s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+109531+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1697047735786410.35736973240466; Wed, 11 Oct 2023 11:08:55 -0700 (PDT) Return-Path: DKIM-Signature: a=rsa-sha256; bh=tAvGQsZj4tNZlYWRqKAp16J9iW2jy55Wf9ZEQEfBDSc=; c=relaxed/simple; d=groups.io; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding:Content-Type; s=20140610; t=1697047735; v=1; b=uH03XA+y9RpPwzT5tj6ES0spXvhLf6jMbC3Xs/ESF6fBXmtMglUJQpieB0cBQU8rGFyosIxz nHW4Pi48QYTGuzeNlFuu6v7NIeFumOQxEhkfr8QoqtCr4RTpa9uHZAtB3mdgsUlqcHWlrTCVbzM Jj4OCh3fuq5h0ahbZ9JP1EZw= X-Received: by 127.0.0.2 with SMTP id P34LYY1788612xs2K8spaQLU; Wed, 11 Oct 2023 11:08:55 -0700 X-Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.148.174]) by mx.groups.io with SMTP id smtpd.web11.23486.1697046834693086907 for ; Wed, 11 Oct 2023 10:53:54 -0700 X-Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39BFvwpX006320; Wed, 11 Oct 2023 10:53:54 -0700 X-Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3tnxtggg95-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 11 Oct 2023 10:53:54 -0700 X-Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 11 Oct 2023 10:53:52 -0700 X-Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 11 Oct 2023 10:53:52 -0700 X-Received: from MRVL-5Lp9he46Ey.marvell.com (unknown [10.193.12.187]) by maili.marvell.com (Postfix) with ESMTP id 4BF5B5B6934; Wed, 11 Oct 2023 10:53:52 -0700 (PDT) From: "Narinder Dhillon" To: CC: , , Narinder Dhillon Subject: [edk2-devel] [edk2-platforms PATCH v1 4/4] Platform/SolidRun: Use new package name and path Date: Wed, 11 Oct 2023 10:53:23 -0700 Message-ID: <20231011175323.14450-5-ndhillon@marvell.com> In-Reply-To: <20231011175323.14450-1-ndhillon@marvell.com> References: <20231011175323.14450-1-ndhillon@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: NIAcB6idqz7shqVcaXuy39cX5jzSL8Up X-Proofpoint-GUID: NIAcB6idqz7shqVcaXuy39cX5jzSL8Up Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ndhillon@marvell.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: s69RBl1dqaq6RpAqsCZ0nHycx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1697047736345100008 Content-Type: text/plain; charset="utf-8" From: Narinder Dhillon New Marvell package name, path, and token space needs to be propagated to all dependent files. Signed-off-by: Narinder Dhillon --- .../Armada80x0McBin/Armada80x0McBin.dsc | 116 +++++++++--------- .../Armada80x0McBinBoardDescLib.inf | 2 +- .../NonDiscoverableInitLib.inf | 2 +- .../BoardDescriptionLib.inf | 2 +- .../Cn913xCEx7Eval/Cn9130Eval.dsc.inc | 40 +++--- .../Cn913xCEx7Eval/Cn9131Eval.dsc.inc | 56 ++++----- .../Cn913xCEx7Eval/Cn9132Eval.dsc.inc | 56 ++++----- .../Cn913xCEx7Eval/Cn913xCEx7.dsc.inc | 60 ++++----- .../Cn913xCEx7Eval/Cn913xCEx7Eval.dsc | 6 +- .../NonDiscoverableInitLib.inf | 2 +- 10 files changed, 171 insertions(+), 171 deletions(-) diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc b/Platfo= rm/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc index 9196300572..469ccc7083 100644 --- a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc +++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc @@ -48,54 +48,54 @@ ##########################################################################= ###### [PcdsFixedAtBuild.common] #Platform description - gMarvellTokenSpaceGuid.PcdProductManufacturer|"SolidRun" - gMarvellTokenSpaceGuid.PcdProductPlatformName|"Armada 8040 MacchiatoBin" - gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.3" + gMarvellSiliconTokenSpaceGuid.PcdProductManufacturer|"SolidRun" + gMarvellSiliconTokenSpaceGuid.PcdProductPlatformName|"Armada 8040 Macchi= atoBin" + gMarvellSiliconTokenSpaceGuid.PcdProductVersion|"Rev. 1.3" =20 #MPP - gMarvellTokenSpaceGuid.PcdMppChipCount|3 + gMarvellSiliconTokenSpaceGuid.PcdMppChipCount|3 =20 # APN806-A0 MPP SET - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 - gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20 - gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x3 } + gMarvellSiliconTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE + gMarvellSiliconTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppPinCount|20 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1,= 0x1, 0x1, 0x1, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x3 } =20 # CP110 MPP SET - master - gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 - gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64 - gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } - gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } - gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } - gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0x0, 0x7, 0xA, 0x7, 0x2, = 0x2, 0x2, 0x2, 0xA } - gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x7, 0x7, 0x8, 0x8, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x0, 0x0, 0x9, 0x0, 0x0, 0x0, 0= xE, 0xE, 0xE, 0xE } - gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE + gMarvellSiliconTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppPinCount|64 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0x0, 0x7, 0xA, 0x7= , 0x2, 0x2, 0x2, 0x2, 0xA } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel4|{ 0x7, 0x7, 0x8, 0x8, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel5|{ 0x0, 0x0, 0x9, 0x0, 0x0,= 0x0, 0xE, 0xE, 0xE, 0xE } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0 } =20 # CP110 MPP SET - slave - gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000 - gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64 - gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0= x8, 0x8, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x3, 0x3, 0x3, 0x3, 0= x3, 0xFF, 0xFF, 0xFF } - gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0x0, 0x= FF, 0x0, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xF= F, 0xFF, 0xFF, 0xFF, 0xFF } - gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } - gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } - gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0x0= , 0x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE + gMarvellSiliconTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppPinCount|64 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4,= 0x4, 0x8, 0x8, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x3, 0x3, 0x3,= 0x3, 0x3, 0xFF, 0xFF, 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, = 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0xFF, 0xFF, 0x= FF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0= x0, 0x0, 0x0, 0x0, 0x0, 0x0 } =20 #SPI - gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF4700680 - gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000 - gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000 + gMarvellSiliconTokenSpaceGuid.PcdSpiRegBase|0xF4700680 + gMarvellSiliconTokenSpaceGuid.PcdSpiMaxFrequency|10000000 + gMarvellSiliconTokenSpaceGuid.PcdSpiClockFrequency|200000000 =20 - gMarvellTokenSpaceGuid.PcdSpiFlashMode|3 - gMarvellTokenSpaceGuid.PcdSpiFlashCs|0 + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashMode|3 + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashCs|0 =20 #ComPhy - gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 } # ComPhy0 # 0: PCIE0 5 Gbps # 1: PCIE0 5 Gbps @@ -103,8 +103,8 @@ # 3: PCIE0 5 Gbps # 4: SFI 10.31 Gbps # 5: SATA1 5 Gbps - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $= (CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)} - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5= G), $(CP_5G), $(CP_10_3125G), $(CP_5G) } + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PC= IE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)} + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G),= $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) } # ComPhy1 # 0: SGMII1 1.25 Gbps # 1: SATA0 5 Gbps @@ -112,36 +112,36 @@ # 3: SATA1 5 Gbps # 4: SFI 10.31 Gbps # 5: SGMII2 3.125 Gbps - gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_SGMII1), $(CP_SATA2), = $(CP_USB3_HOST0), $(CP_SATA3), $(CP_SFI), $(CP_SGMII2) } - gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(C= P_5G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) } + gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_SGMII1), $(CP_S= ATA2), $(CP_USB3_HOST0), $(CP_SATA3), $(CP_SFI), $(CP_SGMII2) } + gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_1_25G), $(CP_5= G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) } =20 #UtmiPhy - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1, 0x0 } - gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) } + gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1,= 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTM= I_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) } =20 #MDIO - gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } =20 #PHY - gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 } - gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 } - gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 } - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + gMarvellSiliconTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE =20 #NET - gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x0, 0x2, 0x3 } - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500) } - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_SFI)= , $(PHY_SGMII), $(PHY_SGMII) } - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0xFF, 0x0, 0xFF } - gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x1, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x0, 0x1, 0x2 } - gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x0, 0x2, 0x3 } + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0= x0 } + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000),= $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500) } + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(P= HY_SFI), $(PHY_SGMII), $(PHY_SGMII) } + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0xFF, 0x0, 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x1, 0x1, 0x1= } + gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x0, 0x1, 0x2 } + gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 } =20 #PciEmulation - gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 } - gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } =20 #RTC - gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF4284000 + gMarvellSiliconTokenSpaceGuid.PcdRtcBaseAddress|0xF4284000 diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/= Armada80x0McBinBoardDescLib.inf b/Platform/SolidRun/Armada80x0McBin/Armada8= 0x0McBinBoardDescLib/Armada80x0McBinBoardDescLib.inf index 4ebe4c3883..3fbfd9f5c7 100644 --- a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada8= 0x0McBinBoardDescLib.inf +++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada8= 0x0McBinBoardDescLib.inf @@ -22,7 +22,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib diff --git a/Platform/SolidRun/Armada80x0McBin/NonDiscoverableInitLib/NonDi= scoverableInitLib.inf b/Platform/SolidRun/Armada80x0McBin/NonDiscoverableIn= itLib/NonDiscoverableInitLib.inf index 469a0323ca..824e10f0b2 100644 --- a/Platform/SolidRun/Armada80x0McBin/NonDiscoverableInitLib/NonDiscovera= bleInitLib.inf +++ b/Platform/SolidRun/Armada80x0McBin/NonDiscoverableInitLib/NonDiscovera= bleInitLib.inf @@ -30,7 +30,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib diff --git a/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDesc= riptionLib.inf b/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/Board= DescriptionLib.inf index ea13ff7ad7..00bf3ff550 100644 --- a/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescription= Lib.inf +++ b/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescription= Lib.inf @@ -23,7 +23,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc b/Platform= /SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc index ad0983087d..0b02740242 100644 --- a/Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc +++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc @@ -15,7 +15,7 @@ ##########################################################################= ###### [PcdsFixedAtBuild.common] # ComPhy - gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } # ComPhy0 # 0: PCIE0 5 Gbps # 1: PCIE0 5 Gbps @@ -23,32 +23,32 @@ # 3: PCIE0 5 Gbps # 4: SFI 10.31 Gbps # 5: SGMII2 3.125 Gbps - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $= (CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SGMII2)} - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5= G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) } + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PC= IE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SGMII2)} + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G),= $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) } =20 # UtmiPhy - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1) } + gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTM= I_USB_HOST1) } =20 # MDIO - gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1 } =20 # PHY - gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 } - gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 } - gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 } - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + gMarvellSiliconTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE =20 # NET - gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 } - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_1000), $(PHY_SPEED_2500) } - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMI= I), $(PHY_SGMII) } - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF } - gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 } - gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 } + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000),= $(PHY_SPEED_1000), $(PHY_SPEED_2500) } + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(P= HY_RGMII), $(PHY_SGMII) } + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 } + gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers|{ 0x1 } =20 # NonDiscoverableDevices - gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc b/Platform= /SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc index c6b0cefa8d..e9a6e34a32 100644 --- a/Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc +++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc @@ -15,25 +15,25 @@ ##########################################################################= ###### [PcdsFixedAtBuild.common] # CP115 count - gMarvellTokenSpaceGuid.PcdMaxCpCount|2 + gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount|2 =20 # MPP - gMarvellTokenSpaceGuid.PcdMppChipCount|3 + gMarvellSiliconTokenSpaceGuid.PcdMppChipCount|3 =20 # CP115 #1 MPP - gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000 - gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64 - gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x0, 0x3, 0x3, 0x3, 0= x3, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x7, 0x7 } - gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x7, 0x0, 0x0, 0x0, 0x2, 0x2, 0= x2, 0x8, 0x8, 0x9 } - gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0x0, 0x0, 0x2, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE + gMarvellSiliconTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppPinCount|64 + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x0, 0x3, 0x3,= 0x3, 0x3, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x7, 0x7 } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel3|{ 0x7, 0x0, 0x0, 0x0, 0x2,= 0x2, 0x2, 0x8, 0x8, 0x9 } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel5|{ 0x0, 0x0, 0x2, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel6|{ 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0 } =20 # ComPhy - gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 } # ComPhy1 # 0: PCIE0 5 Gbps # 1: PCIE0 5 Gbps @@ -41,24 +41,24 @@ # 3: SATA1 5 Gbps # 4: PCIE1 5 Gbps # 5: PCIE2 5 Gbps - gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $= (CP_SFI), $(CP_SATA1), $(CP_PCIE1), $(CP_PCIE2)} - gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5= _15625G), $(CP_5G), $(CP_5G), $(CP_5G) } + gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_PC= IE0), $(CP_SFI), $(CP_SATA1), $(CP_PCIE1), $(CP_PCIE2)} + gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G),= $(CP_5_15625G), $(CP_5G), $(CP_5G), $(CP_5G) } =20 # UtmiPhy - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) } + gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0,= 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTM= I_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) } =20 # NET - gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0 } - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1, 0x0 } - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_1000), $(PHY_SPEED_2500), $(PHY_SPEED_10000) } - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMI= I), $(PHY_SGMII), $(PHY_SFI) } - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0xFF } - gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0 } - gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1, 0= x0 } + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000),= $(PHY_SPEED_1000), $(PHY_SPEED_2500), $(PHY_SPEED_10000) } + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(P= HY_RGMII), $(PHY_SGMII), $(PHY_SFI) } + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1= } + gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 } =20 # NonDiscoverableDevices - gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciEAhci|{ 0x0, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc b/Platform= /SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc index 34f9a3f2fb..74695221c4 100644 --- a/Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc +++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc @@ -15,25 +15,25 @@ ##########################################################################= ###### [PcdsFixedAtBuild.common] # CP115 count - gMarvellTokenSpaceGuid.PcdMaxCpCount|3 + gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount|3 =20 # MPP - gMarvellTokenSpaceGuid.PcdMppChipCount|4 + gMarvellSiliconTokenSpaceGuid.PcdMppChipCount|4 =20 # CP115 #2 MPP - gMarvellTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip3MppBaseAddress|0xF6440000 - gMarvellTokenSpaceGuid.PcdChip3MppPinCount|64 - gMarvellTokenSpaceGuid.PcdChip3MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdChip3MppSel1|{ 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } - gMarvellTokenSpaceGuid.PcdChip3MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0= xFF, 0xFF, 0x0, 0x7, 0x7 } - gMarvellTokenSpaceGuid.PcdChip3MppSel3|{ 0x7, 0x0, 0x0, 0xFF, 0xFF, 0= x2, 0x2, 0x8, 0x8, 0xFF } - gMarvellTokenSpaceGuid.PcdChip3MppSel4|{ 0x0, 0xFF, 0x0, 0x0, 0xFF, 0= xFF, 0xFF, 0xFF, 0xFF, 0xFF } - gMarvellTokenSpaceGuid.PcdChip3MppSel5|{ 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0= x0, 0x0, 0xFF, 0xFF, 0xFF } - gMarvellTokenSpaceGuid.PcdChip3MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE + gMarvellSiliconTokenSpaceGuid.PcdChip3MppBaseAddress|0xF6440000 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppPinCount|64 + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel0|{ 0x0, 0x0, 0x0, 0x0, = 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel1|{ 0x0, 0x0, 0xFF, 0xFF, = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, = 0xFF, 0xFF, 0xFF, 0x0, 0x7, 0x7 } + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel3|{ 0x7, 0x0, 0x0, 0xFF, = 0xFF, 0x2, 0x2, 0x8, 0x8, 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel4|{ 0x0, 0xFF, 0x0, 0x0, = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel5|{ 0x0, 0xFF, 0xFF, 0xFF, = 0xFF, 0x0, 0x0, 0xFF, 0xFF, 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, = 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } =20 # ComPhy - gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1, 0x1 } # ComPhy2 # 0: PCIE0 5 Gbps # 1: USB3_HOST0 5 Gbps @@ -41,24 +41,24 @@ # 3: SATA1 5 Gbps # 4: PCIE1 5 Gbps # 5: PCIE2 5 Gbps - gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes|{ $(CP_PCIE0), $(CP_USB3_HOST= 0), $(CP_SFI), $(CP_SATA1), $(CP_PCIE1), $(CP_PCIE2)} - gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5= _15625G), $(CP_5G), $(CP_5G), $(CP_5G) } + gMarvellSiliconTokenSpaceGuid.PcdChip2ComPhyTypes|{ $(CP_PCIE0), $(CP_US= B3_HOST0), $(CP_SFI), $(CP_SATA1), $(CP_PCIE1), $(CP_PCIE2)} + gMarvellSiliconTokenSpaceGuid.PcdChip2ComPhySpeeds|{ $(CP_5G), $(CP_5G),= $(CP_5_15625G), $(CP_5G), $(CP_5G), $(CP_5G) } =20 # UtmiPhy - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1, 0= x1, 0x1 } - gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H= OST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_= HOST1) } + gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0,= 0x1, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTM= I_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UT= MI_USB_HOST1) } =20 # NET - gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1, 0x0, 0x0= } - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_= SPEED_1000), $(PHY_SPEED_2500), $(PHY_SPEED_10000), $(PHY_SPEED_10000) } - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMI= I), $(PHY_SGMII), $(PHY_SFI), $(PHY_SFI) } - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0xFF, 0xFF } - gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1, 0x2 } - gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0, 0x0= } + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1, 0= x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000),= $(PHY_SPEED_1000), $(PHY_SPEED_2500), $(PHY_SPEED_10000), $(PHY_SPEED_1000= 0) } + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(P= HY_RGMII), $(PHY_SGMII), $(PHY_SFI), $(PHY_SFI) } + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0xFF, = 0xFF } + gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1= , 0x2 } + gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1, 0x1 } =20 # NonDiscoverableDevices - gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x0, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1= } + gMarvellSiliconTokenSpaceGuid.PcdPciEAhci|{ 0x0, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc b/Platform= /SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc index 17463c09c6..31e553ee41 100644 --- a/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc +++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc @@ -15,53 +15,53 @@ ##########################################################################= ###### [PcdsFixedAtBuild.common] # CP115 count - gMarvellTokenSpaceGuid.PcdMaxCpCount|1 + gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount|1 =20 # MPP - gMarvellTokenSpaceGuid.PcdMppChipCount|2 + gMarvellSiliconTokenSpaceGuid.PcdMppChipCount|2 =20 # APN807 MPP - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 - gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20 - gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0= x1, 0x1, 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x1, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x3 } + gMarvellSiliconTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE + gMarvellSiliconTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppPinCount|20 + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1,= 0x1, 0x1, 0x1, 0x1, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x1, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x3 } =20 # CP115 #0 MPP - gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 - gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64 - gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0= x3, 0x3, 0x3, 0x3 } - gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0= x3, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x7, 0x7 } - gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0x7, 0x0, 0x0, 0x0, 0x0, 0x2, 0= x2, 0x2, 0x2, 0x0 } - gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x8, 0x8, 0x8, 0x8, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x6, 0x6, 0x2, 0x0, 0x2, 0xB, 0= xE, 0xE, 0xE, 0xE } - gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE + gMarvellSiliconTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppPinCount|64 + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3,= 0x3, 0x3, 0x3, 0x3, 0x3 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x3, 0x3, 0x3,= 0x3, 0x3, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x7, 0x7 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel3|{ 0x7, 0x0, 0x0, 0x0, 0x0,= 0x2, 0x2, 0x2, 0x2, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel4|{ 0x8, 0x8, 0x8, 0x8, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel5|{ 0x6, 0x6, 0x2, 0x0, 0x2,= 0xB, 0xE, 0xE, 0xE, 0xE } + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0,= 0x0, 0x0, 0x0, 0x0, 0x0 } =20 # I2C - gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50 } - gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 } - gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000 - gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000 + gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50 } + gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 } + gMarvellSiliconTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdI2cClockFrequency|250000000 + gMarvellSiliconTokenSpaceGuid.PcdI2cBaudRate|100000 =20 # SPI - gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF2700680 - gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000 - gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000 + gMarvellSiliconTokenSpaceGuid.PcdSpiRegBase|0xF2700680 + gMarvellSiliconTokenSpaceGuid.PcdSpiMaxFrequency|10000000 + gMarvellSiliconTokenSpaceGuid.PcdSpiClockFrequency|200000000 =20 - gMarvellTokenSpaceGuid.PcdSpiFlashMode|3 - gMarvellTokenSpaceGuid.PcdSpiFlashCs|0 + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashMode|3 + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashCs|0 =20 # NonDiscoverableDevices - gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1 } + gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1 } =20 # RTC - gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000 + gMarvellSiliconTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000 =20 # Variable store - gMarvellTokenSpaceGuid.PcdSpiMemoryBase|0xEF000000 + gMarvellSiliconTokenSpaceGuid.PcdSpiMemoryBase|0xEF000000 [PcdsDynamicDefault.common] gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0xEF3C0000 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0xEF3E0000 diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc b/Platform= /SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc index 6cb82acb13..b995ce0ef1 100644 --- a/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc +++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc @@ -52,6 +52,6 @@ =20 [PcdsFixedAtBuild.common] #Platform description - gMarvellTokenSpaceGuid.PcdProductManufacturer|"SolidRun" - gMarvellTokenSpaceGuid.PcdProductPlatformName|"CN913x CEx7 Evaluation Bo= ard" - gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.1" + gMarvellSiliconTokenSpaceGuid.PcdProductManufacturer|"SolidRun" + gMarvellSiliconTokenSpaceGuid.PcdProductPlatformName|"CN913x CEx7 Evalua= tion Board" + gMarvellSiliconTokenSpaceGuid.PcdProductVersion|"Rev. 1.1" diff --git a/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDis= coverableInitLib.inf b/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInit= Lib/NonDiscoverableInitLib.inf index c58ba8397a..a388ecab02 100644 --- a/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverab= leInitLib.inf +++ b/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverab= leInitLib.inf @@ -24,7 +24,7 @@ EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec - Silicon/Marvell/Marvell.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec =20 [LibraryClasses] DebugLib --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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