From nobody Sun Feb 8 12:39:17 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+108116+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+108116+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1693380895; cv=none; d=zohomail.com; s=zohoarc; b=MBCcoip2hVfyq3UK2LzEW5tfx3U+/0Hzy4tVqLqjinF4NNllTVGhzeBKiYIqgG7mO4yBbxIdvdKM7JhXFJ1w4mAO6RwVtHYstwDpS83eUiysAZpxCdJ/mQaR1rzasdxKhV8A/1l8CtH7mYsUiUYh623AcHJdKGM659Wow9jZus0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1693380895; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=rueP1w7EIeWUCzg8bE6GDL6gIaL0XpThvFqGVaC/NiU=; b=caIRkbv3it6IJlHZznwCqPcl67v/O4ZUjVFqNKDK26rbD3MBx7gF+dPx/MHfZPQTOYzp3dx+kVY/WQZgZKmUmlv2Whm9CWBAfEIaKLuVDa7ogLolw5qEwd0Uh3mT1m8rBOBoK06V4Pj95ssATphGjhlSOafIPNrbkIeOGJXAeVw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+108116+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1693380895290988.0998102552195; Wed, 30 Aug 2023 00:34:55 -0700 (PDT) Return-Path: DKIM-Signature: a=rsa-sha256; bh=oCFqUYIzONpXgDVkDEOjYV3nA6nQ21++lyRjEwZPImA=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1693380895; v=1; b=Xmbw3oCWpsDPqdZwYNzU9JkUxo44J0+k1r5mssGvYqDFKL9n3m++Y1a66FB6Ly3w3GCKP3zt JCcV08kI8K5dv1PRMOPT+7cta5VcE4L7iH4TxEW4sPMLTgivgCnZ7uflqR01ZgDN+xsjRZo1Lar YiIxP2lgZ8tvo4UCScQfLRHw= X-Received: by 127.0.0.2 with SMTP id k4UcYY1788612xME9dWszezZ; Wed, 30 Aug 2023 00:34:55 -0700 X-Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web11.8841.1693380893054315100 for ; Wed, 30 Aug 2023 00:34:54 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="372977054" X-IronPort-AV: E=Sophos;i="6.02,212,1688454000"; d="scan'208";a="372977054" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Aug 2023 00:34:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="768325828" X-IronPort-AV: E=Sophos;i="6.02,212,1688454000"; d="scan'208";a="768325828" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.43]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Aug 2023 00:34:52 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar Subject: [edk2-devel] [Patch V3 4/5] UefiCpuPkg/PiSmmCpuDxe: code refinement for CpuS3.c Date: Wed, 30 Aug 2023 15:34:17 +0800 Message-Id: <20230830073418.586-2-dun.tan@intel.com> In-Reply-To: <20230830073418.586-1-dun.tan@intel.com> References: <20230830073418.586-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 6gHEjKhkwLTWHuIGnZ1ZSfNFx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1693380897289100001 Content-Type: text/plain; charset="utf-8" This commit is code logic refinement for s3 boot flow in CpuS3.c. It doesn't change any code functionality. This commit implementes InitializeAp and InitializeBsp as a single function since they are doing almost the same thing. Then both BSP and AP will execute the same function InitializeCpuProcedure to do CPU initialization. This can make the code logic easier to understand. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Reviewed-by: Ray Ni --- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 266 ++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++----------------------------------------------= ---------------------------------------------------------------------------= ------- 1 file changed, 138 insertions(+), 128 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/= CpuS3.c index 0f7ee0372d..b9dbeaef87 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -539,44 +539,149 @@ SetRegister ( } =20 /** - AP initialization before then after SMBASE relocation in the S3 boot pat= h. + The function is invoked before SMBASE relocation in S3 path to restores = CPU status. + + The function is invoked before SMBASE relocation in S3 path. It does fir= st time microcode load + and restores MTRRs for both BSP and APs. + + @param IsBsp The CPU this function executes on is BSP or not. + **/ VOID -InitializeAp ( - VOID +InitializeCpuBeforeRebase ( + IN BOOLEAN IsBsp ) { - UINTN TopOfStack; - UINT8 Stack[128]; - LoadMtrrData (mAcpiCpuData.MtrrTable); =20 SetRegister (TRUE); =20 + ProgramVirtualWireMode (); + if (!IsBsp) { + DisableLvtInterrupts (); + } + // // Count down the number with lock mechanism. // InterlockedDecrement (&mNumberToFinish); =20 + if (IsBsp) { + // + // Bsp wait here till all AP finish the initialization before rebase + // + while (mNumberToFinish > 0) { + CpuPause (); + } + } +} + +/** + The function is invoked after SMBASE relocation in S3 path to restores C= PU status. + + The function is invoked after SMBASE relocation in S3 path. It restores = configuration according to + data saved by normal boot path for both BSP and APs. + + @param IsBsp The CPU this function executes on is BSP or not. + +**/ +VOID +InitializeCpuAfterRebase ( + IN BOOLEAN IsBsp + ) +{ + UINTN TopOfStack; + UINT8 Stack[128]; + + SetRegister (FALSE); + if (IsBsp) { + while (mNumberToFinish > 0) { + CpuPause (); + } + } else { + // + // Place AP into the safe code, count down the number with lock mechan= ism in the safe code. + // + TopOfStack =3D (UINTN)Stack + sizeof (Stack); + TopOfStack &=3D ~(UINTN)(CPU_STACK_ALIGNMENT - 1); + CopyMem ((VOID *)(UINTN)mApHltLoopCode, mApHltLoopCodeTemplate, sizeof= (mApHltLoopCodeTemplate)); + TransferApToSafeState ((UINTN)mApHltLoopCode, TopOfStack, (UINTN)&mNum= berToFinish); + } +} + +/** + Cpu initialization procedure. + + @param[in,out] Buffer The pointer to private data buffer. + +**/ +VOID +EFIAPI +InitializeCpuProcedure ( + IN OUT VOID *Buffer + ) +{ + BOOLEAN IsBsp; + + IsBsp =3D (BOOLEAN)(mBspApicId =3D=3D GetApicId ()); + // - // Wait for BSP to signal SMM Base relocation done. + // Skip initialization if mAcpiCpuData is not valid // - while (!mInitApsAfterSmmBaseReloc) { - CpuPause (); + if (mAcpiCpuData.NumberOfCpus > 0) { + // + // First time microcode load and restore MTRRs + // + InitializeCpuBeforeRebase (IsBsp); } =20 - ProgramVirtualWireMode (); - DisableLvtInterrupts (); + if (IsBsp) { + DEBUG ((DEBUG_INFO, "SmmRestoreCpu: mSmmRelocated is %d\n", mSmmReloca= ted)); =20 - SetRegister (FALSE); + // + // Check whether Smm Relocation is done or not. + // If not, will do the SmmBases Relocation here!!! + // + if (!mSmmRelocated) { + // + // Restore SMBASE for BSP and all APs + // + SmmRelocateBases (); + } else { + // + // Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) to exec= ute first SMI init. + // + ExecuteFirstSmiInit (); + } + } =20 // - // Place AP into the safe code, count down the number with lock mechanis= m in the safe code. + // Skip initialization if mAcpiCpuData is not valid // - TopOfStack =3D (UINTN)Stack + sizeof (Stack); - TopOfStack &=3D ~(UINTN)(CPU_STACK_ALIGNMENT - 1); - CopyMem ((VOID *)(UINTN)mApHltLoopCode, mApHltLoopCodeTemplate, sizeof (= mApHltLoopCodeTemplate)); - TransferApToSafeState ((UINTN)mApHltLoopCode, TopOfStack, (UINTN)&mNumbe= rToFinish); + if (mAcpiCpuData.NumberOfCpus > 0) { + if (IsBsp) { + // + // mNumberToFinish should be set before AP executes InitializeCpuAft= erRebase() + // + mNumberToFinish =3D (UINT32)(mNumberOfCpus - 1); + // + // Signal that SMM base relocation is complete and to continue initi= alization for all APs. + // + mInitApsAfterSmmBaseReloc =3D TRUE; + } else { + // + // AP Wait for BSP to signal SMM Base relocation done. + // + while (!mInitApsAfterSmmBaseReloc) { + CpuPause (); + } + } + + // + // Restore MSRs for BSP and all APs + // + InitializeCpuAfterRebase (IsBsp); + } } =20 /** @@ -627,91 +732,7 @@ PrepareApStartupVector ( mExchangeInfo->BufferStart =3D (UINT32)StartupVe= ctor; mExchangeInfo->Cr3 =3D (UINT32)(AsmReadC= r3 ()); mExchangeInfo->InitializeFloatingPointUnitsAddress =3D (UINTN)Initialize= FloatingPointUnits; -} - -/** - The function is invoked before SMBASE relocation in S3 path to restores = CPU status. - - The function is invoked before SMBASE relocation in S3 path. It does fir= st time microcode load - and restores MTRRs for both BSP and APs. - -**/ -VOID -InitializeCpuBeforeRebase ( - VOID - ) -{ - LoadMtrrData (mAcpiCpuData.MtrrTable); - - SetRegister (TRUE); - - ProgramVirtualWireMode (); - - PrepareApStartupVector (mAcpiCpuData.StartupVector); - - if (FeaturePcdGet (PcdCpuHotPlugSupport)) { - ASSERT (mNumberOfCpus <=3D mAcpiCpuData.NumberOfCpus); - } else { - ASSERT (mNumberOfCpus =3D=3D mAcpiCpuData.NumberOfCpus); - } - - mNumberToFinish =3D (UINT32)(mNumberOfCpus - 1); - mExchangeInfo->ApFunction =3D (VOID *)(UINTN)InitializeAp; - - // - // Execute code for before SmmBaseReloc. Note: This flag is maintained a= cross S3 boots. - // - mInitApsAfterSmmBaseReloc =3D FALSE; - - // - // Send INIT IPI - SIPI to all APs - // - SendInitSipiSipiAllExcludingSelf ((UINT32)mAcpiCpuData.StartupVector); - - while (mNumberToFinish > 0) { - CpuPause (); - } -} - -/** - The function is invoked after SMBASE relocation in S3 path to restores C= PU status. - - The function is invoked after SMBASE relocation in S3 path. It restores = configuration according to - data saved by normal boot path for both BSP and APs. - -**/ -VOID -InitializeCpuAfterRebase ( - VOID - ) -{ - if (FeaturePcdGet (PcdCpuHotPlugSupport)) { - ASSERT (mNumberOfCpus <=3D mAcpiCpuData.NumberOfCpus); - } else { - ASSERT (mNumberOfCpus =3D=3D mAcpiCpuData.NumberOfCpus); - } - - mNumberToFinish =3D (UINT32)(mNumberOfCpus - 1); - - // - // Signal that SMM base relocation is complete and to continue initializ= ation for all APs. - // - mInitApsAfterSmmBaseReloc =3D TRUE; - - // - // Must begin set register after all APs have continue their initializat= ion. - // This is a requirement to support semaphore mechanism in register tabl= e. - // Because if semaphore's dependence type is package type, semaphore wil= l wait - // for all Aps in one package finishing their tasks before set next regi= ster - // for all APs. If the Aps not begin its task during BSP doing its task,= the - // BSP thread will hang because it is waiting for other Aps in the same - // package finishing their task. - // - SetRegister (FALSE); - - while (mNumberToFinish > 0) { - CpuPause (); - } + mExchangeInfo->ApFunction =3D (VOID *)(UINTN)In= itializeCpuProcedure; } =20 /** @@ -813,44 +834,33 @@ SmmRestoreCpu ( InitializeDebugAgent (DEBUG_AGENT_INIT_THUNK_PEI_IA32TOX64, (VOID *)&I= a32Idtr, NULL); } =20 + mBspApicId =3D GetApicId (); // - // Skip initialization if mAcpiCpuData is not valid + // Skip AP initialization if mAcpiCpuData is not valid // if (mAcpiCpuData.NumberOfCpus > 0) { - // - // First time microcode load and restore MTRRs - // - InitializeCpuBeforeRebase (); - } + if (FeaturePcdGet (PcdCpuHotPlugSupport)) { + ASSERT (mNumberOfCpus <=3D mAcpiCpuData.NumberOfCpus); + } else { + ASSERT (mNumberOfCpus =3D=3D mAcpiCpuData.NumberOfCpus); + } =20 - DEBUG ((DEBUG_INFO, "SmmRestoreCpu: mSmmRelocated is %d\n", mSmmRelocate= d)); + mNumberToFinish =3D (UINT32)mNumberOfCpus; =20 - // - // Check whether Smm Relocation is done or not. - // If not, will do the SmmBases Relocation here!!! - // - if (!mSmmRelocated) { // - // Restore SMBASE for BSP and all APs + // Execute code for before SmmBaseReloc. Note: This flag is maintained= across S3 boots. // - SmmRelocateBases (); - } else { - // - // Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) to execut= e first SMI init. - // - ExecuteFirstSmiInit (); - } + mInitApsAfterSmmBaseReloc =3D FALSE; =20 - // - // Skip initialization if mAcpiCpuData is not valid - // - if (mAcpiCpuData.NumberOfCpus > 0) { + PrepareApStartupVector (mAcpiCpuData.StartupVector); // - // Restore MSRs for BSP and all APs + // Send INIT IPI - SIPI to all APs // - InitializeCpuAfterRebase (); + SendInitSipiSipiAllExcludingSelf ((UINT32)mAcpiCpuData.StartupVector); } =20 + InitializeCpuProcedure (NULL); + // // Set a flag to restore SMM configuration in S3 path. // --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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