From nobody Sat Feb 7 06:55:45 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+106802+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+106802+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1689086247; cv=none; d=zohomail.com; s=zohoarc; b=TU72A9qLNS+MQ+8JZ0Zc13FKhdm1hSS3PxQvC0HMVuGWuEBsw8Ldm/ZyfhMnG0cMGq3vDwcEjJb6yuWi8zPyFubSQ3EBedSFZO9Z+mqK9CXkfQsFIjcqxQ9uum+M3YJT62L/CDrIktX7SGmq3FMU+sNU8TUeu6YNoVdtV+2VjXs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1689086247; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=jAlot1g58m+O2VeRfaV0WJ9HNZ3Ybw8SVZoF30N8Cno=; b=cxyhZ4QTn4k1UsB9+p2PsGKc5lIdBk7QiiUVCrybxFZJ8KvRFemx6zOzKumBGsfnq5PfYkAk7Sv5OyPMkuw3PyzPXFCFYdWxDRpRLFOFkgA4iGC3QBUyVC9AK4ghS0CwM3kTDvFTZcsN5J7C3yY7Frru6/JFQTtYoZSjIW161zk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+106802+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1689086246689418.2933780912447; Tue, 11 Jul 2023 07:37:26 -0700 (PDT) Return-Path: DKIM-Signature: a=rsa-sha256; bh=VHyNkahJlxiDMruuNOrXxP8p7aXJVNaKzyrQIshKT+A=; c=relaxed/simple; d=groups.io; h=X-Received:X-Received:X-Received:X-Received:From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Unsubscribe:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:X-Gm-Message-State:Content-Transfer-Encoding; s=20140610; t=1689086246; v=1; b=HCRauhdb6WtyWIdXupe+3Au+6fVEW1zzVCCRzIMY0QS2EtwepaJTixS+lbOuVdhKRB9Q1mG0 FZ4gvycMDoXnVtR2kV3jeXt4OILt28ujlMGnklMc6MPKFTN8JZb1zt7cahySkDSQjom+1eVOUrh OqC28lfPgMFK5MLwEhl9Ko0M= X-Received: by 127.0.0.2 with SMTP id FJUTYY1788612xvnBs4XR8fB; Tue, 11 Jul 2023 07:37:26 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.1273.1689086245339188894 for ; Tue, 11 Jul 2023 07:37:25 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4316C1FB; Tue, 11 Jul 2023 07:38:07 -0700 (PDT) X-Received: from usa.arm.com (iss-desktop02.cambridge.arm.com [10.1.196.79]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 255CF3F740; Tue, 11 Jul 2023 07:37:24 -0700 (PDT) From: "Nishant Sharma" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Sami Mujawar , Thomas Abraham , Sayanta Pattanayak , Achin Gupta Subject: [edk2-devel] [edk2-platforms][PATCH V1 10/20] StandaloneMmPkg: Populate Hoblist for SP init from StMM boot information Date: Tue, 11 Jul 2023 15:36:48 +0100 Message-Id: <20230711143658.781597-11-nishant.sharma@arm.com> In-Reply-To: <20230711143658.781597-1-nishant.sharma@arm.com> References: <20230711143658.781597-1-nishant.sharma@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nishant.sharma@arm.com X-Gm-Message-State: JYlV2J5RL9UlQEUBiVywddyVx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1689086248691100040 Content-Type: text/plain; charset="utf-8" From: Achin Gupta This patch adds support for creating a hoblist from the reduced boot information retrieved from the SP manifest. Signed-off-by: Achin Gupta Signed-off-by: Nishant Sharma --- StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h = | 16 ++ StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c = | 186 +++++++++++++++++++- StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/StandaloneMmCoreEnt= ryPoint.c | 6 +- 3 files changed, 206 insertions(+), 2 deletions(-) diff --git a/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint= .h b/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h index 90d67a2f25b5..9daa76324221 100644 --- a/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h +++ b/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h @@ -170,6 +170,22 @@ CreateHobListFromBootInfo ( IN EFI_SECURE_PARTITION_BOOT_INFO *PayloadBootInfo ); =20 +/** + Use the boot information passed by the SPMC to populate a HOB list + suitable for consumption by the MM Core and drivers. + + @param [in, out] CpuDriverEntryPoint Address of MM CPU driver entrypo= int + @param [in] StmmBootInfo Boot information passed by privi= leged + firmware + +**/ +VOID * +EFIAPI +CreateHobListFromStmmBootInfo ( + IN OUT PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT *CpuDriverEntryPoint, + IN EFI_STMM_BOOT_INFO *StmmBootInfo + ); + /** The entry point of Standalone MM Foundation. =20 diff --git a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateH= obList.c b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHob= List.c index 2ac2d354f06a..4592089a6020 100644 --- a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c +++ b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c @@ -2,7 +2,7 @@ Creates HOB during Standalone MM Foundation entry point on ARM platforms. =20 -Copyright (c) 2017 - 2021, Arm Ltd. All rights reserved.
+Copyright (c) 2017 - 2023, Arm Ltd. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -203,3 +203,187 @@ CreateHobListFromBootInfo ( =20 return HobStart; } + +STATIC +VOID +CreateMmramInformationHobFromImageLayout ( + IN EFI_STMM_BOOT_INFO *StmmBootInfo, + IN EFI_HOB_HANDOFF_INFO_TABLE *HobStart +) +{ + UINT32 *Idx; + UINT32 BufferSize; + EFI_MMRAM_HOB_DESCRIPTOR_BLOCK *MmramRangesHob; + EFI_MMRAM_DESCRIPTOR *MmramRanges; + + // Find the size of the GUIDed HOB with SRAM ranges. This excludes any m= emory + // shared with the normal world or the SPMC. It includes the memory allo= cated + // to the SP image, used and unused heap. + BufferSize =3D sizeof (EFI_MMRAM_HOB_DESCRIPTOR_BLOCK); + BufferSize +=3D 4 * sizeof (EFI_MMRAM_DESCRIPTOR); + + // Create a GUIDed HOB with SRAM ranges + MmramRangesHob =3D BuildGuidHob (&gEfiMmPeiMmramMemoryReserveGuid, Buffe= rSize); + + // Initialise the number of MMRAM memory regions + MmramRangesHob->NumberOfMmReservedRegions =3D 0; + Idx =3D &MmramRangesHob->NumberOfMmReservedRegions ; + + // Fill up the MMRAM ranges + MmramRanges =3D &MmramRangesHob->Descriptor[0]; + + // Base and size of memory occupied by the Standalone MM image + MmramRanges[*Idx].PhysicalStart =3D StmmBootInfo->SpMemBase; + MmramRanges[*Idx].CpuStart =3D StmmBootInfo->SpMemBase; + MmramRanges[*Idx].PhysicalSize =3D StmmBootInfo->SpMemSize; + MmramRanges[*Idx].RegionState =3D EFI_CACHEABLE | EFI_ALLOCATED; + (*Idx)++; + + // Base and size of memory occupied by the Standalone MM image + MmramRanges[*Idx].PhysicalStart =3D StmmBootInfo->SpSharedBufBase; + MmramRanges[*Idx].CpuStart =3D StmmBootInfo->SpSharedBufBase; + MmramRanges[*Idx].PhysicalSize =3D StmmBootInfo->SpSharedBufSize; + MmramRanges[*Idx].RegionState =3D EFI_CACHEABLE | EFI_ALLOCATED; + (*Idx)++; + + // Base and size of memory occupied by the hoblist + MmramRanges[*Idx].PhysicalStart =3D (EFI_PHYSICAL_ADDRESS) (UINTN) HobSt= art; + MmramRanges[*Idx].CpuStart =3D (EFI_PHYSICAL_ADDRESS) (UINTN) HobSt= art; + MmramRanges[*Idx].PhysicalSize =3D HobStart->EfiFreeMemoryBottom - (EFI= _PHYSICAL_ADDRESS) (UINTN) HobStart; + MmramRanges[*Idx].RegionState =3D EFI_CACHEABLE | EFI_ALLOCATED; + (*Idx)++; + + // Base and size of heap memory shared by all cpus + MmramRanges[*Idx].PhysicalStart =3D HobStart->EfiFreeMemoryBottom; + MmramRanges[*Idx].CpuStart =3D HobStart->EfiFreeMemoryBottom; + MmramRanges[*Idx].PhysicalSize =3D HobStart->EfiFreeMemoryTop - HobStar= t->EfiFreeMemoryBottom; + MmramRanges[*Idx].RegionState =3D EFI_CACHEABLE; + (*Idx)++; + + // Sanity check number of MMRAM regions + ASSERT (MmramRangesHob->NumberOfMmReservedRegions =3D=3D 3); + + return; +} + +STATIC +VOID +CreateMpInformationHobFromCpuInfo ( + IN EFI_SECURE_PARTITION_CPU_INFO *CpuInfo +) +{ + MP_INFORMATION_HOB_DATA *MpInformationHobData; + EFI_PROCESSOR_INFORMATION *ProcInfoBuffer; + UINT32 BufferSize; + UINT32 Flags; + + // Find the size of the GUIDed HOB with MP information + BufferSize =3D sizeof (MP_INFORMATION_HOB_DATA); + BufferSize +=3D sizeof (EFI_PROCESSOR_INFORMATION); + + // Create a Guided MP information HOB to enable the ARM TF CPU driver to + // perform per-cpu allocations. + MpInformationHobData =3D BuildGuidHob (&gMpInformationHobGuid, BufferSiz= e); + + // Populate the MP information HOB under the assumption that this is a + // uniprocessor partition. Hence, only a single CPU is exposed to the MM= Core. + MpInformationHobData->NumberOfProcessors =3D 1; + MpInformationHobData->NumberOfEnabledProcessors =3D 1; + + // Populate the processor information + ProcInfoBuffer =3D MpInformationHobData->ProcessorInfoBuffer; + ProcInfoBuffer[0].ProcessorId =3D CpuInfo[0].Mpidr; + ProcInfoBuffer[0].Location.Package =3D GET_CLUSTER_ID(CpuInfo[0].Mpidr); + ProcInfoBuffer[0].Location.Core =3D GET_CORE_ID(CpuInfo[0].Mpidr); + ProcInfoBuffer[0].Location.Thread =3D GET_CORE_ID(CpuInfo[0].Mpidr); + + // Populate the processor information flags + Flags =3D PROCESSOR_ENABLED_BIT | PROCESSOR_HEALTH_STATUS_BIT | PROCESSO= R_AS_BSP_BIT; + ProcInfoBuffer[0].StatusFlag =3D Flags; + + return; +} + +/** + Use the FF-A boot information passed by the SPMC to populate a HOB list + suitable for consumption by the MM Core and drivers. + + @param [in, out] CpuDriverEntryPoint Address of MM CPU driver entrypo= int + @param [in] StmmBootInfo Boot information passed by the S= PMC + +**/ +VOID * +CreateHobListFromStmmBootInfo ( + IN OUT PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT *CpuDriverEntryPoint, + IN EFI_STMM_BOOT_INFO *StmmBootInfo +) +{ + EFI_HOB_HANDOFF_INFO_TABLE *HobStart; + EFI_RESOURCE_ATTRIBUTE_TYPE Attributes; + EFI_MMRAM_DESCRIPTOR *NsCommBufMmramRange; + ARM_TF_CPU_DRIVER_EP_DESCRIPTOR *CpuDriverEntryPointDesc; + + // Create a hoblist with a PHIT and EOH + HobStart =3D HobConstructor ( + (VOID *) (UINTN) StmmBootInfo->SpMemBase, + (UINTN) StmmBootInfo->SpMemSize, + (VOID *) (UINTN) StmmBootInfo->SpHeapBase, + (VOID *) (UINTN) (StmmBootInfo->SpHeapBase + StmmBootInfo->= SpHeapSize) + ); + + // Check that the Hoblist starts at the bottom of the Heap + ASSERT (HobStart =3D=3D (VOID *) (UINTN) StmmBootInfo->SpHeapBase); + + // Build a Boot Firmware Volume HOB + BuildFvHob (StmmBootInfo->SpMemBase, StmmBootInfo->SpMemSize); + + // Build a resource descriptor Hob that describes the available physical + // memory range + Attributes =3D ( + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_TESTED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE + ); + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + Attributes, + (UINTN) StmmBootInfo->SpMemBase, + StmmBootInfo->SpMemSize + ); + + // Create an MP information hob from cpu information passed in the boot + // information structure + CreateMpInformationHobFromCpuInfo(&StmmBootInfo->CpuInfo); + + // Create a Guided HOB to tell the ARM TF CPU driver the location and le= ngth + // of the communication buffer shared with the Normal world. + NsCommBufMmramRange =3D (EFI_MMRAM_DESCRIPTOR *) BuildGuidHob ( + &gEfiStandaloneMmNonSec= ureBufferGuid, + sizeof (EFI_MMRAM_DESCR= IPTOR) + ); + NsCommBufMmramRange->PhysicalStart =3D StmmBootInfo->SpNsCommBufBase; + NsCommBufMmramRange->CpuStart =3D StmmBootInfo->SpNsCommBufBase; + NsCommBufMmramRange->PhysicalSize =3D StmmBootInfo->SpNsCommBufSize; + NsCommBufMmramRange->RegionState =3D EFI_CACHEABLE | EFI_ALLOCATED; + + // Create a Guided HOB to enable the ARM TF CPU driver to share its entry + // point and populate it with the address of the shared buffer + CpuDriverEntryPointDesc =3D + (ARM_TF_CPU_DRIVER_EP_DESCRIPTOR *) BuildGuidHob ( + &gEfiArmTfCpuDriverEpDescriptorGuid, + sizeof (ARM_TF_CPU_DRIVER_EP_DESCRIPTOR) + ); + + *CpuDriverEntryPoint =3D NULL; + CpuDriverEntryPointDesc->ArmTfCpuDriverEpPtr =3D CpuDriverEntryPoint; + + // Create Mmram range hob from SP image layout + CreateMmramInformationHobFromImageLayout(StmmBootInfo, HobStart); + + return HobStart; +} diff --git a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/Standal= oneMmCoreEntryPoint.c b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/= Arm/StandaloneMmCoreEntryPoint.c index 505786aff07c..8131b1984969 100644 --- a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/StandaloneMmCo= reEntryPoint.c +++ b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/StandaloneMmCo= reEntryPoint.c @@ -823,7 +823,11 @@ ModuleEntryPoint ( // // Create Hoblist based upon boot information passed by privileged softw= are // - HobStart =3D CreateHobListFromBootInfo (&CpuDriverEntryPoint, PayloadBoo= tInfo); + if (UseOnlyFfaAbis) { + HobStart =3D CreateHobListFromStmmBootInfo (&CpuDriverEntryPoint, &Stm= mBootInfo); + } else { + HobStart =3D CreateHobListFromBootInfo (&CpuDriverEntryPoint, PayloadB= ootInfo); + } =20 // // Call the MM Core entry point --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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