From nobody Tue Feb 10 04:29:40 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+106112+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+106112+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1686826273; cv=none; d=zohomail.com; s=zohoarc; b=CKwlLVnn/Dooq3fLQakC3o7j2w2LB7/j2ugmfm8Q37uA9r7ctN3lv9JXttviX1Xr6yXqlnl1yhxtBWqTDlvsa2sa4zp3neXVUKSkwyzW6jM2OmM722drL+kAL3qgENEB34xNbq4LzCXWOmT5L2jDlzn4z/93Xt+GweEuveYi+V0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686826273; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=O1q+GJSMVrAtpwKlKIDJy8tRLnsZhguedKXdy6pH5uM=; b=aqnSt24cJ7wJEgkQcD6eQ7UHuTSaTQ91/YYH8GkaPFHZn1ovMIMq2nuuQbkU4YmJQ5AYroWLvtaZPMBRUC1/ZSuuT1RqIdsdzL1wqo2gPzCTSopGhCejG3tJDmC1zTFfLfhlx3p6sPHe3pI9pxoPEDTIUtmQIn+ahU1O44WqRP4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+106112+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1686826273663893.3020718135863; Thu, 15 Jun 2023 03:51:13 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id SYwVYY1788612x4dTaBCd8Gp; Thu, 15 Jun 2023 03:51:13 -0700 X-Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mx.groups.io with SMTP id smtpd.web10.15125.1686826271830570395 for ; Thu, 15 Jun 2023 03:51:12 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10741"; a="387323154" X-IronPort-AV: E=Sophos;i="6.00,244,1681196400"; d="scan'208";a="387323154" X-Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jun 2023 03:51:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10741"; a="959156162" X-IronPort-AV: E=Sophos;i="6.00,244,1681196400"; d="scan'208";a="959156162" X-Received: from shwdeopenlab706.ccr.corp.intel.com ([10.239.55.95]) by fmsmga006.fm.intel.com with ESMTP; 15 Jun 2023 03:51:01 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Eric Dong , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [PATCH 2/3] UefiCpuPkg/ResetVector: Add guidance of how to guarantee 16B align Date: Thu, 15 Jun 2023 18:50:56 +0800 Message-Id: <20230615105057.297-3-ray.ni@intel.com> In-Reply-To: <20230615105057.297-1-ray.ni@intel.com> References: <20230615105057.297-1-ray.ni@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com X-Gm-Message-State: sZaUDfre1fH5szcu5r0QfyYex1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1686826273; bh=dtQZ2TYaDH+7TDPiHHe8brTN1Xs8PwzytrF9vM+IOyc=; h=Cc:Date:From:Reply-To:Subject:To; b=PlwC3mWwmFwXGI7pFb6Nxm/1fBKlTaQ6E73nO0cC4myS054qWmM0EYa3WDa00cp9Mx3 E0wBbfNxgm6TUCmoff5s/D9SJKieNS9sB3/7dLPxag0p1pvr6MyfS+4ifIsoX6JUv8fJF apcRzyxn/3QBtH4/m0lKMT4JxaN39qEJ1eI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1686826275708100003 Content-Type: text/plain; charset="utf-8" ResetVector assembly implementation puts "ALIGN 16" in the end to guarantee the final executable file size is multiple of 16 bytes. Because the module uses a special GUID which guarantees it's put in the very end of a FV, which should be also the end of the FD. Then to make sure the reset vector "JMP" code is at FFFF_FFF0h, the ResetVector has to be aligned at 16-byte boundary. The patch updates INF file and ReadMe.txt to add guidance how to make sure the module is aligned on 16-byte boundary. Signed-off-by: Ray Ni Cc: Eric Dong Cc: Rahul Kumar Cc: Gerd Hoffmann Reviewed-by: Eric Dong --- UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt | 27 +++++++------------------- UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf | 19 +++++++++++++++++- 2 files changed, 25 insertions(+), 21 deletions(-) diff --git a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt b/UefiCpuPkg/ResetVecto= r/Vtf0/ReadMe.txt index 97f4600968..edeb2d6d3e 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt +++ b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt @@ -1,15 +1,16 @@ =20 =3D=3D=3D HOW TO USE VTF0 =3D=3D=3D +Add this line to your DSC [Components.IA32] or [Components.X64] section: + UefiCpuPkg/ResetVector/Vtf0/ResetVector.inf =20 Add this line to your FDF FV section: -INF RuleOverride=3DRESET_VECTOR USE =3D IA32 UefiCpuPkg/ResetVector/Vtf0/= Bin/ResetVector.inf -(For X64 SEC/PEI change IA32 to X64 =3D> 'USE =3D X64') + INF RuleOverride=3DRESET_VECTOR UefiCpuPkg/ResetVector/Vtf0/ResetVector= .inf =20 In your FDF FFS file rules sections add: -[Rule.Common.SEC.RESET_VECTOR] - FILE RAW =3D $(NAMED_GUID) { - RAW RAW |.raw - } + [Rule.Common.SEC.RESET_VECTOR] + FILE RAW =3D $(NAMED_GUID) { + RAW BIN Align =3D 16 |.bin + } =20 =3D=3D=3D VTF0 Boot Flow =3D=3D=3D =20 @@ -25,17 +26,3 @@ All inputs to SEC image are register based: EAX/RAX - Initial value of the EAX register (BIST: Built-in Self Test) DI - 'BP': boot-strap processor, or 'AP': application processor EBP/RBP - Pointer to the start of the Boot Firmware Volume - -=3D=3D=3D HOW TO BUILD VTF0 =3D=3D=3D - -Dependencies: -* Python 3 or newer -* Nasm 2.03 or newer - -To rebuild the VTF0 binaries: -1. Change to VTF0 source dir: UefiCpuPkg/ResetVector/Vtf0 -2. nasm and python should be in executable path -3. Run this command: - python Build.py -4. Binaries output will be in UefiCpuPkg/ResetVector/Vtf0/Bin - diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf b/UefiCpuPkg/ResetVector/= Vtf0/Vtf0.inf index 9922cb2755..28185a6e60 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf +++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf @@ -1,7 +1,24 @@ ## @file # Reset Vector # -# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+# Note: +# The platform FDF file MUST guarantee the ResetVector is aligned +# on 16-byte boundary. Otherwise, the CPU reset vector will NOT be +# at FFFF_FFF0h. +# +# A sample FDF build rule could be as follows: +# +# [Rule.Common.SEC.RESET_VECTOR] +# FILE RAW =3D $(NAMED_GUID) { +# RAW BIN Align =3D 16 |.bin +# } +# +# Following line in FDF forces to use the above build rule for the Rese= tVector: +# +# INF RuleOverride=3DRESET_VECTOR UefiCpuPkg/ResetVector/Vtf0/Vtf0.i= nf +# +# +# Copyright (c) 2006 - 2023, Intel Corporation. All rights reserved.
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