From nobody Tue Feb 10 23:53:10 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+105902+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+105902+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1686191345; cv=none; d=zohomail.com; s=zohoarc; b=aTmKDHIyujzubvX3jUfklmWx65/scE8UgbgLQ6ymYUIe5+OkZvV4oHOuDX7lbSFW/crDG2sUiFhCjPjo8iKV0BzGiyS+X6rUD7n7FYiODWpIY53gCiCHiGi5ZWM0Mj9s34zLcxX385x7/sNXFrefQfQ3dU+Wjud9lFRIEdq+0IU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686191345; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Spa9YpNKNnXuncWxL8olgoDj1VuHajq+x36+J0eMHc4=; b=ArIOkrxqy2MMVpNh+WYE704FTkNlVeVrpdL++Nai70lKbD9BTbLekVlmLsYTWMNTxb0AzzP4Bv9NFYsFOjIBHfZCi9Zudy/QVb0Ib5H9ttWpStlXt8KAUs8UpOgcSMtXC7dbdAKpB6JaM9TSMBQU1dENgJUW4JimTBSm4XIS7Hk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+105902+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 168619134538782.87032292575668; Wed, 7 Jun 2023 19:29:05 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id ywyIYY1788612xySEq310g6E; Wed, 07 Jun 2023 19:29:05 -0700 X-Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web11.386.1686191344244208222 for ; Wed, 07 Jun 2023 19:29:04 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10734"; a="357184372" X-IronPort-AV: E=Sophos;i="6.00,225,1681196400"; d="scan'208";a="357184372" X-Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jun 2023 19:29:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10734"; a="774877874" X-IronPort-AV: E=Sophos;i="6.00,225,1681196400"; d="scan'208";a="774877874" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.158]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jun 2023 19:29:02 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V5 09/14] UefiCpuPkg: Add GenSmmPageTable() to create smm page table Date: Thu, 8 Jun 2023 10:27:37 +0800 Message-Id: <20230608022742.1292-10-dun.tan@intel.com> In-Reply-To: <20230608022742.1292-1-dun.tan@intel.com> References: <20230608022742.1292-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: gt2x50Q2vFWNogv9sbUIqyk6x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1686191345; bh=JnBpaw169iaADp054C3Fv/hsZ6AvW3Yk9Jd6QzMHnt0=; h=Cc:Date:From:Reply-To:Subject:To; b=VHJ7EQ4/3z1AZmduafpxqar+ZJD+bZ6lVMhBVCM786Hx1tiEPK5eXRVH+nNREHWK9Vf FdzrawxD4U8jYcv8B5byhuETnKOFGw6OQ/G7fkMRoXOVhjtOfRUAdj0ZfU08X8r+9W67A M7hLmvFGV0S7EhA3L0vyCR72gEYOip7L5oQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1686191346965100003 Content-Type: text/plain; charset="utf-8" This commit is code refinement to current smm pagetable generation code. Add a new GenSmmPageTable() API to create smm page table based on the PageTableMap() API in CpuPageTableLib. Caller only needs to specify the paging mode and the PhysicalAddressBits to map. This function can be used to create both IA32 pae paging and X64 5level, 4level paging. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Reviewed-by: Ray Ni --- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 2 +- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 15 +++++++++++++++ UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 65 +++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++ UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 220 +++++++++++++++++= +++++++++------------------------------------------------------------------= ---------------------------------------------------------------------------= ----------------------------------------------------- 4 files changed, 107 insertions(+), 195 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c b/UefiCpuPkg/PiSmmCpu= DxeSmm/Ia32/PageTbl.c index 9c8107080a..b11264ce4a 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c @@ -63,7 +63,7 @@ SmmInitPageTable ( InitializeIDTSmmStackGuard (); } =20 - return Gen4GPageTable (TRUE); + return GenSmmPageTable (PagingPae, mPhysicalAddressBits); } =20 /** diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.h index a7da9673a5..5399659bc0 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -553,6 +553,21 @@ Gen4GPageTable ( IN BOOLEAN Is32BitPageTable ); =20 +/** + Create page table based on input PagingMode and PhysicalAddressBits in s= mm. + + @param[in] PagingMode The paging mode. + @param[in] PhysicalAddressBits The bits of physical address to map. + + @retval PageTable Address + +**/ +UINTN +GenSmmPageTable ( + IN PAGING_MODE PagingMode, + IN UINT8 PhysicalAddressBits + ); + /** Initialize global data for MP synchronization. =20 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPk= g/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c index 4ee99d06d7..4e93d26eb4 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c @@ -1640,6 +1640,71 @@ EdkiiSmmClearMemoryAttributes ( return SmmClearMemoryAttributes (BaseAddress, Length, Attributes); } =20 +/** + Create page table based on input PagingMode and PhysicalAddressBits in s= mm. + + @param[in] PagingMode The paging mode. + @param[in] PhysicalAddressBits The bits of physical address to map. + + @retval PageTable Address + +**/ +UINTN +GenSmmPageTable ( + IN PAGING_MODE PagingMode, + IN UINT8 PhysicalAddressBits + ) +{ + UINTN PageTableBufferSize; + UINTN PageTable; + VOID *PageTableBuffer; + IA32_MAP_ATTRIBUTE MapAttribute; + IA32_MAP_ATTRIBUTE MapMask; + RETURN_STATUS Status; + UINTN GuardPage; + UINTN Index; + UINT64 Length; + + Length =3D LShiftU64 (1, PhysicalAddressBits); + PageTable =3D 0; + PageTableBufferSize =3D 0; + MapMask.Uint64 =3D MAX_UINT64; + MapAttribute.Uint64 =3D mAddressEncMask; + MapAttribute.Bits.Present =3D 1; + MapAttribute.Bits.ReadWrite =3D 1; + MapAttribute.Bits.UserSupervisor =3D 1; + MapAttribute.Bits.Accessed =3D 1; + MapAttribute.Bits.Dirty =3D 1; + + Status =3D PageTableMap (&PageTable, PagingMode, NULL, &PageTableBufferS= ize, 0, Length, &MapAttribute, &MapMask, NULL); + ASSERT (Status =3D=3D RETURN_BUFFER_TOO_SMALL); + DEBUG ((DEBUG_INFO, "GenSMMPageTable: 0x%x bytes needed for initial SMM = page table\n", PageTableBufferSize)); + PageTableBuffer =3D AllocatePageTableMemory (EFI_SIZE_TO_PAGES (PageTabl= eBufferSize)); + ASSERT (PageTableBuffer !=3D NULL); + Status =3D PageTableMap (&PageTable, PagingMode, PageTableBuffer, &PageT= ableBufferSize, 0, Length, &MapAttribute, &MapMask, NULL); + ASSERT (Status =3D=3D RETURN_SUCCESS); + ASSERT (PageTableBufferSize =3D=3D 0); + + if (FeaturePcdGet (PcdCpuSmmStackGuard)) { + // + // Mark the 4KB guard page between known good stack and smm stack as n= on-present + // + for (Index =3D 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOf= Cpus; Index++) { + GuardPage =3D mSmmStackArrayBase + EFI_PAGE_SIZE + Index * (mSmmStac= kSize + mSmmShadowStackSize); + Status =3D ConvertMemoryPageAttributes (PageTable, PagingMode, Gu= ardPage, SIZE_4KB, EFI_MEMORY_RP, TRUE, NULL); + } + } + + if ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) !=3D 0) { + // + // Mark [0, 4k] as non-present + // + Status =3D ConvertMemoryPageAttributes (PageTable, PagingMode, 0, SIZE= _4KB, EFI_MEMORY_RP, TRUE, NULL); + } + + return (UINTN)PageTable; +} + /** This function retrieves the attributes of the memory region specified by BaseAddress and Length. If different attributes are got from different p= art diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuD= xeSmm/X64/PageTbl.c index 46d8ff5d4e..ddd9be66b5 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -167,160 +167,6 @@ CalculateMaximumSupportAddress ( return PhysicalAddressBits; } =20 -/** - Set static page table. - - @param[in] PageTable Address of page table. - @param[in] PhysicalAddressBits The maximum physical address bits supp= orted. -**/ -VOID -SetStaticPageTable ( - IN UINTN PageTable, - IN UINT8 PhysicalAddressBits - ) -{ - UINT64 PageAddress; - UINTN NumberOfPml5EntriesNeeded; - UINTN NumberOfPml4EntriesNeeded; - UINTN NumberOfPdpEntriesNeeded; - UINTN IndexOfPml5Entries; - UINTN IndexOfPml4Entries; - UINTN IndexOfPdpEntries; - UINTN IndexOfPageDirectoryEntries; - UINT64 *PageMapLevel5Entry; - UINT64 *PageMapLevel4Entry; - UINT64 *PageMap; - UINT64 *PageDirectoryPointerEntry; - UINT64 *PageDirectory1GEntry; - UINT64 *PageDirectoryEntry; - - // - // IA-32e paging translates 48-bit linear addresses to 52-bit physical a= ddresses - // when 5-Level Paging is disabled. - // - ASSERT (PhysicalAddressBits <=3D 52); - if (!m5LevelPagingNeeded && (PhysicalAddressBits > 48)) { - PhysicalAddressBits =3D 48; - } - - NumberOfPml5EntriesNeeded =3D 1; - if (PhysicalAddressBits > 48) { - NumberOfPml5EntriesNeeded =3D (UINTN)LShiftU64 (1, PhysicalAddressBits= - 48); - PhysicalAddressBits =3D 48; - } - - NumberOfPml4EntriesNeeded =3D 1; - if (PhysicalAddressBits > 39) { - NumberOfPml4EntriesNeeded =3D (UINTN)LShiftU64 (1, PhysicalAddressBits= - 39); - PhysicalAddressBits =3D 39; - } - - NumberOfPdpEntriesNeeded =3D 1; - ASSERT (PhysicalAddressBits > 30); - NumberOfPdpEntriesNeeded =3D (UINTN)LShiftU64 (1, PhysicalAddressBits - = 30); - - // - // By architecture only one PageMapLevel4 exists - so lets allocate stor= age for it. - // - PageMap =3D (VOID *)PageTable; - - PageMapLevel4Entry =3D PageMap; - PageMapLevel5Entry =3D NULL; - if (m5LevelPagingNeeded) { - // - // By architecture only one PageMapLevel5 exists - so lets allocate st= orage for it. - // - PageMapLevel5Entry =3D PageMap; - } - - PageAddress =3D 0; - - for ( IndexOfPml5Entries =3D 0 - ; IndexOfPml5Entries < NumberOfPml5EntriesNeeded - ; IndexOfPml5Entries++, PageMapLevel5Entry++) - { - // - // Each PML5 entry points to a page of PML4 entires. - // So lets allocate space for them and fill them in in the IndexOfPml4= Entries loop. - // When 5-Level Paging is disabled, below allocation happens only once. - // - if (m5LevelPagingNeeded) { - PageMapLevel4Entry =3D (UINT64 *)((*PageMapLevel5Entry) & ~mAddressE= ncMask & gPhyMask); - if (PageMapLevel4Entry =3D=3D NULL) { - PageMapLevel4Entry =3D AllocatePageTableMemory (1); - ASSERT (PageMapLevel4Entry !=3D NULL); - ZeroMem (PageMapLevel4Entry, EFI_PAGES_TO_SIZE (1)); - - *PageMapLevel5Entry =3D (UINT64)(UINTN)PageMapLevel4Entry | mAddre= ssEncMask | PAGE_ATTRIBUTE_BITS; - } - } - - for (IndexOfPml4Entries =3D 0; IndexOfPml4Entries < (NumberOfPml5Entri= esNeeded =3D=3D 1 ? NumberOfPml4EntriesNeeded : 512); IndexOfPml4Entries++,= PageMapLevel4Entry++) { - // - // Each PML4 entry points to a page of Page Directory Pointer entrie= s. - // - PageDirectoryPointerEntry =3D (UINT64 *)((*PageMapLevel4Entry) & ~mA= ddressEncMask & gPhyMask); - if (PageDirectoryPointerEntry =3D=3D NULL) { - PageDirectoryPointerEntry =3D AllocatePageTableMemory (1); - ASSERT (PageDirectoryPointerEntry !=3D NULL); - ZeroMem (PageDirectoryPointerEntry, EFI_PAGES_TO_SIZE (1)); - - *PageMapLevel4Entry =3D (UINT64)(UINTN)PageDirectoryPointerEntry |= mAddressEncMask | PAGE_ATTRIBUTE_BITS; - } - - if (m1GPageTableSupport) { - PageDirectory1GEntry =3D PageDirectoryPointerEntry; - for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntrie= s < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress= +=3D SIZE_1GB) { - if ((IndexOfPml4Entries =3D=3D 0) && (IndexOfPageDirectoryEntrie= s < 4)) { - // - // Skip the < 4G entries - // - continue; - } - - // - // Fill in the Page Directory entries - // - *PageDirectory1GEntry =3D PageAddress | mAddressEncMask | IA32_P= G_PS | PAGE_ATTRIBUTE_BITS; - } - } else { - PageAddress =3D BASE_4GB; - for (IndexOfPdpEntries =3D 0; IndexOfPdpEntries < (NumberOfPml4Ent= riesNeeded =3D=3D 1 ? NumberOfPdpEntriesNeeded : 512); IndexOfPdpEntries++,= PageDirectoryPointerEntry++) { - if ((IndexOfPml4Entries =3D=3D 0) && (IndexOfPdpEntries < 4)) { - // - // Skip the < 4G entries - // - continue; - } - - // - // Each Directory Pointer entries points to a page of Page Direc= tory entires. - // So allocate space for them and fill them in in the IndexOfPag= eDirectoryEntries loop. - // - PageDirectoryEntry =3D (UINT64 *)((*PageDirectoryPointerEntry) &= ~mAddressEncMask & gPhyMask); - if (PageDirectoryEntry =3D=3D NULL) { - PageDirectoryEntry =3D AllocatePageTableMemory (1); - ASSERT (PageDirectoryEntry !=3D NULL); - ZeroMem (PageDirectoryEntry, EFI_PAGES_TO_SIZE (1)); - - // - // Fill in a Page Directory Pointer Entries - // - *PageDirectoryPointerEntry =3D (UINT64)(UINTN)PageDirectoryEnt= ry | mAddressEncMask | PAGE_ATTRIBUTE_BITS; - } - - for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntr= ies < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress= +=3D SIZE_2MB) { - // - // Fill in the Page Directory entries - // - *PageDirectoryEntry =3D PageAddress | mAddressEncMask | IA32_P= G_PS | PAGE_ATTRIBUTE_BITS; - } - } - } - } - } -} - /** Create PageTable for SMM use. =20 @@ -332,15 +178,16 @@ SmmInitPageTable ( VOID ) { - EFI_PHYSICAL_ADDRESS Pages; - UINT64 *PTEntry; + UINTN PageTable; LIST_ENTRY *FreePage; UINTN Index; UINTN PageFaultHandlerHookAddress; IA32_IDT_GATE_DESCRIPTOR *IdtEntry; EFI_STATUS Status; + UINT64 *PdptEntry; UINT64 *Pml4Entry; UINT64 *Pml5Entry; + UINT8 PhysicalAddressBits; =20 // // Initialize spin lock @@ -357,59 +204,44 @@ SmmInitPageTable ( } else { mPagingMode =3D m1GPageTableSupport ? Paging4Level1GB : Paging4Level; } + DEBUG ((DEBUG_INFO, "5LevelPaging Needed - %d\n", m5LevelPag= ingNeeded)); DEBUG ((DEBUG_INFO, "1GPageTable Support - %d\n", m1GPageTab= leSupport)); DEBUG ((DEBUG_INFO, "PcdCpuSmmRestrictedMemoryAccess - %d\n", mCpuSmmRes= trictedMemoryAccess)); DEBUG ((DEBUG_INFO, "PhysicalAddressBits - %d\n", mPhysicalA= ddressBits)); - // - // Generate PAE page table for the first 4GB memory space - // - Pages =3D Gen4GPageTable (FALSE); =20 // - // Set IA32_PG_PMNT bit to mask this entry + // Generate initial SMM page table. + // Only map [0, 4G] when PcdCpuSmmRestrictedMemoryAccess is FALSE. // - PTEntry =3D (UINT64 *)(UINTN)Pages; - for (Index =3D 0; Index < 4; Index++) { - PTEntry[Index] |=3D IA32_PG_PMNT; - } - - // - // Fill Page-Table-Level4 (PML4) entry - // - Pml4Entry =3D (UINT64 *)AllocatePageTableMemory (1); - ASSERT (Pml4Entry !=3D NULL); - *Pml4Entry =3D Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS; - ZeroMem (Pml4Entry + 1, EFI_PAGE_SIZE - sizeof (*Pml4Entry)); - - // - // Set sub-entries number - // - SetSubEntriesNum (Pml4Entry, 3); - PTEntry =3D Pml4Entry; + PhysicalAddressBits =3D mCpuSmmRestrictedMemoryAccess ? mPhysicalAddress= Bits : 32; + PageTable =3D GenSmmPageTable (mPagingMode, PhysicalAddressBit= s); =20 if (m5LevelPagingNeeded) { + Pml5Entry =3D (UINT64 *)PageTable; // - // Fill PML5 entry - // - Pml5Entry =3D (UINT64 *)AllocatePageTableMemory (1); - ASSERT (Pml5Entry !=3D NULL); - *Pml5Entry =3D (UINTN)Pml4Entry | mAddressEncMask | PAGE_ATTRIBUTE_BIT= S; - ZeroMem (Pml5Entry + 1, EFI_PAGE_SIZE - sizeof (*Pml5Entry)); - // - // Set sub-entries number + // Set Pml5Entry sub-entries number for smm PF handler usage. // SetSubEntriesNum (Pml5Entry, 1); - PTEntry =3D Pml5Entry; + Pml4Entry =3D (UINT64 *)((*Pml5Entry) & ~mAddressEncMask & gPhyMask); + } else { + Pml4Entry =3D (UINT64 *)PageTable; + } + + // + // Set IA32_PG_PMNT bit to mask first 4 PdptEntry. + // + PdptEntry =3D (UINT64 *)((*Pml4Entry) & ~mAddressEncMask & gPhyMask); + for (Index =3D 0; Index < 4; Index++) { + PdptEntry[Index] |=3D IA32_PG_PMNT; } =20 - if (mCpuSmmRestrictedMemoryAccess) { + if (!mCpuSmmRestrictedMemoryAccess) { // - // When access to non-SMRAM memory is restricted, create page table - // that covers all memory space. + // Set Pml4Entry sub-entries number for smm PF handler usage. // - SetStaticPageTable ((UINTN)PTEntry, mPhysicalAddressBits); - } else { + SetSubEntriesNum (Pml4Entry, 3); + // // Add pages to page pool // @@ -466,7 +298,7 @@ SmmInitPageTable ( // // Return the address of PML4/PML5 (to set CR3) // - return (UINT32)(UINTN)PTEntry; + return (UINT32)PageTable; } =20 /** --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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