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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sami.mujawar@arm.com X-Gm-Message-State: oYMGvESvTe0GMp2Oq215vJE8x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1684847087; bh=ZJ5zsBuiHdlP1RXF3N8r9HY7X28MzXjJxXbQGOX30z8=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=RjEW4i/nI8WI088eWaAD2It1lcPiQNzF68xS8ntbeuC5AVC01qD2qZb7NATI8Lervex beGU7MeCa1tpeHkRTqOx0y/E/TZ29bBlcbABmta2tj4bx0t0uB5gsg0irMUhnX0fDWFve BP1o4lIwosJb7sbgzunvWUNVhkqiuJvVnFo= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1684847088475100009 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" According to the GIC architecture version 3 and 4 specification, the maximum number of INTID bits supported in the CPU interface is 24. Considering this the RegShift variable is not required to be more than 8 bits. Therefore, make the RegShift variable type to UINT8. Also add necessary typecasts when calculating the RegOffset and RegShift values. Signed-off-by: Sami Mujawar --- ArmPkg/Drivers/ArmGic/ArmGicLib.c | 24 ++++++++++---------- ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c | 8 +++---- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmG= icLib.c index 0127cca3bf0567bc80702f415e9cbb9bd2709fbc..8f3315d76f6f2b28a551d734009= 38430ff3e23c7 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c +++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c @@ -228,13 +228,13 @@ ArmGicSetInterruptPriority ( ) { UINT32 RegOffset; - UINTN RegShift; + UINT8 RegShift; ARM_GIC_ARCH_REVISION Revision; UINTN GicCpuRedistributorBase; =20 // Calculate register offset and bit position - RegOffset =3D Source / 4; - RegShift =3D (Source % 4) * 8; + RegOffset =3D (UINT32)(Source / 4); + RegShift =3D (UINT8)((Source % 4) * 8); =20 Revision =3D ArmGicGetSupportedArchRevision (); if ((Revision =3D=3D ARM_GIC_ARCH_REVISION_2) || @@ -272,13 +272,13 @@ ArmGicEnableInterrupt ( ) { UINT32 RegOffset; - UINTN RegShift; + UINT8 RegShift; ARM_GIC_ARCH_REVISION Revision; UINTN GicCpuRedistributorBase; =20 // Calculate enable register offset and bit position - RegOffset =3D Source / 32; - RegShift =3D Source % 32; + RegOffset =3D (UINT32)(Source / 32); + RegShift =3D (UINT8)(Source % 32); =20 Revision =3D ArmGicGetSupportedArchRevision (); if ((Revision =3D=3D ARM_GIC_ARCH_REVISION_2) || @@ -317,13 +317,13 @@ ArmGicDisableInterrupt ( ) { UINT32 RegOffset; - UINTN RegShift; + UINT8 RegShift; ARM_GIC_ARCH_REVISION Revision; UINTN GicCpuRedistributorBase; =20 // Calculate enable register offset and bit position - RegOffset =3D Source / 32; - RegShift =3D Source % 32; + RegOffset =3D (UINT32)(Source / 32); + RegShift =3D (UINT8)(Source % 32); =20 Revision =3D ArmGicGetSupportedArchRevision (); if ((Revision =3D=3D ARM_GIC_ARCH_REVISION_2) || @@ -361,14 +361,14 @@ ArmGicIsInterruptEnabled ( ) { UINT32 RegOffset; - UINTN RegShift; + UINT8 RegShift; ARM_GIC_ARCH_REVISION Revision; UINTN GicCpuRedistributorBase; UINT32 Interrupts; =20 // Calculate enable register offset and bit position - RegOffset =3D Source / 32; - RegShift =3D Source % 32; + RegOffset =3D (UINT32)(Source / 32); + RegShift =3D (UINT8)(Source % 32); =20 Revision =3D ArmGicGetSupportedArchRevision (); if ((Revision =3D=3D ARM_GIC_ARCH_REVISION_2) || diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c b/ArmPkg/Drivers/Arm= Gic/GicV2/ArmGicV2Dxe.c index fb40f56ff9231f3a28c3d90939bfd25ac3432f89..ba43150fe57015994573d82c88d= 6a8d9f3174533 100644 --- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c +++ b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c @@ -2,7 +2,7 @@ =20 Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.
Portions copyright (c) 2010, Apple Inc. All rights reserved.
-Portions copyright (c) 2011-2021, Arm Ltd. All rights reserved.
+Portions copyright (c) 2011-2023, Arm Ltd. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -393,7 +393,7 @@ GicV2DxeInitialize ( EFI_STATUS Status; UINTN Index; UINT32 RegOffset; - UINTN RegShift; + UINT8 RegShift; UINT32 CpuTarget; =20 // Make sure the Interrupt Controller Protocol is not already installed = in @@ -408,8 +408,8 @@ GicV2DxeInitialize ( GicV2DisableInterruptSource (&gHardwareInterruptV2Protocol, Index); =20 // Set Priority - RegOffset =3D Index / 4; - RegShift =3D (Index % 4) * 8; + RegOffset =3D (UINT32)(Index / 4); + RegShift =3D (UINT8)((Index % 4) * 8); MmioAndThenOr32 ( mGicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset), ~(0xff << RegShift), --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#105178): https://edk2.groups.io/g/devel/message/105178 Mute This Topic: https://groups.io/mt/99086457/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-