From nobody Sat Apr 20 00:29:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+104832+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104832+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1684116526; cv=none; d=zohomail.com; s=zohoarc; b=Uf1eXky/Xgtn7g14Y5SsqofIVvMOc5rqXCu7F3y14vdbirsE9xPTG6Buq8T3h3Eak/dhAJWJbVS2h9hCZdX32gLmGsCssexKH+Axrv+ZaeU462Yiny65CGA4KrrNargcXgMEWCuQBTwRkn28iOYXGi4hjGpui0A8zpxkqytbz4g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684116526; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=TEWkr2PWpSQEoaAak+5ENX/F64d3Z/r+VxtJgVI0G9Q=; b=JOYTH/oOLmzNXGaXFgHU+aQxZMzGFOcdpGh6XQpuI0J7Ke87Gh9xtu/4/C8dtr/H8HD8NBNvEPFOWWmKwDho17k9JgikagFVVkzbnPFuD9NPbsFJHAHNI/jdVf9x+eD//fAppl97fJyRj1Bne53h2BF3eu6hS7OdJmHgdPdtzC8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104832+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1684116526118183.7353391753113; Sun, 14 May 2023 19:08:46 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 4tKjYY1788612xGaWMflNeXy; Sun, 14 May 2023 19:08:45 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.79068.1684114925302985385 for ; Sun, 14 May 2023 18:42:05 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10710"; a="331457188" X-IronPort-AV: E=Sophos;i="5.99,275,1677571200"; d="scan'208";a="331457188" X-Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2023 18:42:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10710"; a="824987033" X-IronPort-AV: E=Sophos;i="5.99,275,1677571200"; d="scan'208";a="824987033" X-Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.151]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2023 18:42:02 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: "Liu, Zhiguang" , Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann , Debkumar De , Catharine West , Zhiguang Liu Subject: [edk2-devel] [PATCH v6 1/5] UefiCpuPkg/ResetVector: Rename macros about page table. Date: Mon, 15 May 2023 09:41:34 +0800 Message-Id: <20230515014138.1321-2-zhiguang.liu@intel.com> In-Reply-To: <20230515014138.1321-1-zhiguang.liu@intel.com> References: <20230515014138.1321-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,zhiguang.liu@intel.com X-Gm-Message-State: Gwyfl5HW89k3IM1tHweXhlx4x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1684116525; bh=rTmADqNm+iNA7yIa6pPBkpB/lNp/TNWMfmjOiWH/g9U=; h=Cc:Date:From:Reply-To:Subject:To; b=iaPfT+DiDEYF8jRwlp5xmluLmBevjILe5CGra5fQXc33aaTy1NWHxU72OzwQAoaIVmp 8fxJrlIMJSK1siwv7xkxLNGoicEJ4EfcklA3bqr1tT0ucaezvYFoevOnpAgqfOSjTZ4Z0 3YWjNSs2OCN2nGfswSvpp0pR4KhZDJ/1PtI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1684116528351100001 Content-Type: text/plain; charset="utf-8" From: "Liu, Zhiguang" This patch only renames macro, with no code logic impacted. Two purpose to rename macro: 1. Align some macro name in PageTables1G.asm and PageTables2M.asm, so that these two files can be easily combined later. 2. Some Macro names such as PDP are not accurate, since 4 level page entry also uses this macro. PAGE_NLE (no leaf entry) is better Cc: Eric Dong Reviewed-by: Ray Ni Cc: Rahul Kumar Tested-by: Gerd Hoffmann Acked-by: Gerd Hoffmann Cc: Debkumar De Cc: Catharine West Signed-off-by: Zhiguang Liu --- .../ResetVector/Vtf0/X64/PageTables1G.asm | 26 +++++++++----- .../ResetVector/Vtf0/X64/PageTables2M.asm | 35 +++++++++++-------- 2 files changed, 39 insertions(+), 22 deletions(-) diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm b/UefiCpuPkg/= ResetVector/Vtf0/X64/PageTables1G.asm index 19bd3d5a92..20a61f949c 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm @@ -2,7 +2,7 @@ ; @file ; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x8000000000 (512= GB) ; -; Copyright (c) 2021, Intel Corporation. All rights reserved.
+; Copyright (c) 2021 - 2023, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; Linear-Address Translation to a 1-GByte Page ; @@ -12,11 +12,18 @@ BITS 64 =20 %define ALIGN_TOP_TO_4K_FOR_PAGING =20 -%define PAGE_PDP_ATTR (PAGE_ACCESSED + \ +; +; Page table non-leaf entry attribute +; +%define PAGE_NLE_ATTR (PAGE_ACCESSED + \ PAGE_READ_WRITE + \ PAGE_PRESENT) =20 -%define PAGE_PDP_1G_ATTR (PAGE_ACCESSED + \ +; +; Page table big leaf entry attribute: +; PDPTE 1GB entry or PDE 2MB entry +; +%define PAGE_BLE_ATTR (PAGE_ACCESSED + \ PAGE_READ_WRITE + \ PAGE_DIRTY + \ PAGE_PRESENT + \ @@ -25,10 +32,13 @@ BITS 64 %define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) %define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x)) =20 -%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ - PAGE_PDP_ATTR) +; +; Page table non-leaf entry +; +%define PAGE_NLE(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ + PAGE_NLE_ATTR) =20 -%define PDP_1G(x) ((x << 30) + PAGE_PDP_1G_ATTR) +%define PAGE_PDPTE_1GB(x) ((x << 30) + PAGE_BLE_ATTR) =20 ALIGN 16 =20 @@ -37,7 +47,7 @@ TopLevelPageDirectory: ; ; Top level Page Directory Pointers (1 * 512GB entry) ; - DQ PDP(0x1000) + DQ PAGE_NLE(0x1000) =20 TIMES 0x1000-PGTBLS_OFFSET($) DB 0 ; @@ -45,7 +55,7 @@ TopLevelPageDirectory: ; %assign i 0 %rep 512 - DQ PDP_1G(i) + DQ PAGE_PDPTE_1GB(i) %assign i i+1 %endrep TIMES 0x2000-PGTBLS_OFFSET($) DB 0 diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm b/UefiCpuPkg/= ResetVector/Vtf0/X64/PageTables2M.asm index b97df384ac..1221b023fe 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm @@ -2,7 +2,7 @@ ; @file ; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x100000000 (4GB) ; -; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.
+; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;-------------------------------------------------------------------------= ----- @@ -11,29 +11,36 @@ BITS 64 =20 %define ALIGN_TOP_TO_4K_FOR_PAGING =20 -%define PAGE_2M_PDE_ATTR (PAGE_SIZE + \ +; +; Page table big leaf entry attribute: +; PDPTE 1GB entry or PDE 2MB entry +; +%define PAGE_BLE_ATTR (PAGE_SIZE + \ PAGE_ACCESSED + \ PAGE_DIRTY + \ PAGE_READ_WRITE + \ PAGE_PRESENT) =20 -%define PAGE_PDP_ATTR (PAGE_ACCESSED + \ - PAGE_READ_WRITE + \ - PAGE_PRESENT) +; +; Page table non-leaf entry attribute +; +%define PAGE_NLE_ATTR (PAGE_ACCESSED + \ + PAGE_READ_WRITE + \ + PAGE_PRESENT) =20 %define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) %define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x)) =20 -%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ - PAGE_PDP_ATTR) -%define PTE_2MB(x) ((x << 21) + PAGE_2M_PDE_ATTR) +%define PAGE_NLE(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ + PAGE_NLE_ATTR) +%define PAGE_PDE_2MB(x) ((x << 21) + PAGE_BLE_ATTR) =20 TopLevelPageDirectory: =20 ; ; Top level Page Directory Pointers (1 * 512GB entry) ; - DQ PDP(0x1000) + DQ PAGE_NLE(0x1000) =20 =20 ; @@ -41,10 +48,10 @@ TopLevelPageDirectory: ; TIMES 0x1000-PGTBLS_OFFSET($) DB 0 =20 - DQ PDP(0x2000) - DQ PDP(0x3000) - DQ PDP(0x4000) - DQ PDP(0x5000) + DQ PAGE_NLE(0x2000) + DQ PAGE_NLE(0x3000) + DQ PAGE_NLE(0x4000) + DQ PAGE_NLE(0x5000) =20 ; ; Page Table Entries (2048 * 2MB entries =3D> 4GB) @@ -53,7 +60,7 @@ TopLevelPageDirectory: =20 %assign i 0 %rep 0x800 - DQ PTE_2MB(i) + DQ PAGE_PDE_2MB(i) %assign i i+1 %endrep =20 --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#104832): https://edk2.groups.io/g/devel/message/104832 Mute This Topic: https://groups.io/mt/98894731/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 00:29:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+104833+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104833+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1684115029; cv=none; d=zohomail.com; s=zohoarc; b=Vitoa1Cvibp9Y+4uhzIn9ZPeOsM9m46oyhNUk78jDRTWX/46cKnzTNnoK1zw0zPU+KTVQUSsZmzDLbfOAnKd2l/HsdfAtfrjfAoa5MOk29qM9zIXMRZfxcZoqLaOLgJ0kWxj9cPV6dYVV+4oBsQ/fgyBVu42J3oMXtjWHIlb/Ro= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684115029; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=BKirappkH7GJrNG7GnZz5P7tnIqVQ1HtbqyaiDqH9VA=; b=HwgsSErNcNHzDCUt4oy/pyodakuClSPEYrmwhgkO2tcgcWZsE+3XJtRRFh0BV/QRYdBJCCkyZC0xtBT4EeVJgEKKuK+aeSNWsNHiaIPRURgJMqFnzl/BcsWx6Pix32eQRCpgAJrsO5GMUOZopQRJQJPVLghySOamokY5IL3Rom0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104833+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1684115029577750.6079314581026; Sun, 14 May 2023 18:43:49 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 35PTYY1788612xQrczxRrr14; Sun, 14 May 2023 18:43:49 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.79068.1684114925302985385 for ; Sun, 14 May 2023 18:42:07 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10710"; a="331457208" X-IronPort-AV: E=Sophos;i="5.99,275,1677571200"; d="scan'208";a="331457208" X-Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2023 18:42:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10710"; a="824987052" X-IronPort-AV: E=Sophos;i="5.99,275,1677571200"; d="scan'208";a="824987052" X-Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.151]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2023 18:42:04 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: "Liu, Zhiguang" , Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann , Debkumar De , Catharine West , Zhiguang Liu Subject: [edk2-devel] [PATCH v6 2/5] UefiCpuPkg/ResetVector: Simplify page table creation in ResetVector Date: Mon, 15 May 2023 09:41:35 +0800 Message-Id: <20230515014138.1321-3-zhiguang.liu@intel.com> In-Reply-To: <20230515014138.1321-1-zhiguang.liu@intel.com> References: <20230515014138.1321-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,zhiguang.liu@intel.com X-Gm-Message-State: YQnSp9QAGwuGuis5EFqrGXtex1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1684115029; bh=mW50jqHXH2Emc1WExhKGAhKq3sF1G/RGOf+SUaEfthQ=; h=Cc:Date:From:Reply-To:Subject:To; b=BJK+daayX+TpLPmTsjegM03Qu9xNTRvut8sKYngmRF84uZ8cMENnDWNe1JMcGkx6Y6g ZSC5pCxTumha8D5fMqUqW9GCgv/9eosas7EmcEScg0qSwOJHEUtUwX3F/IJRfj0mFlaMg T+8JS/1M6ZLXQTm8l5R56cBLO8R8BKBC57Q= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1684115030707100001 Content-Type: text/plain; charset="utf-8" From: "Liu, Zhiguang" Currently, page table creation has many hard-code values about the offset to the start of page table. To simplify it, add Labels such as Pml4, Pdp and Pd, so that we can remove many hard-code values Cc: Eric Dong Reviewed-by: Ray Ni Cc: Rahul Kumar Tested-by: Gerd Hoffmann Acked-by: Gerd Hoffmann Cc: Debkumar De Cc: Catharine West Signed-off-by: Zhiguang Liu --- .../ResetVector/Vtf0/Ia32/PageTables64.asm | 4 +-- .../ResetVector/Vtf0/X64/PageTables1G.asm | 18 ++++------ .../ResetVector/Vtf0/X64/PageTables2M.asm | 34 ++++++++----------- 3 files changed, 24 insertions(+), 32 deletions(-) diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm b/UefiCpuPkg= /ResetVector/Vtf0/Ia32/PageTables64.asm index 87a4125d4b..f188da20ba 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm @@ -2,7 +2,7 @@ ; @file ; Sets the CR3 register for 64-bit paging ; -; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.
+; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;-------------------------------------------------------------------------= ----- @@ -17,7 +17,7 @@ SetCr3ForPageTables64: ; ; These pages are built into the ROM image in X64/PageTables.asm ; - mov eax, ADDR_OF(TopLevelPageDirectory) + mov eax, ADDR_OF(Pml4) mov cr3, eax =20 OneTimeCallRet SetCr3ForPageTables64 diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm b/UefiCpuPkg/= ResetVector/Vtf0/X64/PageTables1G.asm index 20a61f949c..f5b8da0015 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm @@ -29,35 +29,31 @@ BITS 64 PAGE_PRESENT + \ PAGE_SIZE) =20 -%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) -%define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x)) - ; ; Page table non-leaf entry ; -%define PAGE_NLE(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ +%define PAGE_NLE(address) (ADDR_OF(address) + \ PAGE_NLE_ATTR) =20 %define PAGE_PDPTE_1GB(x) ((x << 30) + PAGE_BLE_ATTR) =20 ALIGN 16 =20 -TopLevelPageDirectory: - +Pml4: ; - ; Top level Page Directory Pointers (1 * 512GB entry) + ; PML4 (1 * 512GB entry) ; - DQ PAGE_NLE(0x1000) + DQ PAGE_NLE(Pdp) + TIMES 0x1000 - ($ - Pml4) DB 0 =20 - TIMES 0x1000-PGTBLS_OFFSET($) DB 0 +Pdp: ; - ; Next level Page Directory Pointers (512 * 1GB entries =3D> 512GB) + ; Page-directory pointer table (512 * 1GB entries =3D> 512GB) ; %assign i 0 %rep 512 DQ PAGE_PDPTE_1GB(i) %assign i i+1 %endrep - TIMES 0x2000-PGTBLS_OFFSET($) DB 0 =20 EndOfPageTables: diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm b/UefiCpuPkg/= ResetVector/Vtf0/X64/PageTables2M.asm index 1221b023fe..731dabad4d 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm @@ -28,36 +28,32 @@ BITS 64 PAGE_READ_WRITE + \ PAGE_PRESENT) =20 -%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) -%define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x)) - -%define PAGE_NLE(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ +%define PAGE_NLE(address) (ADDR_OF(address) + \ PAGE_NLE_ATTR) %define PAGE_PDE_2MB(x) ((x << 21) + PAGE_BLE_ATTR) =20 -TopLevelPageDirectory: - +Pml4: ; - ; Top level Page Directory Pointers (1 * 512GB entry) + ; PML4 (1 * 512GB entry) ; - DQ PAGE_NLE(0x1000) - + DQ PAGE_NLE(Pdp) + TIMES 0x1000 - ($ - Pml4) DB 0 =20 +Pdp: ; - ; Next level Page Directory Pointers (4 * 1GB entries =3D> 4GB) + ; Page-directory pointer table (4 * 1GB entries =3D> 4GB) ; - TIMES 0x1000-PGTBLS_OFFSET($) DB 0 - - DQ PAGE_NLE(0x2000) - DQ PAGE_NLE(0x3000) - DQ PAGE_NLE(0x4000) - DQ PAGE_NLE(0x5000) + DQ PAGE_NLE(Pd) + DQ PAGE_NLE(Pd + 0x1000) + DQ PAGE_NLE(Pd + 0x2000) + DQ PAGE_NLE(Pd + 0x3000) + TIMES 0x1000 - ($ - Pdp) DB 0 =20 +Pd: ; - ; Page Table Entries (2048 * 2MB entries =3D> 4GB) + ; Page-Directory (2048 * 2MB entries =3D> 4GB) + ; Four pages below, each is pointed by one entry in Pdp. ; - TIMES 0x2000-PGTBLS_OFFSET($) DB 0 - %assign i 0 %rep 0x800 DQ PAGE_PDE_2MB(i) --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#104833): https://edk2.groups.io/g/devel/message/104833 Mute This Topic: https://groups.io/mt/98894732/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 00:29:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+104834+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104834+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1684115377; cv=none; d=zohomail.com; s=zohoarc; b=MA+FnVndlN2qZtWu49Ytlot8FeNQ0+E8UErwNXlOly+8uDSR5pzCM7QOVf1w2pgX4Ox1pGwwuB2uZhr8ujU0iaTmqXgu8daAI2nIxH4ttqEKyjsmR7APkYVYGsY19UUjSL8jkW8Y0NAfQx+XXyWaZorssUK5Y83urxpJU38yyTU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684115377; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=HqvRotv65ebM/cv+ke5pMUHn3IEv+kvZJKw+tffi1as=; b=BWB0Dt+UNvheUuE2YGY7JQz+UAiFiIUlrJhaQZDAzM3bQ+qViXQCif4dqlmgTA7GsqZES/WJm1JGrStt/MKJ5ZNvF3w1pvkTYOaApGRclQ0zKoBoBdDefrAl9XPhk62HNj4HglLgGMHjGhOKVdr+3lIEo+e8idiOEmLiOPqoGm0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104834+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1684115377516878.1749019105446; Sun, 14 May 2023 18:49:37 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id NFMKYY1788612xF6jN0EuTGA; Sun, 14 May 2023 18:49:35 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.79068.1684114925302985385 for ; Sun, 14 May 2023 18:42:10 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10710"; a="331457228" X-IronPort-AV: E=Sophos;i="5.99,275,1677571200"; d="scan'208";a="331457228" X-Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2023 18:42:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10710"; a="824987080" X-IronPort-AV: E=Sophos;i="5.99,275,1677571200"; d="scan'208";a="824987080" X-Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.151]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2023 18:42:07 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: "Liu, Zhiguang" , Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann , Debkumar De , Catharine West , Zhiguang Liu Subject: [edk2-devel] [PATCH v6 3/5] UefiCpuPkg/ResetVector: Combine PageTables1G.asm and PageTables2M.asm Date: Mon, 15 May 2023 09:41:36 +0800 Message-Id: <20230515014138.1321-4-zhiguang.liu@intel.com> In-Reply-To: <20230515014138.1321-1-zhiguang.liu@intel.com> References: <20230515014138.1321-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,zhiguang.liu@intel.com X-Gm-Message-State: 4q4ICJAydPMpgX9H4Xznk3N5x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1684115375; bh=3pc0gcJ1JGvA51Hp/Wdv549Vlc2odoLPWrGxmc1RvhY=; h=Cc:Date:From:Reply-To:Subject:To; b=NkVv3I7oSM8XeQ1PR0of3ABiMKruxfsJJaCmW3Wls95TSpN7Wd+OYD8Xz925eQMQjAd m8dPDYf4j6ayhnR49N91REKmxr+nXi0a+IAtTl96S9BGmFKEiEMhRdXruJdhk3fpytsJP Tsx0l4rdICR4i2dvmai/O0J8qSG3faKDFf8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1684115378250100005 Content-Type: text/plain; charset="utf-8" From: "Liu, Zhiguang" Combine PageTables1G.asm and PageTables2M.asm to reuse code. Cc: Eric Dong Reviewed-by: Ray Ni Cc: Rahul Kumar Tested-by: Gerd Hoffmann Acked-by: Gerd Hoffmann Cc: Debkumar De Cc: Catharine West Signed-off-by: Zhiguang Liu --- UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 8 +-- .../X64/{PageTables1G.asm =3D> PageTables.asm} | 38 ++++++++--- .../ResetVector/Vtf0/X64/PageTables2M.asm | 63 ------------------- 3 files changed, 33 insertions(+), 76 deletions(-) rename UefiCpuPkg/ResetVector/Vtf0/X64/{PageTables1G.asm =3D> PageTables.a= sm} (57%) delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb b/UefiCpuPkg/ResetVecto= r/Vtf0/Vtf0.nasmb index bdea1fb875..136361e62c 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb +++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb @@ -2,7 +2,7 @@ ; @file ; This file includes all other code files to assemble the reset vector code ; -; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.
+; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;-------------------------------------------------------------------------= ----- @@ -38,11 +38,7 @@ %include "PageTables.inc" =20 %ifdef ARCH_X64 - %ifdef PAGE_TABLE_1G - %include "X64/PageTables1G.asm" - %else - %include "X64/PageTables2M.asm" - %endif + %include "X64/PageTables.asm" %endif =20 %ifdef DEBUG_PORT80 diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm b/UefiCpuPkg/= ResetVector/Vtf0/X64/PageTables.asm similarity index 57% rename from UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm rename to UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm index f5b8da0015..9b492b063f 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm @@ -1,10 +1,11 @@ ;-------------------------------------------------------------------------= ----- ; @file -; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x8000000000 (512= GB) +; Emits Page Tables for 1:1 mapping. +; If using 1G page table, map addresses 0 - 0x8000000000 (512GB), +; else, map addresses 0 - 0x100000000 (4GB) ; ; Copyright (c) 2021 - 2023, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent -; Linear-Address Translation to a 1-GByte Page ; ;-------------------------------------------------------------------------= ----- =20 @@ -36,6 +37,7 @@ BITS 64 PAGE_NLE_ATTR) =20 %define PAGE_PDPTE_1GB(x) ((x << 30) + PAGE_BLE_ATTR) +%define PAGE_PDE_2MB(x) ((x << 21) + PAGE_BLE_ATTR) =20 ALIGN 16 =20 @@ -46,14 +48,36 @@ Pml4: DQ PAGE_NLE(Pdp) TIMES 0x1000 - ($ - Pml4) DB 0 =20 +%ifdef PAGE_TABLE_1G Pdp: ; ; Page-directory pointer table (512 * 1GB entries =3D> 512GB) ; -%assign i 0 -%rep 512 - DQ PAGE_PDPTE_1GB(i) - %assign i i+1 -%endrep + %assign i 0 + %rep 512 + DQ PAGE_PDPTE_1GB(i) + %assign i i+1 + %endrep +%else +Pdp: + ; + ; Page-directory pointer table (4 * 1GB entries =3D> 4GB) + ; + DQ PAGE_NLE(Pd) + DQ PAGE_NLE(Pd + 0x1000) + DQ PAGE_NLE(Pd + 0x2000) + DQ PAGE_NLE(Pd + 0x3000) + TIMES 0x1000 - ($ - Pdp) DB 0 =20 +Pd: + ; + ; Page-Directory (2048 * 2MB entries =3D> 4GB) + ; Four pages below, each is pointed by one entry in Pdp. + ; + %assign i 0 + %rep 0x800 + DQ PAGE_PDE_2MB(i) + %assign i i+1 + %endrep +%endif EndOfPageTables: diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm b/UefiCpuPkg/= ResetVector/Vtf0/X64/PageTables2M.asm deleted file mode 100644 index 731dabad4d..0000000000 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm +++ /dev/null @@ -1,63 +0,0 @@ -;-------------------------------------------------------------------------= ----- -; @file -; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x100000000 (4GB) -; -; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.
-; SPDX-License-Identifier: BSD-2-Clause-Patent -; -;-------------------------------------------------------------------------= ----- - -BITS 64 - -%define ALIGN_TOP_TO_4K_FOR_PAGING - -; -; Page table big leaf entry attribute: -; PDPTE 1GB entry or PDE 2MB entry -; -%define PAGE_BLE_ATTR (PAGE_SIZE + \ - PAGE_ACCESSED + \ - PAGE_DIRTY + \ - PAGE_READ_WRITE + \ - PAGE_PRESENT) - -; -; Page table non-leaf entry attribute -; -%define PAGE_NLE_ATTR (PAGE_ACCESSED + \ - PAGE_READ_WRITE + \ - PAGE_PRESENT) - -%define PAGE_NLE(address) (ADDR_OF(address) + \ - PAGE_NLE_ATTR) -%define PAGE_PDE_2MB(x) ((x << 21) + PAGE_BLE_ATTR) - -Pml4: - ; - ; PML4 (1 * 512GB entry) - ; - DQ PAGE_NLE(Pdp) - TIMES 0x1000 - ($ - Pml4) DB 0 - -Pdp: - ; - ; Page-directory pointer table (4 * 1GB entries =3D> 4GB) - ; - DQ PAGE_NLE(Pd) - DQ PAGE_NLE(Pd + 0x1000) - DQ PAGE_NLE(Pd + 0x2000) - DQ PAGE_NLE(Pd + 0x3000) - TIMES 0x1000 - ($ - Pdp) DB 0 - -Pd: - ; - ; Page-Directory (2048 * 2MB entries =3D> 4GB) - ; Four pages below, each is pointed by one entry in Pdp. - ; -%assign i 0 -%rep 0x800 - DQ PAGE_PDE_2MB(i) - %assign i i+1 -%endrep - -EndOfPageTables: --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#104834): https://edk2.groups.io/g/devel/message/104834 Mute This Topic: https://groups.io/mt/98894734/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 00:29:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+104835+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104835+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1684115131; cv=none; d=zohomail.com; s=zohoarc; b=c1PDr+h4CueMnlIlKe5C0EimIRMdNnMOK1T++mbotK3bTUkWWfBY1Lvh0rPU88V4j1HSBskcPOYgKhO/JIjHgTorF1xCz7b/0IkR1jyvATNTaZ52NBJ1wafM1IeBHZEgEk33K63zwkj9OjQEk+7+ONU2p6uRMfhcUJ7+Wb4jHvw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684115131; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=P7xonIJr9HaTwa5HM10G3xk2pG4+roGEdQENuqRqfBc=; b=f3EqQvjg9ecHzCBLbcUrlP2M4SEtbr0/uJbrA2ZQVw3VbS9LVjpM15B36KFOrcrNDDwDeY1iuLpyU5qYYcqhggf9wBeFEJVejakGZ/weG1+S8TFsDasDCT01uerBIOS2WC+yxPHoW4fHVM9PNh24c1WtFuYvFdtRFwAQh4rcqUk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104835+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1684115131433455.45756137292517; Sun, 14 May 2023 18:45:31 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id AskdYY1788612xp2jddCKqtD; Sun, 14 May 2023 18:45:31 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.79068.1684114925302985385 for ; Sun, 14 May 2023 18:42:12 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10710"; a="331457247" X-IronPort-AV: E=Sophos;i="5.99,275,1677571200"; d="scan'208";a="331457247" X-Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2023 18:42:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10710"; a="824987120" X-IronPort-AV: E=Sophos;i="5.99,275,1677571200"; d="scan'208";a="824987120" X-Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.151]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2023 18:42:09 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: "Liu, Zhiguang" , Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann , Debkumar De , Catharine West , Zhiguang Liu Subject: [edk2-devel] [PATCH v6 4/5] UefiCpuPkg/ResetVector: Modify Page Table in ResetVector Date: Mon, 15 May 2023 09:41:37 +0800 Message-Id: <20230515014138.1321-5-zhiguang.liu@intel.com> In-Reply-To: <20230515014138.1321-1-zhiguang.liu@intel.com> References: <20230515014138.1321-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,zhiguang.liu@intel.com X-Gm-Message-State: 9JdRMEbHTgXInSXOhXnYS2j5x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1684115131; bh=Kozh3YenvQmtzF3/drCJOpsMCXmq3n8ALgsjuXkS22Q=; h=Cc:Date:From:Reply-To:Subject:To; b=v4wdg6DIjmEnmh9LlNa9wVuJoWcnPCc2iZhONz927siknHGaHPqqDwNEPqmwP8fHkxg bE6LvTxwGvVOUNjYcYJk9RYUsZuTV3vDerfnDM1Y0/B0eVx5w5ZawfFg5OIBRYpQOm39q 0KXCY/H7CLhTpwVt/LxLm8ik/WXRyr/XEZk= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1684115133237100005 Content-Type: text/plain; charset="utf-8" From: "Liu, Zhiguang" In ResetVector, if create page table, its highest address is fixed because after page table, code layout is fixed(4K for normal code, and another 4K only contains reset vector code). Today's implementation organizes the page table as following if 1G page table is used: 4G-16K: PML4 page (PML4[0] points to 4G-12K) 4G-12K: PDP page CR3 is set to 4G-16K When 2M page table is used, the layout is as following: 4G-32K: PML4 page (PML4[0] points to 4G-28K) 4G-28K: PDP page (PDP entries point to PD pages) 4G-24K: PD page mapping 0-1G 4G-20K: PD page mapping 1-2G 4G-16K: PD page mapping 2-3G 4G-12K: PD page mapping 3-4G CR3 is set to 4G-32K CR3 doesn't point to a fixed location which is a bit hard to debug at runtime. The new page table layout will always put PML4 in highest address When 1G page table is used, the layout is as following: 4G-16K: PDP page 4G-12K: PML4 page (PML4[0] points to 4G-16K) When 2M page table is used, the layout is as following: 4G-32K: PD page mapping 0-1G 4G-28K: PD page mapping 1-2G 4G-24K: PD page mapping 2-3G 4G-20K: PD page mapping 3-4G 4G-16K: PDP page (PDP entries point to PD pages) 4G-12K: PML4 page (PML4[0] points to 4G-16K) CR3 is always set to 4G-12K So, this patch can improve debuggability by make sure the init CR3 pointing to a fixed address(4G-12K). Cc: Eric Dong Reviewed-by: Ray Ni Cc: Rahul Kumar Tested-by: Gerd Hoffmann Acked-by: Gerd Hoffmann Cc: Debkumar De Cc: Catharine West Signed-off-by: Zhiguang Liu --- .../ResetVector/Vtf0/X64/PageTables.asm | 33 ++++++++++--------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm b/UefiCpuPkg/Re= setVector/Vtf0/X64/PageTables.asm index 9b492b063f..d66fb62c34 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm @@ -41,13 +41,6 @@ BITS 64 =20 ALIGN 16 =20 -Pml4: - ; - ; PML4 (1 * 512GB entry) - ; - DQ PAGE_NLE(Pdp) - TIMES 0x1000 - ($ - Pml4) DB 0 - %ifdef PAGE_TABLE_1G Pdp: ; @@ -59,15 +52,6 @@ Pdp: %assign i i+1 %endrep %else -Pdp: - ; - ; Page-directory pointer table (4 * 1GB entries =3D> 4GB) - ; - DQ PAGE_NLE(Pd) - DQ PAGE_NLE(Pd + 0x1000) - DQ PAGE_NLE(Pd + 0x2000) - DQ PAGE_NLE(Pd + 0x3000) - TIMES 0x1000 - ($ - Pdp) DB 0 =20 Pd: ; @@ -79,5 +63,22 @@ Pd: DQ PAGE_PDE_2MB(i) %assign i i+1 %endrep +Pdp: + ; + ; Page-directory pointer table (4 * 1GB entries =3D> 4GB) + ; + DQ PAGE_NLE(Pd) + DQ PAGE_NLE(Pd + 0x1000) + DQ PAGE_NLE(Pd + 0x2000) + DQ PAGE_NLE(Pd + 0x3000) + TIMES 0x1000 - ($ - Pdp) DB 0 + %endif + +Pml4: + ; + ; PML4 (1 * 512GB entry) + ; + DQ PAGE_NLE(Pdp) + TIMES 0x1000 - ($ - Pml4) DB 0 EndOfPageTables: --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#104835): https://edk2.groups.io/g/devel/message/104835 Mute This Topic: https://groups.io/mt/98894735/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 00:29:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+104836+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104836+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1684115133; cv=none; d=zohomail.com; s=zohoarc; b=DctvPhuA2kAzMSXSq2bZNCcYEMWsERx0Z7TxQ/b+YWgtVF2zAYMzG7SlFzt4gFFh7wKVHlua3BOokfSNKwl1f3QwTt5Z2ScOnxhDk47Xq68xb9zig/e+6JsA+kLxM6uMnjvsTGQnDM96Jum/ADuaUrFiNrqwnigyHQ/JqhAymdY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684115133; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=MU9M+VUhWvs+80aU0ClQ7WFK6gdsXorxksXqpVvar74=; b=FwoiIt/KBcZ7O4xUNW+bP9hV1fJrquZCElauUKK6ooWTZsaBrUsy/v9kMT8uq/qUn4os8J9DPksEPITf4NkMK5nAS8QR8FOxEQcX9DI4KJSjyT0YvE2JM2/N5G9W47474z/VE/f/L2Ua/bVvo7OSDdnie01fPsEwLndq63EvY4I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104836+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1684115133041722.0607737382882; Sun, 14 May 2023 18:45:33 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id rF80YY1788612xCPPEOH2bUL; Sun, 14 May 2023 18:45:32 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.79068.1684114925302985385 for ; Sun, 14 May 2023 18:42:15 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10710"; a="331457262" X-IronPort-AV: E=Sophos;i="5.99,275,1677571200"; d="scan'208";a="331457262" X-Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2023 18:42:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10710"; a="824987154" X-IronPort-AV: E=Sophos;i="5.99,275,1677571200"; d="scan'208";a="824987154" X-Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.151]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2023 18:42:12 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann , Debkumar De , Catharine West Subject: [edk2-devel] [PATCH v6 5/5] UefiCpuPkg/ResetVector: Support 5 level page table in ResetVector Date: Mon, 15 May 2023 09:41:38 +0800 Message-Id: <20230515014138.1321-6-zhiguang.liu@intel.com> In-Reply-To: <20230515014138.1321-1-zhiguang.liu@intel.com> References: <20230515014138.1321-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,zhiguang.liu@intel.com X-Gm-Message-State: COm2MH7jTB0aXcSunaJPCMwxx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1684115132; bh=r3yejXcs/LqdXz26kDhOXswnCcRNH3drt187IRoAQaw=; h=Cc:Date:From:Reply-To:Subject:To; b=qO6QW3hlHu+ACgHDYqZayLW/bwivyrHtL8AWoDKFZSH26ztcEWIdmFrrlkum5u8prh8 XbCR+/mkskiA6AV5DSdUMGyPuC1y5V3xsVoLiHHEc5YCFx9PN3/arPLhuzaRTg/0/QqN4 Vd2yk8S1RnDyok5Xx1M4r0sLGNUjJiKFq94= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1684115133623100007 Content-Type: text/plain; charset="utf-8" Add a macro USE_5_LEVEL_PAGE_TABLE to determine whether to create 5 level page table. If macro USE_5_LEVEL_PAGE_TABLE is defined, PML5Table is created at (4G-12K), while PML4Table is at (4G-16K). In runtime check, if 5level paging is supported, use PML5Table, otherwise, use PML4Table. If macro USE_5_LEVEL_PAGE_TABLE is not defined, to save space, 5level paging is not created, and 4level paging is at (4G-12K) and be used. V6: In previous version, I merge code from Ia32\PageTables64.asm into Ia32\Flat32ToFlat64.asm to reduce files. However, reset vector from OvmfPkg\Bhyve\ResetVector needs the code from Flat32ToFlat64.asm, and needs its OneTimeCall SetCr3ForPageTables64. To be compatible, in this version, I keep the file PageTables64.asm, and implement 5level paging logic there. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Debkumar De Cc: Catharine West Signed-off-by: Zhiguang Liu Reviewed-by: Ray Ni --- .../ResetVector/Vtf0/Ia32/PageTables64.asm | 20 +++++++++++++++++++ .../ResetVector/Vtf0/X64/PageTables.asm | 9 +++++++++ 2 files changed, 29 insertions(+) diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm b/UefiCpuPkg= /ResetVector/Vtf0/Ia32/PageTables64.asm index f188da20ba..165cebcfaa 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm @@ -17,8 +17,28 @@ SetCr3ForPageTables64: ; ; These pages are built into the ROM image in X64/PageTables.asm ; +%ifdef USE_5_LEVEL_PAGE_TABLE + mov eax, 0 + cpuid + cmp eax, 07h ; check if basic CPUID leaf contai= ns leaf 07 + jb NotSupport5LevelPaging ; 5level paging not support, downg= rade to 4level paging + mov eax, 07h ; check cpuid leaf 7, subleaf 0 + mov ecx, 0 + cpuid + bt ecx, 16 ; [Bits 16] Supports 5-level pagin= g if 1. + jnc NotSupport5LevelPaging ; 5level paging not support, downg= rade to 4level paging + mov eax, ADDR_OF(Pml5) + mov cr3, eax + mov eax, cr4 + bts eax, 12 ; Set LA57=3D1. + mov cr4, eax + jmp SetCr3Done +NotSupport5LevelPaging: +%endif + mov eax, ADDR_OF(Pml4) mov cr3, eax +SetCr3Done: =20 OneTimeCallRet SetCr3ForPageTables64 =20 diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm b/UefiCpuPkg/Re= setVector/Vtf0/X64/PageTables.asm index d66fb62c34..7960b141be 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm @@ -81,4 +81,13 @@ Pml4: ; DQ PAGE_NLE(Pdp) TIMES 0x1000 - ($ - Pml4) DB 0 + +%ifdef USE_5_LEVEL_PAGE_TABLE +Pml5: + ; + ; Pml5 table (only first entry is present, pointing to Pml4) + ; + DQ PAGE_NLE(Pml4) + TIMES 0x1000 - ($ - Pml5) DB 0 +%endif EndOfPageTables: --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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