From nobody Sat Oct 4 19:04:18 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+104759+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104759+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1683864955; cv=none; d=zohomail.com; s=zohoarc; b=lv8celnKdkM6Wckdj1wkfEpSKxo+/8534nMKGeW2a0KADXI5B8wkpX7XjiU1yZ8Ax5b4ZHrGBmrJp2p+Uhul8RKtidJt9BGU9bUBt8lqYfCCLRuG+Hn9xVlYWMIYlxMy7T/fjDv6gkSSo0GTexfftvWozhQq/3uR8by6AjSm9Fw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683864955; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=EO3HjgzV12Y3clvo3M/Zx8Dp8y9wuQjnyQEX3ed6x2w=; b=idd4MvLaHQ/N5muZnlVkjHMTAVznEldUSvAq5NjkSp6Ios6RclxZ/QfIcWkz9JCgFz6NadYWV5DHTYqif3rj3Y4bSmI6+UxaEAmB1WJBRq98KnQa1lJ9qTSSbZz6W5XqGjHLEKNuRZ9HA1oQu3V6RIt45R5Kli2xWACDaaC1has= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104759+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1683864955349573.760702776559; Thu, 11 May 2023 21:15:55 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id XQFoYY1788612xcLjNL8VGEj; Thu, 11 May 2023 21:15:55 -0700 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web10.16549.1683864953043729668 for ; Thu, 11 May 2023 21:15:54 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10707"; a="348193828" X-IronPort-AV: E=Sophos;i="5.99,269,1677571200"; d="scan'208";a="348193828" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2023 21:15:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10707"; a="730658295" X-IronPort-AV: E=Sophos;i="5.99,269,1677571200"; d="scan'208";a="730658295" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by orsmga008.jf.intel.com with ESMTP; 11 May 2023 21:15:52 -0700 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v2 1/5] UefiCpuPkg/SecCore: Migrate page table to permanent memory Date: Fri, 12 May 2023 12:15:44 +0800 Message-Id: <20230512041548.6416-2-jiaxin.wu@intel.com> In-Reply-To: <20230512041548.6416-1-jiaxin.wu@intel.com> References: <20230512041548.6416-1-jiaxin.wu@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com X-Gm-Message-State: 7xc7xZSKKS3D3KvGr3m5VOZbx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1683864955; bh=zDnGz7qeHtcBhT798jKumWPEbOTf93UGdUixp5V1oIU=; h=Cc:Date:From:Reply-To:Subject:To; b=gtJr832yTNwcyyQ2OCoimzu3/2GGfLQd1iC/Do2+QOHbbEoBBglgpl9gBo76pjA1I4I DuuTB4VyN4tZ26xW3qp8AZa6T837uDh3Fo2ECQ7uuNP8Xu2HIn9Dq8jcuH3gV8tHPUbov lEjEzQN3W3YNJL9d/Fn71/kmZZdaLZMo8N4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1683864957210100007 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Background: For arch X64, system will enable the page table in SPI to cover 0-512G range via CR4.PAE & MSR.LME & CR0.PG & CR3 setting (see ResetVector code). Existi= ng code doesn't cover the higher address access above 512G before memory-disco= vered callback. That will be potential problem if system access the higher address after the transition from temporary RAM to permanent MEM RAM. Solution: This patch is to migrate page table to permanent memory to map entire physi= cal address space if CR0.PG is set during temporary RAM Done. Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- UefiCpuPkg/SecCore/SecCore.inf | 1 + UefiCpuPkg/SecCore/SecCoreNative.inf | 1 + UefiCpuPkg/SecCore/SecMain.c | 152 +++++++++++++++++++++++++++++++= ++++ UefiCpuPkg/SecCore/SecMain.h | 4 + 4 files changed, 158 insertions(+) diff --git a/UefiCpuPkg/SecCore/SecCore.inf b/UefiCpuPkg/SecCore/SecCore.inf index 3758aded3b..cab69b8b97 100644 --- a/UefiCpuPkg/SecCore/SecCore.inf +++ b/UefiCpuPkg/SecCore/SecCore.inf @@ -53,10 +53,11 @@ CpuExceptionHandlerLib ReportStatusCodeLib PeiServicesLib PeiServicesTablePointerLib HobLib + CpuPageTableLib =20 [Ppis] ## SOMETIMES_CONSUMES ## PRODUCES gEfiSecPlatformInformationPpiGuid diff --git a/UefiCpuPkg/SecCore/SecCoreNative.inf b/UefiCpuPkg/SecCore/SecC= oreNative.inf index 1ee6ff7d88..fa241cca94 100644 --- a/UefiCpuPkg/SecCore/SecCoreNative.inf +++ b/UefiCpuPkg/SecCore/SecCoreNative.inf @@ -50,10 +50,11 @@ CpuExceptionHandlerLib ReportStatusCodeLib PeiServicesLib PeiServicesTablePointerLib HobLib + CpuPageTableLib =20 [Ppis] ## SOMETIMES_CONSUMES ## PRODUCES gEfiSecPlatformInformationPpiGuid diff --git a/UefiCpuPkg/SecCore/SecMain.c b/UefiCpuPkg/SecCore/SecMain.c index 95375850ec..8ec0b654fb 100644 --- a/UefiCpuPkg/SecCore/SecMain.c +++ b/UefiCpuPkg/SecCore/SecMain.c @@ -70,10 +70,139 @@ MigrateGdt ( AsmWriteGdtr (&Gdtr); =20 return EFI_SUCCESS; } =20 +/** + Migrate page table to permanent memory mapping entire physical address s= pace. + + @retval EFI_SUCCESS The PageTable was migrated successfully. + @retval EFI_UNSUPPORTED Unsupport to migrate page table to perma= nent memory if IA-32e Mode not actived. + @retval EFI_OUT_OF_RESOURCES The PageTable could not be migrated due = to lack of available memory. + +**/ +EFI_STATUS +MigratePageTable ( + VOID + ) +{ + EFI_STATUS Status; + IA32_CR4 Cr4; + BOOLEAN Page5LevelSupport; + UINT32 RegEax; + CPUID_EXTENDED_CPU_SIG_EDX RegEdx; + BOOLEAN Page1GSupport; + PAGING_MODE PagingMode; + CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize; + UINT32 MaxExtendedFunctionId; + UINTN PageTable; + EFI_PHYSICAL_ADDRESS Buffer; + UINTN BufferSize; + IA32_MAP_ATTRIBUTE MapAttribute; + IA32_MAP_ATTRIBUTE MapMask; + + VirPhyAddressSize.Uint32 =3D 0; + PageTable =3D 0; + BufferSize =3D 0; + MapAttribute.Uint64 =3D 0; + MapMask.Uint64 =3D MAX_UINT64; + MapAttribute.Bits.Present =3D 1; + MapAttribute.Bits.ReadWrite =3D 1; + + // + // Check Page5Level Support or not. + // + Cr4.UintN =3D AsmReadCr4 (); + Page5LevelSupport =3D (Cr4.Bits.LA57 ? TRUE : FALSE); + + // + // Check Page1G Support or not. + // + Page1GSupport =3D FALSE; + AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL); + if (RegEax >=3D CPUID_EXTENDED_CPU_SIG) { + AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &(RegEdx.Uint32)); + if ((RegEdx.Bits.Page1GB) !=3D 0) { + Page1GSupport =3D TRUE; + } + } + + // + // Decide Paging Mode according Page5LevelSupport & Page1GSupport. + // + if (Page5LevelSupport) { + PagingMode =3D Page1GSupport ? Paging5Level1GB : Paging5Level; + } else { + PagingMode =3D Page1GSupport ? Paging4Level1GB : Paging4Level; + } + + // + // Get Maximum Physical Address Bits + // Get the number of address lines; Maximum Physical Address is 2^Physic= alAddressBits - 1. + // If CPUID does not supported, then use a max value of 36 as per SDM 3A= , 4.1.4. + // + AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunctionId, NULL, NULL, N= ULL); + if (MaxExtendedFunctionId >=3D CPUID_VIR_PHY_ADDRESS_SIZE) { + AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &VirPhyAddressSize.Uint32, NULL,= NULL, NULL); + } else { + VirPhyAddressSize.Bits.PhysicalAddressBits =3D 36; + } + + if ((PagingMode =3D=3D Paging4Level1GB) || (PagingMode =3D=3D Paging4Lev= el)) { + // + // The max lineaddress bits is 48 for 4 level page table. + // + VirPhyAddressSize.Bits.PhysicalAddressBits =3D MIN (VirPhyAddressSize.= Bits.PhysicalAddressBits, 48); + } + + // + // Get required buffer size for the pagetable that will be created. + // + Status =3D PageTableMap (&PageTable, PagingMode, 0, &BufferSize, 0, LShi= ftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits), &MapAttribute, &MapM= ask, NULL); + ASSERT (Status =3D=3D EFI_BUFFER_TOO_SMALL); + if (Status !=3D EFI_BUFFER_TOO_SMALL) { + return Status; + } + + // + // Allocate required Buffer. + // + Status =3D PeiServicesAllocatePages ( + EfiBootServicesData, + EFI_SIZE_TO_PAGES (BufferSize), + &Buffer + ); + if (EFI_ERROR (Status)) { + return EFI_OUT_OF_RESOURCES; + } + + // + // Create PageTable in permanent memory. + // + Status =3D PageTableMap (&PageTable, PagingMode, (VOID *)(UINTN)Buffer, = &BufferSize, 0, LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits), = &MapAttribute, &MapMask, NULL); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status) || (PageTable =3D=3D 0)) { + return EFI_OUT_OF_RESOURCES; + } + + // + // Write the Pagetable to CR3. + // + AsmWriteCr3 (PageTable); + + DEBUG (( + DEBUG_INFO, + "MigratePageTable: Created PageTable =3D 0x%lx, BufferSize =3D %x, Pag= ingMode =3D 0x%lx, Support Max Physical Address Bits =3D %d\n", + PageTable, + BufferSize, + (UINTN)PagingMode, + VirPhyAddressSize.Bits.PhysicalAddressBits + )); + + return Status; +} + // // These are IDT entries pointing to 10:FFFFFFE4h. // UINT64 mIdtEntryTemplate =3D 0xffff8e000010ffe4ULL; =20 @@ -451,10 +580,11 @@ SecTemporaryRamDone ( EFI_STATUS Status2; UINTN Index; BOOLEAN State; EFI_PEI_PPI_DESCRIPTOR *PeiPpiDescriptor; REPUBLISH_SEC_PPI_PPI *RepublishSecPpiPpi; + IA32_CR0 Cr0; =20 // // Republish Sec Platform Information(2) PPI // RepublishSecPlatformInformationPpi (); @@ -492,10 +622,32 @@ SecTemporaryRamDone ( if (PcdGetBool (PcdMigrateTemporaryRamFirmwareVolumes)) { Status =3D MigrateGdt (); ASSERT_EFI_ERROR (Status); } =20 + // + // Migrate page table to permanent memory mapping entire physical addres= s space if CR0.PG is set. + // + Cr0.UintN =3D AsmReadCr0 (); + if (Cr0.Bits.PG !=3D 0) { + // + // CR4.PAE must be enabled. + // + ASSERT ((AsmReadCr4 () & BIT5) !=3D 0); + + // + // Assume CPU runs in 64bit mode if paging is enabled. + // + ASSERT (sizeof (UINTN) =3D=3D sizeof (UINT64)); + + Status =3D MigratePageTable (); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "SecTemporaryRamDone: Failed to migrate page tab= le to permanent memory: %r.\n", Status)); + ASSERT_EFI_ERROR (Status); + } + } + // // Disable Temporary RAM after Stack and Heap have been migrated at this= point. // SecPlatformDisableTemporaryMemory (); =20 diff --git a/UefiCpuPkg/SecCore/SecMain.h b/UefiCpuPkg/SecCore/SecMain.h index 880e6cd1b8..b50d96e45b 100644 --- a/UefiCpuPkg/SecCore/SecMain.h +++ b/UefiCpuPkg/SecCore/SecMain.h @@ -17,10 +17,11 @@ #include #include =20 #include =20 +#include #include #include #include #include #include @@ -30,10 +31,13 @@ #include #include #include #include #include +#include +#include +#include =20 #define SEC_IDT_ENTRY_COUNT 34 =20 typedef struct _SEC_IDT_TABLE { // --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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