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id 15.20.6363.026; Fri, 5 May 2023 02:49:47 +0000 From: "Minh Nguyen via groups.io" To: devel@edk2.groups.io CC: patches@amperecomputing.com, quic_llindhol@quicinc.com, ardb+tianocore@kernel.org, thang@os.amperecomputing.com, nhi@os.amperecomputing.com, tinhnguyen@os.amperecomputing.com Subject: [edk2-devel][edk2-platforms][PATCH 1/2] AmpereAltraPkg: Add support for PCIe Auto Bifurcation Date: Fri, 5 May 2023 09:49:17 +0700 Message-ID: <20230505024918.1447433-2-minhnguyen1@os.amperecomputing.com> In-Reply-To: <20230505024918.1447433-1-minhnguyen1@os.amperecomputing.com> References: <20230505024918.1447433-1-minhnguyen1@os.amperecomputing.com> X-ClientProxiedBy: SG2PR01CA0167.apcprd01.prod.exchangelabs.com (2603:1096:4:28::23) To PH0PR01MB8048.prod.exchangelabs.com (2603:10b6:510:280::7) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH0PR01MB8048:EE_|BL3PR01MB6948:EE_ X-MS-Office365-Filtering-Correlation-Id: 3feede08-9bab-4068-60f6-08db4d135f70 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os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3feede08-9bab-4068-60f6-08db4d135f70 X-MS-Exchange-CrossTenant-AuthSource: PH0PR01MB8048.prod.exchangelabs.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 May 2023 02:49:40.6511 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: bu8lYcyEoiGxd+62lhQlzFj3jP6Wd47kd5ZOV4OPvGrvlxPcDvff0AbXhwbZh1UM/RVL1Lomwi+kD7zNRc4ap4XoY5S/nxvXbFm6swwqQtSJVr5PEHPW46gqluy/ooIa X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR01MB6948 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,minhnguyen1@os.amperecomputing.com X-Gm-Message-State: 4Raf4WGiJxDLhtVv2DrMEaAUx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1683255021; bh=ydG7X3U2dRAZDsryPkH8+p8lZFWLZGWnz0qgkKijpZw=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=YaufergFOQUXQAX/YtD6arXRs3e+9E+RRXL5E06LxU3IeWlWXOROM9Ki/gTZQx51wtH UNfaXjobCpdbyoYyK28FiwDCgmw/BX7AjEB8zPk9WkS4fQDdlLat/nb9kS6cqKwHPTQy0 Alqs1slqdxzlui3IcuKradUdfpQDx+BFAPo= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1683255023757100010 Content-Type: text/plain; charset="utf-8" From: Vu Nguyen Add extra option call Auto to the Bifurcation selection. This mode will automatically select the best bifurcation mode the current Root Complex. Currently, this option only availabe on the RCA with x16 width. Signed-off-by: Minh Nguyen Reviewed-by: Nhi Pham --- Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexInfoHob.h = | 5 +- Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.h = | 5 + Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.c = | 2 + Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConf= igDxe.c | 12 +- Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c = | 344 +++++++++++++++++++- Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConf= igDxe.uni | 3 +- 6 files changed, 365 insertions(+), 6 deletions(-) diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexInfoHob.= h b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexInfoHob.h index 24599b781646..0b252de37dcc 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexInfoHob.h +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexInfoHob.h @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+ Copyright (c) 2021 - 2023, Ampere Computing LLC. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -40,7 +40,8 @@ typedef enum { DevMapMode2, DevMapMode3, DevMapMode4, - MaxDevMapMode =3D DevMapMode4 + DevMapModeAuto, + MaxDevMapMode =3D DevMapModeAuto } DEV_MAP_MODE; =20 // diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.h b= /Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.h index a18fff7dbb75..988450a54260 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.h +++ b/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.h @@ -46,6 +46,11 @@ #define PFA_MODE_CLEAR 1 #define PFA_MODE_READ 2 =20 +#define BIFURCATION_X000 0 +#define BIFURCATION_X0X0 1 +#define BIFURCATION_X0XX 2 +#define BIFURCATION_XXXX 3 + // // Host Bridge registers // diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexN= VParam.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVP= aram.c index da730c4bd219..08dff0f1311f 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.c +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.c @@ -128,6 +128,7 @@ SetRootComplexBifurcation ( RootComplex->Pcie[RPStart + 3].Active =3D TRUE; break; =20 + case DevMapModeAuto: case DevMapMode4: MaxWidth =3D (RootComplex->Type =3D=3D RootComplexTypeA) ? LINK_WIDTH_= X4 : LINK_WIDTH_X2; RootComplex->Pcie[RPStart].MaxWidth =3D PCIE_GET_MAX_WIDTH (RootComple= x->Pcie[RPStart], MaxWidth); @@ -526,6 +527,7 @@ GetMaxSpeedGen ( } break; =20 + case DevMapModeAuto: case DevMapMode4: /* x4 x4 x4 x4 */ if (RootComplex->Flags & PCIE_ERRATA_SPEED1) { MaxGen =3D ErrataSpeedDevMap4; diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/Roo= tComplexConfigDxe.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConf= igDxe/RootComplexConfigDxe.c index e03be2a2f9dc..52a297ff085d 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComple= xConfigDxe.c +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComple= xConfigDxe.c @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.
+ Copyright (c) 2020 - 2023, Ampere Computing LLC. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -600,6 +600,16 @@ CreateDevMapOptions ( DevMapMode4 ); =20 + if (RootComplex->Type =3D=3D RootComplexTypeA) { + HiiCreateOneOfOptionOpCode ( + OptionsOpCodeHandle, + STRING_TOKEN (STR_PCIE_BIFUR_SELECT_AUTO), + 0, + EFI_IFR_NUMERIC_SIZE_1, + DevMapModeAuto + ); + } + return OptionsOpCodeHandle; } =20 diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c b= /Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c index 855b094f7948..f7c8defc1906 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c +++ b/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c @@ -664,6 +664,267 @@ EnableDbiAccess ( MmioWrite32 (TargetAddress, Val); } =20 +VOID +Ac01PcieUpdateMaxWidth ( + IN AC01_ROOT_COMPLEX *RootComplex + ) +{ + if (RootComplex->Type =3D=3D RootComplexTypeA) { + switch (RootComplex->DevMapLow) { + case DevMapMode1: + RootComplex->Pcie[PcieController0].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 16; + break; + + case DevMapMode2: + RootComplex->Pcie[PcieController0].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 8; + RootComplex->Pcie[PcieController2].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 8; + break; + + case DevMapMode3: + RootComplex->Pcie[PcieController0].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 8; + RootComplex->Pcie[PcieController2].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 4; + RootComplex->Pcie[PcieController3].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 4; + break; + + case DevMapMode4: + RootComplex->Pcie[PcieController0].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 4; + RootComplex->Pcie[PcieController1].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 4; + RootComplex->Pcie[PcieController2].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 4; + RootComplex->Pcie[PcieController3].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 4; + break; + + default: + ASSERT (FALSE); + } + } else { + switch (RootComplex->DevMapLow) { + case DevMapMode1: + RootComplex->Pcie[PcieController0].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 8; + break; + + case DevMapMode2: + RootComplex->Pcie[PcieController0].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 4; + RootComplex->Pcie[PcieController2].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 4; + break; + + case DevMapMode3: + RootComplex->Pcie[PcieController0].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 4; + RootComplex->Pcie[PcieController2].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 2; + RootComplex->Pcie[PcieController3].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 2; + break; + + case DevMapMode4: + RootComplex->Pcie[PcieController0].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 2; + RootComplex->Pcie[PcieController1].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 2; + RootComplex->Pcie[PcieController2].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 2; + RootComplex->Pcie[PcieController3].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 2; + break; + + default: + ASSERT (FALSE); + } + + switch (RootComplex->DevMapHigh) { + case DevMapMode1: + RootComplex->Pcie[PcieController4].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 8; + break; + + case DevMapMode2: + RootComplex->Pcie[PcieController4].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 4; + RootComplex->Pcie[PcieController6].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 4; + break; + + case DevMapMode3: + RootComplex->Pcie[PcieController4].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 4; + RootComplex->Pcie[PcieController6].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 2; + RootComplex->Pcie[PcieController7].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 2; + break; + + case DevMapMode4: + RootComplex->Pcie[PcieController4].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 2; + RootComplex->Pcie[PcieController5].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 2; + RootComplex->Pcie[PcieController6].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 2; + RootComplex->Pcie[PcieController7].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 2; + break; + + default: + ASSERT (FALSE); + } + } +} + +VOID +Ac01PcieUpdateActive ( + IN AC01_ROOT_COMPLEX *RootComplex + ) +{ + switch (RootComplex->DevMapLow) { + case DevMapMode1: + RootComplex->Pcie[PcieController0].Active =3D TRUE; + RootComplex->Pcie[PcieController1].Active =3D FALSE; + RootComplex->Pcie[PcieController2].Active =3D FALSE; + RootComplex->Pcie[PcieController3].Active =3D FALSE; + break; + + case DevMapMode2: + RootComplex->Pcie[PcieController0].Active =3D TRUE; + RootComplex->Pcie[PcieController1].Active =3D FALSE; + RootComplex->Pcie[PcieController2].Active =3D TRUE; + RootComplex->Pcie[PcieController3].Active =3D FALSE; + break; + + case DevMapMode3: + RootComplex->Pcie[PcieController0].Active =3D TRUE; + RootComplex->Pcie[PcieController1].Active =3D FALSE; + RootComplex->Pcie[PcieController2].Active =3D TRUE; + RootComplex->Pcie[PcieController3].Active =3D TRUE; + break; + + case DevMapMode4: + RootComplex->Pcie[PcieController0].Active =3D TRUE; + RootComplex->Pcie[PcieController1].Active =3D TRUE; + RootComplex->Pcie[PcieController2].Active =3D TRUE; + RootComplex->Pcie[PcieController3].Active =3D TRUE; + break; + + default: + ASSERT (FALSE); + } + + if (RootComplex->Type =3D=3D RootComplexTypeB) { + switch (RootComplex->DevMapHigh) { + case DevMapMode1: + RootComplex->Pcie[PcieController4].Active =3D TRUE; + RootComplex->Pcie[PcieController5].Active =3D FALSE; + RootComplex->Pcie[PcieController6].Active =3D FALSE; + RootComplex->Pcie[PcieController7].Active =3D FALSE; + break; + + case DevMapMode2: + RootComplex->Pcie[PcieController4].Active =3D TRUE; + RootComplex->Pcie[PcieController5].Active =3D FALSE; + RootComplex->Pcie[PcieController6].Active =3D TRUE; + RootComplex->Pcie[PcieController7].Active =3D FALSE; + break; + + case DevMapMode3: + RootComplex->Pcie[PcieController4].Active =3D TRUE; + RootComplex->Pcie[PcieController5].Active =3D FALSE; + RootComplex->Pcie[PcieController6].Active =3D TRUE; + RootComplex->Pcie[PcieController7].Active =3D TRUE; + break; + + case DevMapMode4: + RootComplex->Pcie[PcieController4].Active =3D TRUE; + RootComplex->Pcie[PcieController5].Active =3D TRUE; + RootComplex->Pcie[PcieController6].Active =3D TRUE; + RootComplex->Pcie[PcieController7].Active =3D TRUE; + break; + + default: + ASSERT (FALSE); + } + } +} + +EFI_STATUS +Ac01PcieCorrectBifurcation ( + IN AC01_ROOT_COMPLEX *RootComplex, + IN PCI_REG_PCIE_LINK_CAPABILITY *LinkCap, + IN UINTN LinkCapLength, + IN OUT DEV_MAP_MODE *Bifur + ) +{ + UINTN Count; + UINTN Idx; + EFI_STATUS Status; + + Status =3D EFI_SUCCESS; + + if (RootComplex =3D=3D NULL || LinkCap =3D=3D NULL || Bifur =3D=3D NULL)= { + return EFI_INVALID_PARAMETER; + } + + if (LinkCapLength !=3D 4) { + // Only process 4 controller at a same time + return EFI_INVALID_PARAMETER; + } + + if (LinkCap[PcieController1].Uint32 !=3D 0) { + // Bifurcation should be X/X/X/X + *Bifur =3D BIFURCATION_XXXX; + return Status; + } + + Count =3D 0; + for (Idx =3D 0; Idx < LinkCapLength; Idx++) { + if (LinkCap[Idx].Uint32 !=3D 0) { + Count++; + } + } + + switch (Count) { + case 3: + // Bifurcation should be X/0/X/X + *Bifur =3D BIFURCATION_X0XX; + break; + + case 2: + if (LinkCap[PcieController0].Uint32 !=3D 0) { + if (LinkCap[PcieController2].Uint32) { + *Bifur =3D BIFURCATION_X0X0; + } else { + *Bifur =3D BIFURCATION_X0XX; + } + } else { + *Bifur =3D BIFURCATION_XXXX; + } + break; + + case 1: + if (LinkCap[PcieController0].Uint32 !=3D 0) { + *Bifur =3D BIFURCATION_X000; + } else if (LinkCap[PcieController2].Uint32 !=3D 0) { + *Bifur =3D BIFURCATION_X0X0; + } else { + // In the lane reverse case, we choose best width + switch (LinkCap[PcieController3].Bits.MaxLinkWidth) { /* MAX_SPEED [= 9:4] */ + case CAP_MAX_LINK_WIDTH_X1: + case CAP_MAX_LINK_WIDTH_X2: + *Bifur =3D BIFURCATION_XXXX; + break; + + case CAP_MAX_LINK_WIDTH_X4: + if (RootComplex->Type =3D=3D RootComplexTypeA) { + *Bifur =3D BIFURCATION_XXXX; + } else { + *Bifur =3D BIFURCATION_X0X0; + } + break; + + case CAP_MAX_LINK_WIDTH_X8: + if (RootComplex->Type =3D=3D RootComplexTypeA) { + *Bifur =3D BIFURCATION_X0X0; + } else { + *Bifur =3D BIFURCATION_X000; + } + break; + + default: + *Bifur =3D BIFURCATION_X000; + break; + } + } + break; + + default: + Status =3D EFI_NOT_AVAILABLE_YET; + break; + } + + return Status; +} + /** Setup and initialize the AC01 PCIe Root Complex and underneath PCIe cont= rollers =20 @@ -687,12 +948,87 @@ Ac01PcieCoreSetupRC ( RETURN_STATUS Status; UINT32 Val; UINT8 PcieIndex; + BOOLEAN AutoLaneBifurcationEnabled =3D FALSE; + PCI_REG_PCIE_LINK_CAPABILITY LinkCap[MaxPcieController]; + AC01_PCIE_CONTROLLER *Pcie; + DEV_MAP_MODE DevMapMode; =20 DEBUG ((DEBUG_INFO, "Initializing Socket%d RootComplex%d\n", RootComplex= ->Socket, RootComplex->ID)); =20 - ProgramHostBridgeInfo (RootComplex); - +AutoLaneBifurcationRetry: if (!ReInit) { + if (AutoLaneBifurcationEnabled) { + // + // We are here after the first round + // + // As per 2.7.2. AC Specifications of PCIe card specification this T= PVPERL time and + // should be minimum 100ms. So this is minimum time we need add and = found during test. + // + MicroSecondDelay (100000); + SetMem ((VOID *)LinkCap, sizeof (LinkCap), 0); + for (PcieIndex =3D 0; PcieIndex < RootComplex->MaxPcieController; Pc= ieIndex++) { + Pcie =3D &RootComplex->Pcie[PcieIndex]; + if (!Pcie->Active || !PcieLinkUpCheck (Pcie)) { + continue; + } + DEBUG ((DEBUG_INFO, "RootComplex->ID:%d Port:%d link up\n", RootCo= mplex->ID, PcieIndex)); + TargetAddress =3D GetCapabilityBase (RootComplex, PcieIndex, FALSE= , EFI_PCI_CAPABILITY_ID_PCIEXP); + if (TargetAddress =3D=3D 0) { + continue; + } + LinkCap[PcieIndex].Uint32 =3D MmioRead32 (TargetAddress + LINK_CAP= ABILITIES_REG); + } + + Status =3D Ac01PcieCorrectBifurcation (RootComplex, LinkCap, MaxPcie= ControllerOfRootComplexA, &DevMapMode); + if (!EFI_ERROR (Status)) { + RootComplex->DevMapLow =3D DevMapMode; + DEBUG (( + DEBUG_INFO, + "RootComplex->ID:%d Auto Bifurcation done, DevMapMode:%d\n", + RootComplex->ID, + RootComplex->DevMapLow + )); + } else { + RootComplex->DevMapLow =3D DevMapMode1; + DEBUG (( + DEBUG_INFO, + "RootComplex->ID:%d Auto Bifurcation failed, revert to DevMapMod= e1\n", + RootComplex->ID + )); + } + + AutoLaneBifurcationEnabled =3D FALSE; + + if (DevMapMode =3D=3D DevMapMode4) { + // Return directly as the RootComplex already initialized in this = mode + return EFI_SUCCESS; + } + + // + // Update the RootComplex data with new DevMapMode + // + Ac01PcieUpdateActive (RootComplex); + Ac01PcieUpdateMaxWidth (RootComplex); + } else { + if (RootComplex->DevMapLow =3D=3D DevMapModeAuto) { + // Set lowest bifurcation mode + RootComplex->DevMapLow =3D DevMapMode4; + + AutoLaneBifurcationEnabled =3D TRUE; + DEBUG (( + DEBUG_INFO, + "RootComplex->ID:%d Auto Bifurcation enabled\n", + RootComplex->ID + )); + } + } + + ProgramHostBridgeInfo (RootComplex); + + // Fix for UEFI hang due to timing change with bifurcation + // register moved very close to PHY initialization. + MicroSecondDelay (100000); + Status =3D PciePhyInit (RootComplex->SerdesBase); if (RETURN_ERROR (Status)) { DEBUG ((DEBUG_ERROR, "%a: Failed to initialize the PCIe PHY\n", __FU= NCTION__)); @@ -855,6 +1191,10 @@ Ac01PcieCoreSetupRC ( } } =20 + if (AutoLaneBifurcationEnabled) { + goto AutoLaneBifurcationRetry; + } + return RETURN_SUCCESS; } =20 diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/Roo= tComplexConfigDxe.uni b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexCo= nfigDxe/RootComplexConfigDxe.uni index f28fda05def9..06535a9581e3 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComple= xConfigDxe.uni +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComple= xConfigDxe.uni @@ -1,5 +1,5 @@ // -// Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. +// Copyright (c) 2020 - 2023, Ampere Computing LLC. All rights reserved. // // SPDX-License-Identifier: BSD-2-Clause-Patent // @@ -78,6 +78,7 @@ #string STR_PCIE_RC15_FORM #language en-US "Root Complex 15 C= onfiguration" #string STR_PCIE_RC15_FORM_HELP #language en-US "Root Complex 15 C= onfiguration" =20 +#string STR_PCIE_BIFUR_SELECT_AUTO #language en-US "Auto" #string STR_PCIE_BIFUR_SELECT_VALUE0 #language en-US "x16" #string STR_PCIE_BIFUR_SELECT_VALUE1 #language en-US "x8+x8" #string STR_PCIE_BIFUR_SELECT_VALUE2 #language en-US "x8+x4+x4" --=20 2.39.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Fri, 5 May 2023 02:49:47 +0000 From: "Minh Nguyen via groups.io" To: devel@edk2.groups.io CC: patches@amperecomputing.com, quic_llindhol@quicinc.com, ardb+tianocore@kernel.org, thang@os.amperecomputing.com, nhi@os.amperecomputing.com, tinhnguyen@os.amperecomputing.com Subject: [edk2-devel][edk2-platforms][PATCH 2/2] AmpereAltraPkg: Enable auto bifurcation via BoardSetting Date: Fri, 5 May 2023 09:49:18 +0700 Message-ID: <20230505024918.1447433-3-minhnguyen1@os.amperecomputing.com> In-Reply-To: <20230505024918.1447433-1-minhnguyen1@os.amperecomputing.com> References: <20230505024918.1447433-1-minhnguyen1@os.amperecomputing.com> X-ClientProxiedBy: SG2PR01CA0167.apcprd01.prod.exchangelabs.com (2603:1096:4:28::23) To PH0PR01MB8048.prod.exchangelabs.com (2603:10b6:510:280::7) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH0PR01MB8048:EE_|BL3PR01MB6948:EE_ X-MS-Office365-Filtering-Correlation-Id: 268d2644-9ca6-46a5-2e14-08db4d1360d1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Message-Info: LCcuc1B8Kg2aRMmSYjqGzcL5/QHa9J7NMQKosATtLF1Id7YijgeA1pg4ItBabdMkkp6qDHtaU7L//lm1XDQdRmQnR9OA1Xy/SoaqUXT9uerQ8LoceKmZ3pxyH3uf2oOszoTOYWGZYGdngTkhyWrz6L41EIkm15OGoat+GzxRczXTc1p5RH1CSAlZy5MxIbnhv6U0pHCQnzYn0ATdtLUzsLt37gQNX6SQx+wiEt+XvIfKyxmt2Kax9zmpJswMyJah6pHWfZ9tjFp6Au4vqrvM9BQKVFsuBRU/LgiDf5PWkp2883BwThTrsuV8ncWW4ozLXuIsJC5Gq6zx/lZdNCSkNLGSAdTDfocD1Dt7bRmTLgqiiu5pIY22VQi/NbNM2TC4KK+UJWDpbsR844sPZXZRriLi2ByKj1yEziFCc9GMiRiBZMrVu+HLIuTwwXtR5G5LIdMCio/jEcJHijSPar9BsE3MvDhpueU41dmHn8QbyhWuFd6fVuPY156RXuNtU1PxieumeEigSaxenJk6BCqlx9slEPfl6ZbjFOMWiKDjjAHHSc0+4acPkvzfkjQtwtj0vgfOEVYpPQKYQe/JdguTLNF+id/gh9TtnUZtIG7eps7cathTLeWYG4nFVhY4kT+k X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?VLoHwfcCQhutc+L1rvEpyV8HWplxa14SZ4LYVAdeDQ7BgINZExx23yjVQKZb?= =?us-ascii?Q?IhKNl8QCulHG2zOFt71eSi+O0gkccwlIIYCj3oYjuah+J7+3XWvHOpsIuJ32?= =?us-ascii?Q?mMb1p2w4nWn1b/2KxFubxCPJhagslKOT0Oe1cugaDCzrHyECtO7mZnzVYwF1?= =?us-ascii?Q?11zZ/+1sCHAE/gTiP7f52pCGdbRtaybkHktn9dw0ZgbIaTcrcHpHcCPHf4lP?= =?us-ascii?Q?d2YwVjj1fXmt1oWUM7cDXtDf5GewMm0xEYR07m6E680MOIf68VLVN4A7gl8h?= =?us-ascii?Q?RMARElQIIliO7REeqvT0b8oosL/X6ptGknDYK7H2LRJN+AX0AEs2FxZM4g9+?= =?us-ascii?Q?+WQN46X691G3hpRiLzefks1bf65p0Jw4ruASgR6+rBizVRGcsBgZRWV9Oimv?= =?us-ascii?Q?L8UGaHdsP8u/WsGP05rFX0x3+stLU7KtBBJal4ybAw6IdMTmUrjqIrLMqb9I?= =?us-ascii?Q?CZPgzmK21ekQnywVzHo0WZkCVKp1wY3itULj2BfRTVBc/wlBoSOpVntydH0o?= =?us-ascii?Q?BuVl82htQx4khHIa4dAx04/erWsnm1JX9FZoSjt8bjnHqQa1NbDvmrSwMXOh?= =?us-ascii?Q?5WAIDKDq+S8g4OfTeWUYMiaQoMdGpsEui2r6yhJLth1zIcm3jHYbkXMXF4WO?= =?us-ascii?Q?5yrEcHtAft4EQGMKnhT+TjWC7n8FKRZvveKDPiKczX1SMNfLTWafOqDAW++6?= =?us-ascii?Q?4xYJJ2m8PrtE8z5VebZ/uBYaH4ZdVxIumQnxuClW3N3ApK9zdOX9tIAdia2A?= =?us-ascii?Q?BOQIzzKD6OF/+DdZeO6f0p0bPtrYJY/w48SxSQ4SW+QUIuEP3HBLs7+xWu5H?= =?us-ascii?Q?oDDaoD/2dddqcGrNmjjMZp5iaTVIBpmT7wWeFFtMbMiYYxwVr9ltCZuViIcF?= =?us-ascii?Q?b5rOn9hEI3zRBI7htcKct3bZBS9/cCSXXnZO5/3KnZpBk7/F1VK/yurK04ev?= =?us-ascii?Q?j8JwGRxb318uVrf8Vmf/tkGWkofEGRnt5HiiGfPgv+giWbVNwjAScJ0PPrOw?= =?us-ascii?Q?cy2vOP17W1n1towcZNuf0cmOuAV97Nqgdaw660z8JDAgSPftP+m0QJW1yZ/O?= =?us-ascii?Q?3AB8acsTKy1hQ98kPFksbXIBd9sfsgo5qqzUFU6ZLQxBQEVvqLFLXYjsOrYy?= =?us-ascii?Q?98P+4v0wXTB3PhyPrffMi9aE1kv10N+I0TFh1BfFQ2RFabsFY9vvWvp6m3Ko?= =?us-ascii?Q?T3Cme7i/tmMVGp3yGkYXDbUAXDeC/DgzycFIdqegRyxo1Yc78McQeoJekghT?= =?us-ascii?Q?ogW7I4WLnueCfEXsboSQxkr1vOfHAaP94AiB9SeHJjl9K/7UKJvF99KlWpye?= =?us-ascii?Q?HUwqIT4/wSpqZ5dLapeyXKNG3EyQpVgWZBia0bQ1kAN155YPFerWW2e/eFLO?= =?us-ascii?Q?AGqM0VktR+9pChcdZUInbb3J2CquAnXMbnrgmOL+XeSIiIYKQeg9iFOR0ddB?= =?us-ascii?Q?O9vmsM7JmYOBoNq7CQhH0GyG44TilnQHblrsc8ssisR6RuFwx0XaERvFEpPi?= =?us-ascii?Q?XqDfewpqnpgPizYmk0ZOyxR5Tv/4b+hSY0mCPzm1LGOgla7/Gtal53kVNRve?= =?us-ascii?Q?wb1uFnLZFjUChhSJg9au+wZVUvFB0K9lT0/APmWMt+yOpa+DlrNXs/Myls3Z?= =?us-ascii?Q?dm/PZzO3udFH02QnuEGl/3Dnrby7R+nIhduFI8wv9K9f?= X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: 268d2644-9ca6-46a5-2e14-08db4d1360d1 X-MS-Exchange-CrossTenant-AuthSource: PH0PR01MB8048.prod.exchangelabs.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 May 2023 02:49:42.9145 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: fivIQFKhnbR6lusFcz4Ehd/zneXbJAcBPdyx35kst3SMqD3cbaYH12HcMH+dvmdryXGrjHPZmcFGLXwygI2GxFnHiVAOYyA0fO3EQsoMIe1ktdw+rd4FUVgqbOqKk27D X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR01MB6948 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,minhnguyen1@os.amperecomputing.com X-Gm-Message-State: hB1z883RAj5QoBO5Zev0Un8zx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1683255021; bh=6TAp8aYPFZbyvwLOm5Rqv5wM2yy6zsjAEZbv3o5ZZ4E=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=LOhHfT9abf5UJXvAecyplFwFmZ2qxHbSC+5hOYEyI+9d37BB1hpLCwFYsjqR92tUj2M sPUOJDIHvIyfG5kSAn21SrlWQcukGDj2TIgKD+u4DYzPRTuoeRQwZna2czB1lawkQOSBt rDEptFqOnAWql7SRYiVB5CKENhj7kmS3Ku8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1683255022776100003 Content-Type: text/plain; charset="utf-8" From: Vu Nguyen Add support for new BoardSetting's config value (0x0000000A) to enable auto bifurcation mode per Root Complex: Example: NV_SI_RO_BOARD_S0_RCA2_CFG, 0x0098, 0x0000000A NV_SI_RO_BOARD_S0_RCA3_CFG, 0x00A0, 0x0000000A Signed-off-by: Minh Nguyen Reviewed-by: Nhi Pham --- Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.h = | 4 +++- Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.c = | 12 +++++++++++- Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConf= igDxe.c | 7 ++++--- 3 files changed, 18 insertions(+), 5 deletions(-) diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexN= VParam.h b/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVP= aram.h index 008a8db69f2c..8c07f086a58f 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.h +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.h @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.
+ Copyright (c) 2020 - 2023, Ampere Computing LLC. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -13,6 +13,8 @@ #define BYTE_MASK 0xFF #define PCIE_ERRATA_SPEED1 0x0001 // Limited speed errata =20 +#define AUTO_BIFURCATION_SETTING_VALUE 0x0A + #ifndef BIT #define BIT(nr) (1 << (nr)) #endif diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexN= VParam.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVP= aram.c index 08dff0f1311f..a8e23015b605 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.c +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.c @@ -205,7 +205,9 @@ GetDevMap ( // // Get default Devmap low and configure Devmap low accordingly. // - RootComplex->DefaultDevMapLow =3D GetDefaultDevMap (RootComplex, TRUE); + if (RootComplex->DefaultDevMapLow !=3D DevMapModeAuto) { + RootComplex->DefaultDevMapLow =3D GetDefaultDevMap (RootComplex, TRUE); + } if (RootComplex->DevMapLow =3D=3D 0) { RootComplex->DevMapLow =3D RootComplex->DefaultDevMapLow; } @@ -398,6 +400,14 @@ GetLaneAllocation ( } } =20 + // Update RootComplex data to handle auto bifurcation mode on RCA + if (Value =3D=3D AUTO_BIFURCATION_SETTING_VALUE) { + RootComplex->Pcie[PcieController0].MaxWidth =3D LINK_WIDTH_X4; + RootComplex->Pcie[PcieController0].MaxGen =3D LINK_SPEED_GEN3; + RootComplex->Pcie[PcieController0].Active =3D TRUE; + RootComplex->DefaultDevMapLow =3D DevMapModeAuto; + } + if (RootComplex->Type =3D=3D RootComplexTypeB) { NvParamOffset +=3D NV_PARAM_ENTRYSIZE; Status =3D NVParamGet (NvParamOffset, NV_PERM_ALL, &Value); diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/Roo= tComplexConfigDxe.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConf= igDxe/RootComplexConfigDxe.c index 52a297ff085d..bc4812207f63 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComple= xConfigDxe.c +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComple= xConfigDxe.c @@ -733,7 +733,8 @@ PcieRCScreenSetup ( // OptionsOpCodeHandle =3D CreateDevMapOptions (RootComplex); =20 - if (RootComplex->DefaultDevMapLow !=3D 0) { + if ((RootComplex->DefaultDevMapLow !=3D 0) + && (RootComplex->DefaultDevMapLow !=3D DevMapModeAuto)) { QuestionFlags |=3D EFI_IFR_FLAG_READ_ONLY; } =20 @@ -1202,8 +1203,8 @@ RootComplexDriverEntry ( RootComplex =3D GetRootComplex (RCIndex); =20 if (EFI_ERROR (Status)) { - VarStoreConfig->RCBifurcationLow[RCIndex] =3D RootComplex->DevMapLow; - VarStoreConfig->RCBifurcationHigh[RCIndex] =3D RootComplex->DevMapHi= gh; + VarStoreConfig->RCBifurcationLow[RCIndex] =3D RootComplex->DefaultDe= vMapLow; + VarStoreConfig->RCBifurcationHigh[RCIndex] =3D RootComplex->DefaultD= evMapHigh; VarStoreConfig->RCStatus[RCIndex] =3D RootComplex->Active; IsUpdated =3D TRUE; } --=20 2.39.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#104079): https://edk2.groups.io/g/devel/message/104079 Mute This Topic: https://groups.io/mt/98698193/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-