From nobody Wed Feb 11 02:09:08 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+104020+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104020+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683210297; cv=none; d=zohomail.com; s=zohoarc; b=IHvKKh5oNFmqqKE6AG+jw2g18AJV6rsda6Q3RYgJLqNmynMoibDoWu+ESBncpdb66wvImTGw7v8wYAhY7XnqeM6jTrU2Xm8Mj4xIAQKIgye4Du82v+1X625QJKx4P6gmn+aDsTsMg2ZnHT9Hnz6oyxOJYMbaXGKzQ2B0wImQ/I0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683210297; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=FHjC/gXhh6s3tJc4IYdgFYfxuipVb67+ehKDRUoDwrI=; b=Drz516YO11FGn2gd4XbNEM6oJ40vZGfcwe8unV163rFoMDtpNpna6GD48z7DWBAmvZA0YEcLjfQbYWgkegdzP8tLVBNgBA7gbrJdcK7xhDZMo9OwWInBys7CYvl8NLXXOT9x/HSD1DbhOyWlCilV19Sh/C9Ru3teJCEdVJrI8R0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104020+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1683210297598333.4888669492266; Thu, 4 May 2023 07:24:57 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id WAdJYY1788612x5LRcW8hfvD; Thu, 04 May 2023 07:24:57 -0700 X-Received: from muminek.juszkiewicz.com.pl (muminek.juszkiewicz.com.pl [213.251.184.221]) by mx.groups.io with SMTP id smtpd.web10.51615.1683210296251727292 for ; Thu, 04 May 2023 07:24:56 -0700 X-Received: from localhost (localhost [127.0.0.1]) by muminek.juszkiewicz.com.pl (Postfix) with ESMTP id CFD36260A74; Thu, 4 May 2023 16:24:54 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at juszkiewicz.com.pl X-Received: from muminek.juszkiewicz.com.pl ([127.0.0.1]) by localhost (muminek.juszkiewicz.com.pl [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id XUbfEMIDUlRz; Thu, 4 May 2023 16:24:53 +0200 (CEST) X-Received: from applejack.lan (83.11.34.59.ipv4.supernova.orange.pl [83.11.34.59]) by muminek.juszkiewicz.com.pl (Postfix) with ESMTPSA id EBC1E260824; Thu, 4 May 2023 16:24:49 +0200 (CEST) From: "Marcin Juszkiewicz" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Rebecca Cran , Sami Mujawar , Marcin Juszkiewicz Subject: [edk2-devel] [PATCH 6/7] ArmPkg: handle SVE/SME in ArmCpuInfo Date: Thu, 4 May 2023 15:24:39 +0100 Message-Id: <20230504142440.827531-7-marcin.juszkiewicz@linaro.org> In-Reply-To: <20230504142440.827531-1-marcin.juszkiewicz@linaro.org> References: <20230504142440.827531-1-marcin.juszkiewicz@linaro.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,marcin.juszkiewicz@linaro.org X-Gm-Message-State: 6oag5pD8uN9GI72ar3Q1kd0ux1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1683210297; bh=iO2VNxoEpKxZbqohMzPo+i+ElE+iO2ODbLaag60FWqU=; h=Cc:Date:From:Reply-To:Subject:To; b=MIJKGCR/zjQ7Tz98+5o8uOm19rzj3VVGp5OSfz23TZe6mLy/Ow2m9+EF638wTcYEYXt GXFm7Dc3nCLlg07jMZEWHNt9SCYJbEwNtYlhYOxoonFA0pSkHOjkj0pFmG8cc951DD1i6 fgHTVC9U71BS/KtHl/3qOmPMTD2Ccp2AnHw= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1683210299537100025 Content-Type: text/plain; charset="utf-8" If cpu supports SVE or SME then display information of supported features. Signed-off-by: Marcin Juszkiewicz --- ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c | 344 +++++++++++++++++++++ 1 file changed, 344 insertions(+) diff --git a/ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c b/ArmPkg/Applicatio= n/ArmCpuInfo/ArmCpuInfo.c index c2ed6b93d968..ab1cc70933e1 100644 --- a/ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c +++ b/ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c @@ -2353,6 +2353,333 @@ HandleAa64Pfr1 ( // 63:40 are reserved } =20 +/** + Handle ID_AA64SMFR0_EL1 system register. + + @param[in] Aa64Smfr0, value of ID_AA64SMFR0_EL1 system register +**/ +VOID +HandleAa64Smfr0 ( + CONST UINT64 Aa64Smfr0 + ) +{ + UINT64 Value; + STATIC CONST CHAR8 RegName[] =3D "SMFR0"; + CONST CHAR8 *Description; + CONST CHAR8 *Bits; + + // 31:0 reserved + + Bits =3D " 32"; + Value =3D (Aa64Smfr0 >> 32) & 0x1; + switch (Value) { + case 0: + Description =3D "SME F32F32 not implemented."; + break; + case 1: + Description =3D "SME F32F32 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + // 33 reserved + + Bits =3D " 34"; + Value =3D (Aa64Smfr0 >> 34) & 0x1; + switch (Value) { + case 0: + Description =3D "SME B16F32 not implemented."; + break; + case 1: + Description =3D "SME B16F32 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D " 35"; + Value =3D (Aa64Smfr0 >> 35) & 0x1; + switch (Value) { + case 0: + Description =3D "SME F16F32 not implemented."; + break; + case 1: + Description =3D "SME F16F32 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "39:36"; + Value =3D (Aa64Smfr0 >> 36) & 0xf; + switch (Value) { + case b0000: + Description =3D "SME I8I32 not implemented."; + break; + case b1111: + Description =3D "SME I8I32 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + // 47:40 reserved + + Bits =3D " 48"; + Value =3D (Aa64Smfr0 >> 48) & 0x1; + switch (Value) { + case 0: + Description =3D "SME F64F64 not implemented."; + break; + case 1: + Description =3D "SME F64F64 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + // 51:49 reserved + + Bits =3D "55:52"; + Value =3D (Aa64Smfr0 >> 52) & 0xf; + switch (Value) { + case b0000: + Description =3D "SME I16I64 not implemented"; + break; + case b1111: + Description =3D "SME I16I64 implemented"; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "59:56"; + Value =3D (Aa64Smfr0 >> 56) & 0xf; + switch (Value) { + case b0000: + Description =3D "Mandatory SME instructions are implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + // 62:60 reserved + + Bits =3D " 63"; + Value =3D (Aa64Smfr0 >> 63) & 0x1; + switch (Value) { + case 0: + Description =3D "SME_FA64 not implemented."; + break; + case 1: + Description =3D "SME_FA64 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); +} + +/** + Handle ID_AA64ZFR0_EL1 system register. + + @param[in] Aa64Zfr0, value of ID_AA64ZFR0_EL1 system register +**/ +VOID +HandleAa64Zfr0 ( + CONST UINT64 Aa64Zfr0 + ) +{ + UINT64 Value; + STATIC CONST CHAR8 RegName[] =3D "ZFR0"; + CONST CHAR8 *Description; + CONST CHAR8 *Bits; + + Bits =3D "3:0 "; + Value =3D Aa64Zfr0 & 0xf; + switch (Value) { + case b0000: + Description =3D "FEAT_SVE implemented."; + break; + case b0001: + Description =3D "FEAT_SVE2 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "7:4 "; + Value =3D (Aa64Zfr0 >> 4) & 0xf; + switch (Value) { + case b0000: + Description =3D "FEAT_SVE_AES not implemented."; + break; + case b0001: + Description =3D "FEAT_SVE_AES implemented."; + break; + case b0010: + Description =3D "FEAT_SVE_AES and FEAT_SVE_PMULL128 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + // 15:8 reserved + + Bits =3D "19:16"; + Value =3D (Aa64Zfr0 >> 16) & 0xf; + switch (Value) { + case b0000: + Description =3D "FEAT_SVE_BitPerm not implemented."; + break; + case b0001: + Description =3D "FEAT_SVE_BitPerm implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "23:20"; + Value =3D (Aa64Zfr0 >> 20) & 0xf; + switch (Value) { + case b0000: + Description =3D "SVE BFloat16 not implemented."; + break; + case b0001: + Description =3D "FEAT_BF16 SVE implemented."; + break; + case b0010: + Description =3D "FEAT_EBF16 SVE implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + // 31:24 reserved + + Bits =3D "35:32"; + Value =3D (Aa64Zfr0 >> 32) & 0xf; + switch (Value) { + case b0000: + Description =3D "FEAT_SVE_SHA3 not implemented."; + break; + case b0001: + Description =3D "FEAT_SVE_SHA3 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + // 39:36 reserved + + Bits =3D "43:40"; + Value =3D (Aa64Zfr0 >> 40) & 0xf; + switch (Value) { + case b0000: + Description =3D "FEAT_SVE_SM4 not implemented."; + break; + case b0001: + Description =3D "FEAT_SVE_SM4 implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "47:44"; + Value =3D (Aa64Zfr0 >> 44) & 0xf; + switch (Value) { + case b0000: + Description =3D "FEAT_I8MM SVE not implemented."; + break; + case b0001: + Description =3D "FEAT_I8MM SVE implemented."; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + // 51:48 reserved + + Bits =3D "55:52"; + Value =3D (Aa64Zfr0 >> 52) & 0xf; + switch (Value) { + case b0000: + Description =3D "FEAT_F32MM SVE not implemented"; + break; + case b0001: + Description =3D "FEAT_F32MM SVE implemented"; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + Bits =3D "59:56"; + Value =3D (Aa64Zfr0 >> 56) & 0xf; + switch (Value) { + case b0000: + Description =3D "FEAT_F64MM SVE not implemented"; + break; + case b0001: + Description =3D "FEAT_F64MM SVE implemented"; + break; + default: + Description =3D "unknown"; + break; + } + + PrintValues (RegName, Bits, Value, Description); + + // 63:60 reserved +} + /** The user Entry Point for Application. The user code starts with this fun= ction as the real entry point for the application. @@ -2380,6 +2707,8 @@ UefiMain ( UINT64 Aa64Mmfr2; UINT64 Aa64Pfr0; UINT64 Aa64Pfr1; + UINT64 Aa64Smfr0; + UINT64 Aa64Zfr0; =20 Aa64Dfr0 =3D ArmReadIdAA64Dfr0 (); Aa64Isar0 =3D ArmReadIdAA64Isar0 (); @@ -2390,6 +2719,8 @@ UefiMain ( Aa64Mmfr2 =3D ArmReadIdAA64Mmfr2 (); Aa64Pfr0 =3D ArmReadIdAA64Pfr0 (); Aa64Pfr1 =3D ArmReadIdAA64Pfr1 (); + Aa64Smfr0 =3D ArmReadIdAA64Smfr0 (); + Aa64Zfr0 =3D ArmReadIdAA64Zfr0 (); =20 AsciiPrint ("ID_AA64MMFR0_EL1 =3D 0x%016lx\n", Aa64Mmfr0); AsciiPrint ("ID_AA64MMFR1_EL1 =3D 0x%016lx\n", Aa64Mmfr1); @@ -2400,6 +2731,8 @@ UefiMain ( AsciiPrint ("ID_AA64ISAR1_EL1 =3D 0x%016lx\n", Aa64Isar1); AsciiPrint ("ID_AA64ISAR2_EL1 =3D 0x%016lx\n", Aa64Isar2); AsciiPrint ("ID_AA64DFR0_EL1 =3D 0x%016lx\n", Aa64Dfr0); + AsciiPrint ("ID_AA64SMFR0_EL1 =3D 0x%016lx\n", Aa64Smfr0); + AsciiPrint ("ID_AA64ZFR0_EL1 =3D 0x%016lx\n", Aa64Zfr0); AsciiPrint ("\n"); =20 PrintText ("Register", "Bits", "Value", "Feature"); @@ -2440,6 +2773,17 @@ UefiMain ( } =20 HandleAa64Dfr0 (Aa64Dfr0); + PrintSpacer (); + + if (Aa64Smfr0) { + HandleAa64Smfr0 (Aa64Smfr0); + PrintSpacer (); + } + + if (Aa64Zfr0) { + HandleAa64Zfr0 (Aa64Zfr0); + PrintSpacer (); + } =20 return EFI_SUCCESS; } --=20 2.40.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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