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This patch set simplify the page table creation code, remove some hard-code, combine files and support 5 Level paging. V4: Refine comments and update below macro names: PG_NLE -> PAGE_NLE PTE_2MB -> PDE_2MB PDP_1G -> PDPTE_1GB PAGE_BLP_ATTR -> PAGE_BLE_ATTR No code logic impact Zhiguang Liu (5): UefiCpuPkg/ResetVector: Rename macros about page table. UefiCpuPkg/ResetVector: Simplify page table creation in ResetVector UefiCpuPkg/ResetVector: Combine PageTables1G.asm and PageTables2M.asm UefiCpuPkg/ResetVector: Modify Page Table in ResetVector UefiCpuPkg/ResetVector: Support 5 level page table in ResetVector .../ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm | 25 ++++- .../ResetVector/Vtf0/Ia32/PageTables64.asm | 24 ----- UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 9 +- .../ResetVector/Vtf0/X64/PageTables.asm | 93 +++++++++++++++++++ .../ResetVector/Vtf0/X64/PageTables1G.asm | 53 ----------- .../ResetVector/Vtf0/X64/PageTables2M.asm | 60 ------------ 6 files changed, 118 insertions(+), 146 deletions(-) delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm create mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm -- 2.31.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#103925): https://edk2.groups.io/g/devel/message/103925 Mute This Topic: https://groups.io/mt/98676045/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
This patch only renames macro, with no code logic impacted. Two purpose to rename macro: 1. Align some macro name in PageTables1G.asm and PageTables2M.asm, so that these two files can be easily combined later. 2. Some Macro names such as PDP are not accurate, since 4 level page entry also uses this macro. PAGE_NLE (no leaf entry) is better Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Catharine West <catharine.west@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> --- .../ResetVector/Vtf0/X64/PageTables1G.asm | 26 +++++++++----- .../ResetVector/Vtf0/X64/PageTables2M.asm | 35 +++++++++++-------- 2 files changed, 39 insertions(+), 22 deletions(-) diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm index XXXXXXX..XXXXXXX 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm @@ -XXX,XX +XXX,XX @@ ; @file ; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x8000000000 (512GB) ; -; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2021 - 2023, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; Linear-Address Translation to a 1-GByte Page ; @@ -XXX,XX +XXX,XX @@ BITS 64 %define ALIGN_TOP_TO_4K_FOR_PAGING -%define PAGE_PDP_ATTR (PAGE_ACCESSED + \ +; +; Page table non-leaf entry attribute +; +%define PAGE_NLE_ATTR (PAGE_ACCESSED + \ PAGE_READ_WRITE + \ PAGE_PRESENT) -%define PAGE_PDP_1G_ATTR (PAGE_ACCESSED + \ +; +; Page table big leaf entry attribute: +; PDPTE 1GB entry or PDE 2MB entry +; +%define PAGE_BLE_ATTR (PAGE_ACCESSED + \ PAGE_READ_WRITE + \ PAGE_DIRTY + \ PAGE_PRESENT + \ @@ -XXX,XX +XXX,XX @@ BITS 64 %define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) %define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x)) -%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ - PAGE_PDP_ATTR) +; +; Page table non-leaf entry +; +%define PAGE_NLE(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ + PAGE_NLE_ATTR) -%define PDP_1G(x) ((x << 30) + PAGE_PDP_1G_ATTR) +%define PDPTE_1GB(x) ((x << 30) + PAGE_BLE_ATTR) ALIGN 16 @@ -XXX,XX +XXX,XX @@ TopLevelPageDirectory: ; ; Top level Page Directory Pointers (1 * 512GB entry) ; - DQ PDP(0x1000) + DQ PAGE_NLE(0x1000) TIMES 0x1000-PGTBLS_OFFSET($) DB 0 ; @@ -XXX,XX +XXX,XX @@ TopLevelPageDirectory: ; %assign i 0 %rep 512 - DQ PDP_1G(i) + DQ PDPTE_1GB(i) %assign i i+1 %endrep TIMES 0x2000-PGTBLS_OFFSET($) DB 0 diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm index XXXXXXX..XXXXXXX 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm @@ -XXX,XX +XXX,XX @@ ; @file ; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x100000000 (4GB) ; -; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;------------------------------------------------------------------------------ @@ -XXX,XX +XXX,XX @@ BITS 64 %define ALIGN_TOP_TO_4K_FOR_PAGING -%define PAGE_2M_PDE_ATTR (PAGE_SIZE + \ +; +; Page table big leaf entry attribute: +; PDPTE 1GB entry or PDE 2MB entry +; +%define PAGE_BLE_ATTR (PAGE_SIZE + \ PAGE_ACCESSED + \ PAGE_DIRTY + \ PAGE_READ_WRITE + \ PAGE_PRESENT) -%define PAGE_PDP_ATTR (PAGE_ACCESSED + \ - PAGE_READ_WRITE + \ - PAGE_PRESENT) +; +; Page table non-leaf entry attribute +; +%define PAGE_NLE_ATTR (PAGE_ACCESSED + \ + PAGE_READ_WRITE + \ + PAGE_PRESENT) %define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) %define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x)) -%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ - PAGE_PDP_ATTR) -%define PTE_2MB(x) ((x << 21) + PAGE_2M_PDE_ATTR) +%define PAGE_NLE(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ + PAGE_NLE_ATTR) +%define PDE_2MB(x) ((x << 21) + PAGE_BLE_ATTR) TopLevelPageDirectory: ; ; Top level Page Directory Pointers (1 * 512GB entry) ; - DQ PDP(0x1000) + DQ PAGE_NLE(0x1000) ; @@ -XXX,XX +XXX,XX @@ TopLevelPageDirectory: ; TIMES 0x1000-PGTBLS_OFFSET($) DB 0 - DQ PDP(0x2000) - DQ PDP(0x3000) - DQ PDP(0x4000) - DQ PDP(0x5000) + DQ PAGE_NLE(0x2000) + DQ PAGE_NLE(0x3000) + DQ PAGE_NLE(0x4000) + DQ PAGE_NLE(0x5000) ; ; Page Table Entries (2048 * 2MB entries => 4GB) @@ -XXX,XX +XXX,XX @@ TopLevelPageDirectory: %assign i 0 %rep 0x800 - DQ PTE_2MB(i) + DQ PDE_2MB(i) %assign i i+1 %endrep -- 2.31.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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Currently, page table creation has many hard-code values about the offset to the start of page table. To simplify it, add Labels such as Pml4, Pdp and Pd, so that we can remove many hard-code values Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Catharine West <catharine.west@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> --- .../ResetVector/Vtf0/Ia32/PageTables64.asm | 4 +-- .../ResetVector/Vtf0/X64/PageTables1G.asm | 18 ++++------ .../ResetVector/Vtf0/X64/PageTables2M.asm | 34 ++++++++----------- 3 files changed, 24 insertions(+), 32 deletions(-) diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm index XXXXXXX..XXXXXXX 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm @@ -XXX,XX +XXX,XX @@ ; @file ; Sets the CR3 register for 64-bit paging ; -; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;------------------------------------------------------------------------------ @@ -XXX,XX +XXX,XX @@ SetCr3ForPageTables64: ; ; These pages are built into the ROM image in X64/PageTables.asm ; - mov eax, ADDR_OF(TopLevelPageDirectory) + mov eax, ADDR_OF(Pml4) mov cr3, eax OneTimeCallRet SetCr3ForPageTables64 diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm index XXXXXXX..XXXXXXX 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm @@ -XXX,XX +XXX,XX @@ BITS 64 PAGE_PRESENT + \ PAGE_SIZE) -%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) -%define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x)) - ; ; Page table non-leaf entry ; -%define PAGE_NLE(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ +%define PAGE_NLE(address) (ADDR_OF(address) + \ PAGE_NLE_ATTR) %define PDPTE_1GB(x) ((x << 30) + PAGE_BLE_ATTR) ALIGN 16 -TopLevelPageDirectory: - +Pml4: ; - ; Top level Page Directory Pointers (1 * 512GB entry) + ; PML4 (1 * 512GB entry) ; - DQ PAGE_NLE(0x1000) + DQ PAGE_NLE(Pdp) + TIMES 0x1000 - ($ - Pml4) DB 0 - TIMES 0x1000-PGTBLS_OFFSET($) DB 0 +Pdp: ; - ; Next level Page Directory Pointers (512 * 1GB entries => 512GB) + ; Page-directory pointer table (512 * 1GB entries => 512GB) ; %assign i 0 %rep 512 DQ PDPTE_1GB(i) %assign i i+1 %endrep - TIMES 0x2000-PGTBLS_OFFSET($) DB 0 EndOfPageTables: diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm index XXXXXXX..XXXXXXX 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm @@ -XXX,XX +XXX,XX @@ BITS 64 PAGE_READ_WRITE + \ PAGE_PRESENT) -%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) -%define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x)) - -%define PAGE_NLE(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ +%define PAGE_NLE(address) (ADDR_OF(address) + \ PAGE_NLE_ATTR) %define PDE_2MB(x) ((x << 21) + PAGE_BLE_ATTR) -TopLevelPageDirectory: - +Pml4: ; - ; Top level Page Directory Pointers (1 * 512GB entry) + ; PML4 (1 * 512GB entry) ; - DQ PAGE_NLE(0x1000) - + DQ PAGE_NLE(Pdp) + TIMES 0x1000 - ($ - Pml4) DB 0 +Pdp: ; - ; Next level Page Directory Pointers (4 * 1GB entries => 4GB) + ; Page-directory pointer table (4 * 1GB entries => 4GB) ; - TIMES 0x1000-PGTBLS_OFFSET($) DB 0 - - DQ PAGE_NLE(0x2000) - DQ PAGE_NLE(0x3000) - DQ PAGE_NLE(0x4000) - DQ PAGE_NLE(0x5000) + DQ PAGE_NLE(Pd) + DQ PAGE_NLE(Pd + 0x1000) + DQ PAGE_NLE(Pd + 0x2000) + DQ PAGE_NLE(Pd + 0x3000) + TIMES 0x1000 - ($ - Pdp) DB 0 +Pd: ; - ; Page Table Entries (2048 * 2MB entries => 4GB) + ; Page-Directory (2048 * 2MB entries => 4GB) + ; Four pages below, each is pointed by one entry in Pdp. ; - TIMES 0x2000-PGTBLS_OFFSET($) DB 0 - %assign i 0 %rep 0x800 DQ PDE_2MB(i) -- 2.31.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#103927): https://edk2.groups.io/g/devel/message/103927 Mute This Topic: https://groups.io/mt/98676050/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
Combine PageTables1G.asm and PageTables2M.asm to reuse code. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Catharine West <catharine.west@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> --- UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 8 +-- .../X64/{PageTables1G.asm => PageTables.asm} | 38 ++++++++--- .../ResetVector/Vtf0/X64/PageTables2M.asm | 63 ------------------- 3 files changed, 33 insertions(+), 76 deletions(-) rename UefiCpuPkg/ResetVector/Vtf0/X64/{PageTables1G.asm => PageTables.asm} (57%) delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb index XXXXXXX..XXXXXXX 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb +++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb @@ -XXX,XX +XXX,XX @@ ; @file ; This file includes all other code files to assemble the reset vector code ; -; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;------------------------------------------------------------------------------ @@ -XXX,XX +XXX,XX @@ %include "PageTables.inc" %ifdef ARCH_X64 - %ifdef PAGE_TABLE_1G - %include "X64/PageTables1G.asm" - %else - %include "X64/PageTables2M.asm" - %endif + %include "X64/PageTables.asm" %endif %ifdef DEBUG_PORT80 diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm similarity index 57% rename from UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm rename to UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm index XXXXXXX..XXXXXXX 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm @@ -XXX,XX +XXX,XX @@ ;------------------------------------------------------------------------------ ; @file -; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x8000000000 (512GB) +; Emits Page Tables for 1:1 mapping. +; If using 1G page table, map addresses 0 - 0x8000000000 (512GB), +; else, map addresses 0 - 0x100000000 (4GB) ; ; Copyright (c) 2021 - 2023, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent -; Linear-Address Translation to a 1-GByte Page ; ;------------------------------------------------------------------------------ @@ -XXX,XX +XXX,XX @@ BITS 64 PAGE_NLE_ATTR) %define PDPTE_1GB(x) ((x << 30) + PAGE_BLE_ATTR) +%define PDE_2MB(x) ((x << 21) + PAGE_BLE_ATTR) ALIGN 16 @@ -XXX,XX +XXX,XX @@ Pml4: DQ PAGE_NLE(Pdp) TIMES 0x1000 - ($ - Pml4) DB 0 +%ifdef PAGE_TABLE_1G Pdp: ; ; Page-directory pointer table (512 * 1GB entries => 512GB) ; -%assign i 0 -%rep 512 - DQ PDPTE_1GB(i) - %assign i i+1 -%endrep + %assign i 0 + %rep 512 + DQ PDPTE_1GB(i) + %assign i i+1 + %endrep +%else +Pdp: + ; + ; Page-directory pointer table (4 * 1GB entries => 4GB) + ; + DQ PAGE_NLE(Pd) + DQ PAGE_NLE(Pd + 0x1000) + DQ PAGE_NLE(Pd + 0x2000) + DQ PAGE_NLE(Pd + 0x3000) + TIMES 0x1000 - ($ - Pdp) DB 0 +Pd: + ; + ; Page-Directory (2048 * 2MB entries => 4GB) + ; Four pages below, each is pointed by one entry in Pdp. + ; + %assign i 0 + %rep 0x800 + DQ PDE_2MB(i) + %assign i i+1 + %endrep +%endif EndOfPageTables: diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm deleted file mode 100644 index XXXXXXX..XXXXXXX --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm +++ /dev/null @@ -XXX,XX +XXX,XX @@ -;------------------------------------------------------------------------------ -; @file -; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x100000000 (4GB) -; -; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR> -; SPDX-License-Identifier: BSD-2-Clause-Patent -; -;------------------------------------------------------------------------------ - -BITS 64 - -%define ALIGN_TOP_TO_4K_FOR_PAGING - -; -; Page table big leaf entry attribute: -; PDPTE 1GB entry or PDE 2MB entry -; -%define PAGE_BLE_ATTR (PAGE_SIZE + \ - PAGE_ACCESSED + \ - PAGE_DIRTY + \ - PAGE_READ_WRITE + \ - PAGE_PRESENT) - -; -; Page table non-leaf entry attribute -; -%define PAGE_NLE_ATTR (PAGE_ACCESSED + \ - PAGE_READ_WRITE + \ - PAGE_PRESENT) - -%define PAGE_NLE(address) (ADDR_OF(address) + \ - PAGE_NLE_ATTR) -%define PDE_2MB(x) ((x << 21) + PAGE_BLE_ATTR) - -Pml4: - ; - ; PML4 (1 * 512GB entry) - ; - DQ PAGE_NLE(Pdp) - TIMES 0x1000 - ($ - Pml4) DB 0 - -Pdp: - ; - ; Page-directory pointer table (4 * 1GB entries => 4GB) - ; - DQ PAGE_NLE(Pd) - DQ PAGE_NLE(Pd + 0x1000) - DQ PAGE_NLE(Pd + 0x2000) - DQ PAGE_NLE(Pd + 0x3000) - TIMES 0x1000 - ($ - Pdp) DB 0 - -Pd: - ; - ; Page-Directory (2048 * 2MB entries => 4GB) - ; Four pages below, each is pointed by one entry in Pdp. - ; -%assign i 0 -%rep 0x800 - DQ PDE_2MB(i) - %assign i i+1 -%endrep - -EndOfPageTables: -- 2.31.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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In ResetVector, if create page table, its highest address is fixed because after page table, code layout is fixed(4K for normal code, and another 4K only contains reset vector code). Today's implementation organizes the page table as following if 1G page table is used: 4G-16K: PML4 page (PML4[0] points to 4G-12K) 4G-12K: PDP page CR3 is set to 4G-16K When 2M page table is used, the layout is as following: 4G-32K: PML4 page (PML4[0] points to 4G-28K) 4G-28K: PDP page (PDP entries point to PD pages) 4G-24K: PD page mapping 0-1G 4G-20K: PD page mapping 1-2G 4G-16K: PD page mapping 2-3G 4G-12K: PD page mapping 3-4G CR3 is set to 4G-32K CR3 doesn't point to a fixed location which is a bit hard to debug at runtime. The new page table layout will always put PML4 in highest address When 1G page table is used, the layout is as following: 4G-16K: PDP page 4G-12K: PML4 page (PML4[0] points to 4G-16K) When 2M page table is used, the layout is as following: 4G-32K: PD page mapping 0-1G 4G-28K: PD page mapping 1-2G 4G-24K: PD page mapping 2-3G 4G-20K: PD page mapping 3-4G 4G-16K: PDP page (PDP entries point to PD pages) 4G-12K: PML4 page (PML4[0] points to 4G-16K) CR3 is always set to 4G-12K So, this patch can improve biodegradability by make sure the init CR3 pointing to a fixed address(4G-12K). Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Catharine West <catharine.west@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> --- .../ResetVector/Vtf0/X64/PageTables.asm | 33 ++++++++++--------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm index XXXXXXX..XXXXXXX 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm @@ -XXX,XX +XXX,XX @@ BITS 64 ALIGN 16 -Pml4: - ; - ; PML4 (1 * 512GB entry) - ; - DQ PAGE_NLE(Pdp) - TIMES 0x1000 - ($ - Pml4) DB 0 - %ifdef PAGE_TABLE_1G Pdp: ; @@ -XXX,XX +XXX,XX @@ Pdp: %assign i i+1 %endrep %else -Pdp: - ; - ; Page-directory pointer table (4 * 1GB entries => 4GB) - ; - DQ PAGE_NLE(Pd) - DQ PAGE_NLE(Pd + 0x1000) - DQ PAGE_NLE(Pd + 0x2000) - DQ PAGE_NLE(Pd + 0x3000) - TIMES 0x1000 - ($ - Pdp) DB 0 Pd: ; @@ -XXX,XX +XXX,XX @@ Pd: DQ PDE_2MB(i) %assign i i+1 %endrep +Pdp: + ; + ; Page-directory pointer table (4 * 1GB entries => 4GB) + ; + DQ PAGE_NLE(Pd) + DQ PAGE_NLE(Pd + 0x1000) + DQ PAGE_NLE(Pd + 0x2000) + DQ PAGE_NLE(Pd + 0x3000) + TIMES 0x1000 - ($ - Pdp) DB 0 + %endif + +Pml4: + ; + ; PML4 (1 * 512GB entry) + ; + DQ PAGE_NLE(Pdp) + TIMES 0x1000 - ($ - Pml4) DB 0 EndOfPageTables: -- 2.31.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#103929): https://edk2.groups.io/g/devel/message/103929 Mute This Topic: https://groups.io/mt/98676053/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
Add a macro USE_5_LEVEL_PAGE_TABLE to determine whether to create 5 level page table. If macro USE_5_LEVEL_PAGE_TABLE is defined, PML5Table is created at (4G-12K), while PML4Table is at (4G-16K). In runtime check, if 5level paging is supported, use PML5Table, otherwise, use PML4Table. If macro USE_5_LEVEL_PAGE_TABLE is not defined, to save space, 5level paging is not created, and 4level paging is at (4G-12K) and be used. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Catharine West <catharine.west@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> --- .../ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm | 25 +++++++++++++++++-- .../ResetVector/Vtf0/Ia32/PageTables64.asm | 24 ------------------ UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 1 - .../ResetVector/Vtf0/X64/PageTables.asm | 9 +++++++ 4 files changed, 32 insertions(+), 27 deletions(-) delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm index XXXXXXX..XXXXXXX 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm @@ -XXX,XX +XXX,XX @@ ; @file ; Transition from 32 bit flat protected mode into 64 bit flat protected mode ; -; Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;------------------------------------------------------------------------------ @@ -XXX,XX +XXX,XX @@ BITS 32 ; Transition32FlatTo64Flat: - OneTimeCall SetCr3ForPageTables64 +%ifdef USE_5_LEVEL_PAGE_TABLE + mov eax, 0 + cpuid + cmp eax, 07h ; check if basic CPUID leaf contains leaf 07 + jb NotSupport5LevelPaging ; 5level paging not support, downgrade to 4level paging + mov eax, 07h ; check cpuid leaf 7, subleaf 0 + mov ecx, 0 + cpuid + bt ecx, 16 ; [Bits 16] Supports 5-level paging if 1. + jnc NotSupport5LevelPaging ; 5level paging not support, downgrade to 4level paging + mov eax, ADDR_OF(Pml5) + mov cr3, eax + mov eax, cr4 + bts eax, 12 ; Set LA57=1. + mov cr4, eax + jmp SetCr3Done +NotSupport5LevelPaging: +%endif + + mov eax, ADDR_OF(Pml4) + mov cr3, eax +SetCr3Done: mov eax, cr4 bts eax, 5 ; enable PAE diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm deleted file mode 100644 index XXXXXXX..XXXXXXX --- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm +++ /dev/null @@ -XXX,XX +XXX,XX @@ -;------------------------------------------------------------------------------ -; @file -; Sets the CR3 register for 64-bit paging -; -; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR> -; SPDX-License-Identifier: BSD-2-Clause-Patent -; -;------------------------------------------------------------------------------ - -BITS 32 - -; -; Modified: EAX -; -SetCr3ForPageTables64: - - ; - ; These pages are built into the ROM image in X64/PageTables.asm - ; - mov eax, ADDR_OF(Pml4) - mov cr3, eax - - OneTimeCallRet SetCr3ForPageTables64 - diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb index XXXXXXX..XXXXXXX 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb +++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb @@ -XXX,XX +XXX,XX @@ %ifdef ARCH_X64 %include "Ia32/Flat32ToFlat64.asm" -%include "Ia32/PageTables64.asm" %endif %include "Ia16/Real16ToFlat32.asm" diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm index XXXXXXX..XXXXXXX 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm @@ -XXX,XX +XXX,XX @@ Pml4: ; DQ PAGE_NLE(Pdp) TIMES 0x1000 - ($ - Pml4) DB 0 + +%ifdef USE_5_LEVEL_PAGE_TABLE +Pml5: + ; + ; Pml5 table (only first entry is present, pointing to Pml4) + ; + DQ PAGE_NLE(Pml4) + TIMES 0x1000 - ($ - Pml5) DB 0 +%endif EndOfPageTables: -- 2.31.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#103930): https://edk2.groups.io/g/devel/message/103930 Mute This Topic: https://groups.io/mt/98676054/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
This patch set simplify the page table creation code, remove some hard-code, combine files and support 5 Level paging. V4: Refine comments and update below macro names: PG_NLE -> PAGE_NLE PTE_2MB -> PDE_2MB PDP_1G -> PDPTE_1GB PAGE_BLP_ATTR -> PAGE_BLE_ATTR No code logic impact V5: Update below macro names: PDE_2MB -> PAGE_PDE_2MB PDPTE_1GB -> PAGE_PDPTE_1GB No code logic impact V6: Only change the 5th patch to be compatible with reset vector code from OvmfPkg. Other patches keep unchagned. Zhiguang Liu (5): UefiCpuPkg/ResetVector: Rename macros about page table. UefiCpuPkg/ResetVector: Simplify page table creation in ResetVector UefiCpuPkg/ResetVector: Combine PageTables1G.asm and PageTables2M.asm UefiCpuPkg/ResetVector: Modify Page Table in ResetVector UefiCpuPkg/ResetVector: Support 5 level page table in ResetVector .../ResetVector/Vtf0/Ia32/PageTables64.asm | 24 ++++- UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 8 +- .../ResetVector/Vtf0/X64/PageTables.asm | 93 +++++++++++++++++++ .../ResetVector/Vtf0/X64/PageTables1G.asm | 53 ----------- .../ResetVector/Vtf0/X64/PageTables2M.asm | 60 ------------ 5 files changed, 117 insertions(+), 121 deletions(-) create mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm -- 2.31.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#104831): https://edk2.groups.io/g/devel/message/104831 Mute This Topic: https://groups.io/mt/98894727/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
From: "Liu, Zhiguang" <Zhiguang.Liu@intel.com> This patch only renames macro, with no code logic impacted. Two purpose to rename macro: 1. Align some macro name in PageTables1G.asm and PageTables2M.asm, so that these two files can be easily combined later. 2. Some Macro names such as PDP are not accurate, since 4 level page entry also uses this macro. PAGE_NLE (no leaf entry) is better Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Catharine West <catharine.west@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> --- .../ResetVector/Vtf0/X64/PageTables1G.asm | 26 +++++++++----- .../ResetVector/Vtf0/X64/PageTables2M.asm | 35 +++++++++++-------- 2 files changed, 39 insertions(+), 22 deletions(-) diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm index XXXXXXX..XXXXXXX 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm @@ -XXX,XX +XXX,XX @@ ; @file ; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x8000000000 (512GB) ; -; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2021 - 2023, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; Linear-Address Translation to a 1-GByte Page ; @@ -XXX,XX +XXX,XX @@ BITS 64 %define ALIGN_TOP_TO_4K_FOR_PAGING -%define PAGE_PDP_ATTR (PAGE_ACCESSED + \ +; +; Page table non-leaf entry attribute +; +%define PAGE_NLE_ATTR (PAGE_ACCESSED + \ PAGE_READ_WRITE + \ PAGE_PRESENT) -%define PAGE_PDP_1G_ATTR (PAGE_ACCESSED + \ +; +; Page table big leaf entry attribute: +; PDPTE 1GB entry or PDE 2MB entry +; +%define PAGE_BLE_ATTR (PAGE_ACCESSED + \ PAGE_READ_WRITE + \ PAGE_DIRTY + \ PAGE_PRESENT + \ @@ -XXX,XX +XXX,XX @@ BITS 64 %define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) %define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x)) -%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ - PAGE_PDP_ATTR) +; +; Page table non-leaf entry +; +%define PAGE_NLE(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ + PAGE_NLE_ATTR) -%define PDP_1G(x) ((x << 30) + PAGE_PDP_1G_ATTR) +%define PAGE_PDPTE_1GB(x) ((x << 30) + PAGE_BLE_ATTR) ALIGN 16 @@ -XXX,XX +XXX,XX @@ TopLevelPageDirectory: ; ; Top level Page Directory Pointers (1 * 512GB entry) ; - DQ PDP(0x1000) + DQ PAGE_NLE(0x1000) TIMES 0x1000-PGTBLS_OFFSET($) DB 0 ; @@ -XXX,XX +XXX,XX @@ TopLevelPageDirectory: ; %assign i 0 %rep 512 - DQ PDP_1G(i) + DQ PAGE_PDPTE_1GB(i) %assign i i+1 %endrep TIMES 0x2000-PGTBLS_OFFSET($) DB 0 diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm index XXXXXXX..XXXXXXX 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm @@ -XXX,XX +XXX,XX @@ ; @file ; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x100000000 (4GB) ; -; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;------------------------------------------------------------------------------ @@ -XXX,XX +XXX,XX @@ BITS 64 %define ALIGN_TOP_TO_4K_FOR_PAGING -%define PAGE_2M_PDE_ATTR (PAGE_SIZE + \ +; +; Page table big leaf entry attribute: +; PDPTE 1GB entry or PDE 2MB entry +; +%define PAGE_BLE_ATTR (PAGE_SIZE + \ PAGE_ACCESSED + \ PAGE_DIRTY + \ PAGE_READ_WRITE + \ PAGE_PRESENT) -%define PAGE_PDP_ATTR (PAGE_ACCESSED + \ - PAGE_READ_WRITE + \ - PAGE_PRESENT) +; +; Page table non-leaf entry attribute +; +%define PAGE_NLE_ATTR (PAGE_ACCESSED + \ + PAGE_READ_WRITE + \ + PAGE_PRESENT) %define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) %define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x)) -%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ - PAGE_PDP_ATTR) -%define PTE_2MB(x) ((x << 21) + PAGE_2M_PDE_ATTR) +%define PAGE_NLE(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ + PAGE_NLE_ATTR) +%define PAGE_PDE_2MB(x) ((x << 21) + PAGE_BLE_ATTR) TopLevelPageDirectory: ; ; Top level Page Directory Pointers (1 * 512GB entry) ; - DQ PDP(0x1000) + DQ PAGE_NLE(0x1000) ; @@ -XXX,XX +XXX,XX @@ TopLevelPageDirectory: ; TIMES 0x1000-PGTBLS_OFFSET($) DB 0 - DQ PDP(0x2000) - DQ PDP(0x3000) - DQ PDP(0x4000) - DQ PDP(0x5000) + DQ PAGE_NLE(0x2000) + DQ PAGE_NLE(0x3000) + DQ PAGE_NLE(0x4000) + DQ PAGE_NLE(0x5000) ; ; Page Table Entries (2048 * 2MB entries => 4GB) @@ -XXX,XX +XXX,XX @@ TopLevelPageDirectory: %assign i 0 %rep 0x800 - DQ PTE_2MB(i) + DQ PAGE_PDE_2MB(i) %assign i i+1 %endrep -- 2.31.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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From: "Liu, Zhiguang" <Zhiguang.Liu@intel.com> Currently, page table creation has many hard-code values about the offset to the start of page table. To simplify it, add Labels such as Pml4, Pdp and Pd, so that we can remove many hard-code values Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Catharine West <catharine.west@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> --- .../ResetVector/Vtf0/Ia32/PageTables64.asm | 4 +-- .../ResetVector/Vtf0/X64/PageTables1G.asm | 18 ++++------ .../ResetVector/Vtf0/X64/PageTables2M.asm | 34 ++++++++----------- 3 files changed, 24 insertions(+), 32 deletions(-) diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm index XXXXXXX..XXXXXXX 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm @@ -XXX,XX +XXX,XX @@ ; @file ; Sets the CR3 register for 64-bit paging ; -; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;------------------------------------------------------------------------------ @@ -XXX,XX +XXX,XX @@ SetCr3ForPageTables64: ; ; These pages are built into the ROM image in X64/PageTables.asm ; - mov eax, ADDR_OF(TopLevelPageDirectory) + mov eax, ADDR_OF(Pml4) mov cr3, eax OneTimeCallRet SetCr3ForPageTables64 diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm index XXXXXXX..XXXXXXX 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm @@ -XXX,XX +XXX,XX @@ BITS 64 PAGE_PRESENT + \ PAGE_SIZE) -%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) -%define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x)) - ; ; Page table non-leaf entry ; -%define PAGE_NLE(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ +%define PAGE_NLE(address) (ADDR_OF(address) + \ PAGE_NLE_ATTR) %define PAGE_PDPTE_1GB(x) ((x << 30) + PAGE_BLE_ATTR) ALIGN 16 -TopLevelPageDirectory: - +Pml4: ; - ; Top level Page Directory Pointers (1 * 512GB entry) + ; PML4 (1 * 512GB entry) ; - DQ PAGE_NLE(0x1000) + DQ PAGE_NLE(Pdp) + TIMES 0x1000 - ($ - Pml4) DB 0 - TIMES 0x1000-PGTBLS_OFFSET($) DB 0 +Pdp: ; - ; Next level Page Directory Pointers (512 * 1GB entries => 512GB) + ; Page-directory pointer table (512 * 1GB entries => 512GB) ; %assign i 0 %rep 512 DQ PAGE_PDPTE_1GB(i) %assign i i+1 %endrep - TIMES 0x2000-PGTBLS_OFFSET($) DB 0 EndOfPageTables: diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm index XXXXXXX..XXXXXXX 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm @@ -XXX,XX +XXX,XX @@ BITS 64 PAGE_READ_WRITE + \ PAGE_PRESENT) -%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) -%define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x)) - -%define PAGE_NLE(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ +%define PAGE_NLE(address) (ADDR_OF(address) + \ PAGE_NLE_ATTR) %define PAGE_PDE_2MB(x) ((x << 21) + PAGE_BLE_ATTR) -TopLevelPageDirectory: - +Pml4: ; - ; Top level Page Directory Pointers (1 * 512GB entry) + ; PML4 (1 * 512GB entry) ; - DQ PAGE_NLE(0x1000) - + DQ PAGE_NLE(Pdp) + TIMES 0x1000 - ($ - Pml4) DB 0 +Pdp: ; - ; Next level Page Directory Pointers (4 * 1GB entries => 4GB) + ; Page-directory pointer table (4 * 1GB entries => 4GB) ; - TIMES 0x1000-PGTBLS_OFFSET($) DB 0 - - DQ PAGE_NLE(0x2000) - DQ PAGE_NLE(0x3000) - DQ PAGE_NLE(0x4000) - DQ PAGE_NLE(0x5000) + DQ PAGE_NLE(Pd) + DQ PAGE_NLE(Pd + 0x1000) + DQ PAGE_NLE(Pd + 0x2000) + DQ PAGE_NLE(Pd + 0x3000) + TIMES 0x1000 - ($ - Pdp) DB 0 +Pd: ; - ; Page Table Entries (2048 * 2MB entries => 4GB) + ; Page-Directory (2048 * 2MB entries => 4GB) + ; Four pages below, each is pointed by one entry in Pdp. ; - TIMES 0x2000-PGTBLS_OFFSET($) DB 0 - %assign i 0 %rep 0x800 DQ PAGE_PDE_2MB(i) -- 2.31.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#104833): https://edk2.groups.io/g/devel/message/104833 Mute This Topic: https://groups.io/mt/98894732/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
From: "Liu, Zhiguang" <Zhiguang.Liu@intel.com> Combine PageTables1G.asm and PageTables2M.asm to reuse code. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Catharine West <catharine.west@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> --- UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 8 +-- .../X64/{PageTables1G.asm => PageTables.asm} | 38 ++++++++--- .../ResetVector/Vtf0/X64/PageTables2M.asm | 63 ------------------- 3 files changed, 33 insertions(+), 76 deletions(-) rename UefiCpuPkg/ResetVector/Vtf0/X64/{PageTables1G.asm => PageTables.asm} (57%) delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb index XXXXXXX..XXXXXXX 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb +++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb @@ -XXX,XX +XXX,XX @@ ; @file ; This file includes all other code files to assemble the reset vector code ; -; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;------------------------------------------------------------------------------ @@ -XXX,XX +XXX,XX @@ %include "PageTables.inc" %ifdef ARCH_X64 - %ifdef PAGE_TABLE_1G - %include "X64/PageTables1G.asm" - %else - %include "X64/PageTables2M.asm" - %endif + %include "X64/PageTables.asm" %endif %ifdef DEBUG_PORT80 diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm similarity index 57% rename from UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm rename to UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm index XXXXXXX..XXXXXXX 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm @@ -XXX,XX +XXX,XX @@ ;------------------------------------------------------------------------------ ; @file -; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x8000000000 (512GB) +; Emits Page Tables for 1:1 mapping. +; If using 1G page table, map addresses 0 - 0x8000000000 (512GB), +; else, map addresses 0 - 0x100000000 (4GB) ; ; Copyright (c) 2021 - 2023, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent -; Linear-Address Translation to a 1-GByte Page ; ;------------------------------------------------------------------------------ @@ -XXX,XX +XXX,XX @@ BITS 64 PAGE_NLE_ATTR) %define PAGE_PDPTE_1GB(x) ((x << 30) + PAGE_BLE_ATTR) +%define PAGE_PDE_2MB(x) ((x << 21) + PAGE_BLE_ATTR) ALIGN 16 @@ -XXX,XX +XXX,XX @@ Pml4: DQ PAGE_NLE(Pdp) TIMES 0x1000 - ($ - Pml4) DB 0 +%ifdef PAGE_TABLE_1G Pdp: ; ; Page-directory pointer table (512 * 1GB entries => 512GB) ; -%assign i 0 -%rep 512 - DQ PAGE_PDPTE_1GB(i) - %assign i i+1 -%endrep + %assign i 0 + %rep 512 + DQ PAGE_PDPTE_1GB(i) + %assign i i+1 + %endrep +%else +Pdp: + ; + ; Page-directory pointer table (4 * 1GB entries => 4GB) + ; + DQ PAGE_NLE(Pd) + DQ PAGE_NLE(Pd + 0x1000) + DQ PAGE_NLE(Pd + 0x2000) + DQ PAGE_NLE(Pd + 0x3000) + TIMES 0x1000 - ($ - Pdp) DB 0 +Pd: + ; + ; Page-Directory (2048 * 2MB entries => 4GB) + ; Four pages below, each is pointed by one entry in Pdp. + ; + %assign i 0 + %rep 0x800 + DQ PAGE_PDE_2MB(i) + %assign i i+1 + %endrep +%endif EndOfPageTables: diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm deleted file mode 100644 index XXXXXXX..XXXXXXX --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm +++ /dev/null @@ -XXX,XX +XXX,XX @@ -;------------------------------------------------------------------------------ -; @file -; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x100000000 (4GB) -; -; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR> -; SPDX-License-Identifier: BSD-2-Clause-Patent -; -;------------------------------------------------------------------------------ - -BITS 64 - -%define ALIGN_TOP_TO_4K_FOR_PAGING - -; -; Page table big leaf entry attribute: -; PDPTE 1GB entry or PDE 2MB entry -; -%define PAGE_BLE_ATTR (PAGE_SIZE + \ - PAGE_ACCESSED + \ - PAGE_DIRTY + \ - PAGE_READ_WRITE + \ - PAGE_PRESENT) - -; -; Page table non-leaf entry attribute -; -%define PAGE_NLE_ATTR (PAGE_ACCESSED + \ - PAGE_READ_WRITE + \ - PAGE_PRESENT) - -%define PAGE_NLE(address) (ADDR_OF(address) + \ - PAGE_NLE_ATTR) -%define PAGE_PDE_2MB(x) ((x << 21) + PAGE_BLE_ATTR) - -Pml4: - ; - ; PML4 (1 * 512GB entry) - ; - DQ PAGE_NLE(Pdp) - TIMES 0x1000 - ($ - Pml4) DB 0 - -Pdp: - ; - ; Page-directory pointer table (4 * 1GB entries => 4GB) - ; - DQ PAGE_NLE(Pd) - DQ PAGE_NLE(Pd + 0x1000) - DQ PAGE_NLE(Pd + 0x2000) - DQ PAGE_NLE(Pd + 0x3000) - TIMES 0x1000 - ($ - Pdp) DB 0 - -Pd: - ; - ; Page-Directory (2048 * 2MB entries => 4GB) - ; Four pages below, each is pointed by one entry in Pdp. - ; -%assign i 0 -%rep 0x800 - DQ PAGE_PDE_2MB(i) - %assign i i+1 -%endrep - -EndOfPageTables: -- 2.31.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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From: "Liu, Zhiguang" <Zhiguang.Liu@intel.com> In ResetVector, if create page table, its highest address is fixed because after page table, code layout is fixed(4K for normal code, and another 4K only contains reset vector code). Today's implementation organizes the page table as following if 1G page table is used: 4G-16K: PML4 page (PML4[0] points to 4G-12K) 4G-12K: PDP page CR3 is set to 4G-16K When 2M page table is used, the layout is as following: 4G-32K: PML4 page (PML4[0] points to 4G-28K) 4G-28K: PDP page (PDP entries point to PD pages) 4G-24K: PD page mapping 0-1G 4G-20K: PD page mapping 1-2G 4G-16K: PD page mapping 2-3G 4G-12K: PD page mapping 3-4G CR3 is set to 4G-32K CR3 doesn't point to a fixed location which is a bit hard to debug at runtime. The new page table layout will always put PML4 in highest address When 1G page table is used, the layout is as following: 4G-16K: PDP page 4G-12K: PML4 page (PML4[0] points to 4G-16K) When 2M page table is used, the layout is as following: 4G-32K: PD page mapping 0-1G 4G-28K: PD page mapping 1-2G 4G-24K: PD page mapping 2-3G 4G-20K: PD page mapping 3-4G 4G-16K: PDP page (PDP entries point to PD pages) 4G-12K: PML4 page (PML4[0] points to 4G-16K) CR3 is always set to 4G-12K So, this patch can improve debuggability by make sure the init CR3 pointing to a fixed address(4G-12K). Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Catharine West <catharine.west@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> --- .../ResetVector/Vtf0/X64/PageTables.asm | 33 ++++++++++--------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm index XXXXXXX..XXXXXXX 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm @@ -XXX,XX +XXX,XX @@ BITS 64 ALIGN 16 -Pml4: - ; - ; PML4 (1 * 512GB entry) - ; - DQ PAGE_NLE(Pdp) - TIMES 0x1000 - ($ - Pml4) DB 0 - %ifdef PAGE_TABLE_1G Pdp: ; @@ -XXX,XX +XXX,XX @@ Pdp: %assign i i+1 %endrep %else -Pdp: - ; - ; Page-directory pointer table (4 * 1GB entries => 4GB) - ; - DQ PAGE_NLE(Pd) - DQ PAGE_NLE(Pd + 0x1000) - DQ PAGE_NLE(Pd + 0x2000) - DQ PAGE_NLE(Pd + 0x3000) - TIMES 0x1000 - ($ - Pdp) DB 0 Pd: ; @@ -XXX,XX +XXX,XX @@ Pd: DQ PAGE_PDE_2MB(i) %assign i i+1 %endrep +Pdp: + ; + ; Page-directory pointer table (4 * 1GB entries => 4GB) + ; + DQ PAGE_NLE(Pd) + DQ PAGE_NLE(Pd + 0x1000) + DQ PAGE_NLE(Pd + 0x2000) + DQ PAGE_NLE(Pd + 0x3000) + TIMES 0x1000 - ($ - Pdp) DB 0 + %endif + +Pml4: + ; + ; PML4 (1 * 512GB entry) + ; + DQ PAGE_NLE(Pdp) + TIMES 0x1000 - ($ - Pml4) DB 0 EndOfPageTables: -- 2.31.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#104835): https://edk2.groups.io/g/devel/message/104835 Mute This Topic: https://groups.io/mt/98894735/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
Add a macro USE_5_LEVEL_PAGE_TABLE to determine whether to create 5 level page table. If macro USE_5_LEVEL_PAGE_TABLE is defined, PML5Table is created at (4G-12K), while PML4Table is at (4G-16K). In runtime check, if 5level paging is supported, use PML5Table, otherwise, use PML4Table. If macro USE_5_LEVEL_PAGE_TABLE is not defined, to save space, 5level paging is not created, and 4level paging is at (4G-12K) and be used. V6: In previous version, I merge code from Ia32\PageTables64.asm into Ia32\Flat32ToFlat64.asm to reduce files. However, reset vector from OvmfPkg\Bhyve\ResetVector needs the code from Flat32ToFlat64.asm, and needs its OneTimeCall SetCr3ForPageTables64. To be compatible, in this version, I keep the file PageTables64.asm, and implement 5level paging logic there. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Catharine West <catharine.west@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> --- .../ResetVector/Vtf0/Ia32/PageTables64.asm | 20 +++++++++++++++++++ .../ResetVector/Vtf0/X64/PageTables.asm | 9 +++++++++ 2 files changed, 29 insertions(+) diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm index XXXXXXX..XXXXXXX 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm @@ -XXX,XX +XXX,XX @@ SetCr3ForPageTables64: ; ; These pages are built into the ROM image in X64/PageTables.asm ; +%ifdef USE_5_LEVEL_PAGE_TABLE + mov eax, 0 + cpuid + cmp eax, 07h ; check if basic CPUID leaf contains leaf 07 + jb NotSupport5LevelPaging ; 5level paging not support, downgrade to 4level paging + mov eax, 07h ; check cpuid leaf 7, subleaf 0 + mov ecx, 0 + cpuid + bt ecx, 16 ; [Bits 16] Supports 5-level paging if 1. + jnc NotSupport5LevelPaging ; 5level paging not support, downgrade to 4level paging + mov eax, ADDR_OF(Pml5) + mov cr3, eax + mov eax, cr4 + bts eax, 12 ; Set LA57=1. + mov cr4, eax + jmp SetCr3Done +NotSupport5LevelPaging: +%endif + mov eax, ADDR_OF(Pml4) mov cr3, eax +SetCr3Done: OneTimeCallRet SetCr3ForPageTables64 diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm index XXXXXXX..XXXXXXX 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm @@ -XXX,XX +XXX,XX @@ Pml4: ; DQ PAGE_NLE(Pdp) TIMES 0x1000 - ($ - Pml4) DB 0 + +%ifdef USE_5_LEVEL_PAGE_TABLE +Pml5: + ; + ; Pml5 table (only first entry is present, pointing to Pml4) + ; + DQ PAGE_NLE(Pml4) + TIMES 0x1000 - ($ - Pml5) DB 0 +%endif EndOfPageTables: -- 2.31.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#104836): https://edk2.groups.io/g/devel/message/104836 Mute This Topic: https://groups.io/mt/98894736/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-