From nobody Mon Feb 9 12:43:34 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+102596+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+102596+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1680758810; cv=none; d=zohomail.com; s=zohoarc; b=h+ZA1pWkYcseB/7n2wxStY0PQ8rfSYa23Bru0IVlA1FEEStr4aUwr5P7RFuH57ls2Xg5Ed+8cm+0CoKHqzb5fRx/2OjqJaoBGPsa4kl4lQcrKja0pgbpW/ElLwID48xDcqVSvBgVh0NH9n7cCFRQcHllIwqd6hk9BtJNlC1WXcw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680758810; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=U8pcrdglB7thpLJHui5L3mmyue3j35t+l/MGtLpb/5w=; b=bfEUhMNYBIhgnXKuED3FANkkjwTCxllOyiIKEp6RDNbw61mmlKomEY24pxjhIbnNeDcbW/uEiIpnM4U4HvlwqrOZOtVMxvoJfLgupUC1r/9r6o1zR6aXWecq8oXZimgVY34S2MK36MYLa2llJJY4RDquAqIPQFOETEMqB9cfmjU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+102596+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1680758810317318.13726097337064; Wed, 5 Apr 2023 22:26:50 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id rWxKYY1788612xZpdlDlWPkR; Wed, 05 Apr 2023 22:26:50 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.151669.1680758806637645849 for ; Wed, 05 Apr 2023 22:26:49 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10671"; a="323020664" X-IronPort-AV: E=Sophos;i="5.98,322,1673942400"; d="scan'208";a="323020664" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Apr 2023 22:26:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10671"; a="776325009" X-IronPort-AV: E=Sophos;i="5.98,322,1673942400"; d="scan'208";a="776325009" X-Received: from evancy.sh.intel.com ([10.239.158.113]) by FMSMGA003.fm.intel.com with ESMTP; 05 Apr 2023 22:26:47 -0700 From: "Chai, Evan" To: devel@edk2.groups.io Cc: Daniel Schaefer , Sunil V L , Andrei Warkentin Subject: [edk2-devel] [edk2-platforms][PATCH 4/5] Silicon/RISC-V: remove redundant function code from RiscVCpuLib Date: Thu, 6 Apr 2023 13:24:22 +0800 Message-Id: <20230406052423.378702-5-evan.chai@intel.com> In-Reply-To: <20230406052423.378702-1-evan.chai@intel.com> References: <20230406052423.378702-1-evan.chai@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,evan.chai@intel.com X-Gm-Message-State: ZnoIBEs5r23THeFMTTje0Moux1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1680758810; bh=jSCYrG2PaN9U77bt9p0IkF2cDbic+D5uB/OlgpBJ8dU=; h=Cc:Date:From:Reply-To:Subject:To; b=Bc3coDNBAoy0MJ8/Gp1tVLCu96sVTDkTmWQnRbJy8p1uynx6yqYxgfcOz8yFODp7sIb oAAoGAJJ6FJWTBzZUTwzn2REauiyEbegYTSTZCB7BL12OXWog6I+1Zcf1qBnoxV1IFdj6 4vk2IkT3B6jl2qjQ/nO6Yc5kjV6L/mNsKkE= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1680758812465100019 Content-Type: text/plain; charset="utf-8" They had been implemented in MdePkg/Library/BaseLib Cc: Daniel Schaefer Cc: Sunil V L Cc: Andrei Warkentin Signed-off-by: Evan Chai --- Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h | 20 +----------= --------- Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S | 41 +----------= ------------------------------ 2 files changed, 2 insertions(+), 59 deletions(-) diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h b/Si= licon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h index efe85489..f1555843 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h @@ -2,6 +2,7 @@ RISC-V CPU library definitions. =20 Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ Copyright (c) 2023, Intel Corporation. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -96,23 +97,4 @@ RiscVReadMachineImplementId ( VOID ); =20 -VOID - RiscVSetSupervisorAddressTranslationRegister (UINT64); - -VOID - RiscVSetSupervisorScratch (UINT64); - -UINT64 -RiscVGetSupervisorScratch ( - VOID - ); - -VOID - RiscVSetSupervisorStvec (UINT64); - -UINT64 -RiscVGetSupervisorStvec ( - VOID - ); - #endif diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S b/Silico= n/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S index e242c9b8..52ef0788 100644 --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S @@ -3,6 +3,7 @@ // RISC-V CPU functions. // // Copyright (c) 2016 - 2021, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+// Copyright (c) 2023, Intel Corporation. All rights reserved.
// // SPDX-License-Identifier: BSD-2-Clause-Patent // @@ -101,43 +102,3 @@ ASM_FUNC (RiscVReadMachineImplementId) csrr a0, RISCV_CSR_MACHINE_MIMPID ret =20 -// -// Set Supervisor mode scratch. -// @param a0 : Value set to Supervisor mode scratch -// -ASM_FUNC (RiscVSetSupervisorScratch) - csrrw a1, RISCV_CSR_SUPERVISOR_SSCRATCH, a0 - ret - -// -// Get Supervisor mode scratch. -// @retval a0 : Value in Supervisor mode scratch -// -ASM_FUNC (RiscVGetSupervisorScratch) - csrr a0, RISCV_CSR_SUPERVISOR_SSCRATCH - ret - -// -// Set Supervisor mode trap vector. -// @param a0 : Value set to Supervisor mode trap vector -// -ASM_FUNC (RiscVSetSupervisorStvec) - csrrw a1, RISCV_CSR_SUPERVISOR_STVEC, a0 - ret - -// -// Get Supervisor mode scratch. -// @retval a0 : Value in Supervisor mode trap vector -// -ASM_FUNC (RiscVGetSupervisorStvec) - csrr a0, RISCV_CSR_SUPERVISOR_STVEC - ret - -// -// Set Supervisor Address Translation and -// Protection Register. -// -ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister) - csrw RISCV_CSR_SUPERVISOR_SATP, a0 - ret - --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#102596): https://edk2.groups.io/g/devel/message/102596 Mute This Topic: https://groups.io/mt/98099331/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-