From nobody Mon Feb 9 09:16:29 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+102360+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+102360+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1680448724; cv=none; d=zohomail.com; s=zohoarc; b=IeA2EryNTI9gKkpkQxsS1+VcZDOPmUjLIRayTqRTHPLhFkXenM59ihDccQKjWjOA81bJgP/hivMXcZFJGaGZlKjZCs+rE1zYQO73ohZwsHKXe0jVkOpTCvJ7Z57ZaOPk0aR7KLa2eWgqf4Bu3OOtxurxKsOmouSBt5eOm0Q7cTs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680448724; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=ZO0nrPBQgXYu5zgS/dErm4Ar9SFH4hWXlaDCu9tzxQ4=; b=QW+1QxNjJWKJQssbPRbQT4mOIC2/i8/eKNOlAf5wru45BCOEdWSaJmEMeS0bnote9dPFZ+5WlUIw+QhcNqTQ72qCWsgfcqD2J/KR023u4gb8AUdn3Ex9x+8NeYN9pcQ+eAMUpt4c/EH8yddhuG3S5x5ILYwokGU9ThvBvAPqW3M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+102360+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1680448724027199.79463726884512; Sun, 2 Apr 2023 08:18:44 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 8Db8YY1788612xhvizsn9Dnd; Sun, 02 Apr 2023 08:18:43 -0700 X-Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mx.groups.io with SMTP id smtpd.web11.46847.1680448715581016067 for ; Sun, 02 Apr 2023 08:18:43 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10668"; a="321400377" X-IronPort-AV: E=Sophos;i="5.98,312,1673942400"; d="scan'208";a="321400377" X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Apr 2023 08:18:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10668"; a="679188176" X-IronPort-AV: E=Sophos;i="5.98,312,1673942400"; d="scan'208";a="679188176" X-Received: from evancy.sh.intel.com ([10.239.158.113]) by orsmga007.jf.intel.com with ESMTP; 02 Apr 2023 08:18:41 -0700 From: "Chai, Evan" To: devel@edk2.groups.io Cc: Daniel Schaefer , Sunil V L , Andrei Warkentin Subject: [edk2-devel] [PATCH 5/5] Platform/ Siliocn/: Fix building failure caused by wrong lib. Date: Sun, 2 Apr 2023 23:15:42 +0800 Message-Id: <20230402151542.325929-6-evan.chai@intel.com> In-Reply-To: <20230402151542.325929-1-evan.chai@intel.com> References: <20230402151542.325929-1-evan.chai@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,evan.chai@intel.com X-Gm-Message-State: LlZ60qGnfBUe81wvyWO7O4fqx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1680448723; bh=m5xpCH0Rt+TZRjJR0KKva6CwugoldlLDhPewK1/YZM8=; h=Cc:Date:From:Reply-To:Subject:To; b=kCzXDGSX0t4vUK3tRzUbaZnrm9c9E20K+HZG4FkqORk9AoqSCgYMkbhXhfsmRltTVNi bzM+Z9Va4QERqnP7RJHOjMyiEaEQfOy6+PiNXPpYz/JW/q8ZR62Y3z3JJMp0KI6aPLix8 WOTQ1mfWx/dlThVyVhsTDri4G+eXPB3ZUmU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1680448725099100002 Content-Type: text/plain; charset="utf-8" RiscVSbiLib was implemented in MdePkg/Library/BaseRiscVSbiLib. Cc: Daniel Schaefer Cc: Sunil V L Cc: Andrei Warkentin Signed-off-by: Evan Chai --- Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.c = | 4 +++- Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf = | 4 +++- Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf = | 3 ++- Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc = | 4 ++-- Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc = | 4 ++-- Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbServ= icesRuntimeDxe.inf | 2 ++ Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf = | 3 ++- 7 files changed, 16 insertions(+), 8 deletions(-) diff --git a/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystem= Lib.c b/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.c index 524b0a63..30ec8a8b 100644 --- a/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.c +++ b/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.c @@ -2,13 +2,15 @@ Reset System Library functions for RISC-V =20 Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.=
+ Copyright (c) 2023, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ =20 #include #include -#include +#include =20 /** This function causes a system-wide reset (cold reset), in which diff --git a/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystem= Lib.inf b/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib= .inf index 8987adb9..605d9efd 100644 --- a/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf +++ b/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf @@ -2,6 +2,8 @@ # Library instance for ResetSystem library class for RISC-V using SBI eca= lls # # Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2023, Intel Corporation. All rights reserved.
+# # SPDX-License-Identifier: BSD-2-Clause-Patent # =20 @@ -29,4 +31,4 @@ =20 [LibraryClasses] DebugLib - RiscVEdk2SbiLib + RiscVSbiLib diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platfo= rm/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf index 1e8d53f4..8eef9fbb 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf @@ -2,6 +2,7 @@ # RISC-V SEC module. # # Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2023, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -52,7 +53,7 @@ RiscVCpuLib RiscVOpensbiLib RiscVOpensbiPlatformLib - RiscVEdk2SbiLib + RiscVSbiLib =20 [FixedPcd] gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvBase diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc b/P= latform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc index 95bf5ac4..4dc24386 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc +++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc @@ -148,10 +148,10 @@ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf !endif RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.= inf - RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/Risc= VEdk2SbiLib.inf + RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf RiscVPlatformTimerLib|Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformT= imerLib/RiscVPlatformTimerLib.inf MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachine= ModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf - CpuExceptionHandlerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptio= nLib/CpuExceptionHandlerDxeLib.inf + CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandler= Lib/BaseRiscV64CpuExceptionHandlerLib.inf =20 # Flattened Device Tree (FDT) access library FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.d= sc index 099c4e22..9dff112d 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc @@ -149,11 +149,11 @@ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf !endif RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.= inf - RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/Risc= VEdk2SbiLib.inf + RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf RiscVPlatformTimerLib|Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformT= imerLib/RiscVPlatformTimerLib.inf #MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachin= eModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachine= ModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf - CpuExceptionHandlerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptio= nLib/CpuExceptionHandlerDxeLib.inf + CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandler= Lib/BaseRiscV64CpuExceptionHandlerLib.inf =20 =20 # Flattened Device Tree (FDT) access library diff --git a/Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntim= eDxe/FvbServicesRuntimeDxe.inf b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/= RamFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf index 1158fe62..773b149b 100644 --- a/Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/Fv= bServicesRuntimeDxe.inf +++ b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/Fv= bServicesRuntimeDxe.inf @@ -6,6 +6,7 @@ # Protocol for a RAM flash device. # # Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2023, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -37,6 +38,7 @@ MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec + Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec =20 [LibraryClasses] BaseLib diff --git a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib= .inf b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf index 072024dc..13c25506 100644 --- a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf +++ b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf @@ -2,6 +2,7 @@ # Library instance to create core information HOB # # Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2023, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -38,7 +39,7 @@ MemoryAllocationLib PrintLib FirmwareContextProcessorSpecificLib - RiscVEdk2SbiLib + RiscVSbiLib =20 [FixedPcd] gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#102360): https://edk2.groups.io/g/devel/message/102360 Mute This Topic: https://groups.io/mt/98015416/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-