From nobody Sun May 5 11:07:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+102278+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+102278+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1680256916; cv=none; d=zohomail.com; s=zohoarc; b=gRmvZVaVpl9S+9lw3vf09i2MiXOXy2WN84FEeJZDZ/T0+Bnaxl2ydFARSIeTlqkEgXzkMwEBQWuAjOZpfj3OiLI9Z7ee1Sa5SXE9DDlf/Tu5dqqAl/wTvlDMuV2yIBGdOdNEJfIcShJt4Takm4nMSW/NW4VbVneh1aNwpNFRuSI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680256916; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=YV21ERkTCwqLzl+WndIOWCANqIL5PIQQYRTbyyEXs5g=; b=U1TrEhGTdh+oq2+yS+uCWOWQstgBAwyB9tdZH3NIwFwemEvuzaN9pqKqoWzOD+mC0jREYGOTVZA355CC04s/NBUfedm9NysZM/Mc6QjZvly8n9yYVoPQQCXZuebN5doM05t7XFKsi9sQxwa8uUhGbk84prb2EYelcNY5PJp7zgo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+102278+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1680256916970262.470828835372; Fri, 31 Mar 2023 03:01:56 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id rBKTYY1788612x8F4CrvWUb9; Fri, 31 Mar 2023 03:01:56 -0700 X-Received: from mail-pg1-f182.google.com (mail-pg1-f182.google.com [209.85.215.182]) by mx.groups.io with SMTP id smtpd.web10.50924.1680256915795381877 for ; Fri, 31 Mar 2023 03:01:56 -0700 X-Received: by mail-pg1-f182.google.com with SMTP id d10so13070479pgt.12 for ; Fri, 31 Mar 2023 03:01:55 -0700 (PDT) X-Gm-Message-State: TzUUck7VITs8K9jJNnohBWaFx1787277AA= X-Google-Smtp-Source: AKy350aRySxdEKbW6ongw5PWOk161qhDsUENXWuAA6qbi4+y/Q1ABuW9O6ajoCwYRsiPyqC8qSyXew== X-Received: by 2002:a62:180d:0:b0:628:1852:7343 with SMTP id 13-20020a62180d000000b0062818527343mr25850560pfy.2.1680256914955; Fri, 31 Mar 2023 03:01:54 -0700 (PDT) X-Received: from dhaval.. ([2402:3a80:8ff:2244:e77a:2b3c:51a8:11da]) by smtp.gmail.com with ESMTPSA id s25-20020aa78d59000000b0059442ec49a2sm1107411pfe.146.2023.03.31.03.01.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Mar 2023 03:01:54 -0700 (PDT) From: "Dhaval Sharma" To: devel@edk2.groups.io Cc: Sunil V L , Andrei Warkentin , Da Michael D Kinney , Liming Gao , Zhiguang Liu , niel Schaefer Subject: [edk2-devel] [PATCH v2 1/2] WIP: MdePkg/RiscVCMOCacheMaintenanceLib:Enable RISCV CMO Date: Fri, 31 Mar 2023 15:31:45 +0530 Message-Id: <20230331100146.242814-2-dhaval@rivosinc.com> In-Reply-To: <20230331100146.242814-1-dhaval@rivosinc.com> References: <20230331100146.242814-1-dhaval@rivosinc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dhaval@rivosinc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1680256916; bh=szvta7tK5dVawCdzr2yhw2CTs4w53m9y0BLS+SdOPXc=; h=Cc:Date:From:Reply-To:Subject:To; b=NiekI+4P+tz5C8kXxRtfwS95JqoIAWdD5UBg6t4xJtwXhReP9LPIHAgLElyJZ574K9x vjBhOcxzxP9O73alxqwdjAjDqkbX0m+DWiDKqrKcAuhP+8rqWBdMAGholUkqlj6OqVWhL 1sOhd0qC790TBSYyjF4IozEKhRQkb3mWVY4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1680256918265100005 Content-Type: text/plain; charset="utf-8" Adding code to support Cache Management Operations (CMO) defined by RV spec https://github.com/riscv/riscv-CMOs Notes: 1. CMO only supports block based Operations. Meaning complete cache flush/invd/clean Operations are not available 2. Current implementation uses ifence instructions but it maybe platform specific. Many platforms may not support cache Operations based on fence.i 3. For now adding CMO on top of fence.i as it is not supposed to have any adverse effect on CMO operation. 4. This requires support for GCC12.2 onwards. Test: 1. Ensured correct instructions are refelecting in asm 2. Able to boot platform with RiscVVirtQemu config 3. Not able to verify actual instruction in HW as Qemu ignores any actual cache operations. Cc: Sunil V L Cc: Andrei Warkentin Cc: Da Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: niel Schaefer Signed-off-by: Dhaval Sharma --- Notes: v2: - Added separate CMO Lib to RiscV instead of mixing it up with existing BaseCacheMaintenanceLib that has fence.i based implementation. With this we have flexibility to chose the library based on configurable option in dsc. MdePkg/MdePkg.dsc = | 1 + MdePkg/Library/RiscVCMOCacheMaintenanceLib/RiscVCMOCacheMaintenanceLib.inf= | 30 ++ MdePkg/Library/RiscVCMOCacheMaintenanceLib/RiscVCMOCache.c = | 377 ++++++++++++++++++++ MdePkg/Library/RiscVCMOCacheMaintenanceLib/RiscVCMOCacheMaintenanceLib.uni= | 11 + MdePkg/Library/RiscVCMOCacheMaintenanceLib/RiscVCpuCMOCache.S = | 23 ++ 5 files changed, 442 insertions(+) diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc index 0ac7618b4623..78870c916433 100644 --- a/MdePkg/MdePkg.dsc +++ b/MdePkg/MdePkg.dsc @@ -192,5 +192,6 @@ [Components.ARM, Components.AARCH64] =20 [Components.RISCV64] MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf + MdePkg/Library/RiscVCMOCacheMaintenanceLib/RiscVCMOCacheMaintenanceLib.i= nf =20 [BuildOptions] diff --git a/MdePkg/Library/RiscVCMOCacheMaintenanceLib/RiscVCMOCacheMainte= nanceLib.inf b/MdePkg/Library/RiscVCMOCacheMaintenanceLib/RiscVCMOCacheMain= tenanceLib.inf new file mode 100644 index 000000000000..b36a0d97332b --- /dev/null +++ b/MdePkg/Library/RiscVCMOCacheMaintenanceLib/RiscVCMOCacheMaintenanceLi= b.inf @@ -0,0 +1,30 @@ +## @file +# RISCV64 CMO Cache Maintenance Library implementation. +# +# Copyright (c) 2023, Rivos Inc. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D RiscVCMOCacheMaintenanceLib + MODULE_UNI_FILE =3D RiscVCMOCacheMaintenanceLib.uni + FILE_GUID =3D 6F651f1F-CAD5-4059-B1CE-7E60BC624757 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.1 + LIBRARY_CLASS =3D RiscVCMOCacheMaintenanceLib + +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + RiscVCMOCache.c + RiscVCpuCMOCache.S | GCC + +[Packages] + MdePkg/MdePkg.dec + +[LibraryClasses] + DebugLib diff --git a/MdePkg/Library/RiscVCMOCacheMaintenanceLib/RiscVCMOCache.c b/M= dePkg/Library/RiscVCMOCacheMaintenanceLib/RiscVCMOCache.c new file mode 100644 index 000000000000..37ce294dbabf --- /dev/null +++ b/MdePkg/Library/RiscVCMOCacheMaintenanceLib/RiscVCMOCache.c @@ -0,0 +1,377 @@ +/** @file + RISC-V specific functionality for cache. + + Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2023, Rivos Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +/** + Use runtime discovery mechanism in future when avalable + through https://lists.riscv.org/g/tech-privileged/topic/83853282 +**/ +#define RV64_CACHE_BLOCK_SIZE 64 + +typedef enum { + Clean, + Flush, + Invld, +} CACHE_OP; + +/* Ideally we should do this through BaseLib.h by adding + Asm*CacheLine functions. This can be done after Initial + RV refactoring is complete. For now call functions directly +*/ +VOID +EFIAPI +RiscVCpuCacheFlush ( + UINTN + ); + +VOID +EFIAPI +RiscVCpuCacheClean ( + UINTN + ); + +VOID +EFIAPI +RiscVCpuCacheInval ( + UINTN + ); + +/** + Performs required opeartion on cache lines in the cache coherency domain + of the calling CPU. If Address is not aligned on a cache line boundary, + then entire cache line containing Address is operated. If Address + Leng= th + is not aligned on a cache line boundary, then the entire cache line + containing Address + Length -1 is operated. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the cache lines to + invalidate. If the CPU is in a physical addressing mode, + then Address is a physical address. If the CPU is in a virtual + addressing mode, then Address is a virtual address. + + @param Length The number of bytes to invalidate from the instruction + cache. + + @param Op Type of CMO operation to be performed + + @return Address. + +**/ +VOID * +EFIAPI +CacheOpCacheRange ( + IN VOID *Address, + IN UINTN Length, + IN CACHE_OP Op + ) +{ + UINTN CacheLineSize; + UINTN Start; + UINTN End; + + if (Length =3D=3D 0) { + return Address; + } + + ASSERT ((Length - 1) <=3D (MAX_ADDRESS - (UINTN)Address)); + + // + // Cache line size is 8 * Bits 15-08 of EBX returned from CPUID 01H + // + CacheLineSize =3D RV64_CACHE_BLOCK_SIZE; + + Start =3D (UINTN)Address; + // + // Calculate the cache line alignment + // + End =3D (Start + Length + (CacheLineSize - 1)) & ~(CacheLineSize - 1); + Start &=3D ~((UINTN)CacheLineSize - 1); + + DEBUG ( + (DEBUG_INFO, + "%a Performing Cache Management Operation %d \n", __func__, Op) + ); + + do { + switch (Op) { + case Invld: + RiscVCpuCacheInval (Start); + break; + case Flush: + RiscVCpuCacheFlush (Start); + break; + case Clean: + RiscVCpuCacheClean (Start); + break; + default: + DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported operation\n")); + break; + } + + Start =3D Start + CacheLineSize; + } while (Start !=3D End); + + return Address; +} + +/** + RISC-V invalidate instruction cache. +**/ +VOID +EFIAPI +RiscVInvalidateInstCacheAsm ( + VOID + ); + +/** + RISC-V invalidate data cache. +**/ +VOID +EFIAPI +RiscVInvalidateDataCacheAsm ( + VOID + ); + +/** + Invalidates the entire instruction cache in cache coherency domain of the + calling CPU. This may not clear $IC on all RV implementations. + RV CMO only offers block operations as per spec. Entire cache invd will = be + platform dependent implementation. + +**/ +VOID +EFIAPI +InvalidateInstructionCache ( + VOID + ) +{ + RiscVInvalidateInstCacheAsm (); +} + +/** + Invalidates a range of instruction cache lines in the cache coherency do= main + of the calling CPU. + + Invalidates the instruction cache lines specified by Address and Length.= If + Address is not aligned on a cache line boundary, then entire instruction + cache line containing Address is invalidated. If Address + Length is not + aligned on a cache line boundary, then the entire instruction cache line + containing Address + Length -1 is invalidated. This function may choose = to + invalidate the entire instruction cache if that is more efficient than + invalidating the specified range. If Length is 0, then no instruction ca= che + lines are invalidated. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the instruction cache lines to + invalidate. If the CPU is in a physical addressing mode,= then + Address is a physical address. If the CPU is in a virtual + addressing mode, then Address is a virtual address. + + @param Length The number of bytes to invalidate from the instruction c= ache. + + @return Address. + +**/ +VOID * +EFIAPI +InvalidateInstructionCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + DEBUG ( + (DEBUG_ERROR, + "%a:RISC-V unsupported function.\n" + "Invalidating the whole instruction cache instead.\n", __func__) + ); + InvalidateInstructionCache (); + // RV does not support $I specific operation. + CacheOpCacheRange (Address, Length, Invld); + return Address; +} + +/** + Writes back and invalidates the entire data cache in cache coherency dom= ain + of the calling CPU. + + Writes back and invalidates the entire data cache in cache coherency dom= ain + of the calling CPU. This function guarantees that all dirty cache lines = are + written back to system memory, and also invalidates all the data cache l= ines + in the cache coherency domain of the calling CPU. + RV CMO only offers block operations as per spec. Entire cache invd will = be + platform dependent implementation. + +**/ +VOID +EFIAPI +WriteBackInvalidateDataCache ( + VOID + ) +{ + DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__)); +} + +/** + Writes back and invalidates a range of data cache lines in the cache + coherency domain of the calling CPU. + + Writes back and invalidates the data cache lines specified by Address and + Length. If Address is not aligned on a cache line boundary, then entire = data + cache line containing Address is written back and invalidated. If Addres= s + + Length is not aligned on a cache line boundary, then the entire data cac= he + line containing Address + Length -1 is written back and invalidated. This + function may choose to write back and invalidate the entire data cache if + that is more efficient than writing back and invalidating the specified + range. If Length is 0, then no data cache lines are written back and + invalidated. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to write back a= nd + invalidate. If the CPU is in a physical addressing mode,= then + Address is a physical address. If the CPU is in a virtual + addressing mode, then Address is a virtual address. + @param Length The number of bytes to write back and invalidate from the + data cache. + + @return Address of cache invalidation. + +**/ +VOID * +EFIAPI +WriteBackInvalidateDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + CacheOpCacheRange (Address, Length, Flush); + return Address; +} + +/** + Writes back the entire data cache in cache coherency domain of the calli= ng + CPU. + + Writes back the entire data cache in cache coherency domain of the calli= ng + CPU. This function guarantees that all dirty cache lines are written bac= k to + system memory. This function may also invalidate all the data cache line= s in + the cache coherency domain of the calling CPU. + RV CMO only offers block operations as per spec. Entire cache invd will = be + platform dependent implementation. + +**/ +VOID +EFIAPI +WriteBackDataCache ( + VOID + ) +{ + DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__)); +} + +/** + Writes back a range of data cache lines in the cache coherency domain of= the + calling CPU. + + Writes back the data cache lines specified by Address and Length. If Add= ress + is not aligned on a cache line boundary, then entire data cache line + containing Address is written back. If Address + Length is not aligned o= n a + cache line boundary, then the entire data cache line containing Address + + Length -1 is written back. This function may choose to write back the en= tire + data cache if that is more efficient than writing back the specified ran= ge. + If Length is 0, then no data cache lines are written back. This function= may + also invalidate all the data cache lines in the specified range of the c= ache + coherency domain of the calling CPU. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to write back. = If + the CPU is in a physical addressing mode, then Address i= s a + physical address. If the CPU is in a virtual addressing + mode, then Address is a virtual address. + @param Length The number of bytes to write back from the data cache. + + @return Address of cache written in main memory. + +**/ +VOID * +EFIAPI +WriteBackDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + CacheOpCacheRange (Address, Length, Clean); + return Address; +} + +/** + Invalidates the entire data cache in cache coherency domain of the calli= ng + CPU. + + Invalidates the entire data cache in cache coherency domain of the calli= ng + CPU. This function must be used with care because dirty cache lines are = not + written back to system memory. It is typically used for cache diagnostic= s. If + the CPU does not support invalidation of the entire data cache, then a w= rite + back and invalidate operation should be performed on the entire data cac= he. + RV CMO only offers block operations as per spec. Entire cache invd will = be + platform dependent implementation. + +**/ +VOID +EFIAPI +InvalidateDataCache ( + VOID + ) +{ + RiscVInvalidateDataCacheAsm (); +} + +/** + Invalidates a range of data cache lines in the cache coherency domain of= the + calling CPU. + + Invalidates the data cache lines specified by Address and Length. If Add= ress + is not aligned on a cache line boundary, then entire data cache line + containing Address is invalidated. If Address + Length is not aligned on= a + cache line boundary, then the entire data cache line containing Address + + Length -1 is invalidated. This function must never invalidate any cache = lines + outside the specified range. If Length is 0, then no data cache lines are + invalidated. Address is returned. This function must be used with care + because dirty cache lines are not written back to system memory. It is + typically used for cache diagnostics. If the CPU does not support + invalidation of a data cache range, then a write back and invalidate + operation should be performed on the data cache range. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to invalidate. = If + the CPU is in a physical addressing mode, then Address i= s a + physical address. If the CPU is in a virtual addressing = mode, + then Address is a virtual address. + @param Length The number of bytes to invalidate from the data cache. + + @return Address. + +**/ +VOID * +EFIAPI +InvalidateDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + // RV does not support $D specific operation. + CacheOpCacheRange (Address, Length, Invld); + return Address; +} diff --git a/MdePkg/Library/RiscVCMOCacheMaintenanceLib/RiscVCMOCacheMainte= nanceLib.uni b/MdePkg/Library/RiscVCMOCacheMaintenanceLib/RiscVCMOCacheMain= tenanceLib.uni new file mode 100644 index 000000000000..1d16d88e6c15 --- /dev/null +++ b/MdePkg/Library/RiscVCMOCacheMaintenanceLib/RiscVCMOCacheMaintenanceLi= b.uni @@ -0,0 +1,11 @@ +// /** @file +// RiscV Cache Maintenance Library implementation. +// +// Copyright (c) 2023, Rivos Inc. All rights reserved.
+// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_MODULE_ABSTRACT #language en-US "instance of RiscV= Cache Maintenance Library" + +#string STR_MODULE_DESCRIPTION #language en-US "instance of Riscv= Cache Maintenance Library." diff --git a/MdePkg/Library/RiscVCMOCacheMaintenanceLib/RiscVCpuCMOCache.S = b/MdePkg/Library/RiscVCMOCacheMaintenanceLib/RiscVCpuCMOCache.S new file mode 100644 index 000000000000..0cf054da7703 --- /dev/null +++ b/MdePkg/Library/RiscVCMOCacheMaintenanceLib/RiscVCpuCMOCache.S @@ -0,0 +1,23 @@ +// -----------------------------------------------------------------------= ------- +// +// CpuPause for RISC-V +// +// Copyright (c) 2022, Rivos Inc. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// -----------------------------------------------------------------------= ------- +ASM_GLOBAL ASM_PFX (RiscVCpuCacheFlush) +ASM_PFX (RiscVCpuCacheFlush) : + cbo.flush (a0) + ret + +ASM_GLOBAL ASM_PFX (RiscVCpuCacheClean) +ASM_PFX (RiscVCpuCacheClean) : + cbo.clean (a0) + ret + +ASM_GLOBAL ASM_PFX (RiscVCpuCacheInval) +ASM_PFX (RiscVCpuCacheInval) : + cbo.inval (a0) + ret --=20 2.40.0.rc0.57.g454dfcbddf -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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([2402:3a80:8ff:2244:e77a:2b3c:51a8:11da]) by smtp.gmail.com with ESMTPSA id s25-20020aa78d59000000b0059442ec49a2sm1107411pfe.146.2023.03.31.03.01.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Mar 2023 03:01:57 -0700 (PDT) From: "Dhaval Sharma" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Sunil V L , Andrei Warkentin Subject: [edk2-devel] [PATCH v2 2/2] OvmfPkg/RiscVVirt: Enable CMO support Date: Fri, 31 Mar 2023 15:31:46 +0530 Message-Id: <20230331100146.242814-3-dhaval@rivosinc.com> In-Reply-To: <20230331100146.242814-1-dhaval@rivosinc.com> References: <20230331100146.242814-1-dhaval@rivosinc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dhaval@rivosinc.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1680256919; bh=fPFHBv1FSm5vY/vtg+sJJwc73wh5MrFe1heR5xEjmbM=; h=Cc:Date:From:Reply-To:Subject:To; b=aarpCDSwTD2oPi6+JDp+IBcbwsdDXIMXA5wg50bngvwlk+9OM240+cjXjAlL93ISmWO ZlFt41pl64PbqlL5Zg+0VYO6QMnQD7cHUEhXRu7eDckd0DfkVN2jrv5wI/z6b3R+Wmg04 Bq7cZuzHxwZ2O+8yRgPiZY9qWI8V2ij3Y08= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1680256920251100009 Content-Type: text/plain; charset="utf-8" Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Sunil V L Cc: Andrei Warkentin Signed-off-by: Dhaval Sharma Add support for Cache Management Operations by conditionally adding CMO library. --- Notes: v2: - Updated RiscVCMOCacheManagementLib as a separate CMO library OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc b/OvmfPkg/RiscVVirt/RiscVV= irtQemu.dsc index 28d9af4d79b9..16c714625870 100644 --- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc +++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc @@ -46,6 +46,12 @@ [Defines] DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS =3D TRUE DEFINE NETWORK_ISCSI_ENABLE =3D FALSE =20 +# +# CMO support for RV. It depends on 2 factors. First support in compiler +# GCC:Binutils 2.39 (GCC12.2+) is required. +# + DEFINE RV_CMO_FEATURE_AVAILABLE =3D FALSE + !if $(NETWORK_SNP_ENABLE) =3D=3D TRUE !error "NETWORK_SNP_ENABLE is IA32/X64/EBC only" !endif @@ -112,6 +118,9 @@ [LibraryClasses.common] TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLi= bNull/PeiDxeTpmPlatformHierarchyLib.inf !endif =20 +!if $(RV_CMO_FEATURE_AVAILABLE) =3D=3D TRUE + CacheMaintenanceLib|MdePkg/Library/RiscVCMOCacheMaintenanceLib/RiscVCMO= CacheMaintenanceLib.inf +!endif [LibraryClasses.common.DXE_DRIVER] ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf PciExpressLib|OvmfPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExp= ressLib.inf --=20 2.40.0.rc0.57.g454dfcbddf -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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