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X-MS-Exchange-CrossTenant-AuthSource: PH0PR01MB7287.prod.exchangelabs.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Mar 2023 04:36:24.8878 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 6NGdb+6xV1QYdmqI7xd+fthvhkLO/Pj3Cu9I9+vxR9gAJ8Mg9jZCFQcYu/RX8EdsBjXwwTkySpj8i8LmwD+7IgOI3sS/Vu+4aqHydzWWSko= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR01MB4446 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nhi@os.amperecomputing.com X-Gm-Message-State: ktwWkYeIu2ncRAO6qfciQbSYx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1680064588; bh=eKT8ZnKgravPq9M3nB30yWyOs563N4+ZmDKZ74Zoino=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=Ks8AQrqpsnJPPm9OpJr1RErYM33xMssc+euYhglwZAHLCrlwz+VAFTnX/JbHf5MJqkb QgbJTdploD5MQbOcikioptIQV37ksPSGwU4dcfQBT2my06GogITM7b1SyOL5IdiuXE46g wepcLvNY3i1oru8hal7AZBjWkQWNIMFD8VQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1680064590690100002 Content-Type: text/plain; charset="utf-8" From: Vu Nguyen This updates the platform specific PCIe modules to add support for Ampere Altra Max processor which features 128 PCIe Gen4 lanes (distributed across eight x16 RCAs) using 32 controllers. Signed-off-by: Nhi Pham --- .../Library/BoardPcieLib/BoardPcieLib.c | 75 +++- .../Drivers/PcieInitPei/PcieInitPei.c | 131 ++++--- .../Drivers/PcieInitPei/RootComplexNVParam.c | 344 +++++++++++------- 3 files changed, 364 insertions(+), 186 deletions(-) diff --git a/Platform/Ampere/JadePkg/Library/BoardPcieLib/BoardPcieLib.c b/= Platform/Ampere/JadePkg/Library/BoardPcieLib/BoardPcieLib.c index 5041eb726288..bb69587db54f 100644 --- a/Platform/Ampere/JadePkg/Library/BoardPcieLib/BoardPcieLib.c +++ b/Platform/Ampere/JadePkg/Library/BoardPcieLib/BoardPcieLib.c @@ -38,6 +38,54 @@ BoardPcieReleaseAllPerst ( MicroSecondDelay (PCIE_PERST_DELAY); } =20 +EFI_STATUS +GetGpioGroup ( + IN UINT8 RootComplexId, + IN UINT8 PcieIndex, + OUT UINT32 *GpioGroupVal + ) +{ + /* Ampere Altra Max RootComplex->ID: 4:7 */ + if (PcieIndex < 2) { + switch (RootComplexId) { + case 4: + *GpioGroupVal =3D 34 - (PcieIndex * 2); + break; + case 5: + *GpioGroupVal =3D 38 - (PcieIndex * 2); + break; + case 6: + *GpioGroupVal =3D 30 - (PcieIndex * 2); + break; + case 7: + *GpioGroupVal =3D 26 - (PcieIndex * 2); + break; + default: + return EFI_INVALID_PARAMETER; + } + } else { + /* Ampere Altra Max RootComplex->ID: 4:7 */ + switch (RootComplexId) { + case 4: + *GpioGroupVal =3D 46 - ((PcieIndex - 2) * 2); + break; + case 5: + *GpioGroupVal =3D 42 - ((PcieIndex - 2) * 2); + break; + case 6: + *GpioGroupVal =3D 18 - ((PcieIndex - 2) * 2); + break; + case 7: + *GpioGroupVal =3D 22 - ((PcieIndex - 2) * 2); + break; + default: + return EFI_INVALID_PARAMETER; + } + } + + return EFI_SUCCESS; +} + /** Assert PERST of PCIe controller =20 @@ -56,15 +104,28 @@ BoardPcieAssertPerst ( IN BOOLEAN IsPullToHigh ) { - UINT32 GpioGroupVal, Val, GpioIndex, GpioPin; + UINT32 GpioGroupVal; + UINT32 Val; + UINT32 GpioIndex; + UINT32 GpioPin; + EFI_STATUS Status; =20 if (!IsPullToHigh) { if (RootComplex->Type =3D=3D RootComplexTypeA) { - // - // RootComplexTypeA: RootComplex->ID: 0->3 ; PcieIndex: 0->3 - // - GpioGroupVal =3D RCA_MAX_PERST_GROUPVAL - PcieIndex - - RootComplex->ID * MaxPcieControllerOfRootComplexA; + if (RootComplex->ID < MaxPcieControllerOfRootComplexA) { + /* Ampere Altra: 4 */ + // + // RootComplexTypeA: RootComplex->ID: 0->3 ; PcieIndex: 0->3 + // + GpioGroupVal =3D RCA_MAX_PERST_GROUPVAL - PcieIndex + - RootComplex->ID * MaxPcieControllerOfRootComplexA; + } else { + Status =3D GetGpioGroup (RootComplex->ID, PcieIndex, &GpioGroupVal= ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Invalid Root Complex ID %d\n", RootComplex= ->ID)); + return Status; + } + } } else { // // RootComplexTypeB: RootComplex->ID: 4->7 ; PcieIndex: 0->7 @@ -117,5 +178,5 @@ BoardPcieGetSegmentNumber ( return Ac01BoardSegment[RootComplex->Socket][RootComplex->ID]; } =20 - return DEFAULT_SEGMENT_NUMBER; + return (RootComplex->ID - 2); } diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.= c b/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.c index 76d3f90aa833..598a2e64d02f 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.c +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.c @@ -40,61 +40,33 @@ STATIC UINT64 mMmio32Size1P[AC01_PCIE= _MAX_ROOT_COMPLEX] =3D { STATIC UINT64 mMmioBase[AC01_PCIE_MAX_ROOT_COMPLEX] = =3D { AC01_PCIE_MMIO_BASE_LIST }; STATIC UINT64 mMmioSize[AC01_PCIE_MAX_ROOT_COMPLEX] = =3D { AC01_PCIE_MMIO_SIZE_LIST }; =20 +AC01_ROOT_COMPLEX_TYPE +GetRootComplexType ( + UINT8 RootComplexId + ) +{ + if (IsAc01Processor ()) { + return (RootComplexId < MaxRootComplexA) ? RootComplexTypeA : RootComp= lexTypeB; + } + + return RootComplexTypeA; +} + VOID -BuildRootComplexData ( - VOID +ConfigureRootComplex ( + BOOLEAN IsConfigFound, + ROOT_COMPLEX_CONFIG_VARSTORE_DATA RootComplexConfig ) { - AC01_ROOT_COMPLEX *RootComplex; - BOOLEAN ConfigFound; - EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi; - EFI_STATUS Status; - ROOT_COMPLEX_CONFIG_VARSTORE_DATA RootComplexConfig; - UINT8 RCIndex; - UINT8 PcieIndex; - UINTN DataSize; - - ConfigFound =3D FALSE; - - // - // Get the Root Complex config from NVRAM - // - Status =3D PeiServicesLocatePpi ( - &gEfiPeiReadOnlyVariable2PpiGuid, - 0, - NULL, - (VOID **)&VariablePpi - ); - if (!EFI_ERROR (Status)) { - DataSize =3D sizeof (RootComplexConfig); - Status =3D VariablePpi->GetVariable ( - VariablePpi, - ROOT_COMPLEX_CONFIG_VARSTORE_NAME, - &gRootComplexConfigFormSetGuid, - NULL, - &DataSize, - &RootComplexConfig - ); - if (!EFI_ERROR (Status)) { - ConfigFound =3D TRUE; - } - } - - ZeroMem (&mRootComplexList, sizeof (AC01_ROOT_COMPLEX) * AC01_PCIE_MAX_R= OOT_COMPLEX); - - // - // Adjust Root Complex MMIO32 base address in 1P or 2P configuration - // - if (!IsSlaveSocketAvailable ()) { - CopyMem ((VOID *)&mMmio32Base, (VOID *)&mMmio32Base1P, sizeof (mMmio32= Base1P)); - CopyMem ((VOID *)&mMmio32Size, (VOID *)&mMmio32Size1P, sizeof (mMmio32= Size1P)); - } + UINT8 RCIndex; + UINT8 PcieIndex; + AC01_ROOT_COMPLEX *RootComplex; =20 for (RCIndex =3D 0; RCIndex < AC01_PCIE_MAX_ROOT_COMPLEX; RCIndex++) { RootComplex =3D &mRootComplexList[RCIndex]; - RootComplex->Active =3D ConfigFound ? RootComplexConfig.RCStatus[RCInd= ex] : TRUE; - RootComplex->DevMapLow =3D ConfigFound ? RootComplexConfig.RCBifurcati= onLow[RCIndex] : 0; - RootComplex->DevMapHigh =3D ConfigFound ? RootComplexConfig.RCBifurcat= ionHigh[RCIndex] : 0; + RootComplex->Active =3D IsConfigFound ? RootComplexConfig.RCStatus[RCI= ndex] : TRUE; + RootComplex->DevMapLow =3D IsConfigFound ? RootComplexConfig.RCBifurca= tionLow[RCIndex] : 0; + RootComplex->DevMapHigh =3D IsConfigFound ? RootComplexConfig.RCBifurc= ationHigh[RCIndex] : 0; RootComplex->Socket =3D RCIndex / AC01_PCIE_MAX_RCS_PER_SOCKET; RootComplex->ID =3D RCIndex % AC01_PCIE_MAX_RCS_PER_SOCKET; RootComplex->CsrBase =3D mCsrBase[RCIndex]; @@ -106,7 +78,7 @@ BuildRootComplexData ( RootComplex->MmioSize =3D mMmioSize[RCIndex]; RootComplex->Mmio32Base =3D mMmio32Base[RCIndex]; RootComplex->Mmio32Size =3D mMmio32Size[RCIndex]; - RootComplex->Type =3D (RootComplex->ID < MaxRootComplexA) ? RootComple= xTypeA : RootComplexTypeB; + RootComplex->Type =3D GetRootComplexType (RootComplex->ID); RootComplex->MaxPcieController =3D (RootComplex->Type =3D=3D RootCompl= exTypeB) ? MaxPcieControllerOfRootComplexB : M= axPcieControllerOfRootComplexA; RootComplex->Logical =3D BoardPcieGetSegmentNumber (RootComplex); @@ -146,6 +118,60 @@ BuildRootComplexData ( } } =20 +VOID +BuildRootComplexData ( + VOID + ) +{ + BOOLEAN IsConfigFound; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi; + EFI_STATUS Status; + ROOT_COMPLEX_CONFIG_VARSTORE_DATA RootComplexConfig; + UINTN DataSize; + + IsConfigFound =3D FALSE; + ZeroMem ((VOID *)&RootComplexConfig, sizeof (ROOT_COMPLEX_CONFIG_VARSTOR= E_DATA)); + + // + // Get the Root Complex config from NVRAM + // + Status =3D PeiServicesLocatePpi ( + &gEfiPeiReadOnlyVariable2PpiGuid, + 0, + NULL, + (VOID **)&VariablePpi + ); + if (!EFI_ERROR (Status)) { + DataSize =3D sizeof (RootComplexConfig); + Status =3D VariablePpi->GetVariable ( + VariablePpi, + ROOT_COMPLEX_CONFIG_VARSTORE_NAME, + &gRootComplexConfigFormSetGuid, + NULL, + &DataSize, + &RootComplexConfig + ); + if (!EFI_ERROR (Status)) { + IsConfigFound =3D TRUE; + } + } + + ZeroMem (&mRootComplexList, sizeof (AC01_ROOT_COMPLEX) * AC01_PCIE_MAX_R= OOT_COMPLEX); + + // + // Adjust Root Complex MMIO32 base address in 1P or 2P configuration + // + if (!IsSlaveSocketAvailable ()) { + CopyMem ((VOID *)&mMmio32Base, (VOID *)&mMmio32Base1P, sizeof (mMmio32= Base1P)); + CopyMem ((VOID *)&mMmio32Size, (VOID *)&mMmio32Size1P, sizeof (mMmio32= Size1P)); + } + + // + // All necessary information is available, config Root complex according= ly + // + ConfigureRootComplex (IsConfigFound, RootComplexConfig); +} + EFI_STATUS EFIAPI PcieInitEntry ( @@ -168,11 +194,14 @@ PcieInitEntry ( continue; } =20 + DEBUG ((DEBUG_INIT, "Initializing S%d-RC%d...", RootComplex->Socket, R= ootComplex->ID)); Status =3D Ac01PcieCoreSetupRC (RootComplex, FALSE, 0); if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "RootComplex[%d]: Init Failed\n", Index)); + DEBUG ((DEBUG_ERROR, "Failed\n")); RootComplex->Active =3D FALSE; continue; + } else { + DEBUG ((DEBUG_INIT, "Done + DevMapLow/High: %d/%d\n", RootComplex->D= evMapLow, RootComplex->DevMapHigh)); } } =20 diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexN= VParam.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVP= aram.c index aa34a90b44c6..da730c4bd219 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.c +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.c @@ -37,7 +37,7 @@ | Y | Y | Y | Y | 3 | ---------------------------------------- =20 - Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.
+ Copyright (c) 2020 - 2023, Ampere Computing LLC. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -55,6 +55,12 @@ =20 #include "RootComplexNVParam.h" =20 +typedef enum { + Gen3Preset =3D 0, + Gen4Preset, + GenPresetMax +} NVPARAM_PCIE_PRESET_TYPE; + STATIC BOOLEAN IsEmptyRC ( @@ -144,85 +150,233 @@ SetRootComplexBifurcation ( } } =20 -VOID +DEV_MAP_MODE GetDefaultDevMap ( - AC01_ROOT_COMPLEX *RootComplex + IN AC01_ROOT_COMPLEX *RootComplex, + IN BOOLEAN IsGetDevMapLow ) { - if (RootComplex->Pcie[PcieController0].Active - && RootComplex->Pcie[PcieController1].Active - && RootComplex->Pcie[PcieController2].Active - && RootComplex->Pcie[PcieController3].Active) { - RootComplex->DefaultDevMapLow =3D DevMapMode4; - } else if (RootComplex->Pcie[PcieController0].Active - && RootComplex->Pcie[PcieController2].Active - && RootComplex->Pcie[PcieController3].Active) { - RootComplex->DefaultDevMapLow =3D DevMapMode3; - } else if (RootComplex->Pcie[PcieController0].Active - && RootComplex->Pcie[PcieController2].Active) { - RootComplex->DefaultDevMapLow =3D DevMapMode2; - } else { - RootComplex->DefaultDevMapLow =3D DevMapMode1; - } + UINT8 StartIndex; + DEV_MAP_MODE DevMapMode; + + DevMapMode =3D MaxDevMapMode; + StartIndex =3D IsGetDevMapLow ? PcieController0 : PcieController4; + + while (DevMapMode >=3D DevMapMode1) + { + switch (DevMapMode) { + case DevMapMode4: + if (RootComplex->Pcie[StartIndex].Active + && RootComplex->Pcie[StartIndex + 1].Active + && RootComplex->Pcie[StartIndex + 2].Active + && RootComplex->Pcie[StartIndex + 3].Active) { + return DevMapMode4; + } + break; + case DevMapMode3: + if (RootComplex->Pcie[StartIndex].Active + && RootComplex->Pcie[StartIndex + 2].Active + && RootComplex->Pcie[StartIndex + 3].Active) { + return DevMapMode3; + } + break; + case DevMapMode2: + if (RootComplex->Pcie[StartIndex].Active + && RootComplex->Pcie[StartIndex + 2].Active) { + return DevMapMode2; + } + break; + default: + return DevMapMode1; + } =20 - if (RootComplex->Pcie[PcieController4].Active - && RootComplex->Pcie[PcieController5].Active - && RootComplex->Pcie[PcieController6].Active - && RootComplex->Pcie[PcieController7].Active) { - RootComplex->DefaultDevMapHigh =3D DevMapMode4; - } else if (RootComplex->Pcie[PcieController4].Active - && RootComplex->Pcie[PcieController6].Active - && RootComplex->Pcie[PcieController7].Active) { - RootComplex->DefaultDevMapHigh =3D DevMapMode3; - } else if (RootComplex->Pcie[PcieController4].Active - && RootComplex->Pcie[PcieController6].Active) { - RootComplex->DefaultDevMapHigh =3D DevMapMode2; - } else { - RootComplex->DefaultDevMapHigh =3D DevMapMode1; + DevMapMode--; } =20 + return DevMapMode1; +} + +VOID +GetDevMap ( + IN OUT AC01_ROOT_COMPLEX *RootComplex + ) +{ + // + // Get default Devmap low and configure Devmap low accordingly. + // + RootComplex->DefaultDevMapLow =3D GetDefaultDevMap (RootComplex, TRUE); if (RootComplex->DevMapLow =3D=3D 0) { RootComplex->DevMapLow =3D RootComplex->DefaultDevMapLow; } =20 + // + // Get default Devmap high and configure Devmap high accordingly. + // + RootComplex->DefaultDevMapHigh =3D IsAc01Processor () ? GetDefaultDevMap= (RootComplex, FALSE) : DevMapMode1; if (RootComplex->Type =3D=3D RootComplexTypeB && RootComplex->DevMapHigh= =3D=3D 0) { RootComplex->DevMapHigh =3D RootComplex->DefaultDevMapHigh; } =20 + // + // Set bifurcation bases on Devmap high and Devmap low. + // SetRootComplexBifurcation (RootComplex, PcieController0, RootComplex->De= vMapLow); if (RootComplex->Type =3D=3D RootComplexTypeB) { SetRootComplexBifurcation (RootComplex, PcieController4, RootComplex->= DevMapHigh); } } =20 +UINT8 +GetMaxController ( + IN AC01_ROOT_COMPLEX *RootComplex + ) +{ + if (IsAc01Processor ()) { + return MaxPcieControllerOfRootComplexA; + } + + return RootComplex->MaxPcieController; +} + +NVPARAM +CalculateNvParamOffset ( + IN AC01_ROOT_COMPLEX *RootComplex, + IN UINT8 PaddingOrder, + IN UINT8 StartIndex, + IN UINT64 StartOffset + ) +{ + UINT8 NeededPadding; + INT8 PositionFromStartIndex; + NVPARAM NvParamOffset; + + + NeededPadding =3D RootComplex->ID - PaddingOrder; + PositionFromStartIndex =3D (RootComplex->ID - StartIndex) + NeededPaddin= g; + NvParamOffset =3D StartOffset + PositionFromStartIndex * NV_PARAM_ENTRYS= IZE; + + return NvParamOffset; +} + +EFI_STATUS_CODE_TYPE +GetNvParamOffsetLane ( + IN AC01_ROOT_COMPLEX *RootComplex, + OUT NVPARAM *NvParamOffset + ) +{ + BOOLEAN IsAc01; + BOOLEAN IsRootComplexTypeA; + BOOLEAN IsSocket0; + UINT8 StartIndex; + UINT64 StartOffset; + UINT8 PaddingOrder; + + IsSocket0 =3D RootComplex->Socket =3D=3D 0 ? TRUE : FALSE; + IsAc01 =3D IsAc01Processor (); + IsRootComplexTypeA =3D RootComplex->Type =3D=3D RootComplexTypeA ? TRUE = : FALSE; + + if (!IsAc01 && (RootComplex->ID >=3D MaxPcieControllerOfRootComplexA)) { + // Because from NV_SI_RO_BOARD_S0_RCA4_CFG to NV_SI_RO_BOARD_S0_RCA7_C= FG for supporting + // Altra Max are not sequential arrangement with NV_SI_RO_BOARD_S0_RCA= 0_CFG + // so the start index will be the first Root Complex ID which using th= ese NVParams + // (NV_SI_RO_BOARD_S0_RCA4_CFG to NV_SI_RO_BOARD_S0_RCA7_CFG) to suppo= rt Altra Max processor. + StartIndex =3D 4; + StartOffset =3D IsSocket0 ? NV_SI_RO_BOARD_S0_RCA4_CFG : NV_SI_RO_BOAR= D_S1_RCA4_CFG; + PaddingOrder =3D RootComplex->ID; + } else { + StartIndex =3D 0; + StartOffset =3D IsSocket0 ? NV_SI_RO_BOARD_S0_RCA0_CFG : NV_SI_RO_BOAR= D_S1_RCA0_CFG; + PaddingOrder =3D IsRootComplexTypeA ? RootComplex->ID : MaxRootComplex= A; + } + + *NvParamOffset =3D CalculateNvParamOffset (RootComplex, PaddingOrder, St= artIndex, StartOffset); + return EFI_SUCCESS; +} + +EFI_STATUS +GetNvParamOffsetPreset ( + IN AC01_ROOT_COMPLEX *RootComplex, + IN NVPARAM_PCIE_PRESET_TYPE PresetType, + OUT NVPARAM *NvParamOffset + ) +{ + BOOLEAN IsAc01; + BOOLEAN IsRootComplexTypeA; + BOOLEAN IsSocket0; + UINT8 StartIndex; + UINT64 StartOffset; + UINT8 PaddingOrder; + + IsSocket0 =3D RootComplex->Socket =3D=3D 0 ? TRUE : FALSE; + IsAc01 =3D IsAc01Processor (); + IsRootComplexTypeA =3D RootComplex->Type =3D=3D RootComplexTypeA ? TRUE = : FALSE; + + switch (PresetType) { + case Gen3Preset: + if (IsAc01) { + StartOffset =3D IsSocket0 ? NV_SI_RO_BOARD_S0_RCA0_TXRX_G3PRESET : + NV_SI_RO_BOARD_S1_RCA2_TXRX_G3PRESET; + } else { + StartOffset =3D IsSocket0 ? NV_SI_RO_BOARD_MQ_S0_RCA0_TXRX_G3PRESET : + NV_SI_RO_BOARD_MQ_S1_RCA2_TXRX_G3PRESET; + } + break; + + case Gen4Preset: + if (IsAc01) { + StartOffset =3D IsSocket0 ? NV_SI_RO_BOARD_S0_RCA0_TXRX_G4PRESET : + NV_SI_RO_BOARD_S1_RCA2_TXRX_G4PRESET; + } else { + StartOffset =3D IsSocket0 ? NV_SI_RO_BOARD_MQ_S0_RCA0_TXRX_G4PRESET : + NV_SI_RO_BOARD_MQ_S1_RCA2_TXRX_G4PRESET; + } + break; + + default: + return EFI_INVALID_PARAMETER; + } + + // + // For Socket 0, NVParams for all Root Complexes are supported so starti= ng from RCA0. + // For Socket 1, NVParams for RCA0 and RCA1 are not supported so startin= g from RCA2. + // + StartIndex =3D IsSocket0 ? 0 : 2; + // + // There're two NVParam entries per RootComplexTypeB + // so padding need to be start from MaxRootComplexA to + // get the first NVParam entry of RootComplexTypeB + // + PaddingOrder =3D IsRootComplexTypeA ? RootComplex->ID : MaxRootComplexA; + + *NvParamOffset =3D CalculateNvParamOffset (RootComplex, PaddingOrder, St= artIndex, StartOffset); + + return EFI_SUCCESS; +} + VOID GetLaneAllocation ( - AC01_ROOT_COMPLEX *RootComplex + IN OUT AC01_ROOT_COMPLEX *RootComplex ) { EFI_STATUS Status; INTN RPIndex; NVPARAM NvParamOffset; - UINT32 Value, Width; + UINT32 Value; + UINT32 Width; + UINT32 MaxController; =20 - // Retrieve lane allocation and capabilities for each controller - if (RootComplex->Type =3D=3D RootComplexTypeA) { - NvParamOffset =3D (RootComplex->Socket =3D=3D 0) ? NV_SI_RO_BOARD_S0_R= CA0_CFG : NV_SI_RO_BOARD_S1_RCA0_CFG; - NvParamOffset +=3D RootComplex->ID * NV_PARAM_ENTRYSIZE; + Status =3D GetNvParamOffsetLane (RootComplex, &NvParamOffset); + if (!EFI_ERROR (Status)) { + Status =3D NVParamGet (NvParamOffset, NV_PERM_ALL, &Value); + if (EFI_ERROR (Status)) { + Value =3D 0; + } } else { - // - // There're two NVParam entries per RootComplexTypeB - // - NvParamOffset =3D (RootComplex->Socket =3D=3D 0) ? NV_SI_RO_BOARD_S0_R= CB0_LO_CFG : NV_SI_RO_BOARD_S1_RCB0_LO_CFG; - NvParamOffset +=3D (RootComplex->ID - MaxRootComplexA) * (NV_PARAM_ENT= RYSIZE * 2); - } - - Status =3D NVParamGet (NvParamOffset, NV_PERM_ALL, &Value); - if (EFI_ERROR (Status)) { Value =3D 0; } =20 - for (RPIndex =3D 0; RPIndex < MaxPcieControllerOfRootComplexA; RPIndex++= ) { + MaxController =3D GetMaxController (RootComplex); + for (RPIndex =3D PcieController0; RPIndex < MaxController; RPIndex++) { Width =3D (Value >> (RPIndex * BITS_PER_BYTE)) & BYTE_MASK; switch (Width) { case 1: @@ -278,78 +432,6 @@ GetLaneAllocation ( } } =20 -NVPARAM -GetGen3PresetNvParamOffset ( - AC01_ROOT_COMPLEX *RootComplex - ) -{ - NVPARAM NvParamOffset; - - if (RootComplex->Socket =3D=3D 0) { - if (RootComplex->Type =3D=3D RootComplexTypeA) { - if (RootComplex->ID < MaxRootComplexA) { - NvParamOffset =3D NV_SI_RO_BOARD_S0_RCA0_TXRX_G3PRESET + RootCompl= ex->ID * NV_PARAM_ENTRYSIZE; - } else { - NvParamOffset =3D NV_SI_RO_BOARD_S0_RCA4_TXRX_G3PRESET + (RootComp= lex->ID - MaxRootComplexA) * NV_PARAM_ENTRYSIZE; - } - } else { - // - // There're two NVParam entries per RootComplexTypeB - // - NvParamOffset =3D NV_SI_RO_BOARD_S0_RCB0A_TXRX_G3PRESET + (RootCompl= ex->ID - MaxRootComplexA) * (NV_PARAM_ENTRYSIZE * 2); - } - } else if (RootComplex->Type =3D=3D RootComplexTypeA) { - if (RootComplex->ID < MaxRootComplexA) { - NvParamOffset =3D NV_SI_RO_BOARD_S1_RCA2_TXRX_G3PRESET + (RootComple= x->ID - 2) * NV_PARAM_ENTRYSIZE; - } else { - NvParamOffset =3D NV_SI_RO_BOARD_S1_RCA4_TXRX_G3PRESET + (RootComple= x->ID - MaxRootComplexA) * NV_PARAM_ENTRYSIZE; - } - } else { - // - // There're two NVParam entries per RootComplexTypeB - // - NvParamOffset =3D NV_SI_RO_BOARD_S1_RCB0A_TXRX_G3PRESET + (RootComplex= ->ID - MaxRootComplexA) * (NV_PARAM_ENTRYSIZE * 2); - } - - return NvParamOffset; -} - -NVPARAM -GetGen4PresetNvParamOffset ( - AC01_ROOT_COMPLEX *RootComplex - ) -{ - NVPARAM NvParamOffset; - - if (RootComplex->Socket =3D=3D 0) { - if (RootComplex->Type =3D=3D RootComplexTypeA) { - if (RootComplex->ID < MaxRootComplexA) { - NvParamOffset =3D NV_SI_RO_BOARD_S0_RCA0_TXRX_G4PRESET + RootCompl= ex->ID * NV_PARAM_ENTRYSIZE; - } else { - NvParamOffset =3D NV_SI_RO_BOARD_S0_RCA4_TXRX_G4PRESET + (RootComp= lex->ID - MaxRootComplexA) * NV_PARAM_ENTRYSIZE; - } - } else { - // - // There're two NVParam entries per RootComplexTypeB - // - NvParamOffset =3D NV_SI_RO_BOARD_S0_RCB0A_TXRX_G4PRESET + (RootCompl= ex->ID - MaxRootComplexA) * (NV_PARAM_ENTRYSIZE * 2); - } - } else if (RootComplex->Type =3D=3D RootComplexTypeA) { - if (RootComplex->ID < MaxRootComplexA) { - NvParamOffset =3D NV_SI_RO_BOARD_S1_RCA2_TXRX_G4PRESET + (RootComple= x->ID - 2) * NV_PARAM_ENTRYSIZE; - } else { - NvParamOffset =3D NV_SI_RO_BOARD_S1_RCA4_TXRX_G4PRESET + (RootComple= x->ID - MaxRootComplexA) * NV_PARAM_ENTRYSIZE; - } - } else { - // - // There're two NVParam entries per RootComplexTypeB - // - NvParamOffset =3D NV_SI_RO_BOARD_S1_RCB0A_TXRX_G4PRESET + (RootComplex= ->ID - MaxRootComplexA) * (NV_PARAM_ENTRYSIZE * 2); - } - - return NvParamOffset; -} - VOID GetPresetSetting ( AC01_ROOT_COMPLEX *RootComplex @@ -366,9 +448,11 @@ GetPresetSetting ( RootComplex->PresetGen4[Index] =3D PRESET_INVALID; } =20 - NvParamOffset =3D GetGen3PresetNvParamOffset (RootComplex); - - Status =3D NVParamGet (NvParamOffset, NV_PERM_ALL, &Value); + // Get NVParam offset of Gen3 preset + Status =3D GetNvParamOffsetPreset (RootComplex, Gen3Preset, &NvParamOffs= et); + if (!EFI_ERROR (Status)) { + Status =3D NVParamGet (NvParamOffset, NV_PERM_ALL, &Value); + } if (!EFI_ERROR (Status)) { for (Index =3D 0; Index < MaxPcieControllerOfRootComplexA; Index++) { RootComplex->PresetGen3[Index] =3D (Value >> (Index * BITS_PER_BYTE)= ) & BYTE_MASK; @@ -385,9 +469,11 @@ GetPresetSetting ( } } =20 - NvParamOffset =3D GetGen4PresetNvParamOffset (RootComplex); - - Status =3D NVParamGet (NvParamOffset, NV_PERM_ALL, &Value); + // Get NVParam offset of Gen4 preset. + Status =3D GetNvParamOffsetPreset (RootComplex, Gen4Preset, &NvParamOffs= et); + if (!EFI_ERROR (Status)) { + Status =3D NVParamGet (NvParamOffset, NV_PERM_ALL, &Value); + } if (!EFI_ERROR (Status)) { for (Index =3D 0; Index < MaxPcieControllerOfRootComplexA; Index++) { RootComplex->PresetGen4[Index] =3D (Value >> (Index * BITS_PER_BYTE)= ) & BYTE_MASK; @@ -415,6 +501,7 @@ GetMaxSpeedGen ( UINT8 ErrataSpeedDevMap4[MaxPcieControllerOfRootComplexA] =3D { LINK_SPE= ED_GEN1, LINK_SPEED_GEN1, LINK_SPEED_GEN1, LINK_SPEED_GEN1 }; // Bifurcati= on 3: x4 x4 x4 x4 (PCIE_ERRATA_SPEED1) UINT8 ErrataSpeedRcb[MaxPcieControllerOfRootComplexA] =3D { LINK_SPEED_G= EN1, LINK_SPEED_GEN1, LINK_SPEED_GEN1, LINK_SPEED_GEN1 }; // RootCompl= exTypeB PCIE_ERRATA_SPEED1 UINT8 Idx; + UINT8 MaxController; UINT8 *MaxGen; =20 ASSERT (MaxPcieControllerOfRootComplexA =3D=3D 4); @@ -452,7 +539,8 @@ GetMaxSpeedGen ( } } =20 - for (Idx =3D 0; Idx < MaxPcieControllerOfRootComplexA; Idx++) { + MaxController =3D GetMaxController (RootComplex); + for (Idx =3D 0; Idx < MaxController; Idx++) { RootComplex->Pcie[Idx].MaxGen =3D RootComplex->Pcie[Idx].Active ? MaxG= en[Idx] : LINK_SPEED_NONE; } =20 @@ -509,6 +597,6 @@ ParseRootComplexNVParamData ( =20 GetPresetSetting (RootComplex); GetLaneAllocation (RootComplex); - GetDefaultDevMap (RootComplex); + GetDevMap (RootComplex); GetMaxSpeedGen (RootComplex); } --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#102094): https://edk2.groups.io/g/devel/message/102094 Mute This Topic: https://groups.io/mt/97922254/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-