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id 15.20.6254.015; Wed, 29 Mar 2023 04:36:18 +0000 From: "Nhi Pham via groups.io" To: devel@edk2.groups.io CC: patches@amperecomputing.com, quic_llindhol@quicinc.com, ardb+tianocore@kernel.org, Vu Nguyen , Nhi Pham Subject: [edk2-devel] [edk2-platforms][PATCH v2 4/9] AmpereAltraPkg: Update Ampere specific platform PCIe core Date: Wed, 29 Mar 2023 11:32:41 +0700 Message-ID: <20230329043246.495600-5-nhi@os.amperecomputing.com> In-Reply-To: <20230329043246.495600-1-nhi@os.amperecomputing.com> References: <20230329043246.495600-1-nhi@os.amperecomputing.com> X-ClientProxiedBy: TY2PR0101CA0042.apcprd01.prod.exchangelabs.com (2603:1096:404:8000::28) To PH0PR01MB7287.prod.exchangelabs.com (2603:10b6:510:10a::21) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH0PR01MB7287:EE_|SN6PR01MB4446:EE_ X-MS-Office365-Filtering-Correlation-Id: 796e8727-690c-4b2d-a515-08db300f2383 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 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s=20140610; t=1680064583; bh=oYVoCsWAUMtwkkqMMFabafmo/CVMoRkml25vigiKY8c=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=Mr7T7vLmUNKpLR39yYwtMpoFR9CmFNqCoqmlSzqUQACFYJ0QJz2s4OPMCQOcGnp+6Jb gl9kpbrAh6Ujwv5MZFWsiK1H/8IIivRi7wqJM3yjUzXMuxc/QnRmkJPhIYur3q7uzVW3n GSYZWnWr0M0aXR13pj+Wc0EjRYhh5sPNuX4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1680064584670100011 Content-Type: text/plain; charset="utf-8" From: Vu Nguyen This patch updates the following: - Check End Point configuration space is accessible or not before getting its capability. - Add new function to check PCIe card is present or not. - Set CRS (Configuration Request Retry Status) to follow PCIe specifications. Signed-off-by: Nhi Pham --- .../Library/Ac01PcieLib/PcieCore.h | 8 +- .../Library/Ac01PcieLib/PcieCore.c | 150 ++++++++++++++---- 2 files changed, 128 insertions(+), 30 deletions(-) diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.h b= /Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.h index 1db8a68b3df4..a18fff7dbb75 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.h +++ b/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.h @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.
+ Copyright (c) 2020 - 2023, Ampere Computing LLC. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -39,6 +39,7 @@ #define PIPE_CLOCK_TIMEOUT 20000 // 20,000 us #define LTSSM_TRANSITION_TIMEOUT 100000 // 100 ms in total #define EP_LINKUP_TIMEOUT (10 * 1000) // 10ms +#define EP_LINKUP_EXTRA_TIMEOUT (500 * 1000) // 500ms #define LINK_WAIT_INTERVAL_US 50 =20 #define PFA_MODE_ENABLE 0 @@ -80,6 +81,7 @@ #define AC01_PCIE_CORE_IRQ_ENABLE_REG 0x30 #define AC01_PCIE_CORE_IRQ_EVENT_STAT_REG 0x38 #define AC01_PCIE_CORE_BLOCK_EVENT_STAT_REG 0x3C +#define AC01_PCIE_CORE_BUS_CONTROL_REG 0x40 #define AC01_PCIE_CORE_RESET_REG 0xC000 #define AC01_PCIE_CORE_CLOCK_REG 0xC004 #define AC01_PCIE_CORE_MEM_READY_REG 0xC104 @@ -87,6 +89,7 @@ =20 // AC01_PCIE_CORE_LINK_CTRL_REG #define LTSSMENB_SET(dst, src) (((dst) & ~0x1) | (((UINT32) (= src)) & 0x1)) +#define LTSSMENB_GET(dst) ((dst) & (BIT0)) #define HOLD_LINK_TRAINING 0 #define START_LINK_TRAINING 1 #define DEVICETYPE_SET(dst, src) (((dst) & ~0xF0) | (((UINT32) = (src) << 4) & 0xF0)) @@ -120,6 +123,9 @@ // AC01_PCIE_CORE_BLOCK_EVENT_STAT_REG #define LINKUP_MASK 0x1 =20 +// AC01_PCIE_CORE_BUS_CONTROL_REG +#define BUS_CTL_CFG_UR_MASK 0x8 + // AC01_PCIE_CORE_RESET_REG #define DWC_PCIE_SET(dst, src) (((dst) & ~0x1) | (((UINT32) (src)) & 0x1= )) #define RESET_MASK 0x1 diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c b= /Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c index ad648b1b9efd..855b094f7948 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c +++ b/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.
+ Copyright (c) 2020 - 2023, Ampere Computing LLC. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -10,8 +10,10 @@ =20 #include #include +#include #include #include +#include #include #include #include @@ -22,6 +24,25 @@ =20 #include "PcieCore.h" =20 +VOID +EnableDbiAccess ( + AC01_ROOT_COMPLEX *RootComplex, + UINT32 PcieIndex, + BOOLEAN EnableDbi + ); + +BOOLEAN +EndpointCfgReady ( + IN AC01_ROOT_COMPLEX *RootComplex, + IN UINT8 PcieIndex, + IN UINT32 Timeout + ); + +BOOLEAN +PcieLinkUpCheck ( + IN AC01_PCIE_CONTROLLER *Pcie + ); + /** Return the next extended capability base address =20 @@ -41,14 +62,38 @@ GetCapabilityBase ( { BOOLEAN IsExtCapability =3D FALSE; PHYSICAL_ADDRESS CfgBase; + PHYSICAL_ADDRESS Ret =3D 0; + PHYSICAL_ADDRESS RootComplexCfgBase; UINT32 CapabilityId; UINT32 NextCapabilityPtr; UINT32 Val; + UINT32 RestoreVal; =20 - if (IsRootComplex) { - CfgBase =3D RootComplex->MmcfgBase + (RootComplex->Pcie[PcieIndex].Dev= Num << DEV_SHIFT); - } else { + RootComplexCfgBase =3D RootComplex->MmcfgBase + (RootComplex->Pcie[PcieI= ndex].DevNum << DEV_SHIFT); + if (!IsRootComplex) { + // Allow programming to config space + EnableDbiAccess (RootComplex, PcieIndex, TRUE); + + Val =3D MmioRead32 (RootComplexCfgBase + SEC_LAT_TIMER_SUB_BUS_= SEC_BUS_PRI_BUS_REG); + RestoreVal =3D Val; + Val =3D SUB_BUS_SET (Val, DEFAULT_SUB_BUS); + Val =3D SEC_BUS_SET (Val, RootComplex->Pcie[PcieIndex].DevNum); + Val =3D PRIM_BUS_SET (Val, 0x0); + MmioWrite32 (RootComplexCfgBase + SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BU= S_REG, Val); CfgBase =3D RootComplex->MmcfgBase + (RootComplex->Pcie[PcieIndex].Dev= Num << BUS_SHIFT); + + if (!EndpointCfgReady (RootComplex, PcieIndex, EP_LINKUP_TIMEOUT)) { + goto _CheckCapEnd; + } + } else { + CfgBase =3D RootComplexCfgBase; + } + + // Check if device provide capability + Val =3D MmioRead32 (CfgBase + PCI_COMMAND_OFFSET); + Val =3D GET_HIGH_16_BITS (Val); /* Status */ + if (!(Val & EFI_PCI_STATUS_CAPABILITY)) { + goto _CheckCapEnd; } =20 Val =3D MmioRead32 (CfgBase + TYPE1_CAP_PTR_REG); @@ -58,7 +103,8 @@ GetCapabilityBase ( while (1) { if ((NextCapabilityPtr & WORD_ALIGN_MASK) !=3D 0) { // Not alignment, just return - return 0; + Ret =3D 0; + goto _CheckCapEnd; } =20 Val =3D MmioRead32 (CfgBase + NextCapabilityPtr); @@ -69,7 +115,8 @@ GetCapabilityBase ( } =20 if (CapabilityId =3D=3D ExtCapabilityId) { - return (CfgBase + NextCapabilityPtr); + Ret =3D (CfgBase + NextCapabilityPtr); + goto _CheckCapEnd; } =20 if (NextCapabilityPtr < EXT_CAPABILITY_START_BASE) { @@ -84,9 +131,20 @@ GetCapabilityBase ( } =20 if ((NextCapabilityPtr =3D=3D 0) && IsExtCapability) { - return 0; + Ret =3D 0; + goto _CheckCapEnd; } } + +_CheckCapEnd: + if (!IsRootComplex) { + MmioWrite32 (RootComplexCfgBase + SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BU= S_REG, RestoreVal); + + // Disable programming to config space + EnableDbiAccess (RootComplex, PcieIndex, FALSE); + } + + return Ret; } =20 /** @@ -677,6 +735,14 @@ Ac01PcieCoreSetupRC ( // Hold link training StartLinkTraining (RootComplex, PcieIndex, FALSE); =20 + // Clear BUSCTRL.CfgUrMask to set CRS (Configuration Request Retry Sta= tus) to 0xFFFF.FFFF + // rather than 0xFFFF.0001 as per PCIe specification requirement. Othe= rwise, this causes + // device drivers respond incorrectly on timeout due to long device op= erations. + TargetAddress =3D CsrBase + AC01_PCIE_CORE_BUS_CONTROL_REG; + Val =3D MmioRead32 (TargetAddress); + Val &=3D ~BUS_CTL_CFG_UR_MASK; + MmioWrite32 (TargetAddress, Val); + if (!EnableAxiPipeClock (RootComplex, PcieIndex)) { DEBUG ((DEBUG_ERROR, "- Pcie[%d] - PIPE clock is not stable\n", Pcie= Index)); return RETURN_DEVICE_ERROR; @@ -1067,21 +1133,20 @@ Ac01PFACommand ( return Ret; } =20 -UINT32 +BOOLEAN EndpointCfgReady ( - IN AC01_ROOT_COMPLEX *RootComplex, - IN UINT8 PcieIndex + IN AC01_ROOT_COMPLEX *RootComplex, + IN UINT8 PcieIndex, + IN UINT32 TimeOut ) { PHYSICAL_ADDRESS CfgBase; - UINT32 TimeOut; UINT32 Val; =20 CfgBase =3D RootComplex->MmcfgBase + (RootComplex->Pcie[PcieIndex].DevNu= m << BUS_SHIFT); =20 // Loop read CfgBase value until got valid value or - // reach to timeout EP_LINKUP_TIMEOUT (or more depend on card) - TimeOut =3D EP_LINKUP_TIMEOUT; + // reach to Timeout (or more depend on card) do { Val =3D MmioRead32 (CfgBase); if (Val !=3D 0xFFFF0001 && Val !=3D 0xFFFFFFFF) { @@ -1112,6 +1177,7 @@ Ac01PcieCoreGetEndpointInfo ( ) { PHYSICAL_ADDRESS CfgBase; + PHYSICAL_ADDRESS EpCfgAddr; PHYSICAL_ADDRESS PcieCapBase; PHYSICAL_ADDRESS SecLatTimerAddr; PHYSICAL_ADDRESS TargetAddress; @@ -1133,8 +1199,23 @@ Ac01PcieCoreGetEndpointInfo ( Val =3D SEC_BUS_SET (Val, RootComplex->Pcie[PcieIndex].DevNum); Val =3D PRIM_BUS_SET (Val, DEFAULT_PRIM_BUS); MmioWrite32 (SecLatTimerAddr, Val); + EpCfgAddr =3D RootComplex->MmcfgBase + (RootComplex->Pcie[PcieIndex].Dev= Num << BUS_SHIFT); =20 - if (EndpointCfgReady (RootComplex, PcieIndex)) { + if (!EndpointCfgReady (RootComplex, PcieIndex, EP_LINKUP_EXTRA_TIMEOUT))= { + goto Exit; + } + + Val =3D MmioRead32 (EpCfgAddr); + // Check whether EP config space is accessible or not + if (Val =3D=3D 0xFFFFFFFF) { + *EpMaxWidth =3D 0; // Invalid Width + *EpMaxGen =3D 0; // Invalid Speed + DEBUG ((DEBUG_ERROR, "PCIE%d.%d Cannot access EP config space!\n", Roo= tComplex->ID, PcieIndex)); + } else if (Val =3D=3D 0xFFFF0001) { + *EpMaxWidth =3D 0; // Invalid Width + *EpMaxGen =3D 0; // Invalid Speed + DEBUG ((DEBUG_ERROR, "PCIE%d.%d EP config space still not ready to acc= ess, need poll more time!!!\n", RootComplex->ID, PcieIndex)); + } else { PcieCapBase =3D GetCapabilityBase (RootComplex, PcieIndex, FALSE, PCIE= _CAPABILITY_ID); if (PcieCapBase =3D=3D 0) { DEBUG (( @@ -1164,6 +1245,7 @@ Ac01PcieCoreGetEndpointInfo ( } } =20 +Exit: // Restore value in order to not affect enumeration process MmioWrite32 (SecLatTimerAddr, RestoreVal); =20 @@ -1280,6 +1362,30 @@ Ac01PcieCoreQoSLinkCheckRecovery ( return LINK_CHECK_SUCCESS; } =20 +BOOLEAN +Ac01PcieCoreCheckCardPresent ( + IN AC01_PCIE_CONTROLLER *PcieController + ) +{ + EFI_PHYSICAL_ADDRESS TargetAddress; + UINT32 ControlValue; + + ControlValue =3D 0; + + TargetAddress =3D PcieController->CsrBase; + + ControlValue =3D MmioRead32 (TargetAddress + AC01_PCIE_CORE_LINK_CTRL_RE= G); + + if (0 =3D=3D LTSSMENB_GET (ControlValue)) { + // + // LTSSMENB is clear to 0x00 by Hardware -> link partner is connected. + // + return TRUE; + } + + return FALSE; +} + VOID Ac01PcieCoreUpdateLink ( IN AC01_ROOT_COMPLEX *RootComplex, @@ -1314,30 +1420,16 @@ Ac01PcieCoreUpdateLink ( Pcie->LinkUp =3D TRUE; Val =3D MmioRead32 (CfgBase + PCIE_CAPABILITY_BASE + LINK_CONTROL_= LINK_STATUS_REG); =20 - DEBUG (( - DEBUG_INFO, - "%a Socket%d RootComplex%d RP%d NEGO_LINK_WIDTH: 0x%x LINK_SPEED= : 0x%x\n", - __FUNCTION__, - RootComplex->Socket, - RootComplex->ID, - PcieIndex, - CAP_NEGO_LINK_WIDTH_GET (Val), - CAP_LINK_SPEED_GET (Val) - )); - // Doing link checking and recovery if needed Ac01PcieCoreQoSLinkCheckRecovery (RootComplex, PcieIndex); =20 - // Link timeout after 32ms - SetLinkTimeout (RootComplex, PcieIndex, 32); - // Un-mask Completion Timeout DisableCompletionTimeOut (RootComplex, PcieIndex, FALSE); =20 } else { - *IsNextRoundNeeded =3D FALSE; FailedPciePtr[*FailedPcieCount] =3D PcieIndex; *FailedPcieCount +=3D 1; + *IsNextRoundNeeded =3D !(*IsNextRoundNeeded) ? Ac01PcieCoreCheckCa= rdPresent (Pcie) : TRUE; } } } --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#102091): https://edk2.groups.io/g/devel/message/102091 Mute This Topic: https://groups.io/mt/97922251/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-