From nobody Sat Apr 20 12:36:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101774+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101774+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1679655821; cv=none; d=zohomail.com; s=zohoarc; b=Yn0ZexpKq7ykbZrtBPjECbxVpwmPanHC4KcfwwWoVVHV0EyNxAqD6ULmuMuNiSYiSC/7Wna4+qyotoEA8N9+SgMBy+RtPDJYptGfbrSSPNPuQnpbsia1oh5MZtg25h/B23HfjF1Mrl9dw0yjCh2qSxcI167QlyNJ/Z8RYQakYO0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679655821; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=d8vvkYyBmxBz68gk6BjGjeM7Og2gS1Cpto2nxLvxr+A=; b=ZXkfIpiTvJ8iKuvgzFlTGHwN5cWZxt4L5njGSc2WZI/o7O+IWNbdewsR6D4DGRAscGHpioO9VFSDUsul+frnMbXHrDxmta2WifJrajHzHIPM0GEvuHsjgAAaUGnypFWdexJeZgLebdA7POceBkbtJcJoMedHt7gNXP3ImHT5vs4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101774+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679655821490456.6104290728139; Fri, 24 Mar 2023 04:03:41 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id qhJDYY1788612xMTDtuG4rbo; Fri, 24 Mar 2023 04:03:41 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.97972.1679655820383173795 for ; Fri, 24 Mar 2023 04:03:40 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C9E9C11FB; Fri, 24 Mar 2023 04:04:23 -0700 (PDT) X-Received: from usa.arm.com (unknown [10.163.62.245]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 1D3953F6C4; Fri, 24 Mar 2023 04:03:26 -0700 (PDT) From: "Vivek Kumar Gautam" To: devel@edk2.groups.io Cc: ardb+tianocore@kernel.org, leif@nuviainc.com, Sami.Mujawar@arm.com, Pierre.Gondois@arm.com, Vivek.Gautam@arm.com, Pierre Gondois Subject: [edk2-devel] [edk2-platforms][PATCH V3 1/5] Platform/Sgi: Add SSDT table for Virtio-P9 Date: Fri, 24 Mar 2023 16:32:59 +0530 Message-Id: <20230324110303.1168851-2-vivek.gautam@arm.com> In-Reply-To: <20230324110303.1168851-1-vivek.gautam@arm.com> References: <20230324110303.1168851-1-vivek.gautam@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,vivek.gautam@arm.com X-Gm-Message-State: owRHeIyQjeR3FpLWVEexAAu5x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679655821; bh=3/a1DculXupFPXURikzis+/bRq/vzLC+FiTl7inQamM=; h=Cc:Date:From:Reply-To:Subject:To; b=vAJOrm6xJ0Wl/chJJ3OSfoR/JU+EXiTvF4ryWkCotwP4cJpqj8wNsMWn9aUo3lE4Mi9 WGtGNtErVmSqQTJduov/GO+hh+CIxRkM5QUHIZJrPIekEVV5yPIW6KD1bP8An9muTCCLX o16nfCTyamr2nQ3cZ4T2oKwbSCxU6h/UBZ8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679655822615100001 Content-Type: text/plain; charset="utf-8" Some of the Arm reference design FVP platforms support the Virtio-p9 device as part of the RoS subsystem. Add an entry for this device in the SSDT acpi table. The device entry is listed in a new SSDT file as only some of the reference design FVP platforms support it and so this file is included in the build for only the platforms that support Virtio-P9 device. Signed-off-by: Vivek Gautam Reviewed-by: Pierre Gondois Reviewed-by: Pierre Gondois: Reviewed-by: Sami Mujawar --- Platform/ARM/SgiPkg/SgiPlatform.dec | 7 +++- Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc | 7 +++- Platform/ARM/SgiPkg/AcpiTables/SsdtRosVirtioP9.asl | 42 ++++++++++++++++++= ++ 3 files changed, 54 insertions(+), 2 deletions(-) diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec b/Platform/ARM/SgiPkg/SgiP= latform.dec index b9be5c9060b6..e878af24d56b 100644 --- a/Platform/ARM/SgiPkg/SgiPlatform.dec +++ b/Platform/ARM/SgiPkg/SgiPlatform.dec @@ -1,5 +1,5 @@ # -# Copyright (c) 2018 - 2022, Arm Limited. All rights reserved. +# Copyright (c) 2018 - 2023, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -46,6 +46,11 @@ gArmSgiTokenSpaceGuid.PcdVirtioNetSize|0x00000000|UINT32|0x00000008 gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt|0x00000000|UINT32|0x00000009 =20 + # Virtio P9 + gArmSgiTokenSpaceGuid.PcdVirtioP9BaseAddress|0x00000000|UINT32|0x00000028 + gArmSgiTokenSpaceGuid.PcdVirtioP9Size|0x00000000|UINT32|0x00000029 + gArmSgiTokenSpaceGuid.PcdVirtioP9Interrupt|0x00000000|UINT32|0x0000002A + # Chip count on the platform gArmSgiTokenSpaceGuid.PcdChipCount|1|UINT32|0x0000000B =20 diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc b/Platform/ARM/SgiPk= g/SgiMemoryMap2.dsc.inc index 78ee48e354a8..12dcd82eb132 100644 --- a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc +++ b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc @@ -1,5 +1,5 @@ # -# Copyright (c) 2020 - 2022, Arm Limited. All rights reserved. +# Copyright (c) 2020 - 2023, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -38,6 +38,11 @@ gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress|0x0C150000 gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt|460 =20 + # Virtio P9 + gArmSgiTokenSpaceGuid.PcdVirtioP9BaseAddress|0x0C190000 + gArmSgiTokenSpaceGuid.PcdVirtioP9Size|0x10000 + gArmSgiTokenSpaceGuid.PcdVirtioP9Interrupt|459 + # PCIe gArmTokenSpaceGuid.PcdPciMmio32Base|0x60000000 gArmTokenSpaceGuid.PcdPciMmio32Size|0x10000000 diff --git a/Platform/ARM/SgiPkg/AcpiTables/SsdtRosVirtioP9.asl b/Platform/= ARM/SgiPkg/AcpiTables/SsdtRosVirtioP9.asl new file mode 100644 index 000000000000..a1aab5e094b3 --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/SsdtRosVirtioP9.asl @@ -0,0 +1,42 @@ +/** @file +* Secondary System Description Table Fields (SSDT) for Virtio-P9 device. +* +* Some of the Arm Reference Design FVP platforms support the Virtio-P9 dev= ice +* as part of the RoS subsystem. The Virtio-P9 device implements a subset o= f the +* Plan 9 file protocol over a virtio transport. It enables accessing a sha= red +* directory on the host's filesystem from a running FVP platform. +* This file describes the SSDT entry for this Virtio-P9 device +* +* Copyright (c) 2023, Arm Ltd. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +* @par Specification Reference: +* - ACPI 6.4, Chapter 5, Section 5.2.11.2, Secondary System Description = Table +**/ + +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" + +DefinitionBlock ("SsdtRosVirtioP9.aml", "SSDT", 2, "ARMLTD", "ARMSGI", + EFI_ACPI_ARM_OEM_REVISION) { + Scope (_SB) { + // VIRTIO P9 device + Device (VP90) { + Name (_HID, "LNRO0005") + Name (_UID, 2) + Name (_CCA, 1) // mark the device coherent + + Name (_CRS, ResourceTemplate() { + Memory32Fixed ( + ReadWrite, + FixedPcdGet32 (PcdVirtioP9BaseAddress), + FixedPcdGet32 (PcdVirtioP9Size) + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { + FixedPcdGet32 (PcdVirtioP9Interrupt) + } + }) + } + } // Scope(_SB) +} --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101774): https://edk2.groups.io/g/devel/message/101774 Mute This Topic: https://groups.io/mt/97821133/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 12:36:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101775+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101775+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1679655827; cv=none; d=zohomail.com; s=zohoarc; b=MXQDFnJ/60kY1njf1C5wqLP96GYH2cudje71ubthWEP1Ud98HAuVRxopJNGgUxBTqD7dhmemljV2gC9dtjFc+EvT62dW0B9CFrwwdN1XRvcO96CdoGW6QdpiNSsvxCCM0RNfpQ9cPj7vICMzuEAEaMCZJsDhWSjppA4Qvz5sw9A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679655827; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=x3igc4kEJCRRNbWd/wwDUSKTaTOj25c/QDxRXLKXX7M=; b=QGBcrFECC9HZKcGkUPovm4pF90l3HFa4RQO0evXhYVkogDfyCV9m79CD9ASDFVJY8Cy54eiwIybB76tc+tmEi4tEdVAYxweiWV1NrtkPcGTIZyLjR9zyVP5Uzgy8r5Ezx27Z4nuwMcXaPbL0XL/PJ8OF1uUKxRmu6oyr0uhPX+E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101775+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679655827536164.48088158399287; Fri, 24 Mar 2023 04:03:47 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id geRFYY1788612xvOKawmietF; Fri, 24 Mar 2023 04:03:47 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.98498.1679655826590659201 for ; Fri, 24 Mar 2023 04:03:46 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3C4E311FB; Fri, 24 Mar 2023 04:04:30 -0700 (PDT) X-Received: from usa.arm.com (unknown [10.163.62.245]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C7E263F6C4; Fri, 24 Mar 2023 04:03:40 -0700 (PDT) From: "Vivek Kumar Gautam" To: devel@edk2.groups.io Cc: ardb+tianocore@kernel.org, leif@nuviainc.com, Sami.Mujawar@arm.com, Pierre.Gondois@arm.com, Vivek.Gautam@arm.com, Pierre Gondois Subject: [edk2-devel] [edk2-platforms][PATCH V3 2/5] Platform/Sgi: Enable virtio-p9 device on RD-N2 platform variants Date: Fri, 24 Mar 2023 16:33:00 +0530 Message-Id: <20230324110303.1168851-3-vivek.gautam@arm.com> In-Reply-To: <20230324110303.1168851-1-vivek.gautam@arm.com> References: <20230324110303.1168851-1-vivek.gautam@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,vivek.gautam@arm.com X-Gm-Message-State: SVFlPVT1XsU12xnjar5Tiegox1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679655827; bh=RPAVm/+BN6uzGc6fzJ1JfHcR8GDAqKGyhIUexSEqygk=; h=Cc:Date:From:Reply-To:Subject:To; b=AAFUYmAvChpjMg7pAC0uTDvV/BER/6Y/h3GPUnFUn6d3HbGnjZDswgRM95RvNlofPPA bTzyF7fM0rod9C2H36L/6U3B5pIvTxYh+GOM9+8gciKr8ui+hfN8B8W/rwH/Hr+vgwZn7 BrUhH8bg0LQXYxMkkGZ8w9+GzDQ+R94yC3Y= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679655828480100002 Content-Type: text/plain; charset="utf-8" Enable the virtio-p9 device that is present as part of the RoS peripherals on RD-N2 platform variants. This will allow filesystem sharing between the Host PC and target platform. Signed-off-by: Vivek Gautam Reviewed-by: Pierre Gondois Reviewed-by: Pierre Gondois: Reviewed-by: Sami Mujawar --- Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 8 ++++++-- Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf | 8 ++++++-- Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2AcpiTables.inf | 6 +++++- 3 files changed, 17 insertions(+), 5 deletions(-) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf b/Platform/A= RM/SgiPkg/AcpiTables/RdN2AcpiTables.inf index 66d5422df36b..833f87c3e4be 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf @@ -1,7 +1,7 @@ ## @file # ACPI table data and ASL sources required to boot the platform. # -# Copyright (c) 2020-2021, Arm Ltd. All rights reserved. +# Copyright (c) 2020 - 2023, Arm Ltd. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -25,8 +25,9 @@ RdN2/Pptt.aslc Spcr.aslc Ssdt.asl - SsdtRos.asl SsdtEvents.asl + SsdtRos.asl + SsdtRosVirtioP9.asl =20 [Packages] ArmPkg/ArmPkg.dec @@ -70,6 +71,9 @@ gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress gArmSgiTokenSpaceGuid.PcdVirtioNetSize gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt + gArmSgiTokenSpaceGuid.PcdVirtioP9BaseAddress + gArmSgiTokenSpaceGuid.PcdVirtioP9Size + gArmSgiTokenSpaceGuid.PcdVirtioP9Interrupt gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv =20 diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf b/Platfo= rm/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf index 742734ab7348..e3e4e55bc410 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf @@ -1,7 +1,7 @@ ## @file # ACPI table data and ASL sources required to boot the platform. # -# Copyright (c) 2021, Arm Ltd. All rights reserved. +# Copyright (c) 2021 - 2023, Arm Ltd. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -25,8 +25,9 @@ RdN2Cfg1/Pptt.aslc Spcr.aslc Ssdt.asl - SsdtRos.asl SsdtEvents.asl + SsdtRos.asl + SsdtRosVirtioP9.asl =20 [Packages] ArmPkg/ArmPkg.dec @@ -71,6 +72,9 @@ gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress gArmSgiTokenSpaceGuid.PcdVirtioNetSize gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt + gArmSgiTokenSpaceGuid.PcdVirtioP9BaseAddress + gArmSgiTokenSpaceGuid.PcdVirtioP9Size + gArmSgiTokenSpaceGuid.PcdVirtioP9Interrupt gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv =20 diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2AcpiTables.inf b/Platfo= rm/ARM/SgiPkg/AcpiTables/RdN2Cfg2AcpiTables.inf index 2354f2dc65eb..6ce78582da35 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2AcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2AcpiTables.inf @@ -1,7 +1,7 @@ ## @file # ACPI table data and ASL sources required to boot the platform. # -# Copyright (c) 2022, Arm Limited. All rights reserved. +# Copyright (c) 2022 - 2023, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -24,6 +24,7 @@ RdN2Cfg2/Srat.aslc Spcr.aslc SsdtRos.asl + SsdtRosVirtioP9.asl =20 [Packages] ArmPkg/ArmPkg.dec @@ -65,6 +66,9 @@ gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress gArmSgiTokenSpaceGuid.PcdVirtioNetSize gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt + gArmSgiTokenSpaceGuid.PcdVirtioP9BaseAddress + gArmSgiTokenSpaceGuid.PcdVirtioP9Size + gArmSgiTokenSpaceGuid.PcdVirtioP9Interrupt gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv =20 --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101775): https://edk2.groups.io/g/devel/message/101775 Mute This Topic: https://groups.io/mt/97821136/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 12:36:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101776+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101776+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1679655839; cv=none; d=zohomail.com; s=zohoarc; b=HKFNxJfb9gs3uWR46UPeAda1p1yIo2LYe0GQn3PhnBMLloKx8EzOMz9E9FkHK5rWotIgLNy59iPGSZiRfxw/IndSD07nZGLEgsae3VHP63Q0PQMfK3FlyPJEechNnOLQKQkNEff6PMHShvvj2Fs1wJNL6KXqfVwf2LD3OGmdR3I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679655839; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=vkX9Npg+y4w6py87NYOBA8M1ZOXdCWNYWgSxiWYb4lI=; b=ZGBBSvusbzyp9bKm6Zh5WJuBZXTweSvDcowe2VAP2B5Zfk6QA3j0tLrcC8YTpclvcyL/xVVYsdIAh3GK2vk5buft63SpRPVlUJ6bfpbuHGJGA42Byb2Q3gKfIyKjCKgMzQ/pNUcwVrAoHWnTdY+QmJIPEWgpIuTNrq+A7uyx+Mo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101776+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 16796558392342.4071656729324786; Fri, 24 Mar 2023 04:03:59 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id GRkrYY1788612xCbkxiJN1bj; Fri, 24 Mar 2023 04:03:58 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.98502.1679655838034693206 for ; Fri, 24 Mar 2023 04:03:58 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C2AD011FB; Fri, 24 Mar 2023 04:04:41 -0700 (PDT) X-Received: from usa.arm.com (unknown [10.163.62.245]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6408A3F6C4; Fri, 24 Mar 2023 04:03:46 -0700 (PDT) From: "Vivek Kumar Gautam" To: devel@edk2.groups.io Cc: ardb+tianocore@kernel.org, leif@nuviainc.com, Sami.Mujawar@arm.com, Pierre.Gondois@arm.com, Vivek.Gautam@arm.com Subject: [edk2-devel] [edk2-platforms][PATCH V3 3/5] Platform/Sgi: Add SSDT table for IO virtualization SoC expansion block Date: Fri, 24 Mar 2023 16:33:01 +0530 Message-Id: <20230324110303.1168851-4-vivek.gautam@arm.com> In-Reply-To: <20230324110303.1168851-1-vivek.gautam@arm.com> References: <20230324110303.1168851-1-vivek.gautam@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,vivek.gautam@arm.com X-Gm-Message-State: zAfeqwGbseY63f3nEdUZ8Oi4x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679655838; bh=sHn4qp7nPZRYdkQwzrxr1oECeUbUxI0dgTCzQqw8bcM=; h=Cc:Date:From:Reply-To:Subject:To; b=JvP8O6Fs/yVpmd3rNfwWb+YkczuKrLoFlXYHnFvOtnSWAKhmBSEqXO27Ow5uJHkCl5i mIgmUxzEf70qsVPnNNowzH0EBaYlndD0pZHCw9f9dlEpnOUoVIMb1MCrAvahlLk09oAjX B32VOyOnvxD6vKCLzJ7O3MglTDfkame2vh0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679655840537100001 Content-Type: text/plain; charset="utf-8" Arm reference design platforms have multiple IO virtualization blocks that allow connecting PCIe root bus or non-PCIe SoC peripherals to the system. Each of these IO virtualization blocks consists of an instance of SMMUv3, a GIC-ITS and a NCI (network chip interconnect) to support traffic flow and address mapping, as required. The SoC expansion blocks that connect to the IO virtualization block include devices such as UARTs, DMAs and few additional memory nodes. For platforms having SoC expansion block connected to the IO virtualization block add a SSDT table to describe devices included in the SoC expansion block. Preprocessor macros are also added in this change to allow scalability for platforms that implement multiple instances of these SoC expansion blocks. Signed-off-by: Vivek Gautam Reviewed-by: Pierre Gondois: Reviewed-by: Sami Mujawar --- Platform/ARM/SgiPkg/SgiPlatform.dec | 4 + Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc | 3 + Platform/ARM/SgiPkg/Include/IoVirtSoCExp.h | 188 ++++++++++++++++= ++++ Platform/ARM/SgiPkg/AcpiTables/SsdtIoVirtSocExp.asl | 96 ++++++++++ 4 files changed, 291 insertions(+) diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec b/Platform/ARM/SgiPkg/SgiP= latform.dec index e878af24d56b..1613cc01981e 100644 --- a/Platform/ARM/SgiPkg/SgiPlatform.dec +++ b/Platform/ARM/SgiPkg/SgiPlatform.dec @@ -98,5 +98,9 @@ # Address bus width gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip|0x0|UINT64|0x00000027 =20 + # IO virtualization block + gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlk0Base|0|UINT64|0x0000002B + gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlkUartEnable|0|UINT32|0x0000002C + [Ppis] gNtFwConfigDtInfoPpiGuid =3D { 0x6f606eb3, 0x9123, 0x4e15, { 0xa8, 0= x9b, 0x0f, 0xac, 0x66, 0xef, 0xd0, 0x17 } } diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc b/Platform/ARM/SgiPk= g/SgiMemoryMap2.dsc.inc index 12dcd82eb132..de1d8ea24b89 100644 --- a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc +++ b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc @@ -72,3 +72,6 @@ gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress|0x0C1D0000 gArmSgiTokenSpaceGuid.PcdGpioController0Size|0x00010000 gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt|392 + + # IO virtualization block + gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlk0Base|0x1080000000 diff --git a/Platform/ARM/SgiPkg/Include/IoVirtSoCExp.h b/Platform/ARM/SgiP= kg/Include/IoVirtSoCExp.h new file mode 100644 index 000000000000..ab20f7b1413b --- /dev/null +++ b/Platform/ARM/SgiPkg/Include/IoVirtSoCExp.h @@ -0,0 +1,188 @@ +/** @file +* +* Copyright (c) 2023, Arm Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include "SgiPlatform.h" + +#define IO_VIRT_BLK_BASE FixedPcdGet64 (PcdIoVirtSocExpBlk0Base) +#define DEV_OFFSET 0x10000000 +#define RESOURCE_SIZE 0x10000 + +/** Macros to calculate base addresses of UART and DMA devices within IO + virtualization SoC expansion block address space. + + @param [in] n Index of UART or DMA device within SoC expansion b= lock. + Should be either 0 or 1. + + The base address offsets of UART and DMA devices within a SoC expansion = block + are shown below. The UARTs are at offset (2 * index * offset), while the= DMAs + are at offsets ((2 * index + 1) * offset). + +----------------------------------------------+ + | Port # | Peripheral | Base address offset | + |--------|---------------|---------------------| + | x4_0 | PL011_UART0 | 0x0000_0000 | + |--------|---------------|---------------------| + | x4_1 | PL011_DMA0_NS | 0x1000_0000 | + |--------|---------------|---------------------| + | x8 | PL011_UART1 | 0x2000_0000 | + |--------|---------------|---------------------| + | x16 | PL011_DMA1_NS | 0x3000_0000 | + +----------------------------------------------+ +**/ +#define UART_START(n) IO_VIRT_BLK_BASE + (2 * n * DEV_OFFSET) +#define DMA_START(n) IO_VIRT_BLK_BASE + (((2 * n) + 1) * DEV_OFFSE= T) + +// Interrupt numbers of PL330 DMA-0 and DMA-1 devices in the SoC expansion +// connected to the IO Virtualization block. Each DMA PL330 controller uses +// eight data channel interrupts and one instruction channel interrupt to +// notify aborts. +#define RD_IOVIRT_SOC_EXP_DMA0_INTERRUPTS_INIT = \ + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { = \ + 493, 494, 495, 496, 497, 498, 499, 500, 501 = \ + } +#define RD_IOVIRT_SOC_EXP_DMA1_INTERRUPTS_INIT = \ + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { = \ + 503, 504, 505, 506, 507, 508, 509, 510, 511 = \ + } + +#define RD_IOVIRT_SOC_EXP_DMA2_INTERRUPTS_INIT = \ + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { = \ + 973, 974, 975, 976, 977, 978, 979, 980, 981 = \ + } + +#define RD_IOVIRT_SOC_EXP_DMA3_INTERRUPTS_INIT = \ + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { = \ + 983, 984, 985, 986, 987, 988, 989, 990, 991 = \ + } + +#define RD_IOVIRT_SOC_EXP_DMA4_INTERRUPTS_INIT = \ + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { = \ + 4557, 4558, 4559, 4560, 4561, 4562, 4563, 4564, 4565 = \ + } + +#define RD_IOVIRT_SOC_EXP_DMA5_INTERRUPTS_INIT = \ + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { = \ + 4567, 4568, 4569, 4570, 4571, 4572, 4573, 4574, 4575 = \ + } + +#define RD_IOVIRT_SOC_EXP_DMA6_INTERRUPTS_INIT = \ + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { = \ + 5037, 5038, 5039, 5040, 5041, 5042, 5043, 5044, 5045 = \ + } + +#define RD_IOVIRT_SOC_EXP_DMA7_INTERRUPTS_INIT = \ + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { = \ + 5047, 5048, 5049, 5050, 5051, 5052, 5053, 5054, 5055 = \ + } + +/** Macro for PL011 UART controller node instantiation in SSDT table. + + See section 5.2.11.2 of ACPI specification v6.4 for the definition of SS= DT + table. + + @param [in] ComIdx Index of Com device to be initializaed; + to be passed as 2-digit index, such as 01 to + support multichip platforms as well. + @param [in] ChipIdx Index of chip to which this DMA device belon= gs + @param [in] StartOff Starting offset of this device within IO + virtualization block memory map + @param [in] IrqNum Interrupt ID used for the device +**/ +#define RD_IOVIRT_SOC_EXP_COM_INIT(ComIdx, ChipIdx, StartOff, IrqNum) = \ + Device (COM ##ComIdx) { = \ + Name (_HID, "ARMH0011") = \ + Name (_UID, ComIdx) = \ + Name (_STA, 0xF) = \ + = \ + Method (_CRS, 0, Serialized) { = \ + Name (RBUF, ResourceTemplate () { = \ + QWordMemory ( = \ + ResourceProducer, = \ + PosDecode, = \ + MinFixed, = \ + MaxFixed, = \ + NonCacheable, = \ + ReadWrite, = \ + 0x0, = \ + 0, = \ + 1, = \ + 0x0, = \ + 2, = \ + , = \ + , = \ + MMI1, = \ + AddressRangeMemory, = \ + TypeStatic = \ + ) = \ + = \ + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { = \ + IrqNum = \ + } = \ + }) /* end Name(RBUF) */ = \ + /* Work around ASL's inability to add in a resource definition */ = \ + CreateQwordField (RBUF, MMI1._MIN, MIN1) = \ + CreateQwordField (RBUF, MMI1._MAX, MAX1) = \ + CreateQwordField (RBUF, MMI1._LEN, LEN1) = \ + Add (SGI_REMOTE_CHIP_MEM_OFFSET(ChipIdx), StartOff, MIN1) = \ + Add (MIN1, RESOURCE_SIZE - 1, MAX1) = \ + Add (RESOURCE_SIZE, 0, LEN1) = \ + = \ + Return (RBUF) = \ + } /* end Method(_CRS) */ = \ + } + +/** Macro for PL330 DMA controller node instantiation in SSDT table. + + See section 5.2.11.2 of ACPI specification v6.4 for the definition of SS= DT + table. + + @param [in] DmaIdx Index of DMA device to be initializaed + @param [in] ChipIdx Index of chip to which this DMA device belon= gs + @param [in] StartOff Starting offset of this device within IO + virtualization block memory map +**/ +#define RD_IOVIRT_SOC_EXP_DMA_INIT(DmaIdx, ChipIdx, StartOff) = \ + Device (\_SB.DMA ##DmaIdx) { = \ + Name (_HID, "ARMH0330") = \ + Name (_UID, DmaIdx) = \ + Name (_CCA, 1) = \ + Name (_STA, 0xF) = \ + = \ + Method (_CRS, 0, Serialized) { = \ + Name (RBUF, ResourceTemplate () { = \ + QWordMemory ( = \ + ResourceProducer, = \ + PosDecode, = \ + MinFixed, = \ + MaxFixed, = \ + NonCacheable, = \ + ReadWrite, = \ + 0x0, = \ + 0, = \ + 1, = \ + 0x0, = \ + 2, = \ + , = \ + , = \ + MMI2, = \ + AddressRangeMemory, = \ + TypeStatic = \ + ) = \ + = \ + RD_IOVIRT_SOC_EXP_DMA ##DmaIdx## _INTERRUPTS_INIT = \ + }) /* end Name(RBUF) */ = \ + /* Work around ASL's inability to add in a resource definition */ = \ + CreateQwordField (RBUF, MMI2._MIN, MIN2) = \ + CreateQwordField (RBUF, MMI2._MAX, MAX2) = \ + CreateQwordField (RBUF, MMI2._LEN, LEN2) = \ + Add (SGI_REMOTE_CHIP_MEM_OFFSET(ChipIdx), StartOff, MIN2) = \ + Add (MIN2, RESOURCE_SIZE - 1, MAX2) = \ + Add (RESOURCE_SIZE, 0, LEN2) = \ + = \ + Return (RBUF) = \ + } /* end Method(_CRS) */ = \ + } diff --git a/Platform/ARM/SgiPkg/AcpiTables/SsdtIoVirtSocExp.asl b/Platform= /ARM/SgiPkg/AcpiTables/SsdtIoVirtSocExp.asl new file mode 100644 index 000000000000..d852cf4ffeaa --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/SsdtIoVirtSocExp.asl @@ -0,0 +1,96 @@ +/** @file + Secondary System Description Table (SSDT) for IO Virtualization SoC Expa= nsion + + The IO virtualization blocks on Arm Reference Design (RD) platforms allow + connecting PCIe root bus as well as other non-PCIe SoC peripherals. Each= of + these IO virtualization blocks consists of an instance of SMMUv3, a GIC-= ITS + and a NCI (network chip interconnect) to support traffic flow and address + mapping, as required. The PCIe root bus or the SoC peripherals connect t= o the + IO virtualization block over ports namely x4_0, x4_1, x8 and x16. + + Some of the RD platforms utilize one or more IO virtualization blocks to + connect non-PCIe devices mapped in the SoC expansion address space. One + such instance of SoC expansion block consists of a set of non-PCIe devic= es + that includes two PL011 UART controllers, two PL330 DMA controllers and + few additional memory nodes. The devices in this SoC expansion block are + placed at fixed offsets from a base address in the SoC expansion address + space and the read/write accesses to these devices are routed by the IO + virtualization block. + + The table below lists the address offset, address space size and interru= pts + used for the devices present in each instance of this SoC expansion block + that is connected to the IO Virtualization block. + +-----------------------------------------------------------------------= --------+ + | Port | Peripheral | Memory map | Size | In= terrupt | + | # | |-------------------------------------| | = ID | + | | | Start Addr Offset | End Addr Offset | | = | + +-----------------------------------------------------------------------= --------+ + | x4_0 | PL011_UART0 | 0x0000_0000 | 0x0000_FFFF | 64KB | = 492 | + |-----------------------------------------------------------------------= --------| + | x4_1 | PL011_DMA0_NS | 0x1000_0000 | 0x1000_FFFF | 64KB | 49= 3-501 | + |-----------------------------------------------------------------------= --------| + | x8 | PL011_UART1 | 0x2000_0000 | 0x2000_FFFF | 64KB | = 502 | + |-----------------------------------------------------------------------= --------| + | x16 | PL011_DMA1_NS | 0x3000_0000 | 0x3000_FFFF | 64KB | 50= 3-511 | + +-----------------------------------------------------------------------= --------+ + + This SSDT ACPI table lists the SoC expansion block devices connected via= the + IO Virtualization block on RD-N2 platform variants and mapped to SoC exp= ansion + address at an offset of 0x10_8000_0000 from each chip's base address. + + Copyright (c) 2023, Arm Limited. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.4, Chapter 5, Section 5.2.11.2, Secondary System Description = Table +**/ + +#include "IoVirtSoCExp.h" +#include "SgiAcpiHeader.h" + +DefinitionBlock ("SsdtIoVirtSocExp.aml", "SSDT", 2, "ARMLTD", "ARMSGI", + EFI_ACPI_ARM_OEM_REVISION) { + Scope (_SB) + { + + // IO Virtualization SoC Expansion - PL011 UART +#if (FixedPcdGet32 (PcdIoVirtSocExpBlkUartEnable) =3D=3D 1) + RD_IOVIRT_SOC_EXP_COM_INIT(2, 0, UART_START(0), 492) + RD_IOVIRT_SOC_EXP_COM_INIT(3, 0, UART_START(1), 502) + +#if (FixedPcdGet32 (PcdChipCount) > 1) + RD_IOVIRT_SOC_EXP_COM_INIT(4, 1, UART_START(0), 972) + RD_IOVIRT_SOC_EXP_COM_INIT(5, 1, UART_START(1), 982) +#endif + +#if (FixedPcdGet32 (PcdChipCount) > 2) + RD_IOVIRT_SOC_EXP_COM_INIT(6, 2, UART_START(0), 4556) + RD_IOVIRT_SOC_EXP_COM_INIT(7, 2, UART_START(1), 4566) +#endif + +#if (FixedPcdGet32 (PcdChipCount) > 3) + RD_IOVIRT_SOC_EXP_COM_INIT(8, 3, UART_START(0), 5036) + RD_IOVIRT_SOC_EXP_COM_INIT(9, 3, UART_START(1), 5046) +#endif +#endif + + // IO Virtualization SoC Expansion - PL330 DMA + RD_IOVIRT_SOC_EXP_DMA_INIT(0, 0, DMA_START(0)) + RD_IOVIRT_SOC_EXP_DMA_INIT(1, 0, DMA_START(1)) + +#if (FixedPcdGet32 (PcdChipCount) > 1) + RD_IOVIRT_SOC_EXP_DMA_INIT(2, 1, DMA_START(0)) + RD_IOVIRT_SOC_EXP_DMA_INIT(3, 1, DMA_START(1)) +#endif + +#if (FixedPcdGet32 (PcdChipCount) > 2) + RD_IOVIRT_SOC_EXP_DMA_INIT(4, 2, DMA_START(0)) + RD_IOVIRT_SOC_EXP_DMA_INIT(5, 2, DMA_START(1)) +#endif + +#if (FixedPcdGet32 (PcdChipCount) > 3) + RD_IOVIRT_SOC_EXP_DMA_INIT(6, 3, DMA_START(0)) + RD_IOVIRT_SOC_EXP_DMA_INIT(7, 3, DMA_START(1)) +#endif + } // Scope(_SB) +} --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101776): https://edk2.groups.io/g/devel/message/101776 Mute This Topic: https://groups.io/mt/97821140/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 12:36:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101777+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101777+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1679655857; cv=none; d=zohomail.com; s=zohoarc; b=IF2RSSigtAunDjBlyNHb/8f8LnXry9lg/saiSgHtQx8gJU+Te7ECOGXuAZl+A9qu8rjqQl7VBUdIBtqibY4R8mOj7A+HQvigtpuEC2tG5OjOerGOi7/dOhERTkxKPKG0C9QxkqAkoSYsHROD3E2EoncFcqfl1ThOlPOhxD1K+lM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679655857; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=UALlybEv0SF7kY/NhYQnKUj3PheimBGbmutinjLKlqs=; b=I16Pal54oqJTyzNam1rgL69DadV/QlUzC2gTuDh1Dob5XSU58qRjXWOPAZMORn4X/anVoXk6axY8ZksFrajdC3uu+rlolA37t4VY35Mzsg97ATIw9k5S9zy/Liaud38r2A3T40oOyx41gbZV6uCm+Dpf/T6G/jLOheI2wOqgWn4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101777+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679655857374688.2005510815378; Fri, 24 Mar 2023 04:04:17 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id OheNYY1788612xEhft7xAFlR; Fri, 24 Mar 2023 04:04:17 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.98508.1679655856505148087 for ; Fri, 24 Mar 2023 04:04:16 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 39B7011FB; Fri, 24 Mar 2023 04:05:00 -0700 (PDT) X-Received: from usa.arm.com (unknown [10.163.62.245]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 3B1843F6C4; Fri, 24 Mar 2023 04:03:57 -0700 (PDT) From: "Vivek Kumar Gautam" To: devel@edk2.groups.io Cc: ardb+tianocore@kernel.org, leif@nuviainc.com, Sami.Mujawar@arm.com, Pierre.Gondois@arm.com, Vivek.Gautam@arm.com Subject: [edk2-devel] [edk2-platforms][PATCH V3 4/5] Platform/Sgi: Initialize additional UART controllers Date: Fri, 24 Mar 2023 16:33:02 +0530 Message-Id: <20230324110303.1168851-5-vivek.gautam@arm.com> In-Reply-To: <20230324110303.1168851-1-vivek.gautam@arm.com> References: <20230324110303.1168851-1-vivek.gautam@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,vivek.gautam@arm.com X-Gm-Message-State: bQBGI5RXZly43xz0Eh1lmTLjx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679655857; bh=CM02ECqDos0hRNxwJdQb8ocJ+3UyZetfLuniISxv3GM=; h=Cc:Date:From:Reply-To:Subject:To; b=F+shZafOGI0BM9kqeB/lwHbOWK8vMi7Cj3+z6hGO2nTLjJJkAFWpCOYwurLCzD8hd8T jJilzvksBgt7jSIPidCQ3Jl4PF1a7vf/FLisU3mAW2vemfbAOxX2hiFwfwDz4amXiG8Ca W9y6JzzGCV3dMEH0Ut7OX+6Or3uZ9TXOo5M= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679655858669100002 Content-Type: text/plain; charset="utf-8" From: Shriram K The IO virtualization block on reference design platforms allow connecting SoC expansion devices such as PL011 UART. On platforms that support this, initialize the UART controller connected to the IO virtualization block. Signed-off-by: Shriram K Signed-off-by: Vivek Gautam Reviewed-by: Pierre Gondois: Reviewed-by: Sami Mujawar --- Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf | 9 ++- Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf | 6 +- Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c | 64 ++++++++++++= +++++++- Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c | 44 ++++++++++++= +- 4 files changed, 116 insertions(+), 7 deletions(-) diff --git a/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf b/Plat= form/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf index 9d89314a594e..3cd7e2329c22 100644 --- a/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf +++ b/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf @@ -1,5 +1,5 @@ # -# Copyright (c) 2018, ARM Limited. All rights reserved. +# Copyright (c) 2018 - 2023, ARM Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -17,6 +17,7 @@ VirtioDevices.c =20 [Packages] + ArmPlatformPkg/ArmPlatformPkg.dec EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec OvmfPkg/OvmfPkg.dec @@ -37,10 +38,16 @@ gArmSgiTokenSpaceGuid.PcdVirtioNetSupported =20 [FixedPcd] + gArmSgiTokenSpaceGuid.PcdChipCount + gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlk0Base + gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlkUartEnable + gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress gArmSgiTokenSpaceGuid.PcdVirtioBlkSize gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress gArmSgiTokenSpaceGuid.PcdVirtioNetSize =20 + gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz + [Depex] TRUE diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf b/Plat= form/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf index 1ca7679b4191..020bde0d1f56 100644 --- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf +++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf @@ -1,5 +1,5 @@ # -# Copyright (c) 2018 - 2022, Arm Limited. All rights reserved. +# Copyright (c) 2018 - 2023, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -41,10 +41,12 @@ gArmPlatformTokenSpaceGuid.PcdCoreCount gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase =20 - gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip gArmSgiTokenSpaceGuid.PcdDramBlock2Base gArmSgiTokenSpaceGuid.PcdDramBlock2Size gArmSgiTokenSpaceGuid.PcdGicSize + gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlk0Base + gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlkUartEnable + gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip =20 gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize diff --git a/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c b/Platfo= rm/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c index 2f72e7152ff3..b3a998bc1585 100644 --- a/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c +++ b/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2018, ARM Limited. All rights reserved. +* Copyright (c) 2018 - 2023, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -9,6 +9,9 @@ #include #include #include +#include + +#include #include =20 VOID @@ -16,6 +19,64 @@ InitVirtioDevices ( VOID ); =20 +/** + Initialize UART controllers connected to IO Virtualization block. + + Use PL011UartLib Library to initialize UART controllers that are present= in + the SoC expansion block. This SoC expansion block is connected to the IO + virtualization block on Arm infrastructure reference design (RD) platfor= ms. + + @retval None +**/ +STATIC +VOID +InitIoVirtSocExpBlkUartControllers (VOID) +{ + EFI_STATUS Status; + EFI_PARITY_TYPE Parity; + EFI_STOP_BITS_TYPE StopBits; + UINT64 BaudRate; + UINT32 ReceiveFifoDepth; + UINT8 DataBits; + UINT8 UartIdx; + UINT32 ChipIdx; + UINT64 UartAddr; + + if (FixedPcdGet32 (PcdIoVirtSocExpBlkUartEnable) =3D=3D 0) + return; + + ReceiveFifoDepth =3D 0; + Parity =3D 1; + DataBits =3D 8; + StopBits =3D 1; + BaudRate =3D 115200; + + for (ChipIdx =3D 0; ChipIdx < FixedPcdGet32 (PcdChipCount); ChipIdx++) { + for (UartIdx =3D 0; UartIdx < 2; UartIdx++) { + UartAddr =3D SGI_REMOTE_CHIP_MEM_OFFSET(ChipIdx) + UART_START(UartId= x); + + Status =3D PL011UartInitializePort ( + (UINTN)UartAddr, + FixedPcdGet32 (PcdSerialDbgUartClkInHz), + &BaudRate, + &ReceiveFifoDepth, + &Parity, + &DataBits, + &StopBits + ); + + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Failed to init PL011_UART%u on IO Virt Block port, status: %r\n= ", + UartIdx, + Status + )); + } + } + } +} + EFI_STATUS EFIAPI ArmSgiPkgEntryPoint ( @@ -32,6 +93,7 @@ ArmSgiPkgEntryPoint ( } =20 InitVirtioDevices (); + InitIoVirtSocExpBlkUartControllers (); =20 return Status; } diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c b/Pla= tform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c index 8139b75d8ee4..fa3cfbc730f6 100644 --- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c +++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2018-2020, ARM Limited. All rights reserved. +* Copyright (c) 2018-2023, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -13,11 +13,24 @@ #include #include =20 +#include #include =20 // Total number of descriptors, including the final "end-of-table" descrip= tor. -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS \ - (14 + (FixedPcdGet32 (PcdChipCount) * 2)) +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS = \ + ((14 + (FixedPcdGet32 (PcdChipCount) * 2)) + = \ + (FixedPcdGet32 (PcdIoVirtSocExpBlkUartEnable) * = \ + FixedPcdGet32 (PcdChipCount) * 2)) + +// Memory Map descriptor for IO Virtualization SoC Expansion Block UART +#define IO_VIRT_SOC_EXP_BLK_UART_MMAP(UartIdx, ChipIdx) = \ + VirtualMemoryTable[++Index].PhysicalBase =3D = \ + SGI_REMOTE_CHIP_MEM_OFFSET(ChipIdx) + UART_START(UartIdx); = \ + VirtualMemoryTable[Index].VirtualBase =3D = \ + SGI_REMOTE_CHIP_MEM_OFFSET(ChipIdx) + UART_START(UartIdx); = \ + VirtualMemoryTable[Index].Length =3D SIZE_64KB; = \ + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE= _DEVICE; + =20 /** Returns the Virtual Memory Map of the platform. @@ -171,6 +184,31 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Length =3D SIZE_64KB; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; =20 +#if (FixedPcdGet32 (PcdIoVirtSocExpBlkUartEnable) =3D=3D 1) + // Chip-0 IO Virtualization SoC Expansion Block - UART0 + IO_VIRT_SOC_EXP_BLK_UART_MMAP(0, 0) + // Chip-0 IO Virtualization SoC Expansion Block - UART1 + IO_VIRT_SOC_EXP_BLK_UART_MMAP(1, 0) +#if (FixedPcdGet32 (PcdChipCount) > 1) + // Chip-1 IO Virtualization SoC Expansion Block - UART0 + IO_VIRT_SOC_EXP_BLK_UART_MMAP(0, 1) + // Chip-1 IO Virtualization SoC Expansion Block - UART1 + IO_VIRT_SOC_EXP_BLK_UART_MMAP(1, 1) +#if (FixedPcdGet32 (PcdChipCount) > 2) + // Chip-2 IO Virtualization SoC Expansion Block - UART0 + IO_VIRT_SOC_EXP_BLK_UART_MMAP(0, 2) + // Chip-2 IO Virtualization SoC Expansion Block - UART1 + IO_VIRT_SOC_EXP_BLK_UART_MMAP(1, 2) +#if (FixedPcdGet32 (PcdChipCount) > 3) + // Chip-3 IO Virtualization SoC Expansion Block - UART0 + IO_VIRT_SOC_EXP_BLK_UART_MMAP(0, 3) + // Chip-3 IO Virtualization SoC Expansion Block - UART1 + IO_VIRT_SOC_EXP_BLK_UART_MMAP(1, 3) +#endif +#endif +#endif +#endif + // DDR - (2GB - 16MB) VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdSystemMemoryB= ase); VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdSystemMemoryB= ase); --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101777): https://edk2.groups.io/g/devel/message/101777 Mute This Topic: https://groups.io/mt/97821142/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 12:36:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101778+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101778+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1679655868; cv=none; d=zohomail.com; s=zohoarc; b=OYaeIzevvpryNhdeohKwvsYNEmy7Rm+zqJ2TPdVSJCT3iYapWCpja2OpQGhn+D35kYd6f80Wx731an8tjT384VXVZ1A6Gt7ybc8o+LlBRMjrbT/GZf77SKbZGR47jnjLH0Z4iCt4ndeAM6TZcaMpg+4t+v+qccBc6u3sf6x4Iqk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679655868; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=krGoB3XQyUqn7z/IomubOfRceT8rob9bHClFFlvrJzQ=; b=Ase4WTApppghVnoJJsMQhmZwO+XkMrlDjRVah27bmYiugK66YNSb/0s12n+C1kWt4RCphF9ceOtJPM6pYzNHsNwdpDXuGtob5PzZD1PSuhbdnbxO7ITCB7Nh5rqOFlPC1tO53xwzge4yw97vgqx7a30embJKhjT6KwIwMhAVXw0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101778+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679655868055455.9886782492687; Fri, 24 Mar 2023 04:04:28 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id eAgJYY1788612x7mmeCwOa9p; Fri, 24 Mar 2023 04:04:27 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.97985.1679655866959076773 for ; Fri, 24 Mar 2023 04:04:27 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B46BE11FB; Fri, 24 Mar 2023 04:05:10 -0700 (PDT) X-Received: from usa.arm.com (unknown [10.163.62.245]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E21D73F6C4; Fri, 24 Mar 2023 04:04:16 -0700 (PDT) From: "Vivek Kumar Gautam" To: devel@edk2.groups.io Cc: ardb+tianocore@kernel.org, leif@nuviainc.com, Sami.Mujawar@arm.com, Pierre.Gondois@arm.com, Vivek.Gautam@arm.com Subject: [edk2-devel] [edk2-platforms][PATCH V3 5/5] Platform/Sgi: Enable SoC expansion block for RD-N2 variants Date: Fri, 24 Mar 2023 16:33:03 +0530 Message-Id: <20230324110303.1168851-6-vivek.gautam@arm.com> In-Reply-To: <20230324110303.1168851-1-vivek.gautam@arm.com> References: <20230324110303.1168851-1-vivek.gautam@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,vivek.gautam@arm.com X-Gm-Message-State: QwGacdTBulj8ixmRU6ztv0bHx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679655867; bh=ebjM0+VspW+2tslBaI/7z0yrY+3Hhvtl6GEbG+ntzr0=; h=Cc:Date:From:Reply-To:Subject:To; b=eXOAXYME4pnbIOcwzwRtEGWo/oZn8ouqRvzKn88FHfmJyr4Ez9IIuDGndjUtURvenPp jURXAKHSBm/FJqMqhBqvrChlCei1dGiy3/79jKSy7dgwpOdhe78oZVaPbserEKCHrcSBd cGoqhBEjOY32tmgK7L69SeSgZHwJlgAF5i4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679655868665100001 Content-Type: text/plain; charset="utf-8" For all the RD-N2 platform variants, include the SSDT ACPI table that describes the devices present in SoC expansion block that is connected to the IO virtualization block. Signed-off-by: Vivek Gautam Reviewed-by: Pierre Gondois: Reviewed-by: Sami Mujawar --- Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 5 +++++ Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf | 5 +++++ Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2AcpiTables.inf | 3 +++ 3 files changed, 13 insertions(+) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf b/Platform/A= RM/SgiPkg/AcpiTables/RdN2AcpiTables.inf index 833f87c3e4be..8025ef58171b 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf @@ -26,6 +26,7 @@ Spcr.aslc Ssdt.asl SsdtEvents.asl + SsdtIoVirtSocExp.asl SsdtRos.asl SsdtRosVirtioP9.asl =20 @@ -55,11 +56,15 @@ gArmTokenSpaceGuid.PcdPciBusMin gArmTokenSpaceGuid.PcdPciBusMax =20 + gArmSgiTokenSpaceGuid.PcdChipCount gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress gArmSgiTokenSpaceGuid.PcdGpioController0Size gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv + gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlk0Base + gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlkUartEnable + gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip gArmSgiTokenSpaceGuid.PcdOscLpiEnable gArmSgiTokenSpaceGuid.PcdOscCppcEnable gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf b/Platfo= rm/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf index e3e4e55bc410..88e210933f6d 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf @@ -26,6 +26,7 @@ Spcr.aslc Ssdt.asl SsdtEvents.asl + SsdtIoVirtSocExp.asl SsdtRos.asl SsdtRosVirtioP9.asl =20 @@ -55,11 +56,15 @@ gArmTokenSpaceGuid.PcdPciBusMin gArmTokenSpaceGuid.PcdPciBusMax =20 + gArmSgiTokenSpaceGuid.PcdChipCount gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress gArmSgiTokenSpaceGuid.PcdGpioController0Size gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv + gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlk0Base + gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlkUartEnable + gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip gArmSgiTokenSpaceGuid.PcdOscLpiEnable gArmSgiTokenSpaceGuid.PcdOscCppcEnable gArmSgiTokenSpaceGuid.PcdSmmuBase diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2AcpiTables.inf b/Platfo= rm/ARM/SgiPkg/AcpiTables/RdN2Cfg2AcpiTables.inf index 6ce78582da35..ad81be29cd42 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2AcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2AcpiTables.inf @@ -23,6 +23,7 @@ RdN2Cfg2/Pptt.aslc RdN2Cfg2/Srat.aslc Spcr.aslc + SsdtIoVirtSocExp.asl SsdtRos.asl SsdtRosVirtioP9.asl =20 @@ -57,6 +58,8 @@ gArmSgiTokenSpaceGuid.PcdDramBlock2Size gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv + gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlk0Base + gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlkUartEnable gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip gArmSgiTokenSpaceGuid.PcdOscLpiEnable gArmSgiTokenSpaceGuid.PcdOscCppcEnable --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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