From nobody Mon Sep 16 19:29:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101739+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101739+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679637669; cv=none; d=zohomail.com; s=zohoarc; b=fZnNhhlsDpDJSg0ERnmzB8F/JRCiK44m0XVak5u+zr0Dus6ZvShplR/I6cOEJfMAT/ryxBBkZFq4qEZzx30fIqnRvICJ5h3m2A/CNxQl7YhYkn3xDqGXtRzGNnwMv9dxjQgBd2TlWfQQyJhrlvZrSbWxxCYSwPX2ttEZZ1xcWW8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679637669; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=XJUYUXWOFfYnRDXxTYO9sQFaOXt6VRzQugXME1CmyPI=; b=V+QCIBp0jXj/9CryRLAYfaYGNClUZG2P0O4XqtWW7EULjEeODASjCo19+gUO+M0Bpfd+7kVooH8da1771z5PNPU+x8PDVAkgNZtvEZP3EM+QH0vezyAZ6D89icTCo2FouQTo4/rZq9wwrkwm/NDbm575P5OehvYbsAi/Hpp9J7E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101739+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679637669596525.9759940921514; Thu, 23 Mar 2023 23:01:09 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 5L8oYY1788612xkPHfeweR8k; Thu, 23 Mar 2023 23:01:09 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.94534.1679637641374533517 for ; Thu, 23 Mar 2023 23:01:03 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="320094032" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="320094032" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:01:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="1012122154" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="1012122154" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:01:01 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V5 14/22] UefiCpuPkg/CpuPageTableLib: Add OUTPUT IsModified parameter. Date: Fri, 24 Mar 2023 14:00:12 +0800 Message-Id: <20230324060020.940-15-dun.tan@intel.com> In-Reply-To: <20230324060020.940-1-dun.tan@intel.com> References: <20230324060020.940-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: WLIYvB1GUeeCEEns0bT8VctAx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679637669; bh=X52wURB4MlS3i1vxN0eW/zCpFRxsQs5qNbGSqGcHRVc=; h=Cc:Date:From:Reply-To:Subject:To; b=SMWoxZ1lsBNFD4i0a2Dl9zLYrETWMTiQY3Cq8HHw+5x9MVP2weemKW7smck938WauFy awW5PKYNBHIwrXLMS4oSF4k5QVE6eCgNC6dNtXCOrZ4LjDWNwq2rzZk9liKJJ0B8O+x+J Ch6aHyNngzIbUvm5Ew2U84DkrQZvM1QAQxM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679637671456100019 Content-Type: text/plain; charset="utf-8" Add OUTPUT IsModified parameter in PageTableMap() to indicate if page table has been modified. With this parameter, caller can know if need to call FlushTlb when the page table is in CR3. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Tested-by: Gerd Hoffmann Acked-by: Gerd Hoffmann Reviewed-by: Ray Ni --- UefiCpuPkg/Include/Library/CpuPageTableLib.h = | 4 +++- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c = | 46 +++++++++++++++++++++++++++++++++++++++++----- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c = | 72 ++++++++++++++++++++++++++++++++++++----------------------------------= -- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c = | 6 ++++-- UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c = | 6 ++++-- 5 files changed, 88 insertions(+), 46 deletions(-) diff --git a/UefiCpuPkg/Include/Library/CpuPageTableLib.h b/UefiCpuPkg/Incl= ude/Library/CpuPageTableLib.h index 4ef4a8b6af..352b6df6c6 100644 --- a/UefiCpuPkg/Include/Library/CpuPageTableLib.h +++ b/UefiCpuPkg/Include/Library/CpuPageTableLib.h @@ -74,6 +74,7 @@ typedef enum { Page table entries that map the linear ad= dress range are reset to 0 before set to the new attribute when a new physical base address is set. @param[in] Mask The mask used for attribute. The correspo= nding field in Attribute is ignored if that in Mask is 0. + @param[out] IsModified TRUE means page table is modified. FALSE = means page table is not modified. =20 @retval RETURN_UNSUPPORTED PagingMode is not supported. @retval RETURN_INVALID_PARAMETER PageTable, BufferSize, Attribute or Ma= sk is NULL. @@ -97,7 +98,8 @@ PageTableMap ( IN UINT64 LinearAddress, IN UINT64 Length, IN IA32_MAP_ATTRIBUTE *Attribute, - IN IA32_MAP_ATTRIBUTE *Mask + IN IA32_MAP_ATTRIBUTE *Mask, + OUT BOOLEAN *IsModified OPTIONAL ); =20 typedef struct { diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index c0b41472ce..885f1601fc 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -274,6 +274,7 @@ IsAttributesAndMaskValidForNonPresentEntry ( Page table entries that map the linear= address range are reset to 0 before set to the new attribute when a new physical base address is se= t. @param[in] Mask The mask used for attribute. The corre= sponding field in Attribute is ignored if that in Mask is 0. + @param[out] IsModified TRUE means page table is modified. FAL= SE means page table is not modified. =20 @retval RETURN_INVALID_PARAMETER For non-present range, Mask->Bits.Pres= ent is 0 but some other attributes are provided. @retval RETURN_INVALID_PARAMETER For non-present range, Mask->Bits.Pres= ent is 1, Attribute->Bits.Present is 1 but some other attributes are not pr= ovided. @@ -292,7 +293,8 @@ PageTableLibMapInLevel ( IN UINT64 Length, IN UINT64 Offset, IN IA32_MAP_ATTRIBUTE *Attribute, - IN IA32_MAP_ATTRIBUTE *Mask + IN IA32_MAP_ATTRIBUTE *Mask, + OUT BOOLEAN *IsModified ) { RETURN_STATUS Status; @@ -318,6 +320,8 @@ PageTableLibMapInLevel ( IA32_MAP_ATTRIBUTE LocalParentAttribute; UINT64 PhysicalAddrInEntry; UINT64 PhysicalAddrInAttr; + IA32_PAGING_ENTRY OriginalParentPagingEntry; + IA32_PAGING_ENTRY OriginalCurrentPagingEntry; =20 ASSERT (Level !=3D 0); ASSERT ((Attribute !=3D NULL) && (Mask !=3D NULL)); @@ -333,6 +337,8 @@ PageTableLibMapInLevel ( LocalParentAttribute.Uint64 =3D ParentAttribute->Uint64; ParentAttribute =3D &LocalParentAttribute; =20 + OriginalParentPagingEntry.Uint64 =3D ParentPagingEntry->Uint64; + // // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 << 2= 1) or 4K (1 << 12). // @@ -568,7 +574,15 @@ PageTableLibMapInLevel ( ASSERT (CreateNew || (Mask->Bits.Nx =3D=3D 0) || (Attribute->Bit= s.Nx =3D=3D 1)); } =20 + // + // Check if any leaf PagingEntry is modified. + // + OriginalCurrentPagingEntry.Uint64 =3D CurrentPagingEntry->Uint64; PageTableLibSetPle (Level, CurrentPagingEntry, Offset, Attribute, = &CurrentMask); + + if (OriginalCurrentPagingEntry.Uint64 !=3D CurrentPagingEntry->Uin= t64) { + *IsModified =3D TRUE; + } } } else { // @@ -591,7 +605,8 @@ PageTableLibMapInLevel ( Length, Offset, Attribute, - Mask + Mask, + IsModified ); if (RETURN_ERROR (Status)) { return Status; @@ -603,6 +618,14 @@ PageTableLibMapInLevel ( Index++; } =20 + // + // Check if ParentPagingEntry entry is modified here is enough. Except t= he changes happen in leaf PagingEntry during + // the while loop, if there is any other change happens in page table, t= he ParentPagingEntry must has been modified. + // + if (OriginalParentPagingEntry.Uint64 !=3D ParentPagingEntry->Uint64) { + *IsModified =3D TRUE; + } + return RETURN_SUCCESS; } =20 @@ -623,6 +646,7 @@ PageTableLibMapInLevel ( Page table entries that map the linear ad= dress range are reset to 0 before set to the new attribute when a new physical base address is set. @param[in] Mask The mask used for attribute. The correspo= nding field in Attribute is ignored if that in Mask is 0. + @param[out] IsModified TRUE means page table is modified. FALSE = means page table is not modified. =20 @retval RETURN_UNSUPPORTED PagingMode is not supported. @retval RETURN_INVALID_PARAMETER PageTable, BufferSize, Attribute or Ma= sk is NULL. @@ -646,7 +670,8 @@ PageTableMap ( IN UINT64 LinearAddress, IN UINT64 Length, IN IA32_MAP_ATTRIBUTE *Attribute, - IN IA32_MAP_ATTRIBUTE *Mask + IN IA32_MAP_ATTRIBUTE *Mask, + OUT BOOLEAN *IsModified OPTIONAL ) { RETURN_STATUS Status; @@ -656,6 +681,7 @@ PageTableMap ( IA32_PAGE_LEVEL MaxLevel; IA32_PAGE_LEVEL MaxLeafLevel; IA32_MAP_ATTRIBUTE ParentAttribute; + BOOLEAN LocalIsModified; =20 if (Length =3D=3D 0) { return RETURN_SUCCESS; @@ -718,6 +744,12 @@ PageTableMap ( TopPagingEntry.Pce.Nx =3D 0; } =20 + if (IsModified =3D=3D NULL) { + IsModified =3D &LocalIsModified; + } + + *IsModified =3D FALSE; + ParentAttribute.Uint64 =3D 0; ParentAttribute.Bits.PageTableBaseAddress =3D 1; ParentAttribute.Bits.Present =3D 1; @@ -741,8 +773,10 @@ PageTableMap ( Length, 0, Attribute, - Mask + Mask, + IsModified ); + ASSERT (*IsModified =3D=3D FALSE); if (RETURN_ERROR (Status)) { return Status; } @@ -773,8 +807,10 @@ PageTableMap ( Length, 0, Attribute, - Mask + Mask, + IsModified ); + if (!RETURN_ERROR (Status)) { *PageTable =3D (UINTN)(TopPagingEntry.Uintn & IA32_PE_BASE_ADDRESS_MAS= K_40); } diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUni= tTestHost.c b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUn= itTestHost.c index c682d4ea04..759da09271 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c @@ -51,26 +51,26 @@ TestCaseForParameter ( // // If the input linear address is not 4K align, it should return invalid= parameter // - UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 1, SIZE_4KB, &MapAttribute, &MapMask), RETURN_INVALID_PARAMET= ER); + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 1, SIZE_4KB, &MapAttribute, &MapMask, NULL), RETURN_INVALID_P= ARAMETER); =20 // // If the input PageTableBufferSize is not 4K align, it should return in= valid parameter // PageTableBufferSize =3D 10; - UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 0, SIZE_4KB, &MapAttribute, &MapMask), RETURN_INVALID_PARAMET= ER); + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 0, SIZE_4KB, &MapAttribute, &MapMask, NULL), RETURN_INVALID_P= ARAMETER); =20 // // If the input PagingMode is Paging32bit, it should return invalid para= meter // PageTableBufferSize =3D 0; PagingMode =3D Paging32bit; - UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 1, SIZE_4KB, &MapAttribute, &MapMask), RETURN_UNSUPPORTED); + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 1, SIZE_4KB, &MapAttribute, &MapMask, NULL), RETURN_UNSUPPORT= ED); =20 // // If the input MapMask is NULL, it should return invalid parameter // PagingMode =3D Paging5Level1GB; - UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 1, SIZE_4KB, &MapAttribute, NULL), RETURN_INVALID_PARAMETER); + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 1, SIZE_4KB, &MapAttribute, NULL, NULL), RETURN_INVALID_PARAM= ETER); =20 return UNIT_TEST_PASSED; } @@ -119,10 +119,10 @@ TestCaseWhichNoNeedExtraSize ( // // Create page table to cover [0, 10M], it should have 5 PTE // - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, (UINT64)SIZE_2MB * 5, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, (UINT64)SIZE_2MB * 5, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, (UINT64)SIZE_2MB * 5, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, (UINT64)SIZE_2MB * 5, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); TestStatus =3D IsPageTableValid (PageTable, PagingMode); if (TestStatus !=3D UNIT_TEST_PASSED) { @@ -134,7 +134,7 @@ TestCaseWhichNoNeedExtraSize ( // We assume the fucntion doesn't need to change page table, return succ= ess and output BufferSize is 0 // Buffer =3D NULL; - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, (UINT64)SIZE_4KB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, (UINT64)SIZE_4KB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (PageTableBufferSize, 0); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); TestStatus =3D IsPageTableValid (PageTable, PagingMode); @@ -148,7 +148,7 @@ TestCaseWhichNoNeedExtraSize ( // MapMask.Bits.Nx =3D 0; PageTableBufferSize =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, NULL, &Pag= eTableBufferSize, 0, (UINT64)SIZE_4KB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, NULL, &Pag= eTableBufferSize, 0, (UINT64)SIZE_4KB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); UT_ASSERT_EQUAL (PageTableBufferSize, 0); TestStatus =3D IsPageTableValid (PageTable, PagingMode); @@ -164,7 +164,7 @@ TestCaseWhichNoNeedExtraSize ( MapAttribute.Bits.Accessed =3D 1; MapMask.Bits.Accessed =3D 1; PageTableBufferSize =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, NUL= L, &PageTableBufferSize, (UINT64)SIZE_2MB, (UINT64)SIZE_2MB, &MapAttribute,= &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, NUL= L, &PageTableBufferSize, (UINT64)SIZE_2MB, (UINT64)SIZE_2MB, &MapAttribute,= &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); UT_ASSERT_EQUAL (PageTableBufferSize, 0); TestStatus =3D IsPageTableValid (PageTable, PagingMode); @@ -217,10 +217,10 @@ TestCase1Gmapto4K ( MapAttribute.Bits.Present =3D 1; MapMask.Bits.Present =3D 1; MapMask.Uint64 =3D MAX_UINT64; - Status =3D PageTableMap (&PageTable, PagingMode, Buff= er, &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapM= ask); + Status =3D PageTableMap (&PageTable, PagingMode, Buff= er, &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapM= ask, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); =20 // @@ -281,11 +281,11 @@ TestCaseManualChangeReadWrite ( // // Create Page table to cover [0,2G], with ReadWrite =3D 1 // - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); BackupPageTableBufferSize =3D PageTableBufferSize; Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTabl= eBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buff= er, &PageTableBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buff= er, &PageTableBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); IsPageTableValid (PageTable, PagingMode); =20 @@ -331,7 +331,7 @@ TestCaseManualChangeReadWrite ( // Call library to change ReadWrite to 0 for [0,2M] // MapAttribute.Bits.ReadWrite =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, NU= LL, &PageTableBufferSize, 0, SIZE_2MB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, NU= LL, &PageTableBufferSize, 0, SIZE_2MB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); IsPageTableValid (PageTable, PagingMode); MapCount =3D 0; @@ -360,7 +360,7 @@ TestCaseManualChangeReadWrite ( // MapAttribute.Bits.ReadWrite =3D 1; PageTableBufferSize =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, NU= LL, &PageTableBufferSize, 0, SIZE_2MB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, NU= LL, &PageTableBufferSize, 0, SIZE_2MB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); IsPageTableValid (PageTable, PagingMode); MapCount =3D 0; @@ -434,10 +434,10 @@ TestCaseManualSizeNotMatch ( // // Create Page table to cover [2M-4K, 4M], with ReadWrite =3D 1 // - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, SIZE_2MB - SIZE_4KB, SIZE_4KB + SIZE_2MB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, SIZE_2MB - SIZE_4KB, SIZE_4KB + SIZE_2MB, &MapAttribute, &MapMask, N= ULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, SIZE_2MB - SIZE_4KB, SIZE_4KB + SIZE_2MB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, SIZE_2MB - SIZE_4KB, SIZE_4KB + SIZE_2MB, &MapAttribute, &MapMask, N= ULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); IsPageTableValid (PageTable, PagingMode); =20 @@ -493,7 +493,7 @@ TestCaseManualSizeNotMatch ( MapAttribute.Bits.ReadWrite =3D 1; PageTableBufferSize =3D 0; MapAttribute.Bits.PageTableBaseAddress =3D (SIZE_2MB - SIZE_4KB) >> 12; - Status =3D PageTableMap (&PageTable, Pag= ingMode, Buffer, &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB * 2, &= MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, Pag= ingMode, Buffer, &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB * 2, &= MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); return UNIT_TEST_PASSED; } @@ -540,10 +540,10 @@ TestCaseManualNotMergeEntry ( // // Create Page table to cover [0,4M], and [4M, 1G] is not present // - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_2MB * 2, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_2MB * 2, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_2MB * 2, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_2MB * 2, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); TestStatus =3D IsPageTableValid (PageTable, PagingMode); if (TestStatus !=3D UNIT_TEST_PASSED) { @@ -555,7 +555,7 @@ TestCaseManualNotMergeEntry ( // It looks like the chioce is not bad, but sometime, we need to keep so= me small entry // PageTableBufferSize =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, NULL, &Pag= eTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, NULL, &Pag= eTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapMask, NUL= L); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); TestStatus =3D IsPageTableValid (PageTable, PagingMode); if (TestStatus !=3D UNIT_TEST_PASSED) { @@ -564,7 +564,7 @@ TestCaseManualNotMergeEntry ( =20 MapAttribute.Bits.Accessed =3D 1; PageTableBufferSize =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, NUL= L, &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_2MB, &MapAttribute, &MapMa= sk); + Status =3D PageTableMap (&PageTable, PagingMode, NUL= L, &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_2MB, &MapAttribute, &MapMa= sk, NULL); // // If it didn't use a big 1G entry to cover whole range, only change [0,= 2M] for some attribute won't need extra memory // @@ -619,10 +619,10 @@ TestCaseManualChangeNx ( // // Create Page table to cover [0,2G], with Nx =3D 0 // - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_1GB * 2, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_1GB * 2, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_1GB * 2, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_1GB * 2, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); TestStatus =3D IsPageTableValid (PageTable, PagingMode); if (TestStatus !=3D UNIT_TEST_PASSED) { @@ -666,7 +666,7 @@ TestCaseManualChangeNx ( // // Call library to change Nx to 0 for [0,1G] // - Status =3D PageTableMap (&PageTable, PagingMode, NULL, &PageTableBufferS= ize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, NULL, &PageTableBufferS= ize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); TestStatus =3D IsPageTableValid (PageTable, PagingMode); if (TestStatus !=3D UNIT_TEST_PASSED) { @@ -741,30 +741,30 @@ TestCaseToCheckMapMaskAndAttr ( // // Create Page table to cover [0, 2G]. All fields of MapMask should be s= et. // - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); MapMask.Uint64 =3D MAX_UINT64; - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTa= bleBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTa= bleBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); =20 // // Update Page table to set [2G - 8K, 2G] from present to non-present. A= ll fields of MapMask except present should not be set. // PageTableBufferSize =3D 0; - MapAttribute.Uint64 =3D SIZE_2GB - SIZE_8KB; + MapAttribute.Uint64 =3D 0; MapMask.Uint64 =3D 0; MapMask.Bits.Present =3D 1; MapMask.Bits.ReadWrite =3D 1; - Status =3D PageTableMap (&PageTable, PagingMode, Buffer,= &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMa= sk); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer,= &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMa= sk, NULL); UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); MapMask.Bits.ReadWrite =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, Buffer,= &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMa= sk); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer,= &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMa= sk, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); =20 // @@ -774,11 +774,11 @@ TestCaseToCheckMapMaskAndAttr ( MapAttribute.Uint64 =3D 0; MapMask.Uint64 =3D 0; MapMask.Bits.Present =3D 1; - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &= PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMask= ); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &= PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMask= , NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); MapAttribute.Bits.ReadWrite =3D 1; MapMask.Bits.ReadWrite =3D 1; - Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &= MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &= MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); =20 // @@ -791,10 +791,10 @@ TestCaseToCheckMapMaskAndAttr ( MapMask.Uint64 =3D 0; MapMask.Bits.ReadWrite =3D 1; MapMask.Bits.Present =3D 1; - Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &= MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &= MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); MapMask.Uint64 =3D MAX_UINT64; - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTa= bleBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTa= bleBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMask, NULL= ); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); =20 MapCount =3D 0; diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c index 121cc4f2b2..e603dba269 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c @@ -699,7 +699,8 @@ SingleMapEntryTest ( LastMapEntry->LinearAddress, LastMapEntry->Length, &LastMapEntry->Attribute, - &LastMapEntry->Mask + &LastMapEntry->Mask, + NULL ); =20 Attribute =3D &LastMapEntry->Attribute; @@ -759,7 +760,8 @@ SingleMapEntryTest ( LastMapEntry->LinearAddress, LastMapEntry->Length, &LastMapEntry->Attribute, - &LastMapEntry->Mask + &LastMapEntry->Mask, + NULL ); } =20 diff --git a/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c b/UefiCpuPk= g/Library/MpInitLib/X64/CreatePageTable.c index f20068152b..da8729e752 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c +++ b/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c @@ -57,7 +57,8 @@ CreatePageTable ( Address, Length, &MapAttribute, - &MapMask + &MapMask, + NULL ); ASSERT (Status =3D=3D EFI_BUFFER_TOO_SMALL); DEBUG ((DEBUG_INFO, "AP Page Table Buffer Size =3D %x\n", PageTableBuffe= rSize)); @@ -72,7 +73,8 @@ CreatePageTable ( Address, Length, &MapAttribute, - &MapMask + &MapMask, + NULL ); ASSERT_EFI_ERROR (Status); return PageTable; --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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