From nobody Fri Mar 29 15:13:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101726+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101726+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679637641; cv=none; d=zohomail.com; s=zohoarc; b=gHjIIa3EoT+b5nWqFBP3Im0NO4u0Em6MQxDmDbdl3WB0+4snpNcZH5DfmRNdUI6QvSxzVtku4rMO5WQZ25E+JNuGd/4TMyrPDR+/XyDJeCGO1MWBpUFyrHFk0Pm0va+7CGKf03qwmCS+wgrVCZKCf5CC6gzyVrxOhr7KhMPSXx0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679637641; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=LY7HkvnCBeA6U3XoKHon75L36mb7goDRAWpysrmEfbE=; b=X/ZAGPazl2rnBTk7D2smg0uN1hNo7g6QZNjmNHy9uN0lhJp140p84hOfmWs5kuJn4wqZV+67G6Rhjh4oNJyEMStsOm252wZrnO0p8MnjlA3F3VLT09Y36wJuawY2CR+yF5S04sl3PngPH8cHNNV/2m3NzPbQl9PzeRxwI4hTLUM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101726+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679637641427553.7659153409974; Thu, 23 Mar 2023 23:00:41 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id PM3dYY1788612xnRHZWKrKRe; Thu, 23 Mar 2023 23:00:41 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web10.95185.1679637638981244777 for ; Thu, 23 Mar 2023 23:00:39 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="320093831" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="320093831" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:00:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="1012122014" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="1012122014" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:00:31 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V5 01/22] UefiCpuPkg/CpuPageTableLib: Remove unneeded 'if' condition Date: Fri, 24 Mar 2023 13:59:59 +0800 Message-Id: <20230324060020.940-2-dun.tan@intel.com> In-Reply-To: <20230324060020.940-1-dun.tan@intel.com> References: <20230324060020.940-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: pHqoRl1Mz0zTFDZOJuAbemsXx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679637641; bh=Fz1u7Tglzl6cy4B/o+XHllcenORq8A2CLi5yFTDhn9M=; h=Cc:Date:From:Reply-To:Subject:To; b=dSqpziA0xdFJ/MXYSY9WSO3F65SP+6hFu/xRMqt7G1kxynN1QA32x+7OdqM+hIk2Zu8 pqpof360EfOL7Iz2kcJ6AE9ZJSC60eWtJlcW47RGhfzU+LMQuQOiyDHEJYyUykol0zPhJ A+bmvmyPVBmcZbiG6rzPaNuPCniTRA7p0uE= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679637641842100003 Content-Type: text/plain; charset="utf-8" Remove unneeded 'if' condition in CpuPageTableLib code. The deleted code is in the code branch for present non-leaf parent entry. So the 'if' check for (ParentPagingEntry->Pnle.Bits.Present =3D=3D 0) is always FALSE. Signed-off-by: Dun Tan Cc: Eric Dong Reviewed-by: Ray Ni Cc: Rahul Kumar Tested-by: Gerd Hoffmann Acked-by: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 37713ec659..52535e5a8d 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -1,7 +1,7 @@ /** @file This library implements CpuPageTableLib that are generic for IA32 family= CPU. =20 - Copyright (c) 2022, Intel Corporation. All rights reserved.
+ Copyright (c) 2022 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -375,15 +375,6 @@ PageTableLibMapInLevel ( // we need to change PDPTE[0].ReadWrite =3D 1 and let all P= DE[0-255].ReadWrite =3D 0 in this step. // when PDPTE[0].Nx =3D 1 but caller wants to map [0-2MB] as Nx = =3D 0 (PDT[0].Nx =3D 0) // we need to change PDPTE[0].Nx =3D 0 and let all PDE[0-25= 5].Nx =3D 1 in this step. - if ((ParentPagingEntry->Pnle.Bits.Present =3D=3D 0) && (Mask->Bits.Pre= sent =3D=3D 1) && (Attribute->Bits.Present =3D=3D 1)) { - if (Modify) { - ParentPagingEntry->Pnle.Bits.Present =3D 1; - } - - ChildAttribute.Bits.Present =3D 0; - ChildMask.Bits.Present =3D 1; - } - if ((ParentPagingEntry->Pnle.Bits.ReadWrite =3D=3D 0) && (Mask->Bits.R= eadWrite =3D=3D 1) && (Attribute->Bits.ReadWrite =3D=3D 1)) { if (Modify) { ParentPagingEntry->Pnle.Bits.ReadWrite =3D 1; --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101726): https://edk2.groups.io/g/devel/message/101726 Mute This Topic: https://groups.io/mt/97818221/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 15:13:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101729+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101729+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679637642; cv=none; d=zohomail.com; s=zohoarc; b=N2NSbvTaa29Ar74+0xsIpjgadmlezsFe8XlL+q5wfpbM0XEE4NRZI+pGMLyBkiOUjHPUGUj+G9BpR0+CrQLBaDlPopvYx0Oni4AAZjDNGaLYP8Fk8kdimtc0IUU4g5jk9b0BkDF2gP8miwLde6hcYrqjWtsy+/vj5QkgMlblyCA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679637642; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=inrirUoagfOUhvh0xBkuD3xZf5O635FGUCx1o093tu8=; b=S+AebMzYzDRA0KhmTO7IZO3qgVGpEj41nBjm+7XFVRgDSk9ymMvs1h7I7k3MTZCrQ+HzKnGZuCSMxfHy8Gbs5KSm0AFODMhr7bjvCpHxeYKDsjrBi8sBfC42Rge8tSS5/t+In7BegkKpMj/HTyeffVVnf06g/BmSuw+v2QnVuBM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101729+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679637642404266.2799170423831; Thu, 23 Mar 2023 23:00:42 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id Owa9YY1788612xguCaUfKSGA; Thu, 23 Mar 2023 23:00:42 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web10.95186.1679637639945874708 for ; Thu, 23 Mar 2023 23:00:39 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="320093851" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="320093851" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:00:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="1012122022" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="1012122022" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:00:33 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V5 02/22] UefiCpuPkg/CpuPageTableLib: Add check for input Length Date: Fri, 24 Mar 2023 14:00:00 +0800 Message-Id: <20230324060020.940-3-dun.tan@intel.com> In-Reply-To: <20230324060020.940-1-dun.tan@intel.com> References: <20230324060020.940-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: 5OPVoSzsK8HPMSKscvVZuduex1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679637642; bh=DZFEDfCPfobQ3S/iuQaNctJdb0wJ6Sw1Wva3/enxaV0=; h=Cc:Date:From:Reply-To:Subject:To; b=oD0Q0i5DuVhI2IXK0BaMeCGFxmDPr9E+Y7L1GWN8ayoqIQokTWhUkw0GvoXKrMkrRvl wxqeOM3aGw9NtXNfyEsG10+27J0ulGiDLI5+Ep3A5sTGf6yHY+F9rYaTVd9GnWf+tNxE6 eOk7mt+xQe3v08BUeq/TyvBB56THLxjz78I= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679637643834100019 Content-Type: text/plain; charset="utf-8" Add check for input Length in PageTableMap (). Return RETURN_SUCCESS when input Length is 0. Signed-off-by: Dun Tan Cc: Eric Dong Reviewed-by: Ray Ni Cc: Rahul Kumar Tested-by: Gerd Hoffmann Acked-by: Gerd Hoffmann --- UefiCpuPkg/Include/Library/CpuPageTableLib.h | 4 ++-- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 6 +++++- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/UefiCpuPkg/Include/Library/CpuPageTableLib.h b/UefiCpuPkg/Incl= ude/Library/CpuPageTableLib.h index 2dc9b7d18e..5f44ece548 100644 --- a/UefiCpuPkg/Include/Library/CpuPageTableLib.h +++ b/UefiCpuPkg/Include/Library/CpuPageTableLib.h @@ -1,7 +1,7 @@ /** @file Public include file for PageTableLib library. =20 - Copyright (c) 2022, Intel Corporation. All rights reserved.
+ Copyright (c) 2022 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -81,7 +81,7 @@ typedef enum { @retval RETURN_BUFFER_TOO_SMALL The buffer is too small for page table= creation/updating. BufferSize is updated to indicate the = expected buffer size. Caller may still get RETURN_BUFFER_TOO= _SMALL with the new BufferSize. - @retval RETURN_SUCCESS PageTable is created/updated successfu= lly. + @retval RETURN_SUCCESS PageTable is created/updated successfu= lly or the input Length is 0. **/ RETURN_STATUS EFIAPI diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 52535e5a8d..218068a3e1 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -544,7 +544,7 @@ PageTableLibMapInLevel ( @retval RETURN_BUFFER_TOO_SMALL The buffer is too small for page table= creation/updating. BufferSize is updated to indicate the = expected buffer size. Caller may still get RETURN_BUFFER_TOO= _SMALL with the new BufferSize. - @retval RETURN_SUCCESS PageTable is created/updated successfu= lly. + @retval RETURN_SUCCESS PageTable is created/updated successfu= lly or the input Length is 0. **/ RETURN_STATUS EFIAPI @@ -567,6 +567,10 @@ PageTableMap ( IA32_PAGE_LEVEL MaxLeafLevel; IA32_MAP_ATTRIBUTE ParentAttribute; =20 + if (Length =3D=3D 0) { + return RETURN_SUCCESS; + } + if ((PagingMode =3D=3D Paging32bit) || (PagingMode =3D=3D PagingPae) || = (PagingMode >=3D PagingModeMax)) { // // 32bit paging is never supported. --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101729): https://edk2.groups.io/g/devel/message/101729 Mute This Topic: https://groups.io/mt/97818224/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 15:13:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101727+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101727+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679637641; cv=none; d=zohomail.com; s=zohoarc; b=leznuc3h2CFkhwshAZoNgJ64aHB352S8im4LYRArBz5DdrcVcOTvjTLzprMlJ7fO+OWVZ8POJdLXM91kPiGcekSRYHHtL9M+f865VpCSVws7mKeDP3DteI+HYdh2UUxS8DJ5a5vmMsZ3dx3gHxny8TKH8JdjMo223ggmlJUqc3E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679637641; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=FfeoTtuWfSRTgKNpl4qz5KiDEdY5pYy4+c36EXfEQ+U=; b=k+9cQ+DOETI2a2DyTTwznZ50t22cSxH1KMjzIcJ0IQIOVgEprgUER6qa92Y7FqCpCd7BnhuubgxE7Tk3liWi3106GhVSNRgWdubYw9brsumaKX/Dw+PDIa/zvW36PX0MnOEdHRtDp7xBGfitZ6XoOEDH3k//a9AqsKiZmMd1lWs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101727+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679637641052114.24722913272183; Thu, 23 Mar 2023 23:00:41 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id ca4wYY1788612xV1TSqZeK9t; Thu, 23 Mar 2023 23:00:40 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web10.95185.1679637638981244777 for ; Thu, 23 Mar 2023 23:00:39 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="320093864" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="320093864" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:00:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="1012122039" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="1012122039" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:00:35 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V5 03/22] UefiCpuPkg/CpuPageTableLib:Initialize some LocalVariable at beginning Date: Fri, 24 Mar 2023 14:00:01 +0800 Message-Id: <20230324060020.940-4-dun.tan@intel.com> In-Reply-To: <20230324060020.940-1-dun.tan@intel.com> References: <20230324060020.940-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: cmJBIEkudLDpbeTsigGyTrxYx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679637640; bh=S8zxabAUlL1uGtzP07ulPTpq5z6MVsR1igJvAXieI+A=; h=Cc:Date:From:Reply-To:Subject:To; b=pKbCM7QJFjyzG7hYIVPoMmwWOTnIeLiM9e6PEZAbTcO+0Qcx+P6g9bsIgl4ra52Wi00 aNK+XNfyMkdNNkb3C26XrZKFI2xylM6uyaAjqjBJNFRgfAiMGQuKffhO+90M6u0hlOlTq B8yTp7w0swrcKbAshefNGGLmaWouBbVcpGs= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679637641845100005 Content-Type: text/plain; charset="utf-8" Move some local variable initialization to the beginning of the function. Also delete duplicated calculation for RegionLength. Signed-off-by: Dun Tan Cc: Eric Dong Reviewed-by: Ray Ni Cc: Rahul Kumar Tested-by: Gerd Hoffmann Acked-by: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 21 ++++++++++++----= ----- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 218068a3e1..127b65183f 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -258,6 +258,7 @@ PageTableLibMapInLevel ( UINTN BitStart; UINTN Index; IA32_PAGING_ENTRY *PagingEntry; + UINTN PagingEntryIndex; IA32_PAGING_ENTRY *CurrentPagingEntry; UINT64 RegionLength; UINT64 SubLength; @@ -288,6 +289,14 @@ PageTableLibMapInLevel ( LocalParentAttribute.Uint64 =3D ParentAttribute->Uint64; ParentAttribute =3D &LocalParentAttribute; =20 + // + // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 << 2= 1) or 4K (1 << 12). + // + BitStart =3D 12 + (Level - 1) * 9; + PagingEntryIndex =3D (UINTN)BitFieldRead64 (LinearAddress + Offset, BitS= tart, BitStart + 9 - 1); + RegionLength =3D REGION_LENGTH (Level); + RegionMask =3D RegionLength - 1; + // // ParentPagingEntry ONLY is deferenced for checking Present and MustBeO= ne bits // when Modify is FALSE. @@ -353,8 +362,7 @@ PageTableLibMapInLevel ( // PageTableLibSetPnle (&ParentPagingEntry->Pnle, &NopAttribute, &AllOn= eMask); =20 - RegionLength =3D REGION_LENGTH (Level); - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BA= SE_ADDRESS (&ParentPagingEntry->Pnle); + PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BAS= E_ADDRESS (&ParentPagingEntry->Pnle); for (SubOffset =3D 0, Index =3D 0; Index < 512; Index++) { PagingEntry[Index].Uint64 =3D OneOfPagingEntry.Uint64 + SubOffset; SubOffset +=3D RegionLength; @@ -425,15 +433,10 @@ PageTableLibMapInLevel ( } =20 // - // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 << 2= 1) or 4K (1 << 12). // RegionStart: points to the linear address that's aligned on RegionLe= ngth and lower than (LinearAddress + Offset). // - BitStart =3D 12 + (Level - 1) * 9; - Index =3D (UINTN)BitFieldRead64 (LinearAddress + Offset, BitStart= , BitStart + 9 - 1); - RegionLength =3D LShiftU64 (1, BitStart); - RegionMask =3D RegionLength - 1; - RegionStart =3D (LinearAddress + Offset) & ~RegionMask; - + Index =3D PagingEntryIndex; + RegionStart =3D (LinearAddress + Offset) & ~RegionMask; ParentAttribute->Uint64 =3D PageTableLibGetPnleMapAttribute (&ParentPagi= ngEntry->Pnle, ParentAttribute); =20 // --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101727): https://edk2.groups.io/g/devel/message/101727 Mute This Topic: https://groups.io/mt/97818222/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 15:13:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101728+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101728+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679637641; cv=none; d=zohomail.com; s=zohoarc; b=Tmlqit52CoSMaI12CTiWBa6tJY9B6LOMZhMmGMq5gtZy80r1p0xCTDcEkJUCRXAo5b1YMs1kpkj6nymiAnWNiHpA9gmZv7wojSfaedKsF8OyyTRZpGlxwPUM8QN0D3VVJmEH6jxNmtC4POchG8YhKe8FosxFwB7I1bmigQ+Mf1U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679637641; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=VdKt9+SAHSBokfEVDgOsLSTUp3894b8n6+pVEKKO46k=; b=UScQ81dtbzjftRI1U3+1wF/OIyAZ67NJ5e4xWS08VInDl/qrPAnWnXinNsV3DG9Dfjl807JlsGt2Wc6bZV7YFaG2B1PmsC/54nkZWRoBjJcJFZd2JU3a2/QpUQnrzcPGzSMnpSYfQCmmnrhSIFEC4H67yEMooBtW/jrW7LPY4IM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101728+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679637641942528.8394121673873; Thu, 23 Mar 2023 23:00:41 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id vIvZYY1788612xrlHwAfG4jU; Thu, 23 Mar 2023 23:00:41 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web10.95185.1679637638981244777 for ; Thu, 23 Mar 2023 23:00:39 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="320093873" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="320093873" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:00:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="1012122049" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="1012122049" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:00:37 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V5 04/22] UefiCpuPkg/CpuPageTableLib: Fix the non-1:1 mapping issue Date: Fri, 24 Mar 2023 14:00:02 +0800 Message-Id: <20230324060020.940-5-dun.tan@intel.com> In-Reply-To: <20230324060020.940-1-dun.tan@intel.com> References: <20230324060020.940-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: aqriuCBwfxJI4sWH9NEQFWQMx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679637641; bh=+4vahiO+ca9DYTe8LuiS4a+11tlkZa4G/DNRa/CGvLQ=; h=Cc:Date:From:Reply-To:Subject:To; b=LFlY+LWcSU94AzqS4tkRtSI7Hw7kg7VweRny8f/mjbwu3DGRhcJHOmoEhUVtpgBEeQf 37QRH3aBAl24ZVmTqEzejdExEonSZWZoL5WZh4qSLlq5PMl3dqS8iduPg4UOYOJ0unTwy QdVnCoDb6A/orr5OBxb3ePnrKByDoTBEboE= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679637643827100016 Content-Type: text/plain; charset="utf-8" In previous code logic, when splitting a leaf parent entry to smaller granularity child page table, if the parent entry Attribute&Mask(without PageTableBaseAddress field) is equal to the input attribute&mask(without PageTableBaseAddress field), the split process won't happen. This may lead to failure in non-1:1 mapping. For example, there is a page table in which [0, 1G] is mapped(Lv4[0] ,Lv3[0,0], a non-leaf level4 entry and a leaf level3 entry). And we want to remap [0, 2M] linear address range to [1G, 1G + 2M] with the same attibute. The expected behaviour should be: split Lv3[0,0] entry into 512 level2 entries and remap the first level2 entry to cover [0, 2M]. But the split won't happen in previous code since PageTableBaseAddress of input Attribute is not checked. So, when checking if a leaf parent entry needs to be splitted, we should also check if PageTableBaseAddress calculated by parent entry is equal to the value caculated by input attribute. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Tested-by: Gerd Hoffmann Acked-by: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 127b65183f..6ab2961790 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -274,6 +274,8 @@ PageTableLibMapInLevel ( IA32_MAP_ATTRIBUTE ChildMask; IA32_MAP_ATTRIBUTE CurrentMask; IA32_MAP_ATTRIBUTE LocalParentAttribute; + UINT64 PhysicalAddrInEntry; + UINT64 PhysicalAddrInAttr; =20 ASSERT (Level !=3D 0); ASSERT ((Attribute !=3D NULL) && (Mask !=3D NULL)); @@ -341,7 +343,15 @@ PageTableLibMapInLevel ( // This function is called when the memory length is less than the r= egion length of the parent level. // No need to split the page when the attributes equal. // - return RETURN_SUCCESS; + if (Mask->Bits.PageTableBaseAddress =3D=3D 0) { + return RETURN_SUCCESS; + } + + PhysicalAddrInEntry =3D IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (= &PleBAttribute) + (UINT64)PagingEntryIndex * RegionLength; + PhysicalAddrInAttr =3D (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS = (Attribute) + Offset) & (~RegionMask); + if (PhysicalAddrInEntry =3D=3D PhysicalAddrInAttr) { + return RETURN_SUCCESS; + } } =20 ASSERT (Buffer =3D=3D NULL || *BufferSize >=3D SIZE_4KB); --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101728): https://edk2.groups.io/g/devel/message/101728 Mute This Topic: https://groups.io/mt/97818223/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 15:13:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101730+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101730+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679637642; cv=none; d=zohomail.com; s=zohoarc; b=WIlseng+9EbqWDuQGt0DXjmWwne0dDzGUSX1748kHr3ByxIbPCrcsvWECPssz2bMsIDPax6lB17mBb5sBBMAsZrFkDuGPnVITc3XxKiH9xqYCPB7dRuT7Ob5gxYwzf26eK+v/o1hHrXOGWKQO/X9/c8NnP0u1GYMV00UI4W3K+A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679637642; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=L1k2Nzn29+uAzpRE7jzBneopcplKKdddUPdcknRZkEk=; b=ON/Ufpu45oBwtQCo74oaUZ3gUCzdsz5uYmVipn3y2tca69TQXMdxTI0LwyWiovFbQi4OXNfBHUnvBwsevZNxTKtDvGDrJ2LvruvVxtrZySfFS7zyAxqUs7H0lq9wn2/10x8kfzctEapmQdbag3GYnAkTmjLwEdMaLsImvPUkQH0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101730+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 167963764279610.881928043483299; Thu, 23 Mar 2023 23:00:42 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id c6rxYY1788612xbhAY1PxYyU; Thu, 23 Mar 2023 23:00:42 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.94534.1679637641374533517 for ; Thu, 23 Mar 2023 23:00:41 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="320093898" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="320093898" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:00:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="1012122054" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="1012122054" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:00:39 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V5 05/22] UefiCpuPkg/CpuPageTableLib:Clear PageSize bit(Bit7) for non-leaf Date: Fri, 24 Mar 2023 14:00:03 +0800 Message-Id: <20230324060020.940-6-dun.tan@intel.com> In-Reply-To: <20230324060020.940-1-dun.tan@intel.com> References: <20230324060020.940-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: 1orlQrsmt3x6GqCsGUweQECHx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679637642; bh=qs3I95ZVceRM/+HhthFex621pXj2/F2Xo2AFQsn2g1c=; h=Cc:Date:From:Reply-To:Subject:To; b=LWJUaBYRD7YGrq/RhlJn4kUhcagW3Oe9zgVi/aiqorAv0FYfAzz6nx0XHgaR6FdJ0De d5qjOzXDUUbxrRCXZRQm+uQvOBvGVD96sP3EH4NSUlTfjusVIZ6eVt1ZBMtuf1dxLFSRq q1ncUVhGfeV+xd/BzkxEpVEnLSLtUQvC7pU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679637643831100018 Content-Type: text/plain; charset="utf-8" Clear PageSize bit(Bit7) for non-leaf entry in PageTableLibSetPnle. This function is used to set non-leaf entry attributes so it should make sure that the PageSize bit of the entry should be 0. Signed-off-by: Dun Tan Cc: Eric Dong Reviewed-by: Ray Ni Cc: Rahul Kumar Tested-by: Gerd Hoffmann Acked-by: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 6ab2961790..a242710afa 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -202,7 +202,8 @@ PageTableLibSetPnle ( Pnle->Bits.Nx =3D Attribute->Bits.Nx; } =20 - Pnle->Bits.Accessed =3D 0; + Pnle->Bits.Accessed =3D 0; + Pnle->Bits.MustBeZero =3D 0; =20 // // Set the attributes (WT, CD, A) to 0. --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101730): https://edk2.groups.io/g/devel/message/101730 Mute This Topic: https://groups.io/mt/97818226/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 15:13:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101731+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101731+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679637644; cv=none; d=zohomail.com; s=zohoarc; b=EZy6BsuK8tiza4G8YXGJNuN89o5AFNu+pWd4wyphlMAutaABq7sI3EymcOB6bOYUt2QOjdrGI0lJhQ+KR9+J0pQhCtpWAml5ZWtSuMFl1uNF9uCXuPv4kUslfj8aHfLdNjt6w5OaC9XnUZ+3F+lLgUAJTy+Myyp+3EMI1+tyR1Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679637644; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=QWA8jCNRB0jvoskJ07+udszJex6yCdtKFTVEItjTkmo=; b=J8nkOpa1DJzNzQWKuvsD6hSoCs0CJL+VqdORwnR4AZn2GMQRzgW2zgE1RoBRv9jeRJ6xtoF1n13+xypo/QJ5gJdTSbziq49JquS3iarQRsm3/IbNee8bBhvT4416vOMoAvbLEyqvIdR/PhutnMGJeGbGrovxGLy1iLbalkkJ/IQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101731+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679637644128595.7764355576036; Thu, 23 Mar 2023 23:00:44 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id kg7BYY1788612xR8Y2El1AWs; Thu, 23 Mar 2023 23:00:43 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.94534.1679637641374533517 for ; Thu, 23 Mar 2023 23:00:43 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="320093904" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="320093904" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:00:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="1012122059" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="1012122059" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:00:41 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V5 06/22] UefiCpuPkg/CpuPageTableLib: Fix issue when splitting leaf entry Date: Fri, 24 Mar 2023 14:00:04 +0800 Message-Id: <20230324060020.940-7-dun.tan@intel.com> In-Reply-To: <20230324060020.940-1-dun.tan@intel.com> References: <20230324060020.940-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: uEbPbjfZSv2j8Ux72v7NPTAmx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679637643; bh=c7tVs2FOSULm+5Ix6qRLwCQpM3EjwpBgEGEIDnirqFM=; h=Cc:Date:From:Reply-To:Subject:To; b=LE1o9qQ9zILQ0lhmgF+eZf67W81u/pZGBmaUwQixR6SVwdoZ8oFXolFaygBqFMy7YYQ 5zTtM5NZsDEva38p9etU64TNpRucyH79gF4nQ4Ibn3kjUQzq7r+bxRNINTr54jVSb9FKT Hl7bgMyJk85XJb5NtA+Vw7XpxG3XyBLHRx8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679637649370100002 Content-Type: text/plain; charset="utf-8" When splitting leaf parent entry to smaller granularity, create child page table before modifing parent entry. In previous code logic, when splitting a leaf parent entry, parent entry will point to a null 4k memory before child page table is created in this 4k memory. When the page table to be modified is the page table in CR3, if the executed CpuPageTableLib code is in the range mapped by the modified leaf parent entry, then issue will happen. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Tested-by: Gerd Hoffmann Acked-by: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 19 +++++++++++-----= --- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index a242710afa..c87eb23248 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -363,21 +363,24 @@ PageTableLibMapInLevel ( // // Create 512 child-level entries that map to 2M/4K. // - ParentPagingEntry->Uintn =3D (UINTN)Buffer + *BufferSize; - ZeroMem ((VOID *)ParentPagingEntry->Uintn, SIZE_4KB); + PagingEntry =3D (IA32_PAGING_ENTRY *)((UINTN)Buffer + *BufferSize); + ZeroMem (PagingEntry, SIZE_4KB); + + for (SubOffset =3D 0, Index =3D 0; Index < 512; Index++) { + PagingEntry[Index].Uint64 =3D OneOfPagingEntry.Uint64 + SubOffset; + SubOffset +=3D RegionLength; + } =20 // // Set NOP attributes // Note: Should NOT inherit the attributes from the original entry b= ecause a zero RW bit // will make the entire region read-only even the child entrie= s set the RW bit. // + // Use IA32_PE_BASE_ADDRESS_MASK_40 to only get the generic attribut= e fields. + // The Pat bit(bit 12) for LEAF_ENTRY_BIG_PAGESIZE is cleared here. + // PageTableLibSetPnle (&ParentPagingEntry->Pnle, &NopAttribute, &AllOn= eMask); - - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BAS= E_ADDRESS (&ParentPagingEntry->Pnle); - for (SubOffset =3D 0, Index =3D 0; Index < 512; Index++) { - PagingEntry[Index].Uint64 =3D OneOfPagingEntry.Uint64 + SubOffset; - SubOffset +=3D RegionLength; - } + ParentPagingEntry->Uint64 =3D ((UINTN)(VOID *)PagingEntry) | (Parent= PagingEntry->Uint64 & (~IA32_PE_BASE_ADDRESS_MASK_40)); } } else { // --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101731): https://edk2.groups.io/g/devel/message/101731 Mute This Topic: https://groups.io/mt/97818227/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 15:13:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101732+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101732+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679637646; cv=none; d=zohomail.com; s=zohoarc; b=cMJtDC9rgiRLyQdTWyKgYbVu6rPBC4zBMRhdLqzb2bQYhDQVXGpx6h6s+BQ/U1+zkYPPWbmF8LNoKs+86fD+0IfSWTSWJcf6/RWzyn5U0dWdnur/i2yzAvXHmhTiwGfbSvRxPi6ieuT5cP5NF5py4tjo17KQ/xRpg+QoYPcrsvY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679637646; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=tjZrOimkFbg9g0CrGyOI0LEjKnkDrJwQccqqJml87Lk=; b=X0UuEGw6qkbmqmDOyosxzqgYKTAM7Tsvxu+2fVWvb2DADbaDBkjnol7RpTv3vhYM18hiOYMwFR0j7V7nE6OM/d8iGnEB/FnccMJG6UatIP12bxOxxxXm0qPplpglchuDT22BPDrbLFxR31ZwjTQs4BT/wk3W00hP+qj3hEgr1nE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101732+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679637646401891.019664570134; Thu, 23 Mar 2023 23:00:46 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id JGBlYY1788612xyG2N2kVwQP; Thu, 23 Mar 2023 23:00:46 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.94534.1679637641374533517 for ; Thu, 23 Mar 2023 23:00:45 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="320093912" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="320093912" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:00:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="1012122068" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="1012122068" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:00:43 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V5 07/22] UefiCpuPkg/MpInitLib: Add code to initialize MapMask Date: Fri, 24 Mar 2023 14:00:05 +0800 Message-Id: <20230324060020.940-8-dun.tan@intel.com> In-Reply-To: <20230324060020.940-1-dun.tan@intel.com> References: <20230324060020.940-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: YpNPLoXNUzp9YbVEQbPrDyNkx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679637646; bh=5IA6lgAwzgU9tWdXPEIoTKL+CafoWSZKGthRcy+Mo2c=; h=Cc:Date:From:Reply-To:Subject:To; b=tePfQFEjrDpqwxo4wnU5rGY5t3wdaHHWnMoqEOxq0/s+Xn/9uDV7zaqOakV2FVuYKks raXS/u0/5aDRdA1Xsw9OVw1AJvMJNY+gZE3FfX0Hxc10GNF5U4LoOcCYdv0IuL1iX4+mH JDE0xO/Uw3luJmuCrFlgU8XhepJXAHamaZY= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679637650484100006 Content-Type: text/plain; charset="utf-8" In function CreatePageTable(), add code to initialize MapMask to MAX_UINT64. When creating new page table or map non-present range to present, all attributes should be provided. Signed-off-by: Dun Tan Cc: Eric Dong Reviewed-by: Ray Ni Cc: Rahul Kumar Tested-by: Gerd Hoffmann Acked-by: Gerd Hoffmann --- UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c b/UefiCpuPk= g/Library/MpInitLib/X64/CreatePageTable.c index 7cf91ed9c4..f20068152b 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c +++ b/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c @@ -36,10 +36,7 @@ CreatePageTable ( MapAttribute.Uint64 =3D Address; MapAttribute.Bits.Present =3D 1; MapAttribute.Bits.ReadWrite =3D 1; - - MapMask.Bits.PageTableBaseAddress =3D 1; - MapMask.Bits.Present =3D 1; - MapMask.Bits.ReadWrite =3D 1; + MapMask.Uint64 =3D MAX_UINT64; =20 PageTable =3D 0; PageTableBufferSize =3D 0; --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101732): https://edk2.groups.io/g/devel/message/101732 Mute This Topic: https://groups.io/mt/97818229/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 15:13:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101733+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101733+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679637648; cv=none; d=zohomail.com; s=zohoarc; b=FW5ljuaeRv5qEtT3BvOpSmwCFw7cdue9JDNKPM5G5fQJeE2dUWzWxw5oHfzeoH75oiwed0kFI560bocc7nxyO/4Nc8Spc3cfTL/x9gGdyjLcpndLuchBXoVc1WWbXUABn/Tfl7F6GCKR3U03zrfesU7/fwlY6J44aveZerRJIIk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679637648; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=5AkrjaLE+vIkV+JmC2WDsVysLwK1nHXJHDeIMeLqWXw=; b=Z4IAqjDRq10nn4xRxep7O71MZogFHwjXjRg/FiC4BLQ3e10wIyS4jEv7dbuNwAMb2CRAxM+F4PmZZ0/O6Z06zJoMbvPSrswYsSk62FM/Pd+hAZ7wtBjGdfndW1kj4/YDRMi8th+wqHd4ba224RMSv5belFxMdGaTwWzRkpscOcY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101733+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679637648378995.1156931225586; Thu, 23 Mar 2023 23:00:48 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id scw5YY1788612xYOxnDYzgLR; Thu, 23 Mar 2023 23:00:48 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.94534.1679637641374533517 for ; Thu, 23 Mar 2023 23:00:47 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="320093917" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="320093917" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:00:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="1012122074" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="1012122074" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:00:45 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V5 08/22] UefiCpuPkg/CpuPageTableLib:Add check for Mask and Attr Date: Fri, 24 Mar 2023 14:00:06 +0800 Message-Id: <20230324060020.940-9-dun.tan@intel.com> In-Reply-To: <20230324060020.940-1-dun.tan@intel.com> References: <20230324060020.940-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: 8q43RxfQvfWck9vQI8dLVFzdx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679637648; bh=VQP5HLhItyJwCqSgF/xo1jzp9S+z5Dx+dOuXGJkYDS4=; h=Cc:Date:From:Reply-To:Subject:To; b=jXPTyJiehsaCG+9JEETYLM6f01gUQCchw94GmSWhItiMXdc4w6zh26P2xgQXDR7Djs4 UlZrjo1NhcV8o8Yq/QV2OXLm0r/4katSmjw4uMaJPe0FQs+tJcjK5u425YiWPo3iPtGkA +ErFN0IljT8iQUJcLo5XpE49tp5I0NnyBTM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679637650504100007 Content-Type: text/plain; charset="utf-8" For different usage, check if the combination for Mask and Attr is valid when creating or updating page table. 1.For non-present range 1.1Mask.Present is 0 but some other attributes is provided. This case is invalid. 1.2Mask.Present is 1 and Attr.Present is 0. In this case,all other attributes should not be provided. 1.3Mask.Present is 1 and Attr.Present is 1. In this case,all attributes should be provided to intialize the attribute. 2.For present range 2.1Mask.Present is 1 and Attr.Present is 0.In this case, all other attributes should not be provided. All other usage for present range is permitted. In the mentioned cases, 1.2 and 2.1 can be merged into 1 check. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Tested-by: Gerd Hoffmann Acked-by: Gerd Hoffmann Reviewed-by: Ray Ni --- UefiCpuPkg/Include/Library/CpuPageTableLib.h | 4 ++++ UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 83 ++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 86 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/Include/Library/CpuPageTableLib.h b/UefiCpuPkg/Incl= ude/Library/CpuPageTableLib.h index 5f44ece548..4ef4a8b6af 100644 --- a/UefiCpuPkg/Include/Library/CpuPageTableLib.h +++ b/UefiCpuPkg/Include/Library/CpuPageTableLib.h @@ -77,6 +77,10 @@ typedef enum { =20 @retval RETURN_UNSUPPORTED PagingMode is not supported. @retval RETURN_INVALID_PARAMETER PageTable, BufferSize, Attribute or Ma= sk is NULL. + @retval RETURN_INVALID_PARAMETER For non-present range, Mask->Bits.Pres= ent is 0 but some other attributes are provided. + @retval RETURN_INVALID_PARAMETER For non-present range, Mask->Bits.Pres= ent is 1, Attribute->Bits.Present is 1 but some other attributes are not pr= ovided. + @retval RETURN_INVALID_PARAMETER For non-present range, Mask->Bits.Pres= ent is 1, Attribute->Bits.Present is 0 but some other attributes are provid= ed. + @retval RETURN_INVALID_PARAMETER For present range, Mask->Bits.Present = is 1, Attribute->Bits.Present is 0 but some other attributes are provided. @retval RETURN_INVALID_PARAMETER *BufferSize is not multiple of 4KB. @retval RETURN_BUFFER_TOO_SMALL The buffer is too small for page table= creation/updating. BufferSize is updated to indicate the = expected buffer size. diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index c87eb23248..c0b41472ce 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -215,6 +215,44 @@ PageTableLibSetPnle ( Pnle->Bits.CacheDisabled =3D 0; } =20 +/** + Check if the combination for Attribute and Mask is valid for non-present= entry. + 1.Mask.Present is 0 but some other attributes is provided. This case sho= uld be invalid. + 2.Map non-present range to present. In this case, all attributes should = be provided. + + @param[in] Attribute The attribute of the linear address range. + @param[in] Mask The mask used for attribute to check. + + @retval RETURN_INVALID_PARAMETER For non-present range, Mask->Bits.Pres= ent is 0 but some other attributes are provided. + @retval RETURN_INVALID_PARAMETER For non-present range, Mask->Bits.Pres= ent is 1, Attribute->Bits.Present is 1 but some other attributes are not pr= ovided. + @retval RETURN_SUCCESS The combination for Attribute and Mask= is valid. +**/ +RETURN_STATUS +IsAttributesAndMaskValidForNonPresentEntry ( + IN IA32_MAP_ATTRIBUTE *Attribute, + IN IA32_MAP_ATTRIBUTE *Mask + ) +{ + if ((Mask->Bits.Present =3D=3D 1) && (Attribute->Bits.Present =3D=3D 1))= { + // + // Creating new page table or remapping non-present range to present. + // + if ((Mask->Bits.ReadWrite =3D=3D 0) || (Mask->Bits.UserSupervisor =3D= =3D 0) || (Mask->Bits.WriteThrough =3D=3D 0) || (Mask->Bits.CacheDisabled = =3D=3D 0) || + (Mask->Bits.Accessed =3D=3D 0) || (Mask->Bits.Dirty =3D=3D 0) || (= Mask->Bits.Pat =3D=3D 0) || (Mask->Bits.Global =3D=3D 0) || + (Mask->Bits.PageTableBaseAddress =3D=3D 0) || (Mask->Bits.Protecti= onKey =3D=3D 0) || (Mask->Bits.Nx =3D=3D 0)) + { + return RETURN_INVALID_PARAMETER; + } + } else if ((Mask->Bits.Present =3D=3D 0) && (Mask->Uint64 > 1)) { + // + // Only change other attributes for non-present range is not permitted. + // + return RETURN_INVALID_PARAMETER; + } + + return RETURN_SUCCESS; +} + /** Update page table to map [LinearAddress, LinearAddress + Length) with sp= ecified attribute in the specified level. =20 @@ -237,6 +275,8 @@ PageTableLibSetPnle ( when a new physical base address is se= t. @param[in] Mask The mask used for attribute. The corre= sponding field in Attribute is ignored if that in Mask is 0. =20 + @retval RETURN_INVALID_PARAMETER For non-present range, Mask->Bits.Pres= ent is 0 but some other attributes are provided. + @retval RETURN_INVALID_PARAMETER For non-present range, Mask->Bits.Pres= ent is 1, Attribute->Bits.Present is 1 but some other attributes are not pr= ovided. @retval RETURN_SUCCESS PageTable is created/updated successfu= lly. **/ RETURN_STATUS @@ -260,6 +300,7 @@ PageTableLibMapInLevel ( UINTN Index; IA32_PAGING_ENTRY *PagingEntry; UINTN PagingEntryIndex; + UINTN PagingEntryIndexEnd; IA32_PAGING_ENTRY *CurrentPagingEntry; UINT64 RegionLength; UINT64 SubLength; @@ -306,6 +347,14 @@ PageTableLibMapInLevel ( // =20 if (ParentPagingEntry->Pce.Present =3D=3D 0) { + // + // [LinearAddress, LinearAddress + Length] contains non-present range. + // + Status =3D IsAttributesAndMaskValidForNonPresentEntry (Attribute, Mask= ); + if (RETURN_ERROR (Status)) { + return Status; + } + // // The parent entry is CR3 or PML5E/PML4E/PDPTE/PDE. // It does NOT point to an existing page directory. @@ -383,6 +432,27 @@ PageTableLibMapInLevel ( ParentPagingEntry->Uint64 =3D ((UINTN)(VOID *)PagingEntry) | (Parent= PagingEntry->Uint64 & (~IA32_PE_BASE_ADDRESS_MASK_40)); } } else { + // + // If (LinearAddress + Length - 1) is not in the same ParentPagingEntr= y with (LinearAddress + Offset), then the remaining child PagingEntry + // starting from PagingEntryIndex of ParentPagingEntry is all covered = by [LinearAddress + Offset, LinearAddress + Length - 1]. + // + PagingEntryIndexEnd =3D (BitFieldRead64 (LinearAddress + Length - 1, B= itStart + 9, 63) !=3D BitFieldRead64 (LinearAddress + Offset, BitStart + 9,= 63)) ? 511 : + (UINTN)BitFieldRead64 (LinearAddress + Length - = 1, BitStart, BitStart + 9 - 1); + PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_= ADDRESS (&ParentPagingEntry->Pnle); + for (Index =3D PagingEntryIndex; Index <=3D PagingEntryIndexEnd; Index= ++) { + if (PagingEntry[Index].Pce.Present =3D=3D 0) { + // + // [LinearAddress, LinearAddress + Length] contains non-present ra= nge. + // + Status =3D IsAttributesAndMaskValidForNonPresentEntry (Attribute, = Mask); + if (RETURN_ERROR (Status)) { + return Status; + } + + break; + } + } + // // It's a non-leaf entry // @@ -430,7 +500,6 @@ PageTableLibMapInLevel ( // Update child entries to use restrictive attribute inherited fro= m parent. // e.g.: Set PDE[0-255].ReadWrite =3D 0 // - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_B= ASE_ADDRESS (&ParentPagingEntry->Pnle); for (Index =3D 0; Index < 512; Index++) { if (PagingEntry[Index].Pce.Present =3D=3D 0) { continue; @@ -557,6 +626,10 @@ PageTableLibMapInLevel ( =20 @retval RETURN_UNSUPPORTED PagingMode is not supported. @retval RETURN_INVALID_PARAMETER PageTable, BufferSize, Attribute or Ma= sk is NULL. + @retval RETURN_INVALID_PARAMETER For non-present range, Mask->Bits.Pres= ent is 0 but some other attributes are provided. + @retval RETURN_INVALID_PARAMETER For non-present range, Mask->Bits.Pres= ent is 1, Attribute->Bits.Present is 1 but some other attributes are not pr= ovided. + @retval RETURN_INVALID_PARAMETER For non-present range, Mask->Bits.Pres= ent is 1, Attribute->Bits.Present is 0 but some other attributes are provid= ed. + @retval RETURN_INVALID_PARAMETER For present range, Mask->Bits.Present = is 1, Attribute->Bits.Present is 0 but some other attributes are provided. @retval RETURN_INVALID_PARAMETER *BufferSize is not multiple of 4KB. @retval RETURN_BUFFER_TOO_SMALL The buffer is too small for page table= creation/updating. BufferSize is updated to indicate the = expected buffer size. @@ -618,6 +691,14 @@ PageTableMap ( return RETURN_INVALID_PARAMETER; } =20 + // + // If to map [LinearAddress, LinearAddress + Length] as non-present, + // all attributes except Present should not be provided. + // + if ((Attribute->Bits.Present =3D=3D 0) && (Mask->Bits.Present =3D=3D 1) = && (Mask->Uint64 > 1)) { + return RETURN_INVALID_PARAMETER; + } + MaxLeafLevel =3D (IA32_PAGE_LEVEL)(UINT8)PagingMode; MaxLevel =3D (IA32_PAGE_LEVEL)(UINT8)(PagingMode >> 8); MaxLinearAddress =3D LShiftU64 (1, 12 + MaxLevel * 9); --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101733): https://edk2.groups.io/g/devel/message/101733 Mute This Topic: https://groups.io/mt/97818230/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 15:13:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101734+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101734+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679637650; cv=none; d=zohomail.com; s=zohoarc; b=MF0RC76yXvM/GORe/Tynih9q6n9dnknx1f13dVrJzfFc4Wg1+yHoy5s/eqxkXn4N+RvndaXfYqk2YUbqLMiQ3ERmc3ZbKHUhSuIYng+8SMu357M3ANeUAxBZV0oCI7EFT7Euu/0gRu0kyuWzvUDizDf1hDjCCYIYo82UarxCcMY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679637650; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=b1eFvz79F85MZYx+JGoDykzI1iSM3eX2x3x0MiaSj4s=; b=glee8v1rlWRTcEI7SOO+Dsnenz1xme/1EEuyMx1ZMdNXmdEmXKTHHo8Dug+U7EtkqhpgLRTObMCHH5L135EsTzBGMCcV+VDcJsY4QujPz+icWcuojOwSZBC2muSJ8R2uIVGvTsQikerutHgH5nKEU6xUUOgh8BZMA2YAd8Bsrbo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101734+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679637650945830.8865425818393; Thu, 23 Mar 2023 23:00:50 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id KZ9fYY1788612xkuHCB53HBb; Thu, 23 Mar 2023 23:00:50 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.94534.1679637641374533517 for ; Thu, 23 Mar 2023 23:00:49 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="320093923" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="320093923" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:00:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="1012122077" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="1012122077" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:00:48 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V5 09/22] UefiCpuPkg/CpuPageTableLib: Add manual test to check Mask and Attr Date: Fri, 24 Mar 2023 14:00:07 +0800 Message-Id: <20230324060020.940-10-dun.tan@intel.com> In-Reply-To: <20230324060020.940-1-dun.tan@intel.com> References: <20230324060020.940-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: xdIZ5kx8GG01GBw4pIEuHblKx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679637650; bh=/xP5td9w1XHKG5jXvL8T5T/C6eJWl9jJ+XojNRdDakY=; h=Cc:Date:From:Reply-To:Subject:To; b=VxvY2ffSEMFUiimsiwzRJ8EOIl0o1x2gTpwKfzZrZmtwpSCMCpiZB8f1YPefuRnMiTu jdRXEvO5frnwa1LWGFwRpZeANSwitE0QJBDJ++T20vNvC030RHU76G83VopqwAnaCmPb7 byYJtXDXlLvTueTsCGm428GGfiwmVkJaP9Y= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679637651417100013 Content-Type: text/plain; charset="utf-8" Add manual test case to check input Mask and Attribute. The check steps are: 1.Create Page table to cover [0, 2G]. All fields of MapMask should be set. 2.Update Page table to set [2G - 8K,2G] from present to non-present. All fields of MapMask except present should not be set. 3.Still set [2G - 8K, 2G] as not present, this case is permitted. But set [2G - 8K, 2G] as RW is not permitted. 4.Update Page table to set [2G - 8K, 2G] as present and RW. All fields of MapMask should be set. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Tested-by: Gerd Hoffmann Acked-by: Gerd Hoffmann Reviewed-by: Ray Ni --- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c = | 129 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 127 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUni= tTestHost.c b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUn= itTestHost.c index 3014a03243..52fae1864a 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c @@ -1,7 +1,7 @@ /** @file Unit tests of the CpuPageTableLib instance of the CpuPageTableLib class =20 - Copyright (c) 2022, Intel Corporation. All rights reserved.
+ Copyright (c) 2022 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -697,6 +697,131 @@ TestCaseManualChangeNx ( return UNIT_TEST_PASSED; } =20 +/** + Check if the input Mask and Attribute is as expected when creating new p= age table or + updating existing page table. + + @param[in] Context [Optional] An optional parameter that enables: + 1) test-case reuse with varied parameters and + 2) test-case re-entry for Target tests that need a + reboot. This parameter is a VOID* and it is the + responsibility of the test author to ensure that = the + contents are well understood by all test cases th= at may + consume it. + + @retval UNIT_TEST_PASSED The Unit test has completed and th= e test + case was successful. + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. +**/ +UNIT_TEST_STATUS +EFIAPI +TestCaseToCheckMapMaskAndAttr ( + IN UNIT_TEST_CONTEXT Context + ) +{ + UINTN PageTable; + PAGING_MODE PagingMode; + VOID *Buffer; + UINTN PageTableBufferSize; + IA32_MAP_ATTRIBUTE MapAttribute; + IA32_MAP_ATTRIBUTE ExpectedMapAttribute; + IA32_MAP_ATTRIBUTE MapMask; + RETURN_STATUS Status; + IA32_MAP_ENTRY *Map; + UINTN MapCount; + + PagingMode =3D Paging4Level; + PageTableBufferSize =3D 0; + PageTable =3D 0; + Buffer =3D NULL; + MapAttribute.Uint64 =3D 0; + MapAttribute.Bits.Present =3D 1; + MapMask.Uint64 =3D 0; + MapMask.Bits.Present =3D 1; + // + // Create Page table to cover [0, 2G]. All fields of MapMask should be s= et. + // + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); + MapMask.Uint64 =3D MAX_UINT64; + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTa= bleBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); + Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); + + // + // Update Page table to set [2G - 8K, 2G] from present to non-present. A= ll fields of MapMask except present should not be set. + // + PageTableBufferSize =3D 0; + MapAttribute.Uint64 =3D SIZE_2GB - SIZE_8KB; + MapMask.Uint64 =3D 0; + MapMask.Bits.Present =3D 1; + MapMask.Bits.ReadWrite =3D 1; + Status =3D PageTableMap (&PageTable, PagingMode, Buffer,= &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMa= sk); + UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); + MapMask.Bits.ReadWrite =3D 0; + Status =3D PageTableMap (&PageTable, PagingMode, Buffer,= &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMa= sk); + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); + Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); + + // + // Still set [2G - 8K, 2G] as not present, this case is permitted. But s= et [2G - 8K, 2G] as RW is not permitted. + // + PageTableBufferSize =3D 0; + MapAttribute.Uint64 =3D 0; + MapMask.Uint64 =3D 0; + MapMask.Bits.Present =3D 1; + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &= PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMask= ); + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); + MapAttribute.Bits.ReadWrite =3D 1; + MapMask.Bits.ReadWrite =3D 1; + Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &= MapMask); + UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); + + // + // Update Page table to set [2G - 8K, 2G] as present and RW. All fields = of MapMask should be set. + // + PageTableBufferSize =3D 0; + MapAttribute.Uint64 =3D SIZE_2GB - SIZE_8KB; + MapAttribute.Bits.ReadWrite =3D 1; + MapAttribute.Bits.Present =3D 1; + MapMask.Uint64 =3D 0; + MapMask.Bits.ReadWrite =3D 1; + MapMask.Bits.Present =3D 1; + Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &= MapMask); + UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); + MapMask.Uint64 =3D MAX_UINT64; + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTa= bleBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMask); + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); + + MapCount =3D 0; + Status =3D PageTableParse (PageTable, PagingMode, NULL, &MapCount); + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); + Map =3D AllocatePages (EFI_SIZE_TO_PAGES (MapCount* sizeof (IA32_MAP_= ENTRY))); + Status =3D PageTableParse (PageTable, PagingMode, Map, &MapCount); + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); + + // + // There should be two ranges [0, 2G-8k] with RW =3D 0 and [2G-8k, 2G] w= ith RW =3D 1 + // + UT_ASSERT_EQUAL (MapCount, 2); + UT_ASSERT_EQUAL (Map[0].LinearAddress, 0); + UT_ASSERT_EQUAL (Map[0].Length, SIZE_2GB - SIZE_8KB); + ExpectedMapAttribute.Uint64 =3D 0; + ExpectedMapAttribute.Bits.Present =3D 1; + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, ExpectedMapAttribute.Uint64); + UT_ASSERT_EQUAL (Map[1].LinearAddress, SIZE_2GB - SIZE_8KB); + UT_ASSERT_EQUAL (Map[1].Length, SIZE_8KB); + ExpectedMapAttribute.Uint64 =3D SIZE_2GB - SIZE_8KB; + ExpectedMapAttribute.Bits.Present =3D 1; + ExpectedMapAttribute.Bits.ReadWrite =3D 1; + UT_ASSERT_EQUAL (Map[1].Attribute.Uint64, ExpectedMapAttribute.Uint64); + return UNIT_TEST_PASSED; +} + /** Initialize the unit test framework, suite, and unit tests for the sample unit tests and run the unit tests. @@ -746,7 +871,7 @@ UefiTestMain ( AddTestCase (ManualTestCase, "Check if the parent entry has different Re= adWrite attribute", "Manual Test Case5", TestCaseManualChangeReadWrite, NUL= L, NULL, NULL); AddTestCase (ManualTestCase, "Check if the parent entry has different Nx= attribute", "Manual Test Case6", TestCaseManualChangeNx, NULL, NULL, NULL); AddTestCase (ManualTestCase, "Check if the needed size is expected", "Ma= nual Test Case7", TestCaseManualSizeNotMatch, NULL, NULL, NULL); - + AddTestCase (ManualTestCase, "Check MapMask when creating new page table= or mapping not-present range", "Manual Test Case8", TestCaseToCheckMapMask= AndAttr, NULL, NULL, NULL); // // Populate the Random Test Cases. // --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101734): https://edk2.groups.io/g/devel/message/101734 Mute This Topic: https://groups.io/mt/97818231/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 15:13:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101735+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101735+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679637653; cv=none; d=zohomail.com; s=zohoarc; b=ZFubLH+HFDlG/8djnUqvS+xUU5wp9WyQI0xQkacSKxNEgWj+pMoZjD846ddJD+2kvId8r799oTqSzd+QkooJx7uU3H9N9kBRe+yLc9Vv7Rm5vs1TIQkzktNS7Z3IW/cOAKK5AsiQ9xuBPxm5mjJDX9VU89VRqYKVrD3jiYdkv9o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679637653; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=EygVtmGa4h/Rnl/7OqyLVP1JONcDlA+XlGbpyLgNvqA=; b=ZzRSlq2bk5z262PhARnbN5hnYWShii7clnDW9Ebk1sknrq4tQSqBMDQHwQIIteVcM2X9uj5UZw3WzD+NeI/mtSPjKvPGBLNVFAQ4bom8kZR/qqIBCSPMybynOmzPqaQZVvqVLgabJxKvl7pOI0Htrp3d/xDi7ST1Om5bo1fyYDY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101735+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679637653097675.6366963885998; Thu, 23 Mar 2023 23:00:53 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 2KtqYY1788612xYKG7b88rzU; Thu, 23 Mar 2023 23:00:52 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.94534.1679637641374533517 for ; Thu, 23 Mar 2023 23:00:52 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="320093935" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="320093935" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:00:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="1012122085" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="1012122085" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:00:50 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V5 10/22] UefiCpuPkg/CpuPageTableLib:Modify RandomBoolean() in RandomTest Date: Fri, 24 Mar 2023 14:00:08 +0800 Message-Id: <20230324060020.940-11-dun.tan@intel.com> In-Reply-To: <20230324060020.940-1-dun.tan@intel.com> References: <20230324060020.940-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: F4zCQcwv9qskRiI3m1Aab5xnx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679637652; bh=CRJKgPzOuoDp/xRiL3h39m33z8pBhadWcGQpu/FFIFc=; h=Cc:Date:From:Reply-To:Subject:To; b=jaGGqyM+w1HPSAkm/Ss4aW/btoCdVQyxKq/sftaEKWkX81ilsWuUxasADqOsCe7bU1Y hhWff78WsfsGVHufTPOIdCURopJfCr9hl8d2PIelWwdAr1e2s8azLEVcjFZZTiskRk50L 6gtzZQ1KXznOOjyEFHnahRVK0ZxLnFiITis= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679637655320100019 Content-Type: text/plain; charset="utf-8" Add an input parameter to control the probability of returning true. Change RandomBoolean() in RandomTest from 50% chance returning true to returning true with the percentage of input Probability. Signed-off-by: Dun Tan Cc: Eric Dong Reviewed-by: Ray Ni Cc: Rahul Kumar Tested-by: Gerd Hoffmann Acked-by: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c | 43 ++++++++++++= +++++++++---------------------- 1 file changed, 21 insertions(+), 22 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c index 97a388ca1c..52eb9daa10 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c @@ -1,7 +1,7 @@ /** @file Random test case for Unit tests of the CpuPageTableLib instance of the C= puPageTableLib class =20 - Copyright (c) 2022, Intel Corporation. All rights reserved.
+ Copyright (c) 2022 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -81,22 +81,6 @@ LocalRandomBytes ( } } =20 -/** - Return a random boolean. - - @return boolean -**/ -BOOLEAN -RandomBoolean ( - VOID - ) -{ - BOOLEAN Value; - - LocalRandomBytes ((UINT8 *)&Value, sizeof (BOOLEAN)); - return Value%2; -} - /** Return a 32bit random number. =20 @@ -139,6 +123,21 @@ Random64 ( return (UINT64)(Value % (Limit - Start + 1)) + Start; } =20 +/** + Returns true with the percentage of input Probability. + + @param[in] Probability The percentage to return true. + + @return boolean +**/ +BOOLEAN +RandomBoolean ( + UINT8 Probability + ) +{ + return ((Probability > ((UINT8)Random64 (0, 100))) ? TRUE : FALSE); +} + /** Check if the Page table entry is valid =20 @@ -178,7 +177,7 @@ ValidateAndRandomeModifyPageTablePageTableEntry ( UT_ASSERT_EQUAL ((PagingEntry->Uint64 & mValidMaskLeaf[Level].Uint64= ), PagingEntry->Uint64); } =20 - if ((RandomNumber < 100) && RandomBoolean ()) { + if ((RandomNumber < 100) && RandomBoolean (50)) { RandomNumber++; if (Level =3D=3D 1) { TempPhysicalBase =3D PagingEntry->Pte4K.Bits.PageTableBaseAddress; @@ -211,7 +210,7 @@ ValidateAndRandomeModifyPageTablePageTableEntry ( UT_ASSERT_EQUAL ((PagingEntry->Uint64 & mValidMaskNoLeaf[Level].Uint64= ), PagingEntry->Uint64); } =20 - if ((RandomNumber < 100) && RandomBoolean ()) { + if ((RandomNumber < 100) && RandomBoolean (50)) { RandomNumber++; TempPhysicalBase =3D PagingEntry->Pnle.Bits.PageTableBaseAddress; =20 @@ -299,7 +298,7 @@ GenerateSingleRandomMapEntry ( // // use AlignedTable to avoid that a random number can be very hard to be= 1G or 2M aligned // - if ((MapsIndex !=3D 0) && (RandomBoolean ())) { + if ((MapsIndex !=3D 0) && (RandomBoolean (50))) { FormerLinearAddress =3D MapEntrys->Maps[Random32 (0, (UINT32)MapsIndex= -1)].LinearAddress; if (FormerLinearAddress < 2 * (UINT64)SIZE_1GB) { FormerLinearAddressBottom =3D 0; @@ -323,7 +322,7 @@ GenerateSingleRandomMapEntry ( // MapEntrys->Maps[MapsIndex].Length =3D Random64 (0, MIN (MaxAddress - Map= Entrys->Maps[MapsIndex].LinearAddress, 10 * (UINT64)SIZE_1GB)) & AlignedTab= le[Random32 (0, ARRAY_SIZE (AlignedTable) -1)]; =20 - if ((MapsIndex !=3D 0) && (RandomBoolean ())) { + if ((MapsIndex !=3D 0) && (RandomBoolean (50))) { MapEntrys->Maps[MapsIndex].Attribute.Uint64 =3D MapEntrys->Maps[Random= 32 (0, (UINT32)MapsIndex-1)].Attribute.Uint64; MapEntrys->Maps[MapsIndex].Mask.Uint64 =3D MapEntrys->Maps[Random= 32 (0, (UINT32)MapsIndex-1)].Mask.Uint64; } else { @@ -344,7 +343,7 @@ GenerateSingleRandomMapEntry ( // Need to avoid such case when remove the Random option ONLY_ON= E_ONE_MAPPING // MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress =3D (Ra= ndom64 (0, (((UINT64)1)<<52) - 1) & AlignedTable[Random32 (0, ARRAY_SIZE (A= lignedTable) -1)])>> 12; - if (RandomBoolean ()) { + if (RandomBoolean (50)) { MapEntrys->Maps[MapsIndex].Mask.Bits.PageTableBaseAddress =3D 0; } } --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101735): https://edk2.groups.io/g/devel/message/101735 Mute This Topic: https://groups.io/mt/97818232/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 15:13:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101736+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101736+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679637656; cv=none; d=zohomail.com; s=zohoarc; b=eT8u4Pz6+hyYRZf7KG9D4Q3eAbbk8aw7IS9eiWMYjvXAv2OGW0qJfJ3ywcLIN2e2mPfPJ5Lu+X126yX2t8EeFZsbIqkWwWfLAjbEec5q8sRViMH0axO8Mr04gdb/aEso6aeFtjyCDsBYYJ5+uwbPq1nQx2GOI0IxBPYbCrQZurE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679637656; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=/abYtwJhMXZvNq2MTnsE86xyxBrXpdpwB8itOm5zA0c=; b=Ao9+cdQcp1ewd2QAgzSF7uZuOHQUmiz5FC5KautQSoa/tLidicRrzVfPHtgaOrwh+Wbsks0S/4/8m38uybvycXCVtx0ConvaSZaAt5ICeZiB4zjlei88MbPoijUYYrl9SCbAcQ84QU1xIAmYtzqNs5nQc9i9w0ftWeZgHiKr+Fo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101736+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679637656616409.8001834190784; Thu, 23 Mar 2023 23:00:56 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id MgI8YY1788612xjKO5EkTYFv; Thu, 23 Mar 2023 23:00:56 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.94534.1679637641374533517 for ; Thu, 23 Mar 2023 23:00:55 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="320093950" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="320093950" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:00:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="1012122101" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="1012122101" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:00:54 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V5 11/22] UefiCpuPkg/CpuPageTableLib: Add LastMapEntry pointer Date: Fri, 24 Mar 2023 14:00:09 +0800 Message-Id: <20230324060020.940-12-dun.tan@intel.com> In-Reply-To: <20230324060020.940-1-dun.tan@intel.com> References: <20230324060020.940-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: c5UBu0N2O7o9QzxVcP1Vhxyjx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679637656; bh=rKUSWMEWn8UI93N9ywYTk1sXyW8ysL8nwhSzVZ5fb0Q=; h=Cc:Date:From:Reply-To:Subject:To; b=qT/EdHSgfaHiVw4uP+GJpvy42roTIeb4IjTtVhc9Qz6e4omy1G/DYntaNzFQBXJSNy0 5juQHM8cbYV1HVmcOcnba61YxkVT2zWRvGJWKpebhzV60is+iNjdJH9VyNHBWMsTpk0z9 ZiKe8EXj7BO1Body7LDQeeKC3ASLLEfuys4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679637657347100022 Content-Type: text/plain; charset="utf-8" Add LastMapEntry pointer to replace MapEntrys->Maps[MapsIndex] in SingleMapEntryTest () of RandomTest. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Reviewed-by: Ray Ni --- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c | 18 ++++++++++--= ------ 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c index 52eb9daa10..612fddcee0 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c @@ -621,10 +621,12 @@ SingleMapEntryTest ( UINTN Level; UINT64 Value; UNIT_TEST_STATUS TestStatus; + MAP_ENTRY *LastMapEntry; =20 MapsIndex =3D MapEntrys->Count; =20 GenerateSingleRandomMapEntry (MaxAddress, MapEntrys); + LastMapEntry =3D &MapEntrys->Maps[MapsIndex]; =20 PageTableBufferSize =3D 0; Status =3D PageTableMap ( @@ -632,10 +634,10 @@ SingleMapEntryTest ( PagingMode, NULL, &PageTableBufferSize, - MapEntrys->Maps[MapsIndex].LinearAddress, - MapEntrys->Maps[MapsIndex].Length, - &MapEntrys->Maps[MapsIndex].Attribute, - &MapEntrys->Maps[MapsIndex].Mask + LastMapEntry->LinearAddress, + LastMapEntry->Length, + &LastMapEntry->Attribute, + &LastMapEntry->Mask ); if (PageTableBufferSize !=3D 0) { UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); @@ -651,10 +653,10 @@ SingleMapEntryTest ( PagingMode, Buffer, &PageTableBufferSize, - MapEntrys->Maps[MapsIndex].LinearAddress, - MapEntrys->Maps[MapsIndex].Length, - &MapEntrys->Maps[MapsIndex].Attribute, - &MapEntrys->Maps[MapsIndex].Mask + LastMapEntry->LinearAddress, + LastMapEntry->Length, + &LastMapEntry->Attribute, + &LastMapEntry->Mask ); } =20 --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101736): https://edk2.groups.io/g/devel/message/101736 Mute This Topic: https://groups.io/mt/97818233/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 15:13:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101737+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101737+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679637659; cv=none; d=zohomail.com; s=zohoarc; b=jDdEpp1PXedKQFwGYLe7R6nb8fh0EFjJNGUaT3i7Uds73re9CP93eM54surjNczTGKGNHjpE/Y8haOw+phnAtZ0FzWUMjNIe5GjMSj5UKU3ZJndbpTBukz7+Fg3VszvYEJ8OvaXwS3B7Ak/ON62Lle0drGQSvtwCk5i/PnhkZAQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679637659; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=XuimgCaURvsq53s8H5PsVe0DlZ7gZrVOXmXcbBdz+QY=; b=kFsGAkbqMcpcBvMiqHI4fGtqEfA663d/VXnAL0WO33wyOY986Oh2HbfBwDhrR9ll6Kw/LnBfRERGOUSqhQJETf0F+LT/4ro4XkGGHXnxt03zYowZRFRDYWpBVAJLbRu6RTXOj6lcvc1RTeILo6XbLTuZ+fiM/fg8CSX/A5TbfUg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101737+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 16796376591851005.1501597791856; Thu, 23 Mar 2023 23:00:59 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id gQGPYY1788612xxZhFBtHg2n; Thu, 23 Mar 2023 23:00:58 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.94534.1679637641374533517 for ; Thu, 23 Mar 2023 23:00:58 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="320093960" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="320093960" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:00:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="1012122125" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="1012122125" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:00:56 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann , Zhiguang Liu Subject: [edk2-devel] [Patch V5 12/22] UefiCpuPkg/CpuPageTableLib:Modify RandomTest to check Mask/Attr Date: Fri, 24 Mar 2023 14:00:10 +0800 Message-Id: <20230324060020.940-13-dun.tan@intel.com> In-Reply-To: <20230324060020.940-1-dun.tan@intel.com> References: <20230324060020.940-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: XjftKmQ4X3DtkLGpUZZthL4ux1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679637658; bh=6Ys61tuw9XP98AU9bPKNmXVqkGiRghYltdGmlLvR4Qk=; h=Cc:Date:From:Reply-To:Subject:To; b=YzVqSufDheIvuqT8GnhoksVSgqzCf3rvEIBjAxOSXxoOXfFEuw5gUNLRzFq5jLCFcEB blSOVaVohjGP0RSVcFjBri3aqbpvMIZt6QPJmJf4x5+NT0AjwsyuOUe4deaBcsjPX6G8Z sP9KYghLUFxkTrTPpf2z4fjq9GuihVy/kak= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679637661684100002 Content-Type: text/plain; charset="utf-8" Modify RandomTest to check invalid input. When creating new page table or updating exsiting page table: 1.If set [LinearAddress, LinearAddress+Length] to non-present, all other attributes should not be provided. 2.If [LinearAddress, LinearAddress+Length] contain non-present range, the Returnstatus of PageTableMap() should be InvalidParameter when: 2.1Some of attributes are not provided when mapping non-present range to present. 2.2Set any other attribute without setting the non-present range to Present. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Tested-by: Gerd Hoffmann Acked-by: Gerd Hoffmann Cc: Zhiguang Liu Reviewed-by: Ray Ni --- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c | 153 +++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++------------------------- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c | 6 +++++- 2 files changed, 133 insertions(+), 26 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c index 612fddcee0..121cc4f2b2 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c @@ -273,6 +273,27 @@ ValidateAndRandomeModifyPageTable ( return Status; } =20 +/** + Remove the last MAP_ENTRY in MapEntrys. + + @param MapEntrys Pointer to MapEntrys buffer +**/ +VOID +RemoveLastMapEntry ( + IN OUT MAP_ENTRYS *MapEntrys + ) +{ + UINTN MapsIndex; + + if (MapEntrys->Count =3D=3D 0) { + return; + } + + MapsIndex =3D MapEntrys->Count - 1; + ZeroMem (&(MapEntrys->Maps[MapsIndex]), sizeof (MAP_ENTRY)); + MapEntrys->Count =3D MapsIndex; +} + /** Generate single random map entry. The map entry can be the input of function PageTableMap @@ -327,7 +348,16 @@ GenerateSingleRandomMapEntry ( MapEntrys->Maps[MapsIndex].Mask.Uint64 =3D MapEntrys->Maps[Random= 32 (0, (UINT32)MapsIndex-1)].Mask.Uint64; } else { MapEntrys->Maps[MapsIndex].Attribute.Uint64 =3D Random64 (0, MAX_UINT6= 4) & mSupportedBit.Uint64; - MapEntrys->Maps[MapsIndex].Mask.Uint64 =3D Random64 (0, MAX_UINT6= 4) & mSupportedBit.Uint64; + if (RandomBoolean (5)) { + // + // The probability to get random Mask should be small since all bits= of a random number + // have a high probability of containing 0, which may be a invalid i= nput. + // + MapEntrys->Maps[MapsIndex].Mask.Uint64 =3D Random64 (0, MAX_UINT64) = & mSupportedBit.Uint64; + } else { + MapEntrys->Maps[MapsIndex].Mask.Uint64 =3D MAX_UINT64; + } + if (MapEntrys->Maps[MapsIndex].Mask.Bits.ProtectionKey !=3D 0) { MapEntrys->Maps[MapsIndex].Mask.Bits.ProtectionKey =3D 0xF; } @@ -337,15 +367,7 @@ GenerateSingleRandomMapEntry ( MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress =3D Map= Entrys->Maps[MapsIndex].LinearAddress >> 12; MapEntrys->Maps[MapsIndex].Mask.Bits.PageTableBaseAddress =3D 0xF= FFFFFFFFF; } else { - // - // Todo: If the mask bit for base address is zero, when dump the paget= able, every entry mapping to physical address zeor. - // This means the map count will be a large number, and impossib= le to finish in proper time. - // Need to avoid such case when remove the Random option ONLY_ON= E_ONE_MAPPING - // MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress =3D (Ra= ndom64 (0, (((UINT64)1)<<52) - 1) & AlignedTable[Random32 (0, ARRAY_SIZE (A= lignedTable) -1)])>> 12; - if (RandomBoolean (50)) { - MapEntrys->Maps[MapsIndex].Mask.Bits.PageTableBaseAddress =3D 0; - } } =20 MapEntrys->Count +=3D 1; @@ -608,25 +630,65 @@ SingleMapEntryTest ( IN UINTN InitMapCount ) { - UINTN MapsIndex; - RETURN_STATUS Status; - UINTN PageTableBufferSize; - VOID *Buffer; - IA32_MAP_ENTRY *Map; - UINTN MapCount; - UINTN Index; - UINTN KeyPointCount; - UINTN NewKeyPointCount; - UINT64 *KeyPointBuffer; - UINTN Level; - UINT64 Value; - UNIT_TEST_STATUS TestStatus; - MAP_ENTRY *LastMapEntry; - - MapsIndex =3D MapEntrys->Count; + UINTN MapsIndex; + RETURN_STATUS Status; + UINTN PageTableBufferSize; + VOID *Buffer; + IA32_MAP_ENTRY *Map; + UINTN MapCount; + UINTN Index; + UINTN KeyPointCount; + UINTN NewKeyPointCount; + UINT64 *KeyPointBuffer; + UINTN Level; + UINT64 Value; + UNIT_TEST_STATUS TestStatus; + MAP_ENTRY *LastMapEntry; + IA32_MAP_ATTRIBUTE *Mask; + IA32_MAP_ATTRIBUTE *Attribute; + UINT64 LastNotPresentRegionStart; + BOOLEAN IsNotPresent; + + MapsIndex =3D MapEntrys->Count; + MapCount =3D 0; + LastNotPresentRegionStart =3D 0; + IsNotPresent =3D FALSE; =20 GenerateSingleRandomMapEntry (MaxAddress, MapEntrys); LastMapEntry =3D &MapEntrys->Maps[MapsIndex]; + Status =3D PageTableParse (*PageTable, PagingMode, NULL, &MapCount= ); + + if (MapCount !=3D 0) { + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); + Map =3D AllocatePages (EFI_SIZE_TO_PAGES (MapCount * sizeof (IA32_MAP_= ENTRY))); + ASSERT (Map !=3D NULL); + Status =3D PageTableParse (*PageTable, PagingMode, Map, &MapCount); + } + + // + // Check if the generated MapEntrys->Maps[MapsIndex] contains not-presen= t range. + // + if (LastMapEntry->Length > 0) { + for (Index =3D 0; Index < MapCount; Index++) { + if ((LastNotPresentRegionStart < Map[Index].LinearAddress) && + (LastMapEntry->LinearAddress < Map[Index].LinearAddress) && (Las= tMapEntry->LinearAddress + LastMapEntry->Length > LastNotPresentRegionStart= )) + { + // + // MapEntrys->Maps[MapsIndex] contains not-present range in exsiti= ng page table. + // + break; + } + + LastNotPresentRegionStart =3D Map[Index].LinearAddress + Map[Index].= Length; + } + + // + // Either LastMapEntry overlaps with the not-present region in the ver= y end + // Or it overlaps with one in the middle + if (LastNotPresentRegionStart < LastMapEntry->LinearAddress + LastMapE= ntry->Length) { + IsNotPresent =3D TRUE; + } + } =20 PageTableBufferSize =3D 0; Status =3D PageTableMap ( @@ -639,6 +701,47 @@ SingleMapEntryTest ( &LastMapEntry->Attribute, &LastMapEntry->Mask ); + + Attribute =3D &LastMapEntry->Attribute; + Mask =3D &LastMapEntry->Mask; + // + // If set [LinearAddress, LinearAddress+Attribute] to not preset, all + // other attributes should not be provided. + // + if ((LastMapEntry->Length > 0) && (Attribute->Bits.Present =3D=3D 0) && = (Mask->Bits.Present =3D=3D 1) && (Mask->Uint64 > 1)) { + RemoveLastMapEntry (MapEntrys); + UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); + return UNIT_TEST_PASSED; + } + + // + // Return Status for non-present range also should be InvalidParameter w= hen: + // 1. Some of attributes are not provided when mapping non-present range= to present. + // 2. Set any other attribute without setting the non-present range to P= resent. + // + if (IsNotPresent) { + if ((Mask->Bits.Present =3D=3D 1) && (Attribute->Bits.Present =3D=3D 1= )) { + // + // Creating new page table or remapping non-present range to present. + // + if ((Mask->Bits.ReadWrite =3D=3D 0) || (Mask->Bits.UserSupervisor = =3D=3D 0) || (Mask->Bits.WriteThrough =3D=3D 0) || (Mask->Bits.CacheDisable= d =3D=3D 0) || + (Mask->Bits.Accessed =3D=3D 0) || (Mask->Bits.Dirty =3D=3D 0) ||= (Mask->Bits.Pat =3D=3D 0) || (Mask->Bits.Global =3D=3D 0) || + (Mask->Bits.PageTableBaseAddress =3D=3D 0) || (Mask->Bits.Protec= tionKey =3D=3D 0) || (Mask->Bits.Nx =3D=3D 0)) + { + RemoveLastMapEntry (MapEntrys); + UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); + return UNIT_TEST_PASSED; + } + } else if ((Mask->Bits.Present =3D=3D 0) && (Mask->Uint64 > 1)) { + // + // Only change other attributes for non-present range is not permitt= ed. + // + RemoveLastMapEntry (MapEntrys); + UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); + return UNIT_TEST_PASSED; + } + } + if (PageTableBufferSize !=3D 0) { UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); =20 diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c index 5bd70c0f65..10fdee2f94 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c @@ -1,7 +1,7 @@ /** @file helper file for Unit tests of the CpuPageTableLib instance of the CpuPag= eTableLib class =20 - Copyright (c) 2022, Intel Corporation. All rights reserved.
+ Copyright (c) 2022 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -171,6 +171,10 @@ IsPageTableValid ( UNIT_TEST_STATUS Status; IA32_PAGING_ENTRY *PagingEntry; =20 + if (PageTable =3D=3D 0) { + return UNIT_TEST_PASSED; + } + if ((PagingMode =3D=3D Paging32bit) || (PagingMode =3D=3D PagingPae) || = (PagingMode >=3D PagingModeMax)) { // // 32bit paging is never supported. --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101737): https://edk2.groups.io/g/devel/message/101737 Mute This Topic: https://groups.io/mt/97818234/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 15:13:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101738+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101738+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679637661; cv=none; d=zohomail.com; s=zohoarc; b=To6RcSzYtdFtxqhtK25KnqyDdqHQYchUkag7G96PMOAg53VlbDAnUlTGuZLQYwwB8x9AoS9mDNYpIGeMWIOwYHXVTOcL2N7GkbsVrWnDXIgljQrsGFqsBn82WmQVbyZDpSogxLoSd5tI3soWzBXXCjcL+U7C5acNe5BVdfQU2RY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679637661; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=f4p6Y0NFy1cCxmxy4Fh7BiKy1EjkGBhgUQ4d7+hz0yY=; b=iDbG0Ejw34nySxyv821xV3phpcY1SKOvIxg7fqAtSafQ3+4csvPmDgLynxhS7b3UAPb4hEKyzkxw+w1LR3AhMbwBRdabhj1PQuRuCFcVk6J7zZVSGkDhgm0E+S8rPl6dOGHMQVlsvViC9GJOTR3zMKXbMpI6ZKTnGfUCZq+gGzI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101738+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679637661902802.3774463469334; Thu, 23 Mar 2023 23:01:01 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id OZSkYY1788612xYRq9Srrvss; Thu, 23 Mar 2023 23:01:01 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.94534.1679637641374533517 for ; Thu, 23 Mar 2023 23:01:01 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="320094001" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="320094001" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:01:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="1012122134" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="1012122134" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:00:59 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V5 13/22] UefiCpuPkg/CpuPageTableLib: Enable non-1:1 mapping in random test Date: Fri, 24 Mar 2023 14:00:11 +0800 Message-Id: <20230324060020.940-14-dun.tan@intel.com> In-Reply-To: <20230324060020.940-1-dun.tan@intel.com> References: <20230324060020.940-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: NdN8U5TTgTRCVYZhQG9fAIEtx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679637661; bh=QG/VC7UVz8j33Y7d1QoptSft87Zxx3O8QGwP6Gbffr8=; h=Cc:Date:From:Reply-To:Subject:To; b=hMansLYkOg8RXrTNJXzsXEjsNZox7RSaopLIMopnCZS97iYtl/i9BsuhXRlPEA5UFCF s4YdXEZTkLyvWvwBUu3YON5/XbEE75tF2j4U1z86Lvmzz41bIvV5HosX8l44UDUQQ1eaL +DgiOlWOI5RVJaRVax611o+MIjm398rOZYs= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679637663412100005 Content-Type: text/plain; charset="utf-8" Enable non-1:1 mapping in random test. In previous test, non-1:1 test will fail due to the non-1:1 mapping issue in CpuPageTableLib and invalid Input Mask when creating new page table or mapping not-present range. Now these issue have been fixed. Signed-off-by: Dun Tan Cc: Eric Dong Reviewed-by: Ray Ni Cc: Rahul Kumar Tested-by: Gerd Hoffmann Acked-by: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c = | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUni= tTestHost.c b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUn= itTestHost.c index 52fae1864a..c682d4ea04 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c @@ -9,10 +9,10 @@ #include "CpuPageTableLibUnitTest.h" =20 // -----------------------------------------------------------------------= PageMode--TestCount-TestRangeCount---RandomOptions -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging4Level = =3D { Paging4Level, 100, 20, ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY }; -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging4Level1GB= =3D { Paging4Level1GB, 100, 20, ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY }; -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging5Level = =3D { Paging5Level, 100, 20, ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY }; -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging5Level1GB= =3D { Paging5Level1GB, 100, 20, ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY }; +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging4Level = =3D { Paging4Level, 100, 20, USE_RANDOM_ARRAY }; +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging4Level1GB= =3D { Paging4Level1GB, 100, 20, USE_RANDOM_ARRAY }; +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging5Level = =3D { Paging5Level, 100, 20, USE_RANDOM_ARRAY }; +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging5Level1GB= =3D { Paging5Level1GB, 100, 20, USE_RANDOM_ARRAY }; =20 /** Check if the input parameters are not supported. --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101738): https://edk2.groups.io/g/devel/message/101738 Mute This Topic: https://groups.io/mt/97818236/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 15:13:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101739+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101739+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679637669; cv=none; d=zohomail.com; s=zohoarc; b=fZnNhhlsDpDJSg0ERnmzB8F/JRCiK44m0XVak5u+zr0Dus6ZvShplR/I6cOEJfMAT/ryxBBkZFq4qEZzx30fIqnRvICJ5h3m2A/CNxQl7YhYkn3xDqGXtRzGNnwMv9dxjQgBd2TlWfQQyJhrlvZrSbWxxCYSwPX2ttEZZ1xcWW8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679637669; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=XJUYUXWOFfYnRDXxTYO9sQFaOXt6VRzQugXME1CmyPI=; b=V+QCIBp0jXj/9CryRLAYfaYGNClUZG2P0O4XqtWW7EULjEeODASjCo19+gUO+M0Bpfd+7kVooH8da1771z5PNPU+x8PDVAkgNZtvEZP3EM+QH0vezyAZ6D89icTCo2FouQTo4/rZq9wwrkwm/NDbm575P5OehvYbsAi/Hpp9J7E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101739+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679637669596525.9759940921514; Thu, 23 Mar 2023 23:01:09 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 5L8oYY1788612xkPHfeweR8k; Thu, 23 Mar 2023 23:01:09 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.94534.1679637641374533517 for ; Thu, 23 Mar 2023 23:01:03 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="320094032" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="320094032" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:01:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="1012122154" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="1012122154" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:01:01 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V5 14/22] UefiCpuPkg/CpuPageTableLib: Add OUTPUT IsModified parameter. Date: Fri, 24 Mar 2023 14:00:12 +0800 Message-Id: <20230324060020.940-15-dun.tan@intel.com> In-Reply-To: <20230324060020.940-1-dun.tan@intel.com> References: <20230324060020.940-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: WLIYvB1GUeeCEEns0bT8VctAx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679637669; bh=X52wURB4MlS3i1vxN0eW/zCpFRxsQs5qNbGSqGcHRVc=; h=Cc:Date:From:Reply-To:Subject:To; b=SMWoxZ1lsBNFD4i0a2Dl9zLYrETWMTiQY3Cq8HHw+5x9MVP2weemKW7smck938WauFy awW5PKYNBHIwrXLMS4oSF4k5QVE6eCgNC6dNtXCOrZ4LjDWNwq2rzZk9liKJJ0B8O+x+J Ch6aHyNngzIbUvm5Ew2U84DkrQZvM1QAQxM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679637671456100019 Content-Type: text/plain; charset="utf-8" Add OUTPUT IsModified parameter in PageTableMap() to indicate if page table has been modified. With this parameter, caller can know if need to call FlushTlb when the page table is in CR3. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Tested-by: Gerd Hoffmann Acked-by: Gerd Hoffmann Reviewed-by: Ray Ni --- UefiCpuPkg/Include/Library/CpuPageTableLib.h = | 4 +++- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c = | 46 +++++++++++++++++++++++++++++++++++++++++----- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c = | 72 ++++++++++++++++++++++++++++++++++++----------------------------------= -- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c = | 6 ++++-- UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c = | 6 ++++-- 5 files changed, 88 insertions(+), 46 deletions(-) diff --git a/UefiCpuPkg/Include/Library/CpuPageTableLib.h b/UefiCpuPkg/Incl= ude/Library/CpuPageTableLib.h index 4ef4a8b6af..352b6df6c6 100644 --- a/UefiCpuPkg/Include/Library/CpuPageTableLib.h +++ b/UefiCpuPkg/Include/Library/CpuPageTableLib.h @@ -74,6 +74,7 @@ typedef enum { Page table entries that map the linear ad= dress range are reset to 0 before set to the new attribute when a new physical base address is set. @param[in] Mask The mask used for attribute. The correspo= nding field in Attribute is ignored if that in Mask is 0. + @param[out] IsModified TRUE means page table is modified. FALSE = means page table is not modified. =20 @retval RETURN_UNSUPPORTED PagingMode is not supported. @retval RETURN_INVALID_PARAMETER PageTable, BufferSize, Attribute or Ma= sk is NULL. @@ -97,7 +98,8 @@ PageTableMap ( IN UINT64 LinearAddress, IN UINT64 Length, IN IA32_MAP_ATTRIBUTE *Attribute, - IN IA32_MAP_ATTRIBUTE *Mask + IN IA32_MAP_ATTRIBUTE *Mask, + OUT BOOLEAN *IsModified OPTIONAL ); =20 typedef struct { diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index c0b41472ce..885f1601fc 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -274,6 +274,7 @@ IsAttributesAndMaskValidForNonPresentEntry ( Page table entries that map the linear= address range are reset to 0 before set to the new attribute when a new physical base address is se= t. @param[in] Mask The mask used for attribute. The corre= sponding field in Attribute is ignored if that in Mask is 0. + @param[out] IsModified TRUE means page table is modified. FAL= SE means page table is not modified. =20 @retval RETURN_INVALID_PARAMETER For non-present range, Mask->Bits.Pres= ent is 0 but some other attributes are provided. @retval RETURN_INVALID_PARAMETER For non-present range, Mask->Bits.Pres= ent is 1, Attribute->Bits.Present is 1 but some other attributes are not pr= ovided. @@ -292,7 +293,8 @@ PageTableLibMapInLevel ( IN UINT64 Length, IN UINT64 Offset, IN IA32_MAP_ATTRIBUTE *Attribute, - IN IA32_MAP_ATTRIBUTE *Mask + IN IA32_MAP_ATTRIBUTE *Mask, + OUT BOOLEAN *IsModified ) { RETURN_STATUS Status; @@ -318,6 +320,8 @@ PageTableLibMapInLevel ( IA32_MAP_ATTRIBUTE LocalParentAttribute; UINT64 PhysicalAddrInEntry; UINT64 PhysicalAddrInAttr; + IA32_PAGING_ENTRY OriginalParentPagingEntry; + IA32_PAGING_ENTRY OriginalCurrentPagingEntry; =20 ASSERT (Level !=3D 0); ASSERT ((Attribute !=3D NULL) && (Mask !=3D NULL)); @@ -333,6 +337,8 @@ PageTableLibMapInLevel ( LocalParentAttribute.Uint64 =3D ParentAttribute->Uint64; ParentAttribute =3D &LocalParentAttribute; =20 + OriginalParentPagingEntry.Uint64 =3D ParentPagingEntry->Uint64; + // // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 << 2= 1) or 4K (1 << 12). // @@ -568,7 +574,15 @@ PageTableLibMapInLevel ( ASSERT (CreateNew || (Mask->Bits.Nx =3D=3D 0) || (Attribute->Bit= s.Nx =3D=3D 1)); } =20 + // + // Check if any leaf PagingEntry is modified. + // + OriginalCurrentPagingEntry.Uint64 =3D CurrentPagingEntry->Uint64; PageTableLibSetPle (Level, CurrentPagingEntry, Offset, Attribute, = &CurrentMask); + + if (OriginalCurrentPagingEntry.Uint64 !=3D CurrentPagingEntry->Uin= t64) { + *IsModified =3D TRUE; + } } } else { // @@ -591,7 +605,8 @@ PageTableLibMapInLevel ( Length, Offset, Attribute, - Mask + Mask, + IsModified ); if (RETURN_ERROR (Status)) { return Status; @@ -603,6 +618,14 @@ PageTableLibMapInLevel ( Index++; } =20 + // + // Check if ParentPagingEntry entry is modified here is enough. Except t= he changes happen in leaf PagingEntry during + // the while loop, if there is any other change happens in page table, t= he ParentPagingEntry must has been modified. + // + if (OriginalParentPagingEntry.Uint64 !=3D ParentPagingEntry->Uint64) { + *IsModified =3D TRUE; + } + return RETURN_SUCCESS; } =20 @@ -623,6 +646,7 @@ PageTableLibMapInLevel ( Page table entries that map the linear ad= dress range are reset to 0 before set to the new attribute when a new physical base address is set. @param[in] Mask The mask used for attribute. The correspo= nding field in Attribute is ignored if that in Mask is 0. + @param[out] IsModified TRUE means page table is modified. FALSE = means page table is not modified. =20 @retval RETURN_UNSUPPORTED PagingMode is not supported. @retval RETURN_INVALID_PARAMETER PageTable, BufferSize, Attribute or Ma= sk is NULL. @@ -646,7 +670,8 @@ PageTableMap ( IN UINT64 LinearAddress, IN UINT64 Length, IN IA32_MAP_ATTRIBUTE *Attribute, - IN IA32_MAP_ATTRIBUTE *Mask + IN IA32_MAP_ATTRIBUTE *Mask, + OUT BOOLEAN *IsModified OPTIONAL ) { RETURN_STATUS Status; @@ -656,6 +681,7 @@ PageTableMap ( IA32_PAGE_LEVEL MaxLevel; IA32_PAGE_LEVEL MaxLeafLevel; IA32_MAP_ATTRIBUTE ParentAttribute; + BOOLEAN LocalIsModified; =20 if (Length =3D=3D 0) { return RETURN_SUCCESS; @@ -718,6 +744,12 @@ PageTableMap ( TopPagingEntry.Pce.Nx =3D 0; } =20 + if (IsModified =3D=3D NULL) { + IsModified =3D &LocalIsModified; + } + + *IsModified =3D FALSE; + ParentAttribute.Uint64 =3D 0; ParentAttribute.Bits.PageTableBaseAddress =3D 1; ParentAttribute.Bits.Present =3D 1; @@ -741,8 +773,10 @@ PageTableMap ( Length, 0, Attribute, - Mask + Mask, + IsModified ); + ASSERT (*IsModified =3D=3D FALSE); if (RETURN_ERROR (Status)) { return Status; } @@ -773,8 +807,10 @@ PageTableMap ( Length, 0, Attribute, - Mask + Mask, + IsModified ); + if (!RETURN_ERROR (Status)) { *PageTable =3D (UINTN)(TopPagingEntry.Uintn & IA32_PE_BASE_ADDRESS_MAS= K_40); } diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUni= tTestHost.c b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUn= itTestHost.c index c682d4ea04..759da09271 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c @@ -51,26 +51,26 @@ TestCaseForParameter ( // // If the input linear address is not 4K align, it should return invalid= parameter // - UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 1, SIZE_4KB, &MapAttribute, &MapMask), RETURN_INVALID_PARAMET= ER); + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 1, SIZE_4KB, &MapAttribute, &MapMask, NULL), RETURN_INVALID_P= ARAMETER); =20 // // If the input PageTableBufferSize is not 4K align, it should return in= valid parameter // PageTableBufferSize =3D 10; - UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 0, SIZE_4KB, &MapAttribute, &MapMask), RETURN_INVALID_PARAMET= ER); + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 0, SIZE_4KB, &MapAttribute, &MapMask, NULL), RETURN_INVALID_P= ARAMETER); =20 // // If the input PagingMode is Paging32bit, it should return invalid para= meter // PageTableBufferSize =3D 0; PagingMode =3D Paging32bit; - UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 1, SIZE_4KB, &MapAttribute, &MapMask), RETURN_UNSUPPORTED); + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 1, SIZE_4KB, &MapAttribute, &MapMask, NULL), RETURN_UNSUPPORT= ED); =20 // // If the input MapMask is NULL, it should return invalid parameter // PagingMode =3D Paging5Level1GB; - UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 1, SIZE_4KB, &MapAttribute, NULL), RETURN_INVALID_PARAMETER); + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 1, SIZE_4KB, &MapAttribute, NULL, NULL), RETURN_INVALID_PARAM= ETER); =20 return UNIT_TEST_PASSED; } @@ -119,10 +119,10 @@ TestCaseWhichNoNeedExtraSize ( // // Create page table to cover [0, 10M], it should have 5 PTE // - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, (UINT64)SIZE_2MB * 5, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, (UINT64)SIZE_2MB * 5, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, (UINT64)SIZE_2MB * 5, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, (UINT64)SIZE_2MB * 5, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); TestStatus =3D IsPageTableValid (PageTable, PagingMode); if (TestStatus !=3D UNIT_TEST_PASSED) { @@ -134,7 +134,7 @@ TestCaseWhichNoNeedExtraSize ( // We assume the fucntion doesn't need to change page table, return succ= ess and output BufferSize is 0 // Buffer =3D NULL; - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, (UINT64)SIZE_4KB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, (UINT64)SIZE_4KB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (PageTableBufferSize, 0); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); TestStatus =3D IsPageTableValid (PageTable, PagingMode); @@ -148,7 +148,7 @@ TestCaseWhichNoNeedExtraSize ( // MapMask.Bits.Nx =3D 0; PageTableBufferSize =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, NULL, &Pag= eTableBufferSize, 0, (UINT64)SIZE_4KB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, NULL, &Pag= eTableBufferSize, 0, (UINT64)SIZE_4KB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); UT_ASSERT_EQUAL (PageTableBufferSize, 0); TestStatus =3D IsPageTableValid (PageTable, PagingMode); @@ -164,7 +164,7 @@ TestCaseWhichNoNeedExtraSize ( MapAttribute.Bits.Accessed =3D 1; MapMask.Bits.Accessed =3D 1; PageTableBufferSize =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, NUL= L, &PageTableBufferSize, (UINT64)SIZE_2MB, (UINT64)SIZE_2MB, &MapAttribute,= &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, NUL= L, &PageTableBufferSize, (UINT64)SIZE_2MB, (UINT64)SIZE_2MB, &MapAttribute,= &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); UT_ASSERT_EQUAL (PageTableBufferSize, 0); TestStatus =3D IsPageTableValid (PageTable, PagingMode); @@ -217,10 +217,10 @@ TestCase1Gmapto4K ( MapAttribute.Bits.Present =3D 1; MapMask.Bits.Present =3D 1; MapMask.Uint64 =3D MAX_UINT64; - Status =3D PageTableMap (&PageTable, PagingMode, Buff= er, &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapM= ask); + Status =3D PageTableMap (&PageTable, PagingMode, Buff= er, &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapM= ask, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); =20 // @@ -281,11 +281,11 @@ TestCaseManualChangeReadWrite ( // // Create Page table to cover [0,2G], with ReadWrite =3D 1 // - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); BackupPageTableBufferSize =3D PageTableBufferSize; Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTabl= eBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buff= er, &PageTableBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buff= er, &PageTableBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); IsPageTableValid (PageTable, PagingMode); =20 @@ -331,7 +331,7 @@ TestCaseManualChangeReadWrite ( // Call library to change ReadWrite to 0 for [0,2M] // MapAttribute.Bits.ReadWrite =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, NU= LL, &PageTableBufferSize, 0, SIZE_2MB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, NU= LL, &PageTableBufferSize, 0, SIZE_2MB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); IsPageTableValid (PageTable, PagingMode); MapCount =3D 0; @@ -360,7 +360,7 @@ TestCaseManualChangeReadWrite ( // MapAttribute.Bits.ReadWrite =3D 1; PageTableBufferSize =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, NU= LL, &PageTableBufferSize, 0, SIZE_2MB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, NU= LL, &PageTableBufferSize, 0, SIZE_2MB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); IsPageTableValid (PageTable, PagingMode); MapCount =3D 0; @@ -434,10 +434,10 @@ TestCaseManualSizeNotMatch ( // // Create Page table to cover [2M-4K, 4M], with ReadWrite =3D 1 // - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, SIZE_2MB - SIZE_4KB, SIZE_4KB + SIZE_2MB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, SIZE_2MB - SIZE_4KB, SIZE_4KB + SIZE_2MB, &MapAttribute, &MapMask, N= ULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, SIZE_2MB - SIZE_4KB, SIZE_4KB + SIZE_2MB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, SIZE_2MB - SIZE_4KB, SIZE_4KB + SIZE_2MB, &MapAttribute, &MapMask, N= ULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); IsPageTableValid (PageTable, PagingMode); =20 @@ -493,7 +493,7 @@ TestCaseManualSizeNotMatch ( MapAttribute.Bits.ReadWrite =3D 1; PageTableBufferSize =3D 0; MapAttribute.Bits.PageTableBaseAddress =3D (SIZE_2MB - SIZE_4KB) >> 12; - Status =3D PageTableMap (&PageTable, Pag= ingMode, Buffer, &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB * 2, &= MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, Pag= ingMode, Buffer, &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB * 2, &= MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); return UNIT_TEST_PASSED; } @@ -540,10 +540,10 @@ TestCaseManualNotMergeEntry ( // // Create Page table to cover [0,4M], and [4M, 1G] is not present // - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_2MB * 2, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_2MB * 2, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_2MB * 2, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_2MB * 2, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); TestStatus =3D IsPageTableValid (PageTable, PagingMode); if (TestStatus !=3D UNIT_TEST_PASSED) { @@ -555,7 +555,7 @@ TestCaseManualNotMergeEntry ( // It looks like the chioce is not bad, but sometime, we need to keep so= me small entry // PageTableBufferSize =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, NULL, &Pag= eTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, NULL, &Pag= eTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapMask, NUL= L); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); TestStatus =3D IsPageTableValid (PageTable, PagingMode); if (TestStatus !=3D UNIT_TEST_PASSED) { @@ -564,7 +564,7 @@ TestCaseManualNotMergeEntry ( =20 MapAttribute.Bits.Accessed =3D 1; PageTableBufferSize =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, NUL= L, &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_2MB, &MapAttribute, &MapMa= sk); + Status =3D PageTableMap (&PageTable, PagingMode, NUL= L, &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_2MB, &MapAttribute, &MapMa= sk, NULL); // // If it didn't use a big 1G entry to cover whole range, only change [0,= 2M] for some attribute won't need extra memory // @@ -619,10 +619,10 @@ TestCaseManualChangeNx ( // // Create Page table to cover [0,2G], with Nx =3D 0 // - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_1GB * 2, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_1GB * 2, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_1GB * 2, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_1GB * 2, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); TestStatus =3D IsPageTableValid (PageTable, PagingMode); if (TestStatus !=3D UNIT_TEST_PASSED) { @@ -666,7 +666,7 @@ TestCaseManualChangeNx ( // // Call library to change Nx to 0 for [0,1G] // - Status =3D PageTableMap (&PageTable, PagingMode, NULL, &PageTableBufferS= ize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, NULL, &PageTableBufferS= ize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); TestStatus =3D IsPageTableValid (PageTable, PagingMode); if (TestStatus !=3D UNIT_TEST_PASSED) { @@ -741,30 +741,30 @@ TestCaseToCheckMapMaskAndAttr ( // // Create Page table to cover [0, 2G]. All fields of MapMask should be s= et. // - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); MapMask.Uint64 =3D MAX_UINT64; - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTa= bleBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTa= bleBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); =20 // // Update Page table to set [2G - 8K, 2G] from present to non-present. A= ll fields of MapMask except present should not be set. // PageTableBufferSize =3D 0; - MapAttribute.Uint64 =3D SIZE_2GB - SIZE_8KB; + MapAttribute.Uint64 =3D 0; MapMask.Uint64 =3D 0; MapMask.Bits.Present =3D 1; MapMask.Bits.ReadWrite =3D 1; - Status =3D PageTableMap (&PageTable, PagingMode, Buffer,= &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMa= sk); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer,= &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMa= sk, NULL); UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); MapMask.Bits.ReadWrite =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, Buffer,= &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMa= sk); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer,= &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMa= sk, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); =20 // @@ -774,11 +774,11 @@ TestCaseToCheckMapMaskAndAttr ( MapAttribute.Uint64 =3D 0; MapMask.Uint64 =3D 0; MapMask.Bits.Present =3D 1; - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &= PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMask= ); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &= PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMask= , NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); MapAttribute.Bits.ReadWrite =3D 1; MapMask.Bits.ReadWrite =3D 1; - Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &= MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &= MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); =20 // @@ -791,10 +791,10 @@ TestCaseToCheckMapMaskAndAttr ( MapMask.Uint64 =3D 0; MapMask.Bits.ReadWrite =3D 1; MapMask.Bits.Present =3D 1; - Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &= MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &= MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); MapMask.Uint64 =3D MAX_UINT64; - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTa= bleBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTa= bleBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMask, NULL= ); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); =20 MapCount =3D 0; diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c index 121cc4f2b2..e603dba269 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c @@ -699,7 +699,8 @@ SingleMapEntryTest ( LastMapEntry->LinearAddress, LastMapEntry->Length, &LastMapEntry->Attribute, - &LastMapEntry->Mask + &LastMapEntry->Mask, + NULL ); =20 Attribute =3D &LastMapEntry->Attribute; @@ -759,7 +760,8 @@ SingleMapEntryTest ( LastMapEntry->LinearAddress, LastMapEntry->Length, &LastMapEntry->Attribute, - &LastMapEntry->Mask + &LastMapEntry->Mask, + NULL ); } =20 diff --git a/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c b/UefiCpuPk= g/Library/MpInitLib/X64/CreatePageTable.c index f20068152b..da8729e752 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c +++ b/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c @@ -57,7 +57,8 @@ CreatePageTable ( Address, Length, &MapAttribute, - &MapMask + &MapMask, + NULL ); ASSERT (Status =3D=3D EFI_BUFFER_TOO_SMALL); DEBUG ((DEBUG_INFO, "AP Page Table Buffer Size =3D %x\n", PageTableBuffe= rSize)); @@ -72,7 +73,8 @@ CreatePageTable ( Address, Length, &MapAttribute, - &MapMask + &MapMask, + NULL ); ASSERT_EFI_ERROR (Status); return PageTable; --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101739): https://edk2.groups.io/g/devel/message/101739 Mute This Topic: https://groups.io/mt/97818237/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 15:13:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101740+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101740+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679637665; cv=none; d=zohomail.com; s=zohoarc; b=DgbxQJAZ9S2hA2aX8KxYzDfogB44eLKclsUtqGbi6tXfn41GFWmMp9AtS5Vk3BxttAoQ+s9h/bQT5/s5TXWwfajE63KYO4F0q1/OSKTGsqJEs0J7LKz59VS8VDtxAcJA0wNGhREL3lzzd3uQYE8Aih1KNUqiSuJXejxeZIBfIGw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679637665; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=XWhiaTzpC4xr0zh6LCf15Qyvs7uKkZ9NF3tEFOPgX+w=; b=lYKo48vtmXVldf4i3OK/vkmpHkSXwKXZ+BKT6gVQ3ZiI6YGpwns1lJV5yp07mbNWRLG17LHS5F575DgtVZieei9wBAw7e9M3AQaGkufzRwMtfL9yEkkLvmBf8OkzE/Fquybvzille3EZO+c7JYKt40WL85lAAeh4OYAoqUnhEuc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101740+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679637665646514.0029015207208; Thu, 23 Mar 2023 23:01:05 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 6j6cYY1788612xecN6rU7YLc; Thu, 23 Mar 2023 23:01:05 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.94534.1679637641374533517 for ; Thu, 23 Mar 2023 23:01:04 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="320094040" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="320094040" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:01:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="1012122199" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="1012122199" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:01:03 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann , Zhiguang Liu Subject: [edk2-devel] [Patch V5 15/22] UefiCpuPkg/CpuPageTableLib: Modify RandomTest to check IsModified Date: Fri, 24 Mar 2023 14:00:13 +0800 Message-Id: <20230324060020.940-16-dun.tan@intel.com> In-Reply-To: <20230324060020.940-1-dun.tan@intel.com> References: <20230324060020.940-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: oLDYAgx8v0JRFVK3LxXxt37Dx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679637665; bh=TeiU2HyVY3UXIeGXL0yH/CFec5P1Fmr5o7f/0qGqsGk=; h=Cc:Date:From:Reply-To:Subject:To; b=vzX1HC7EJiTmyZJ6IO/s1Fv5CsK7CbpxY25TEIx5Vb0WmEujsrUCJPkJi7HvTH9BdB3 G/dhx5T34Y6K3eDQOBo75eOLdCs3sZGhcHzLoCLPOEJM3iMivx10eDKYjIzFD/FXt3mPy NQ1A00gfSxUX/LaxgUdIp1M/ukU1TMbxA9I= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679637667396100011 Content-Type: text/plain; charset="utf-8" Modify RandomTest to check if parameter IsModified of PageTableMap() correctlly indicates whether input page table is modified or not. Signed-off-by: Dun Tan Cc: Eric Dong Reviewed-by: Ray Ni Cc: Rahul Kumar Tested-by: Gerd Hoffmann Acked-by: Gerd Hoffmann Cc: Zhiguang Liu --- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c | 45 ++++++++++++= +++++++++++++++++++++------------ 1 file changed, 33 insertions(+), 12 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c index e603dba269..bffd95c898 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c @@ -636,6 +636,8 @@ SingleMapEntryTest ( VOID *Buffer; IA32_MAP_ENTRY *Map; UINTN MapCount; + IA32_MAP_ENTRY *Map2; + UINTN MapCount2; UINTN Index; UINTN KeyPointCount; UINTN NewKeyPointCount; @@ -648,11 +650,13 @@ SingleMapEntryTest ( IA32_MAP_ATTRIBUTE *Attribute; UINT64 LastNotPresentRegionStart; BOOLEAN IsNotPresent; + BOOLEAN IsModified; =20 MapsIndex =3D MapEntrys->Count; MapCount =3D 0; LastNotPresentRegionStart =3D 0; IsNotPresent =3D FALSE; + IsModified =3D FALSE; =20 GenerateSingleRandomMapEntry (MaxAddress, MapEntrys); LastMapEntry =3D &MapEntrys->Maps[MapsIndex]; @@ -700,7 +704,7 @@ SingleMapEntryTest ( LastMapEntry->Length, &LastMapEntry->Attribute, &LastMapEntry->Mask, - NULL + &IsModified ); =20 Attribute =3D &LastMapEntry->Attribute; @@ -761,7 +765,7 @@ SingleMapEntryTest ( LastMapEntry->Length, &LastMapEntry->Attribute, &LastMapEntry->Mask, - NULL + &IsModified ); } =20 @@ -775,18 +779,31 @@ SingleMapEntryTest ( return TestStatus; } =20 - MapCount =3D 0; - Status =3D PageTableParse (*PageTable, PagingMode, NULL, &MapCount); - if (MapCount !=3D 0) { + MapCount2 =3D 0; + Status =3D PageTableParse (*PageTable, PagingMode, NULL, &MapCount2); + if (MapCount2 !=3D 0) { UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); =20 // - // Allocate memory for Maps + // Allocate memory for Map2 // Note the memory is only used in this one Single MapEntry Test // - Map =3D AllocatePages (EFI_SIZE_TO_PAGES (MapCount * sizeof (IA32_MAP_= ENTRY))); - ASSERT (Map !=3D NULL); - Status =3D PageTableParse (*PageTable, PagingMode, Map, &MapCount); + Map2 =3D AllocatePages (EFI_SIZE_TO_PAGES (MapCount2 * sizeof (IA32_MA= P_ENTRY))); + ASSERT (Map2 !=3D NULL); + Status =3D PageTableParse (*PageTable, PagingMode, Map2, &MapCount2); + } + + // + // Check if PageTable has been modified. + // + if (MapCount2 !=3D MapCount) { + UT_ASSERT_EQUAL (IsModified, TRUE); + } else { + if (CompareMem (Map, Map2, MapCount2 * sizeof (IA32_MAP_ENTRY)) !=3D 0= ) { + UT_ASSERT_EQUAL (IsModified, TRUE); + } else { + UT_ASSERT_EQUAL (IsModified, FALSE); + } } =20 UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); @@ -796,17 +813,17 @@ SingleMapEntryTest ( // Note the memory is only used in this one Single MapEntry Test // KeyPointCount =3D 0; - GetKeyPointList (MapEntrys, Map, MapCount, NULL, &KeyPointCount); + GetKeyPointList (MapEntrys, Map2, MapCount2, NULL, &KeyPointCount); KeyPointBuffer =3D AllocatePages (EFI_SIZE_TO_PAGES (KeyPointCount * siz= eof (UINT64))); ASSERT (KeyPointBuffer !=3D NULL); NewKeyPointCount =3D 0; - GetKeyPointList (MapEntrys, Map, MapCount, KeyPointBuffer, &NewKeyPointC= ount); + GetKeyPointList (MapEntrys, Map2, MapCount2, KeyPointBuffer, &NewKeyPoin= tCount); =20 // // Compare all key point's attribute // for (Index =3D 0; Index < NewKeyPointCount; Index++) { - if (!CompareEntrysforOnePoint (KeyPointBuffer[Index], MapEntrys, Map, = MapCount, InitMap, InitMapCount)) { + if (!CompareEntrysforOnePoint (KeyPointBuffer[Index], MapEntrys, Map2,= MapCount2, InitMap, InitMapCount)) { DEBUG ((DEBUG_INFO, "Error happens at below key point\n")); DEBUG ((DEBUG_INFO, "Index =3D %d KeyPointBuffer[Index] =3D 0x%lx\n"= , Index, KeyPointBuffer[Index])); Value =3D GetEntryFromPageTable (*PageTable, PagingMode, KeyPointBuf= fer[Index], &Level); @@ -820,6 +837,10 @@ SingleMapEntryTest ( FreePages (Map, EFI_SIZE_TO_PAGES (MapCount * sizeof (IA32_MAP_ENTRY))= ); } =20 + if (MapCount2 !=3D 0) { + FreePages (Map2, EFI_SIZE_TO_PAGES (MapCount2 * sizeof (IA32_MAP_ENTRY= ))); + } + return UNIT_TEST_PASSED; } =20 --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101740): https://edk2.groups.io/g/devel/message/101740 Mute This Topic: https://groups.io/mt/97818238/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 15:13:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101741+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101741+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679637668; cv=none; d=zohomail.com; s=zohoarc; b=Mm4xUjojgGKA2RamPriFfAUlOWH8HeUaTFmWexiNUQ7HLi1u/RUb49M0RBLqwJ+w1Iek+ZHqTsw6KA7oOGrVCws4u5j6Q3IWqLxgS+zz2d5K0DLcKIJFhwIpsLonoPQFRpQt+cfgemvjp3BpYdr1b63ldk/0ZeiUJteN039uG7A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679637668; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=RWLtXFm5qlF4YNzovorhTkoxHYLZ/2L+ouoM7LONUrA=; b=RPs0tM6XZMHwdeNAg6XlInUvlg+p+Gdcxo3bChvRa6NwNaDn78p7ZesGtqVhj8r8X3C34uKpgSsxHDrGT1HeMGkidP21ytwQv9gOpbL6cWbnALXbbhF15ks6PreTlVXYbizVghgBorIvN7MOwdCKDaPuiYyFuBD0W8r++nLqhxg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101741+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679637668220704.4183160200233; Thu, 23 Mar 2023 23:01:08 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id YYLLYY1788612xIAceQE0pcN; Thu, 23 Mar 2023 23:01:07 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.94534.1679637641374533517 for ; Thu, 23 Mar 2023 23:01:07 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="320094046" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="320094046" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:01:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="1012122240" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="1012122240" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:01:05 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V5 16/22] UefiCpuPkg: Fix IA32 build failure in CpuPageTableLib.inf Date: Fri, 24 Mar 2023 14:00:14 +0800 Message-Id: <20230324060020.940-17-dun.tan@intel.com> In-Reply-To: <20230324060020.940-1-dun.tan@intel.com> References: <20230324060020.940-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: vbFZlGd7ss4KSEhAG8jGIZRwx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679637667; bh=qYX8LVER+WBwTpK06kKQ8qObLJpwKuVtlOQGl3NvtyE=; h=Cc:Date:From:Reply-To:Subject:To; b=PZu5rIss8JV3cBxhW+bEJ+qib+PavGqVYx+x4sYK04+9Qo4z+M0OJ/4DpqSi0VqcPZG cmvVv7AOq70qqi/osyAXG3oYnlq17P0rLzDIMPKZnuYaGYcoBK86X8Pp4HRdaXYYudsBE zEa9eD8s+quWxg7Uiv4CF+wX17Q2Au0TqWM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679637669460100016 Content-Type: text/plain; charset="utf-8" From: Zhiguang Liu The definition of IA32_MAP_ATTRIBUTE has 64 bits, and one of the bit field PageTableBaseAddress is from bit 12 to bit 52. This means if the compiler treats the 64bits value as two UINT32 value, the field PageTableBaseAddress spans two UINT32 value. That's why when building in NOOPT mode in IA32, the below issue is noticed: unresolved external symbol __allshl This patch fix the build failure by seperate field PageTableBaseAddress into two fields, make sure no field spans two UINT32 value. Cc: Eric Dong Reviewed-by: Ray Ni Cc: Rahul Kumar Tested-by: Gerd Hoffmann Acked-by: Gerd Hoffmann Signed-off-by: Zhiguang Liu Signed-off-by: Ray Ni --- UefiCpuPkg/Include/Library/CpuPageTableLib.h | 32 +++++++++++++++= +---------------- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h | 125 +++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++---------------------------= ----------------------------------- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 22 +++++++++++----= ------- 3 files changed, 90 insertions(+), 89 deletions(-) diff --git a/UefiCpuPkg/Include/Library/CpuPageTableLib.h b/UefiCpuPkg/Incl= ude/Library/CpuPageTableLib.h index 352b6df6c6..78aa83b8de 100644 --- a/UefiCpuPkg/Include/Library/CpuPageTableLib.h +++ b/UefiCpuPkg/Include/Library/CpuPageTableLib.h @@ -11,22 +11,22 @@ =20 typedef union { struct { - UINT64 Present : 1; // 0 =3D Not present in memory, 1 = =3D Present in memory - UINT64 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Write - UINT64 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser - UINT64 WriteThrough : 1; // 0 =3D Write-Back caching, 1=3DW= rite-Through caching - UINT64 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cached - UINT64 Accessed : 1; // 0 =3D Not accessed, 1 =3D Acces= sed (set by CPU) - UINT64 Dirty : 1; // 0 =3D Not dirty, 1 =3D Dirty (s= et by CPU) - UINT64 Pat : 1; // PAT - - UINT64 Global : 1; // 0 =3D Not global, 1 =3D Global = (if CR4.PGE =3D 1) - UINT64 Reserved1 : 3; // Ignored - - UINT64 PageTableBaseAddress : 40; // Page Table Base Address - UINT64 Reserved2 : 7; // Ignored - UINT64 ProtectionKey : 4; // Protection key - UINT64 Nx : 1; // No Execute bit + UINT32 Present : 1; // 0 =3D Not present in memor= y, 1 =3D Present in memory + UINT32 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read= /Write + UINT32 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser + UINT32 WriteThrough : 1; // 0 =3D Write-Back caching, = 1=3DWrite-Through caching + UINT32 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cach= ed + UINT32 Accessed : 1; // 0 =3D Not accessed, 1 =3D = Accessed (set by CPU) + UINT32 Dirty : 1; // 0 =3D Not dirty, 1 =3D Dir= ty (set by CPU) + UINT32 Pat : 1; // PAT + UINT32 Global : 1; // 0 =3D Not global, 1 =3D Gl= obal (if CR4.PGE =3D 1) + UINT32 Reserved1 : 3; // Ignored + UINT32 PageTableBaseAddressLow : 20; // Page Table Base Address Low + + UINT32 PageTableBaseAddressHigh : 20; // Page Table Base Address Hi= gh + UINT32 Reserved2 : 7; // Ignored + UINT32 ProtectionKey : 4; // Protection key + UINT32 Nx : 1; // No Execute bit } Bits; UINT64 Uint64; } IA32_MAP_ATTRIBUTE; diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h b/UefiCpuPkg= /Library/CpuPageTableLib/CpuPageTable.h index 8d856d7c7e..2c67ecb469 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h @@ -29,11 +29,12 @@ typedef enum { } IA32_PAGE_LEVEL; =20 typedef struct { - UINT64 Present : 1; // 0 =3D Not present in memory, 1 = =3D Present in memory - UINT64 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Write - UINT64 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser - UINT64 Reserved : 58; - UINT64 Nx : 1; // No Execute bit + UINT32 Present : 1; // 0 =3D Not present in memory, 1 = =3D Present in memory + UINT32 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Write + UINT32 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser + UINT32 Reserved0 : 29; + UINT32 Reserved1 : 31; + UINT32 Nx : 1; // No Execute bit } IA32_PAGE_COMMON_ENTRY; =20 /// @@ -41,20 +42,20 @@ typedef struct { /// typedef union { struct { - UINT64 Present : 1; // 0 =3D Not present in memory, 1 = =3D Present in memory - UINT64 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Write - UINT64 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser - UINT64 WriteThrough : 1; // 0 =3D Write-Back caching, 1=3DW= rite-Through caching - UINT64 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cached - UINT64 Accessed : 1; // 0 =3D Not accessed, 1 =3D Acces= sed (set by CPU) - UINT64 Available0 : 1; // Ignored - UINT64 MustBeZero : 1; // Must Be Zero - - UINT64 Available2 : 4; // Ignored - - UINT64 PageTableBaseAddress : 40; // Page Table Base Address - UINT64 Available3 : 11; // Ignored - UINT64 Nx : 1; // No Execute bit + UINT32 Present : 1; // 0 =3D Not present in memor= y, 1 =3D Present in memory + UINT32 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read= /Write + UINT32 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser + UINT32 WriteThrough : 1; // 0 =3D Write-Back caching, = 1=3DWrite-Through caching + UINT32 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cach= ed + UINT32 Accessed : 1; // 0 =3D Not accessed, 1 =3D = Accessed (set by CPU) + UINT32 Available0 : 1; // Ignored + UINT32 MustBeZero : 1; // Must Be Zero + UINT32 Available2 : 4; // Ignored + UINT32 PageTableBaseAddressLow : 20; // Page Table Base Address Low + + UINT32 PageTableBaseAddressHigh : 20; // Page Table Base Address Hi= gh + UINT32 Available3 : 11; // Ignored + UINT32 Nx : 1; // No Execute bit } Bits; UINT64 Uint64; } IA32_PAGE_NON_LEAF_ENTRY; @@ -86,23 +87,23 @@ typedef IA32_PAGE_NON_LEAF_ENTRY IA32_PDE; /// typedef union { struct { - UINT64 Present : 1; // 0 =3D Not present in memory, 1 = =3D Present in memory - UINT64 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Write - UINT64 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser - UINT64 WriteThrough : 1; // 0 =3D Write-Back caching, 1=3DW= rite-Through caching - UINT64 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cached - UINT64 Accessed : 1; // 0 =3D Not accessed, 1 =3D Acces= sed (set by CPU) - UINT64 Dirty : 1; // 0 =3D Not dirty, 1 =3D Dirty (s= et by CPU) - UINT64 MustBeOne : 1; // Page Size. Must Be One - - UINT64 Global : 1; // 0 =3D Not global, 1 =3D Global = (if CR4.PGE =3D 1) - UINT64 Available1 : 3; // Ignored - UINT64 Pat : 1; // PAT - - UINT64 PageTableBaseAddress : 39; // Page Table Base Address - UINT64 Available3 : 7; // Ignored - UINT64 ProtectionKey : 4; // Protection key - UINT64 Nx : 1; // No Execute bit + UINT32 Present : 1; // 0 =3D Not present in memor= y, 1 =3D Present in memory + UINT32 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read= /Write + UINT32 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser + UINT32 WriteThrough : 1; // 0 =3D Write-Back caching, = 1=3DWrite-Through caching + UINT32 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cach= ed + UINT32 Accessed : 1; // 0 =3D Not accessed, 1 =3D = Accessed (set by CPU) + UINT32 Dirty : 1; // 0 =3D Not dirty, 1 =3D Dir= ty (set by CPU) + UINT32 MustBeOne : 1; // Page Size. Must Be One + UINT32 Global : 1; // 0 =3D Not global, 1 =3D Gl= obal (if CR4.PGE =3D 1) + UINT32 Available1 : 3; // Ignored + UINT32 Pat : 1; // PAT + UINT32 PageTableBaseAddressLow : 19; // Page Table Base Address Low + + UINT32 PageTableBaseAddressHigh : 20; // Page Table Base Address Hi= gh + UINT32 Available3 : 7; // Ignored + UINT32 ProtectionKey : 4; // Protection key + UINT32 Nx : 1; // No Execute bit } Bits; UINT64 Uint64; } IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE; @@ -123,22 +124,22 @@ typedef IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE IA32_PDPTE_= 1G; /// typedef union { struct { - UINT64 Present : 1; // 0 =3D Not present in memory, 1 = =3D Present in memory - UINT64 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Write - UINT64 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser - UINT64 WriteThrough : 1; // 0 =3D Write-Back caching, 1=3DW= rite-Through caching - UINT64 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cached - UINT64 Accessed : 1; // 0 =3D Not accessed, 1 =3D Acces= sed (set by CPU) - UINT64 Dirty : 1; // 0 =3D Not dirty, 1 =3D Dirty (s= et by CPU) - UINT64 Pat : 1; // PAT - - UINT64 Global : 1; // 0 =3D Not global, 1 =3D Global = (if CR4.PGE =3D 1) - UINT64 Available1 : 3; // Ignored - - UINT64 PageTableBaseAddress : 40; // Page Table Base Address - UINT64 Available3 : 7; // Ignored - UINT64 ProtectionKey : 4; // Protection key - UINT64 Nx : 1; // No Execute bit + UINT32 Present : 1; // 0 =3D Not present in memor= y, 1 =3D Present in memory + UINT32 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read= /Write + UINT32 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser + UINT32 WriteThrough : 1; // 0 =3D Write-Back caching, = 1=3DWrite-Through caching + UINT32 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cach= ed + UINT32 Accessed : 1; // 0 =3D Not accessed, 1 =3D = Accessed (set by CPU) + UINT32 Dirty : 1; // 0 =3D Not dirty, 1 =3D Dir= ty (set by CPU) + UINT32 Pat : 1; // PAT + UINT32 Global : 1; // 0 =3D Not global, 1 =3D Gl= obal (if CR4.PGE =3D 1) + UINT32 Available1 : 3; // Ignored + UINT32 PageTableBaseAddressLow : 20; // Page Table Base Address Low + + UINT32 PageTableBaseAddressHigh : 20; // Page Table Base Address Hi= gh + UINT32 Available3 : 7; // Ignored + UINT32 ProtectionKey : 4; // Protection key + UINT32 Nx : 1; // No Execute bit } Bits; UINT64 Uint64; } IA32_PTE_4K; @@ -149,16 +150,16 @@ typedef union { /// typedef union { struct { - UINT64 Present : 1; // 0 =3D Not present in memory, 1 = =3D Present in memory - UINT64 MustBeZero : 2; // Must Be Zero - UINT64 WriteThrough : 1; // 0 =3D Write-Back caching, 1=3DW= rite-Through caching - UINT64 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cached - UINT64 MustBeZero2 : 4; // Must Be Zero - - UINT64 Available : 3; // Ignored - - UINT64 PageTableBaseAddress : 40; // Page Table Base Address - UINT64 MustBeZero3 : 12; // Must Be Zero + UINT32 Present : 1; // 0 =3D Not present in memor= y, 1 =3D Present in memory + UINT32 MustBeZero : 2; // Must Be Zero + UINT32 WriteThrough : 1; // 0 =3D Write-Back caching, = 1=3DWrite-Through caching + UINT32 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cach= ed + UINT32 MustBeZero2 : 4; // Must Be Zero + UINT32 Available : 3; // Ignored + UINT32 PageTableBaseAddressLow : 20; // Page Table Base Address Low + + UINT32 PageTableBaseAddressHigh : 20; // Page Table Base Address Hi= gh + UINT32 MustBeZero3 : 12; // Must Be Zero } Bits; UINT64 Uint64; } IA32_PDPTE_PAE; diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 885f1601fc..3ea89aacaf 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -26,7 +26,7 @@ PageTableLibSetPte4K ( IN IA32_MAP_ATTRIBUTE *Mask ) { - if (Mask->Bits.PageTableBaseAddress) { + if (Mask->Bits.PageTableBaseAddressLow || Mask->Bits.PageTableBaseAddres= sHigh) { Pte4K->Uint64 =3D (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribu= te) + Offset) | (Pte4K->Uint64 & ~IA32_PE_BASE_ADDRESS_MASK_40); } =20 @@ -93,7 +93,7 @@ PageTableLibSetPleB ( IN IA32_MAP_ATTRIBUTE *Mask ) { - if (Mask->Bits.PageTableBaseAddress) { + if (Mask->Bits.PageTableBaseAddressLow || Mask->Bits.PageTableBaseAddres= sHigh) { PleB->Uint64 =3D (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribut= e) + Offset) | (PleB->Uint64 & ~IA32_PE_BASE_ADDRESS_MASK_39); } =20 @@ -239,7 +239,7 @@ IsAttributesAndMaskValidForNonPresentEntry ( // if ((Mask->Bits.ReadWrite =3D=3D 0) || (Mask->Bits.UserSupervisor =3D= =3D 0) || (Mask->Bits.WriteThrough =3D=3D 0) || (Mask->Bits.CacheDisabled = =3D=3D 0) || (Mask->Bits.Accessed =3D=3D 0) || (Mask->Bits.Dirty =3D=3D 0) || (= Mask->Bits.Pat =3D=3D 0) || (Mask->Bits.Global =3D=3D 0) || - (Mask->Bits.PageTableBaseAddress =3D=3D 0) || (Mask->Bits.Protecti= onKey =3D=3D 0) || (Mask->Bits.Nx =3D=3D 0)) + ((Mask->Bits.PageTableBaseAddressLow =3D=3D 0) && (Mask->Bits.Page= TableBaseAddressHigh =3D=3D 0)) || (Mask->Bits.ProtectionKey =3D=3D 0) || (= Mask->Bits.Nx =3D=3D 0)) { return RETURN_INVALID_PARAMETER; } @@ -399,7 +399,7 @@ PageTableLibMapInLevel ( // This function is called when the memory length is less than the r= egion length of the parent level. // No need to split the page when the attributes equal. // - if (Mask->Bits.PageTableBaseAddress =3D=3D 0) { + if ((Mask->Bits.PageTableBaseAddressLow =3D=3D 0) && (Mask->Bits.Pag= eTableBaseAddressHigh =3D=3D 0)) { return RETURN_SUCCESS; } =20 @@ -706,7 +706,7 @@ PageTableMap ( return RETURN_INVALID_PARAMETER; } =20 - if ((LinearAddress % SIZE_4KB !=3D 0) || (Length % SIZE_4KB !=3D 0)) { + if (((UINTN)LinearAddress % SIZE_4KB !=3D 0) || ((UINTN)Length % SIZE_4K= B !=3D 0)) { // // LinearAddress and Length should be multiple of 4K. // @@ -750,12 +750,12 @@ PageTableMap ( =20 *IsModified =3D FALSE; =20 - ParentAttribute.Uint64 =3D 0; - ParentAttribute.Bits.PageTableBaseAddress =3D 1; - ParentAttribute.Bits.Present =3D 1; - ParentAttribute.Bits.ReadWrite =3D 1; - ParentAttribute.Bits.UserSupervisor =3D 1; - ParentAttribute.Bits.Nx =3D 0; + ParentAttribute.Uint64 =3D 0; + ParentAttribute.Bits.PageTableBaseAddressLow =3D 1; + ParentAttribute.Bits.Present =3D 1; + ParentAttribute.Bits.ReadWrite =3D 1; + ParentAttribute.Bits.UserSupervisor =3D 1; + ParentAttribute.Bits.Nx =3D 0; =20 // // Query the required buffer size without modifying the page table. --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101741): https://edk2.groups.io/g/devel/message/101741 Mute This Topic: https://groups.io/mt/97818239/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 15:13:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101742+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101742+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679637670; cv=none; d=zohomail.com; s=zohoarc; b=EfUMooiwhcv6QDrGMNymeOLpnsSfcRCz7UzmhDPTLNhhc8GBtrhGhGwlyQBYD2tXLQFcTOozYp4/CdgwxO0SJE80e4cCUOOCu4cV23o+2fioK4pUXeecs8CtedAjpX288vx6zj5D806pGtWnqTPce7cNw+qs38KDfn2IyHHb5SE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679637670; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=4yw6oNESBMaAu2Xis+zVxUm7PRbmhxy3iIn6a4j78pA=; b=cMNGmA9CATz9GD+kpJBAKnGhUBMp1JKKRbMBOiAckke1I3tKZp4bNHviI2RFnFtEHFILRu9RbrJo3M/DRAxddG0BX0AutQ48oAnQ95lcRuG1FdohMuim53zZCBx0XZ3u3XzoC48rWkqWaPB6veYe7rHSPYFFtc0Z+w/YmKEFrjc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101742+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679637670159208.1234243060086; Thu, 23 Mar 2023 23:01:10 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id PDfeYY1788612xyEUulP6kD2; Thu, 23 Mar 2023 23:01:09 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.94534.1679637641374533517 for ; Thu, 23 Mar 2023 23:01:09 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="320094054" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="320094054" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:01:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="1012122284" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="1012122284" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:01:07 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V5 17/22] UefiCpuPkg: Modify UnitTest code since tested API is changed Date: Fri, 24 Mar 2023 14:00:15 +0800 Message-Id: <20230324060020.940-18-dun.tan@intel.com> In-Reply-To: <20230324060020.940-1-dun.tan@intel.com> References: <20230324060020.940-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: aEUnFTqkFPlQMmjr45sIV2Nyx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679637669; bh=wSGP6mkftM+WO4GK+/4S2x41m7hJLuLd/5KsHwFQ/Io=; h=Cc:Date:From:Reply-To:Subject:To; b=wS1OrJvmbl7iV8KLhN4o1bVzKyyy5LTSN74fVl2MLrionK+RZ+ydVTaIlP17viRaRRy A9MkvqStosesxlaHtX78f4yRKRIqP+F1PbmZGtplD4/V+QznrJS8uNDt6tqGAP+5gR83C 585L31ccbkjWvK8gPula6vdKoqnq176GcW8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679637671487100021 Content-Type: text/plain; charset="utf-8" From: Zhiguang Liu Last commit changed the CpuPageTableLib API PageTableMap, unit test code should also be modified. Cc: Eric Dong Reviewed-by: Ray Ni Cc: Rahul Kumar Tested-by: Gerd Hoffmann Acked-by: Gerd Hoffmann Signed-off-by: Zhiguang Liu --- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c = | 38 ++++++++++++++++++-------------------- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c = | 84 +++++++++++++++++++++++++++++++++++++++++++++++-----------------------= -------------- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c = | 4 ++-- 3 files changed, 67 insertions(+), 59 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUni= tTestHost.c b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUn= itTestHost.c index 759da09271..4303095579 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c @@ -422,15 +422,14 @@ TestCaseManualSizeNotMatch ( UINTN MapCount; IA32_PAGING_ENTRY *PagingEntry; =20 - PagingMode =3D Paging4Level; - PageTableBufferSize =3D 0; - PageTable =3D 0; - Buffer =3D NULL; - MapAttribute.Uint64 =3D 0; - MapMask.Uint64 =3D MAX_UINT64; - MapAttribute.Bits.Present =3D 1; - MapAttribute.Bits.ReadWrite =3D 1; - MapAttribute.Bits.PageTableBaseAddress =3D (SIZE_2MB - SIZE_4KB) >> 12; + PagingMode =3D Paging4Level; + PageTableBufferSize =3D 0; + PageTable =3D 0; + Buffer =3D NULL; + MapMask.Uint64 =3D MAX_UINT64; + MapAttribute.Uint64 =3D (SIZE_2MB - SIZE_4KB); + MapAttribute.Bits.Present =3D 1; + MapAttribute.Bits.ReadWrite =3D 1; // // Create Page table to cover [2M-4K, 4M], with ReadWrite =3D 1 // @@ -460,9 +459,9 @@ TestCaseManualSizeNotMatch ( // [2M-4K,2M], R/W =3D 0 // [2M ,4M], R/W =3D 1 // - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)PageTable; = // Get 4 level entry - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(PagingEntry->Pnle.B= its.PageTableBaseAddress << 12); // Get 3 level entry - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(PagingEntry->Pnle.B= its.PageTableBaseAddress << 12); // Get 2 level entry + PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)PageTable; = // Get 4 level entry + PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE= _BASE_ADDRESS (PagingEntry); // Get 3 level entry + PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE= _BASE_ADDRESS (PagingEntry); // Get 2 level entry PagingEntry->Uint64 =3D PagingEntry->Uint64 & (~(UINT64)0x2); MapCount =3D 0; Status =3D PageTableParse (PageTable, PagingMode, NULL, &Ma= pCount); @@ -480,20 +479,19 @@ TestCaseManualSizeNotMatch ( =20 UT_ASSERT_EQUAL (Map[1].LinearAddress, SIZE_2MB); UT_ASSERT_EQUAL (Map[1].Length, SIZE_2MB); - ExpectedMapAttribute.Uint64 =3D MapAttribute.Uint64; - ExpectedMapAttribute.Bits.ReadWrite =3D 1; - ExpectedMapAttribute.Bits.PageTableBaseAddress =3D SIZE_2MB >> 12; + ExpectedMapAttribute.Uint64 =3D MapAttribute.Uint64 + SIZE_4KB; + ExpectedMapAttribute.Bits.ReadWrite =3D 1; UT_ASSERT_EQUAL (Map[1].Attribute.Uint64, ExpectedMapAttribute.Uint64); =20 // // Set Page table [2M-4K, 2M+4K]'s ReadWrite =3D 1, [2M,2M+4K]'s ReadWri= te is already 1 // Just need to set [2M-4K,2M], won't need extra size, so the status sho= uld be success // - MapAttribute.Bits.Present =3D 1; - MapAttribute.Bits.ReadWrite =3D 1; - PageTableBufferSize =3D 0; - MapAttribute.Bits.PageTableBaseAddress =3D (SIZE_2MB - SIZE_4KB) >> 12; - Status =3D PageTableMap (&PageTable, Pag= ingMode, Buffer, &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB * 2, &= MapAttribute, &MapMask, NULL); + MapAttribute.Uint64 =3D SIZE_2MB - SIZE_4KB; + MapAttribute.Bits.Present =3D 1; + MapAttribute.Bits.ReadWrite =3D 1; + PageTableBufferSize =3D 0; + Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB * 2, &MapAttribut= e, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); return UNIT_TEST_PASSED; } diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c index bffd95c898..2db49f7de7 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c @@ -157,7 +157,8 @@ ValidateAndRandomeModifyPageTablePageTableEntry ( ) { UINT64 Index; - UINT64 TempPhysicalBase; + UINT32 PageTableBaseAddressLow; + UINT32 PageTableBaseAddressHigh; IA32_PAGING_ENTRY *ChildPageEntry; UNIT_TEST_STATUS Status; =20 @@ -180,17 +181,21 @@ ValidateAndRandomeModifyPageTablePageTableEntry ( if ((RandomNumber < 100) && RandomBoolean (50)) { RandomNumber++; if (Level =3D=3D 1) { - TempPhysicalBase =3D PagingEntry->Pte4K.Bits.PageTableBaseAddress; + PageTableBaseAddressLow =3D PagingEntry->Pte4K.Bits.PageTableBase= AddressLow; + PageTableBaseAddressHigh =3D PagingEntry->Pte4K.Bits.PageTableBase= AddressHigh; } else { - TempPhysicalBase =3D PagingEntry->PleB.Bits.PageTableBaseAddress; + PageTableBaseAddressLow =3D PagingEntry->PleB.Bits.PageTableBaseA= ddressLow; + PageTableBaseAddressHigh =3D PagingEntry->PleB.Bits.PageTableBaseA= ddressHigh; } =20 PagingEntry->Uint64 =3D (Random64 (0, MAX_UINT64) & mVal= idMaskLeaf[Level].Uint64) | mValidMaskLeafFlag[Level].Uint64; PagingEntry->Pte4K.Bits.Present =3D 1; if (Level =3D=3D 1) { - PagingEntry->Pte4K.Bits.PageTableBaseAddress =3D TempPhysicalBase; + PagingEntry->Pte4K.Bits.PageTableBaseAddressLow =3D PageTableBase= AddressLow; + PagingEntry->Pte4K.Bits.PageTableBaseAddressHigh =3D PageTableBase= AddressHigh; } else { - PagingEntry->PleB.Bits.PageTableBaseAddress =3D TempPhysicalBase; + PagingEntry->PleB.Bits.PageTableBaseAddressLow =3D PageTableBaseA= ddressLow; + PagingEntry->PleB.Bits.PageTableBaseAddressHigh =3D PageTableBaseA= ddressHigh; } =20 if ((PagingEntry->Uint64 & mValidMaskLeaf[Level].Uint64) !=3D Paging= Entry->Uint64) { @@ -212,15 +217,17 @@ ValidateAndRandomeModifyPageTablePageTableEntry ( =20 if ((RandomNumber < 100) && RandomBoolean (50)) { RandomNumber++; - TempPhysicalBase =3D PagingEntry->Pnle.Bits.PageTableBaseAddress; + PageTableBaseAddressLow =3D PagingEntry->PleB.Bits.PageTableBaseAddre= ssLow; + PageTableBaseAddressHigh =3D PagingEntry->PleB.Bits.PageTableBaseAddre= ssHigh; =20 - PagingEntry->Uint64 =3D Random64 (0, MAX_UINT6= 4) & mValidMaskNoLeaf[Level].Uint64; - PagingEntry->Pnle.Bits.Present =3D 1; - PagingEntry->Pnle.Bits.PageTableBaseAddress =3D TempPhysicalBase; + PagingEntry->Uint64 =3D Random64 (0, MAX_U= INT64) & mValidMaskNoLeaf[Level].Uint64; + PagingEntry->Pnle.Bits.Present =3D 1; + PagingEntry->PleB.Bits.PageTableBaseAddressLow =3D PageTableBaseAddre= ssLow; + PagingEntry->PleB.Bits.PageTableBaseAddressHigh =3D PageTableBaseAddre= ssHigh; ASSERT ((PagingEntry->Uint64 & mValidMaskLeafFlag[Level].Uint64) !=3D = mValidMaskLeafFlag[Level].Uint64); } =20 - ChildPageEntry =3D (IA32_PAGING_ENTRY *)(UINTN)((PagingEntry->Pnle.Bits= .PageTableBaseAddress) << 12); + ChildPageEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(IA32_PNLE_PAGE_TABLE_BA= SE_ADDRESS (&PagingEntry->Pnle)); for (Index =3D 0; Index < 512; Index++) { Status =3D ValidateAndRandomeModifyPageTablePageTableEntry (&ChildPage= Entry[Index], Level-1, MaxLeafLevel, Address + (Index<<(9*(Level-1) + 3))); if (Status !=3D UNIT_TEST_PASSED) { @@ -364,10 +371,12 @@ GenerateSingleRandomMapEntry ( } =20 if (mRandomOption & ONLY_ONE_ONE_MAPPING) { - MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress =3D Map= Entrys->Maps[MapsIndex].LinearAddress >> 12; - MapEntrys->Maps[MapsIndex].Mask.Bits.PageTableBaseAddress =3D 0xF= FFFFFFFFF; + MapEntrys->Maps[MapsIndex].Attribute.Uint64 &=3D (~IA32_MAP_ATTRIBUTE_= PAGE_TABLE_BASE_ADDRESS_MASK); + MapEntrys->Maps[MapsIndex].Attribute.Uint64 |=3D MapEntrys->Maps[MapsI= ndex].LinearAddress; + MapEntrys->Maps[MapsIndex].Mask.Uint64 |=3D IA32_MAP_ATTRIBUTE_PA= GE_TABLE_BASE_ADDRESS_MASK; } else { - MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress =3D (Ra= ndom64 (0, (((UINT64)1)<<52) - 1) & AlignedTable[Random32 (0, ARRAY_SIZE (A= lignedTable) -1)])>> 12; + MapEntrys->Maps[MapsIndex].Attribute.Uint64 &=3D (~IA32_MAP_ATTRIBUTE_= PAGE_TABLE_BASE_ADDRESS_MASK); + MapEntrys->Maps[MapsIndex].Attribute.Uint64 |=3D (Random64 (0, (((UINT= 64)1)<<52) - 1) & AlignedTable[Random32 (0, ARRAY_SIZE (AlignedTable) -1)]); } =20 MapEntrys->Count +=3D 1; @@ -414,8 +423,9 @@ CompareEntrysforOnePoint ( // for (Index =3D 0; Index < MapCount; Index++) { if ((Address >=3D Map[Index].LinearAddress) && (Address < (Map[Index].= LinearAddress + Map[Index].Length))) { - AttributeInMap.Uint64 =3D (Map[Index].Attribute.U= int64 & mSupportedBit.Uint64); - AttributeInMap.Bits.PageTableBaseAddress =3D ((Address - Map[Index].= LinearAddress) >> 12) + Map[Index].Attribute.Bits.PageTableBaseAddress; + AttributeInMap.Uint64 =3D (Map[Index].Attribute.Uint64 & mSupported= Bit.Uint64); + AttributeInMap.Uint64 &=3D (~IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDR= ESS_MASK); + AttributeInMap.Uint64 |=3D (Address - Map[Index].LinearAddress + IA3= 2_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&Map[Index].Attribute)) & IA32_MAP= _ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK; break; } } @@ -425,8 +435,10 @@ CompareEntrysforOnePoint ( // for (Index =3D 0; Index < InitMapCount; Index++) { if ((Address >=3D InitMap[Index].LinearAddress) && (Address < (InitMap= [Index].LinearAddress + InitMap[Index].Length))) { - AttributeInInitMap.Uint64 =3D (InitMap[Index].Att= ribute.Uint64 & mSupportedBit.Uint64); - AttributeInInitMap.Bits.PageTableBaseAddress =3D ((Address - InitMap= [Index].LinearAddress) >> 12) + InitMap[Index].Attribute.Bits.PageTableBase= Address; + AttributeInInitMap.Uint64 =3D (InitMap[Index].Attribute.Uint64 & mS= upportedBit.Uint64); + AttributeInInitMap.Uint64 &=3D (~IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_= ADDRESS_MASK); + AttributeInInitMap.Uint64 |=3D (Address - InitMap[Index].LinearAddre= ss + IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&InitMap[Index].Attribute)= ) & IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK; + break; } } @@ -443,8 +455,9 @@ CompareEntrysforOnePoint ( MaskInMapEntrys.Uint64 |=3D MapEntrys->Maps[Index].Mask.Uint64; AttributeInMapEntrys.Uint64 &=3D (~MapEntrys->Maps[Index].Mask.Uint6= 4); AttributeInMapEntrys.Uint64 |=3D (MapEntrys->Maps[Index].Attribute.= Uint64 & MapEntrys->Maps[Index].Mask.Uint64); - if (MapEntrys->Maps[Index].Mask.Bits.PageTableBaseAddress !=3D 0) { - AttributeInMapEntrys.Bits.PageTableBaseAddress =3D ((Address - Map= Entrys->Maps[Index].LinearAddress) >> 12) + MapEntrys->Maps[Index].Attribut= e.Bits.PageTableBaseAddress; + if (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&MapEntrys->Maps[Ind= ex].Mask) !=3D 0) { + AttributeInMapEntrys.Uint64 &=3D (~IA32_MAP_ATTRIBUTE_PAGE_TABLE_B= ASE_ADDRESS_MASK); + AttributeInMapEntrys.Uint64 |=3D (Address - MapEntrys->Maps[Index]= .LinearAddress + IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&MapEntrys->Ma= ps[Index].Attribute)) & IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK; } } } @@ -458,8 +471,8 @@ CompareEntrysforOnePoint ( if ((AttributeInMap.Uint64 & MaskInMapEntrys.Uint64) !=3D (AttributeInMa= pEntrys.Uint64 & MaskInMapEntrys.Uint64)) { DEBUG ((DEBUG_INFO, "=3D=3D=3D=3D=3D=3Ddetailed information begin=3D= =3D=3D=3D=3D\n")); DEBUG ((DEBUG_INFO, "\nError: Detect different attribute on a point wi= th linear address: 0x%lx\n", Address)); - DEBUG ((DEBUG_INFO, "By parsing page table, the point has Attribute 0x= %lx, and map to physical address 0x%lx\n", IA32_MAP_ATTRIBUTE_ATTRIBUTES (&= AttributeInMap) & MaskInMapEntrys.Uint64, AttributeInMap.Bits.PageTableBase= Address)); - DEBUG ((DEBUG_INFO, "While according to inputs, the point should Attri= bute 0x%lx, and should map to physical address 0x%lx\n", IA32_MAP_ATTRIBUTE= _ATTRIBUTES (&AttributeInMapEntrys) & MaskInMapEntrys.Uint64, AttributeInMa= pEntrys.Bits.PageTableBaseAddress)); + DEBUG ((DEBUG_INFO, "By parsing page table, the point has Attribute 0x= %lx, and map to physical address 0x%lx\n", IA32_MAP_ATTRIBUTE_ATTRIBUTES (&= AttributeInMap) & MaskInMapEntrys.Uint64, IA32_MAP_ATTRIBUTE_PAGE_TABLE_BAS= E_ADDRESS (&AttributeInMap))); + DEBUG ((DEBUG_INFO, "While according to inputs, the point should Attri= bute 0x%lx, and should map to physical address 0x%lx\n", IA32_MAP_ATTRIBUTE= _ATTRIBUTES (&AttributeInMapEntrys) & MaskInMapEntrys.Uint64, IA32_MAP_ATTR= IBUTE_PAGE_TABLE_BASE_ADDRESS (&AttributeInMapEntrys))); DEBUG ((DEBUG_INFO, "The total Mask is 0x%lx\n", MaskInMapEntrys.Uint6= 4)); =20 if (MapEntrys->InitCount !=3D 0) { @@ -731,7 +744,7 @@ SingleMapEntryTest ( // if ((Mask->Bits.ReadWrite =3D=3D 0) || (Mask->Bits.UserSupervisor = =3D=3D 0) || (Mask->Bits.WriteThrough =3D=3D 0) || (Mask->Bits.CacheDisable= d =3D=3D 0) || (Mask->Bits.Accessed =3D=3D 0) || (Mask->Bits.Dirty =3D=3D 0) ||= (Mask->Bits.Pat =3D=3D 0) || (Mask->Bits.Global =3D=3D 0) || - (Mask->Bits.PageTableBaseAddress =3D=3D 0) || (Mask->Bits.Protec= tionKey =3D=3D 0) || (Mask->Bits.Nx =3D=3D 0)) + ((Mask->Bits.PageTableBaseAddressLow =3D=3D 0) && (Mask->Bits.Pa= geTableBaseAddressHigh =3D=3D 0)) || (Mask->Bits.ProtectionKey =3D=3D 0) ||= (Mask->Bits.Nx =3D=3D 0)) { RemoveLastMapEntry (MapEntrys); UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); @@ -1016,21 +1029,18 @@ TestCaseforRandomTest ( UT_ASSERT_EQUAL (Random64 (100, 100), 100); UT_ASSERT_TRUE ((Random32 (9, 10) >=3D 9) & (Random32 (9, 10) <=3D 10)); UT_ASSERT_TRUE ((Random64 (9, 10) >=3D 9) & (Random64 (9, 10) <=3D 10)); - - mSupportedBit.Bits.Present =3D 1; - mSupportedBit.Bits.ReadWrite =3D 1; - mSupportedBit.Bits.UserSupervisor =3D 1; - mSupportedBit.Bits.WriteThrough =3D 1; - mSupportedBit.Bits.CacheDisabled =3D 1; - mSupportedBit.Bits.Accessed =3D 1; - mSupportedBit.Bits.Dirty =3D 1; - mSupportedBit.Bits.Pat =3D 1; - mSupportedBit.Bits.Global =3D 1; - mSupportedBit.Bits.Reserved1 =3D 0; - mSupportedBit.Bits.PageTableBaseAddress =3D 0; - mSupportedBit.Bits.Reserved2 =3D 0; - mSupportedBit.Bits.ProtectionKey =3D 0xF; - mSupportedBit.Bits.Nx =3D 1; + mSupportedBit.Uint64 =3D 0; + mSupportedBit.Bits.Present =3D 1; + mSupportedBit.Bits.ReadWrite =3D 1; + mSupportedBit.Bits.UserSupervisor =3D 1; + mSupportedBit.Bits.WriteThrough =3D 1; + mSupportedBit.Bits.CacheDisabled =3D 1; + mSupportedBit.Bits.Accessed =3D 1; + mSupportedBit.Bits.Dirty =3D 1; + mSupportedBit.Bits.Pat =3D 1; + mSupportedBit.Bits.Global =3D 1; + mSupportedBit.Bits.ProtectionKey =3D 0xF; + mSupportedBit.Bits.Nx =3D 1; =20 mRandomOption =3D ((CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT *)Context)->R= andomOption; mNumberIndex =3D 0; diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c index 10fdee2f94..22f179c21f 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c @@ -140,7 +140,7 @@ IsPageTableEntryValid ( UT_ASSERT_EQUAL ((PagingEntry->Uint64 & mValidMaskNoLeaf[Level].Uint64= ), PagingEntry->Uint64); } =20 - ChildPageEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(((UINTN)(PagingEntry->P= nle.Bits.PageTableBaseAddress)) << 12); + ChildPageEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(IA32_PNLE_PAGE_TABLE_BA= SE_ADDRESS (&PagingEntry->Pnle)); for (Index =3D 0; Index < 512; Index++) { Status =3D IsPageTableEntryValid (&ChildPageEntry[Index], Level-1, Max= LeafLevel, Address + (Index<<(9*(Level-1) + 3))); if (Status !=3D UNIT_TEST_PASSED) { @@ -233,7 +233,7 @@ GetEntryFromSubPageTable ( // // Not a leaf // - ChildPageEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(((UINTN)(PagingEntry->P= nle.Bits.PageTableBaseAddress)) << 12); + ChildPageEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(IA32_PNLE_PAGE_TABLE_BA= SE_ADDRESS (&PagingEntry->Pnle)); *Level =3D *Level -1; Index =3D Address >> (*Level * 9 + 3); ASSERT (Index =3D=3D (Index & ((1<< 9) - 1))); --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101742): https://edk2.groups.io/g/devel/message/101742 Mute This Topic: https://groups.io/mt/97818240/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 15:13:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101743+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101743+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679637672; cv=none; d=zohomail.com; s=zohoarc; b=CPCQXKCJYjCpw+4kefSfXiZze7rJUoe/XcXQG83LE4HnURaDcTGZP+pdtiYwfPNc8eFzVKhgbHyWgdDVgchsqDWUO7mlc1oVd+A0OvVbZoU+Fij7SLbQEdmy4JzlRrvYzahE3iaB7xNooTOI/n9kcg9J0klUmHy56oS0kSunYZs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679637672; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=AUH6HSnJEknbY5iZUoVXgICyrFU7jLDH/OPVDLDYLQs=; b=UYMohwFCNSZhzMq5Lq8m60/3aQCk0aT13SNJ6LiuiQTodUI13Tx/WbSRQ3ypHLVQCWijt6pESu9xZX7y5nc3fqOyKcj0G3z50vA9Z9+JPcCIiUX1fykNS/aHVWjO6GGicq+yOruhH+EuCcv3u9gbp3O2v+bEKaMMYcfKE8jfpPg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101743+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679637672440892.6076081458109; Thu, 23 Mar 2023 23:01:12 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id Q3HqYY1788612xmpGJB1Z9u8; Thu, 23 Mar 2023 23:01:11 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.94534.1679637641374533517 for ; Thu, 23 Mar 2023 23:01:11 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="320094066" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="320094066" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:01:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="1012122311" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="1012122311" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:01:09 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V5 18/22] UefiCpuPkg/CpuPageTableLib: Add check for page table creation Date: Fri, 24 Mar 2023 14:00:16 +0800 Message-Id: <20230324060020.940-19-dun.tan@intel.com> In-Reply-To: <20230324060020.940-1-dun.tan@intel.com> References: <20230324060020.940-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: qDL4yy3p4caYwzDzLCVWymN1x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679637671; bh=ZHMpPvDZFd41fIo2nQOIyG6X7E6mZ2lWyv9DzyaUoJQ=; h=Cc:Date:From:Reply-To:Subject:To; b=imi0aH6dvAh0+2dgjUAgCYWOyitAP829pik8RgGF6Bc2fNHGQ57lbWWiLG+dUKCQjxC Gabv1yGCyX/4PVMvqC9M7TbGkGLa+dI6ZV/1+L3wf+aMFRVELLdv6s+cN/+yN6RbBn0wf EVjNMLFTb2mPYLBysKtZ3Y+GsBfgKPB4+u4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679637673430100026 Content-Type: text/plain; charset="utf-8" Add code to compare ParentPagingEntry Attribute&Mask and input Attribute&Mask to decide if new next level page table is needed in non-present ParentPagingEntry condition. This can help avoid unneccessary page table creation. For example, there is a page table in which [0, 1G] is mapped(Lv4[0] ,Lv3[0,0], a non-leaf level4 entry and a leaf level3 entry).And we only want to map [1G, 1G+2M] linear address still as non-present. The expected behaviour should be nothing happens in the process. However, previous code logic doesn't check if ParentPagingEntry Attribute&Mask and input Attribute&Mask are the same in non-present ParentPagingEntry condition. Then a new 4K memory is allocated for Lv2 since 1G+2M is not 1G-aligned. So when ParentPagingEntry is non-present, before allocate 4K memory for next level paging, we also check if ParentPagingEntry Attribute& Mask and input Attribute&Mask are the same. Signed-off-by: Dun Tan Cc: Eric Dong Reviewed-by: Ray Ni Cc: Rahul Kumar Tested-by: Gerd Hoffmann Acked-by: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 3ea89aacaf..ad1e263084 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -361,6 +361,16 @@ PageTableLibMapInLevel ( return Status; } =20 + // + // Check the attribute in ParentPagingEntry is equal to attribute calc= ulated by input Attribue and Mask. + // + PleBAttribute.Uint64 =3D PageTableLibGetPleBMapAttribute (&ParentPagin= gEntry->PleB, ParentAttribute); + if ((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRIBU= TE_ATTRIBUTES (Mask)) + =3D=3D (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATTRI= BUTE_ATTRIBUTES (Mask))) + { + return RETURN_SUCCESS; + } + // // The parent entry is CR3 or PML5E/PML4E/PDPTE/PDE. // It does NOT point to an existing page directory. --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101743): https://edk2.groups.io/g/devel/message/101743 Mute This Topic: https://groups.io/mt/97818241/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 15:13:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101744+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101744+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679637674; cv=none; d=zohomail.com; s=zohoarc; b=SmoQQYMvJQAeIT5fvef1MmEuOKybsvAQzTXaxUXL6ScQR31bZGZr6mHufqCblQrY5O0zP2W/r4ESExuGz3t7ri8GgRVd+JzXwHYf/m9v8fpV7clGDCFRzsb96UxU/YsWEI/ICkssNhe0oCha0jOuSJYJqlA9pnRDmqiCG1b2oz8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679637674; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=NX1ZMkFQaguURuSwwal67CczqzSrBOiKpDPkLpFkALs=; b=IYVg27wVDixMU7pgYalNx6cS3yVN99neO25VtOBwUxd1sVUuK3U0FJfjR4h1JS+jJ2yvzn3yZCIVLWZ+a7WBScq6LFWsFvl7Ey33m0ESHxwuS3FwXDe+Fuv739KasOxLUnIeAubCNcgyvJijpvgYY2Lx8DXrtO9J0OyhQ2Yg8WA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101744+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679637674366241.26028476953093; Thu, 23 Mar 2023 23:01:14 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id dRtiYY1788612xAEvaC8C3MH; Thu, 23 Mar 2023 23:01:13 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.94534.1679637641374533517 for ; Thu, 23 Mar 2023 23:01:13 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="320094074" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="320094074" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:01:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="1012122316" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="1012122316" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:01:11 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V5 19/22] UefiCpuPkg: Combine branch for non-present and leaf ParentEntry Date: Fri, 24 Mar 2023 14:00:17 +0800 Message-Id: <20230324060020.940-20-dun.tan@intel.com> In-Reply-To: <20230324060020.940-1-dun.tan@intel.com> References: <20230324060020.940-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: EYfkVtH1bUxoVy4TGzZHngHdx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679637673; bh=OPVCWVbmdFe2+y4kramXlEjKISqyC9IGC4TUUE7ozkk=; h=Cc:Date:From:Reply-To:Subject:To; b=Nqi5K1IvIGh4+OkPcpdKx+c1O6RiTPtAWtrZW0yeB7a/yvreAwlNcdimWwcOGkWdPWm 0dlwP7m/FGdchDfzaLpqha6hE46opE+PazLm49GBgyJuCf7aX+LgsEchP2/jpWciGoSqN qWuKpzG8y796m0J7wTQEuH9WXnH5Ko+teT4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679637675472100029 Content-Type: text/plain; charset="utf-8" Combine 'if' condition branch for non-present and leaf Parent Entry in PageTableLibMapInLevel. Most steps of these two condition are the same. This commit doesn't change any functionality. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Tested-by: Gerd Hoffmann Acked-by: Gerd Hoffmann Reviewed-by: Ray Ni --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 85 ++++++++++++++++= ++++++++++++++++----------------------------------------------------- 1 file changed, 32 insertions(+), 53 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index ad1e263084..2430f1b37c 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -351,68 +351,45 @@ PageTableLibMapInLevel ( // ParentPagingEntry ONLY is deferenced for checking Present and MustBeO= ne bits // when Modify is FALSE. // - - if (ParentPagingEntry->Pce.Present =3D=3D 0) { - // - // [LinearAddress, LinearAddress + Length] contains non-present range. - // - Status =3D IsAttributesAndMaskValidForNonPresentEntry (Attribute, Mask= ); - if (RETURN_ERROR (Status)) { - return Status; - } - - // - // Check the attribute in ParentPagingEntry is equal to attribute calc= ulated by input Attribue and Mask. - // - PleBAttribute.Uint64 =3D PageTableLibGetPleBMapAttribute (&ParentPagin= gEntry->PleB, ParentAttribute); - if ((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRIBU= TE_ATTRIBUTES (Mask)) - =3D=3D (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATTRI= BUTE_ATTRIBUTES (Mask))) - { - return RETURN_SUCCESS; - } - + if ((ParentPagingEntry->Pce.Present =3D=3D 0) || IsPle (ParentPagingEntr= y, Level + 1)) { // - // The parent entry is CR3 or PML5E/PML4E/PDPTE/PDE. + // When ParentPagingEntry is non-present, parent entry is CR3 or PML5E= /PML4E/PDPTE/PDE. // It does NOT point to an existing page directory. + // When ParentPagingEntry is present, parent entry is leaf PDPTE_1G or= PDE_2M. Split to 2M or 4K pages. + // Note: it's impossible the parent entry is a PTE_4K. // - ASSERT (Buffer =3D=3D NULL || *BufferSize >=3D SIZE_4KB); - CreateNew =3D TRUE; - *BufferSize -=3D SIZE_4KB; - - if (Modify) { - ParentPagingEntry->Uintn =3D (UINTN)Buffer + *BufferSize; - ZeroMem ((VOID *)ParentPagingEntry->Uintn, SIZE_4KB); - // - // Set default attribute bits for PML5E/PML4E/PDPTE/PDE. - // - PageTableLibSetPnle (&ParentPagingEntry->Pnle, &NopAttribute, &AllOn= eMask); - } else { + PleBAttribute.Uint64 =3D PageTableLibGetPleBMapAttribute (&ParentPagin= gEntry->PleB, ParentAttribute); + if (ParentPagingEntry->Pce.Present =3D=3D 0) { // - // Just make sure Present and MustBeZero (PageSize) bits are accurat= e. + // [LinearAddress, LinearAddress + Length] contains non-present rang= e. // + Status =3D IsAttributesAndMaskValidForNonPresentEntry (Attribute, Ma= sk); + if (RETURN_ERROR (Status)) { + return Status; + } + OneOfPagingEntry.Pnle.Uint64 =3D 0; + } else { + PageTableLibSetPle (Level, &OneOfPagingEntry, 0, &PleBAttribute, &Al= lOneMask); } - } else if (IsPle (ParentPagingEntry, Level + 1)) { - // - // The parent entry is a PDPTE_1G or PDE_2M. Split to 2M or 4K pages. - // Note: it's impossible the parent entry is a PTE_4K. - // + // - // Use NOP attributes as the attribute of grand-parents because CPU wi= ll consider - // the actual attributes of grand-parents when determing the memory ty= pe. + // Check if the attribute, the physical address calculated by ParentPa= gingEntry is equal to + // the attribute, the physical address calculated by input Attribue an= d Mask. // - PleBAttribute.Uint64 =3D PageTableLibGetPleBMapAttribute (&ParentPagin= gEntry->PleB, ParentAttribute); if ((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRIBU= TE_ATTRIBUTES (Mask)) =3D=3D (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATTRI= BUTE_ATTRIBUTES (Mask))) { - // - // This function is called when the memory length is less than the r= egion length of the parent level. - // No need to split the page when the attributes equal. - // if ((Mask->Bits.PageTableBaseAddressLow =3D=3D 0) && (Mask->Bits.Pag= eTableBaseAddressHigh =3D=3D 0)) { return RETURN_SUCCESS; } =20 + // + // Non-present entry won't reach there since: + // 1.When map non-present entry to present, the attribute must be di= fferent. + // 2.When still map non-present entry to non-present, PageTableBaseA= ddressLow and High in Mask must be 0. + // + ASSERT (ParentPagingEntry->Pce.Present =3D=3D 1); PhysicalAddrInEntry =3D IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (= &PleBAttribute) + (UINT64)PagingEntryIndex * RegionLength; PhysicalAddrInAttr =3D (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS = (Attribute) + Offset) & (~RegionMask); if (PhysicalAddrInEntry =3D=3D PhysicalAddrInAttr) { @@ -423,17 +400,19 @@ PageTableLibMapInLevel ( ASSERT (Buffer =3D=3D NULL || *BufferSize >=3D SIZE_4KB); CreateNew =3D TRUE; *BufferSize -=3D SIZE_4KB; - PageTableLibSetPle (Level, &OneOfPagingEntry, 0, &PleBAttribute, &AllO= neMask); + if (Modify) { - // - // Create 512 child-level entries that map to 2M/4K. - // PagingEntry =3D (IA32_PAGING_ENTRY *)((UINTN)Buffer + *BufferSize); ZeroMem (PagingEntry, SIZE_4KB); =20 - for (SubOffset =3D 0, Index =3D 0; Index < 512; Index++) { - PagingEntry[Index].Uint64 =3D OneOfPagingEntry.Uint64 + SubOffset; - SubOffset +=3D RegionLength; + if (ParentPagingEntry->Pce.Present) { + // + // Create 512 child-level entries that map to 2M/4K. + // + for (SubOffset =3D 0, Index =3D 0; Index < 512; Index++) { + PagingEntry[Index].Uint64 =3D OneOfPagingEntry.Uint64 + SubOffse= t; + SubOffset +=3D RegionLength; + } } =20 // --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101744): https://edk2.groups.io/g/devel/message/101744 Mute This Topic: https://groups.io/mt/97818242/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 15:13:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101745+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101745+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679637677; cv=none; d=zohomail.com; s=zohoarc; b=mUSgfokPfQKKWlw5IqJWYctblTtgqYdC1iO5bucnVoX9HfiCojtCy7Y6XBJX6ZXParYTR3Q4XMgTLgReqLDll1o950Ir8DXH+JJ394mKllSJmUhIJ/Quw7gE2gzwb8H2Uay2h0rIKk7Ispqy4/Wo56sMzbkdYW2I7qSGduH0eb8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679637677; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=rWgUCj5jbZbZcyVFlgorIQH0+Ak2dqlb+NZXbgbdzTI=; b=DiAqwIO/BN0OqyvbBCT51+rXuLI2mvvpZo1hJZNO9fB+lOA3Lf0Zi7l4lx4JPz1ryE5kybD314zE4aI7KQnrMtrNoXbz5WqRUYbRFm8xm7n1tWv6XaheRv1M2Lcq7udzdvd3zRL5er5cN6Z5np2Zfm+vwNWjaXYZo1adCmOBV1w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101745+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679637677098173.21194330097921; Thu, 23 Mar 2023 23:01:17 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id IixXYY1788612xTbZ5rB98cy; Thu, 23 Mar 2023 23:01:16 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.94534.1679637641374533517 for ; Thu, 23 Mar 2023 23:01:15 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="320094086" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="320094086" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:01:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="1012122321" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="1012122321" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:01:13 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V5 20/22] UefiCpuPkg/CpuPageTableLib: Enable PAE paging Date: Fri, 24 Mar 2023 14:00:18 +0800 Message-Id: <20230324060020.940-21-dun.tan@intel.com> In-Reply-To: <20230324060020.940-1-dun.tan@intel.com> References: <20230324060020.940-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: hAWoeE5Qh9290POKcqvtcdV1x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679637676; bh=9hhJaEX9ulETnM0A2Q7bkHczUCyNoCqanaGhrLTEETs=; h=Cc:Date:From:Reply-To:Subject:To; b=FcFNA9jq/Wa3N/reO3OKxxq3BVWaLIPVANMKM4bvqqc9xeP+kP7H9/6BvlNDU6ipjKd dSm1si9ItYZ8VxYgthYSCFNPOBjNY5/lw/PFC8saGcpDx+2BacD2UL4sVzVZl7BDZcO1p YAUDgJnmx1LanXjgneVQR8GfjwgOnPhiQ7o= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679637677488100032 Content-Type: text/plain; charset="utf-8" Modify CpuPageTableLib code to enable PAE paging. In PageTableMap() API: When creating new PAE page table, after creating page table, set all MustBeZero fields of 4 PDPTE to 0. The MustBeZero fields are treated as RW and other attributes by the common map logic. So they might be set to 1. When updating exsiting PAE page table, the special steps are: 1.Prepare 4K-aligned 32bytes memory in stack for 4 temp PDPTE. 2.Copy original 4 PDPTE to the 4 temp PDPTE and set the RW, UserSupervisor to 1 and set Nx of 4 temp PDPTE to 0. 4.After updating the page table, set the MustBeZero fields of 4 temp PDPTE to 0. 5.Copy the temp PDPTE to original PDPTE. In PageTableParse() API, also create 4 temp PDPTE in stack. Copy original 4 PDPTE to the 4 temp PDPTE. Then set the RW, UserSupervisor to 1 and set Nx of 4 temp PDPTE to 0. Finally use the address of temp PDPTE as the page table address. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Tested-by: Gerd Hoffmann Acked-by: Gerd Hoffmann Reviewed-by: Ray Ni --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h | 2 ++ UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 53 ++++++++++++++= ++++++++++++++++++++++++++++++++++----- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableParse.c | 25 ++++++++++++++= +++++++---- 3 files changed, 71 insertions(+), 9 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h b/UefiCpuPkg= /Library/CpuPageTableLib/CpuPageTable.h index 2c67ecb469..8c4d43be89 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h @@ -20,6 +20,8 @@ =20 #define REGION_LENGTH(l) LShiftU64 (1, (l) * 9 + 3) =20 +#define MAX_PAE_PDPTE_NUM 4 + typedef enum { Pte =3D 1, Pde =3D 2, diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 2430f1b37c..7cdba0d77f 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -671,15 +671,17 @@ PageTableMap ( IA32_PAGE_LEVEL MaxLeafLevel; IA32_MAP_ATTRIBUTE ParentAttribute; BOOLEAN LocalIsModified; + UINTN Index; + IA32_PAGING_ENTRY *PagingEntry; + UINT8 BufferInStack[SIZE_4KB - 1 + MAX_PAE_PDPTE_NUM * siz= eof (IA32_PAGING_ENTRY)]; =20 if (Length =3D=3D 0) { return RETURN_SUCCESS; } =20 - if ((PagingMode =3D=3D Paging32bit) || (PagingMode =3D=3D PagingPae) || = (PagingMode >=3D PagingModeMax)) { + if ((PagingMode =3D=3D Paging32bit) || (PagingMode >=3D PagingModeMax)) { // // 32bit paging is never supported. - // PAE paging will be supported later. // return RETURN_UNSUPPORTED; } @@ -716,17 +718,32 @@ PageTableMap ( =20 MaxLeafLevel =3D (IA32_PAGE_LEVEL)(UINT8)PagingMode; MaxLevel =3D (IA32_PAGE_LEVEL)(UINT8)(PagingMode >> 8); - MaxLinearAddress =3D LShiftU64 (1, 12 + MaxLevel * 9); + MaxLinearAddress =3D (PagingMode =3D=3D PagingPae) ? LShiftU64 (1, 32) := LShiftU64 (1, 12 + MaxLevel * 9); =20 if ((LinearAddress > MaxLinearAddress) || (Length > MaxLinearAddress - L= inearAddress)) { // - // Maximum linear address is (1 << 48) or (1 << 57) + // Maximum linear address is (1 << 32), (1 << 48) or (1 << 57) // return RETURN_INVALID_PARAMETER; } =20 TopPagingEntry.Uintn =3D *PageTable; if (TopPagingEntry.Uintn !=3D 0) { + if (PagingMode =3D=3D PagingPae) { + // + // Create 4 temporary PDPTE at a 4k-aligned address. + // Copy the original PDPTE content and set ReadWrite, UserSupervisor= to 1, set Nx to 0. + // + TopPagingEntry.Uintn =3D ALIGN_VALUE ((UINTN)BufferInStack, BASE_4KB= ); + PagingEntry =3D (IA32_PAGING_ENTRY *)(TopPagingEntry.Uintn); + CopyMem (PagingEntry, (VOID *)(*PageTable), MAX_PAE_PDPTE_NUM * size= of (IA32_PAGING_ENTRY)); + for (Index =3D 0; Index < MAX_PAE_PDPTE_NUM; Index++) { + PagingEntry[Index].Pnle.Bits.ReadWrite =3D 1; + PagingEntry[Index].Pnle.Bits.UserSupervisor =3D 1; + PagingEntry[Index].Pnle.Bits.Nx =3D 0; + } + } + TopPagingEntry.Pce.Present =3D 1; TopPagingEntry.Pce.ReadWrite =3D 1; TopPagingEntry.Pce.UserSupervisor =3D 1; @@ -801,7 +818,33 @@ PageTableMap ( ); =20 if (!RETURN_ERROR (Status)) { - *PageTable =3D (UINTN)(TopPagingEntry.Uintn & IA32_PE_BASE_ADDRESS_MAS= K_40); + PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(TopPagingEntry.Uintn & IA= 32_PE_BASE_ADDRESS_MASK_40); + + if (PagingMode =3D=3D PagingPae) { + // + // These MustBeZero fields are treated as RW and other attributes by= the common map logic. So they might be set to 1. + // + for (Index =3D 0; Index < MAX_PAE_PDPTE_NUM; Index++) { + PagingEntry[Index].PdptePae.Bits.MustBeZero =3D 0; + PagingEntry[Index].PdptePae.Bits.MustBeZero2 =3D 0; + PagingEntry[Index].PdptePae.Bits.MustBeZero3 =3D 0; + } + + if (*PageTable !=3D 0) { + // + // Copy temp PDPTE to original PDPTE. + // + CopyMem ((VOID *)(*PageTable), PagingEntry, MAX_PAE_PDPTE_NUM * si= zeof (IA32_PAGING_ENTRY)); + } + } + + if (*PageTable =3D=3D 0) { + // + // Do not assign the *PageTable when it's an existing page table. + // If it's an existing PAE page table, PagingEntry is the temp buffe= r in stack. + // + *PageTable =3D (UINTN)PagingEntry; + } } =20 return Status; diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableParse.c b/UefiC= puPkg/Library/CpuPageTableLib/CpuPageTableParse.c index 65490751ab..f6d7b9bb4c 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableParse.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableParse.c @@ -158,6 +158,7 @@ VOID PageTableLibParsePnle ( IN UINT64 PageTableBaseAddress, IN UINTN Level, + IN UINTN MaxLevel, IN UINT64 RegionStart, IN IA32_MAP_ATTRIBUTE *ParentMapAttribute, IN OUT IA32_MAP_ENTRY *Map, @@ -171,13 +172,15 @@ PageTableLibParsePnle ( UINTN Index; IA32_MAP_ATTRIBUTE MapAttribute; UINT64 RegionLength; + UINTN PagingEntryNumber; =20 ASSERT (OneEntry !=3D NULL); =20 - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)PageTableBaseAddress; - RegionLength =3D REGION_LENGTH (Level); + PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)PageTableBaseAddress; + RegionLength =3D REGION_LENGTH (Level); + PagingEntryNumber =3D ((MaxLevel =3D=3D 3) && (Level =3D=3D 3)) ? MAX_PA= E_PDPTE_NUM : 512; =20 - for (Index =3D 0; Index < 512; Index++, RegionStart +=3D RegionLength) { + for (Index =3D 0; Index < PagingEntryNumber; Index++, RegionStart +=3D R= egionLength) { if (PagingEntry[Index].Pce.Present =3D=3D 0) { continue; } @@ -228,6 +231,7 @@ PageTableLibParsePnle ( PageTableLibParsePnle ( IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&PagingEntry[Index].Pnle), Level - 1, + MaxLevel, RegionStart, &MapAttribute, Map, @@ -269,6 +273,8 @@ PageTableParse ( IA32_MAP_ENTRY *LastEntry; IA32_MAP_ENTRY OneEntry; UINTN MaxLevel; + UINTN Index; + IA32_PAGING_ENTRY BufferInStack[MAX_PAE_PDPTE_NUM]; =20 if ((PagingMode =3D=3D Paging32bit) || (PagingMode >=3D PagingModeMax)) { // @@ -290,6 +296,17 @@ PageTableParse ( return RETURN_SUCCESS; } =20 + if (PagingMode =3D=3D PagingPae) { + CopyMem (BufferInStack, (VOID *)PageTable, sizeof (BufferInStack)); + for (Index =3D 0; Index < MAX_PAE_PDPTE_NUM; Index++) { + BufferInStack[Index].Pnle.Bits.ReadWrite =3D 1; + BufferInStack[Index].Pnle.Bits.UserSupervisor =3D 1; + BufferInStack[Index].Pnle.Bits.Nx =3D 0; + } + + PageTable =3D (UINTN)BufferInStack; + } + // // Page table layout is as below: // @@ -319,7 +336,7 @@ PageTableParse ( MapCapacity =3D *MapCount; *MapCount =3D 0; LastEntry =3D NULL; - PageTableLibParsePnle ((UINT64)PageTable, MaxLevel, 0, &NopAttribute, Ma= p, MapCount, MapCapacity, &LastEntry, &OneEntry); + PageTableLibParsePnle ((UINT64)PageTable, MaxLevel, MaxLevel, 0, &NopAtt= ribute, Map, MapCount, MapCapacity, &LastEntry, &OneEntry); =20 if (*MapCount > MapCapacity) { return RETURN_BUFFER_TOO_SMALL; --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101745): https://edk2.groups.io/g/devel/message/101745 Mute This Topic: https://groups.io/mt/97818243/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 15:13:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101746+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101746+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679637681; cv=none; d=zohomail.com; s=zohoarc; b=Euv07NnJ8fhay8NtfVgFKdGXhSA1CfdKP7Aw0HwzfO/h5QBc/q4BKQsSm3hlMDib2u0WUhrTE1I6adeS6fJHyUPjXAXnQR8pM+YrvLdEUrLzjyqE9zs/C9MzH/Zp99mH6Wb0xp+dgvallyvUAAPKwu1b+/k0mIkJIIXb53dhVDw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679637681; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=WfaISIVnaxF1e6aH0F+BI3FQcVi7J/BvL5CANiMXdLY=; b=kokfv7UavsaklHz8X3KamJSbbZge4M3C4FV4ibZVYUaRVm90uLRQzZEM1+bH459hCAgCy5HFVM9BJvM5heTg+veCPIiJnyQx3zyCB6E9f4zS3kLg0Drtn3vqDIUuRRqYxynmLAIOhwy5TLIGJ3sLiPiRbfOAv6JOBhhKU2suRfQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101746+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 167963768147750.845971032957436; Thu, 23 Mar 2023 23:01:21 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id Apz1YY1788612xvsv8pBkofu; Thu, 23 Mar 2023 23:01:21 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.94534.1679637641374533517 for ; Thu, 23 Mar 2023 23:01:20 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="320094102" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="320094102" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:01:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="1012122343" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="1012122343" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:01:18 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V5 21/22] UefiCpuPkg/CpuPageTableLib: Add RandomTest for PAE paging Date: Fri, 24 Mar 2023 14:00:19 +0800 Message-Id: <20230324060020.940-22-dun.tan@intel.com> In-Reply-To: <20230324060020.940-1-dun.tan@intel.com> References: <20230324060020.940-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: paECyDULJIFpcHVTwDkST73jx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679637681; bh=33eALp0PXmcOJ4hR2EtdTZ9Hdvy+rCvxMzaNgtcDSTw=; h=Cc:Date:From:Reply-To:Subject:To; b=YrgAnr2DqLG74iOIb8Rp7zInAvGh2PpH5wcwCiWPoxqAj5crfmDAJMHgZSR8/TFDLXk 2nLA120pyv4MPBoZ2UimmY9reFq3jwLMRhPqP3sOmVmwlTZQZaT1cOZa26ZmvaUygv7Co qHa4jQGbKNcEONO/jkLvCogy50Y3929o4sM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679637683436100001 Content-Type: text/plain; charset="utf-8" Add RandomTest for PAE paging. Signed-off-by: Dun Tan Cc: Eric Dong Reviewed-by: Ray Ni Cc: Rahul Kumar Tested-by: Gerd Hoffmann Acked-by: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c = | 2 ++ UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c = | 3 +-- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c = | 12 ++++++++---- 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUni= tTestHost.c b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUn= itTestHost.c index 4303095579..d3fb9e2fcb 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c @@ -9,6 +9,7 @@ #include "CpuPageTableLibUnitTest.h" =20 // -----------------------------------------------------------------------= PageMode--TestCount-TestRangeCount---RandomOptions +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPagingPae = =3D { PagingPae, 100, 20, USE_RANDOM_ARRAY }; static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging4Level = =3D { Paging4Level, 100, 20, USE_RANDOM_ARRAY }; static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging4Level1GB= =3D { Paging4Level1GB, 100, 20, USE_RANDOM_ARRAY }; static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging5Level = =3D { Paging5Level, 100, 20, USE_RANDOM_ARRAY }; @@ -880,6 +881,7 @@ UefiTestMain ( goto EXIT; } =20 + AddTestCase (RandomTestCase, "Random Test for PagingPae", "Random Test C= ase1", TestCaseforRandomTest, NULL, NULL, &mTestContextPagingPae); AddTestCase (RandomTestCase, "Random Test for Paging4Level", "Random Tes= t Case1", TestCaseforRandomTest, NULL, NULL, &mTestContextPaging4Level); AddTestCase (RandomTestCase, "Random Test for Paging4Level1G", "Random T= est Case2", TestCaseforRandomTest, NULL, NULL, &mTestContextPaging4Level1GB= ); AddTestCase (RandomTestCase, "Random Test for Paging5Level", "Random Tes= t Case3", TestCaseforRandomTest, NULL, NULL, &mTestContextPaging5Level); diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c index 2db49f7de7..f7a77d00e7 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c @@ -258,10 +258,9 @@ ValidateAndRandomeModifyPageTable ( UNIT_TEST_STATUS Status; IA32_PAGING_ENTRY *PagingEntry; =20 - if ((PagingMode =3D=3D Paging32bit) || (PagingMode =3D=3D PagingPae) || = (PagingMode >=3D PagingModeMax)) { + if ((PagingMode =3D=3D Paging32bit) || (PagingMode >=3D PagingModeMax)) { // // 32bit paging is never supported. - // PAE paging will be supported later. // return UNIT_TEST_ERROR_TEST_FAILED; } diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c index 22f179c21f..67776255c2 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c @@ -175,10 +175,9 @@ IsPageTableValid ( return UNIT_TEST_PASSED; } =20 - if ((PagingMode =3D=3D Paging32bit) || (PagingMode =3D=3D PagingPae) || = (PagingMode >=3D PagingModeMax)) { + if ((PagingMode =3D=3D Paging32bit) || (PagingMode >=3D PagingModeMax)) { // // 32bit paging is never supported. - // PAE paging will be supported later. // return UNIT_TEST_ERROR_TEST_FAILED; } @@ -187,7 +186,12 @@ IsPageTableValid ( MaxLevel =3D (UINT8)(PagingMode >> 8); =20 PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)PageTable; - for (Index =3D 0; Index < 512; Index++) { + for (Index =3D 0; Index < ((PagingMode =3D=3D PagingPae) ? 4 : 512); Ind= ex++) { + if (PagingMode =3D=3D PagingPae) { + UT_ASSERT_EQUAL (PagingEntry[Index].PdptePae.Bits.MustBeZero, 0); + UT_ASSERT_EQUAL (PagingEntry[Index].PdptePae.Bits.MustBeZero2, 0); + } + Status =3D IsPageTableEntryValid (&PagingEntry[Index], MaxLevel, MaxLe= afLevel, Index << (9 * MaxLevel + 3)); if (Status !=3D UNIT_TEST_PASSED) { return Status; @@ -264,7 +268,7 @@ GetEntryFromPageTable ( UINT64 Index; IA32_PAGING_ENTRY *PagingEntry; =20 - if ((PagingMode =3D=3D Paging32bit) || (PagingMode =3D=3D PagingPae) || = (PagingMode >=3D PagingModeMax)) { + if ((PagingMode =3D=3D Paging32bit) || (PagingMode >=3D PagingModeMax)) { // // 32bit paging is never supported. // PAE paging will be supported later. --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101746): https://edk2.groups.io/g/devel/message/101746 Mute This Topic: https://groups.io/mt/97818244/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 15:13:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101747+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101747+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679637683; cv=none; d=zohomail.com; s=zohoarc; b=BCcFFszEV6wDvWxu3QV02wS0lnpXSZvdxaSvSLnh2HdjOvxifrO4n7oG1FHwfQl6V4F8BizxMiHSVlZnsLsnsm7Yud17hrHmnukReuP5pESzOytC8xofVbaWnkhkQYLXyNHnBIhA3SipjN+vATY4PdRpw0vl/sFzJJWcS58hZ68= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679637683; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=NPXvKvgvFqwFe1Uti21yHtc9KEBwVgtpb3ZvoTjva8A=; b=Eqha/BN/brsxojC6udldB8BePcuZ+aopNdIdYqlSADZbt/9NYMihHCAULXhqd5sxNLeyCs1Jv+YxGBTQsztplQkor8zf4iYlip/raEi0bv7Pph9FFoDzL2KMCyn8muALp7RFT6kfjqFIBoGP3rM6mAPmsc4VjJB56mdNz/n2FAc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101747+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679637683752367.78856881738625; Thu, 23 Mar 2023 23:01:23 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id whXtYY1788612xqAOJG2c5PP; Thu, 23 Mar 2023 23:01:23 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.94534.1679637641374533517 for ; Thu, 23 Mar 2023 23:01:22 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="320094106" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="320094106" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:01:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="1012122349" X-IronPort-AV: E=Sophos;i="5.98,286,1673942400"; d="scan'208";a="1012122349" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 23:01:21 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V5 22/22] UefiCpuPkg/CpuPageTableLib: Reduce the number of random tests Date: Fri, 24 Mar 2023 14:00:20 +0800 Message-Id: <20230324060020.940-23-dun.tan@intel.com> In-Reply-To: <20230324060020.940-1-dun.tan@intel.com> References: <20230324060020.940-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: rUZuCGtcq0gzujXsgIEv3yrHx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679637683; bh=saTe5Sw6S79DSw4PTnEJuI3ATOZW/gIWSfgbIaU3giw=; h=Cc:Date:From:Reply-To:Subject:To; b=P7bGejLKADqPuidjQfDwOzE26rLNh3h9vKGgC1BFlEz9TmHpDiWeQRHdMVR0wW9vQgV owAlSkcCfCN/JZCjVw9YHbiMUg7Sm3qxOIl32x3PdoDy/6VB/uKWixzJ5V4wkxiTOIGtd 4XEiYplTo75Qx1R/0meW+VFy6YjJd5Vg6gI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679637685487100006 Content-Type: text/plain; charset="utf-8" Reduce the number of random tests. In previous patch, non-1:1 mapping is enbaled and it may need more than an hour and a half for the CI test, which may lead to CI timeout. Reduce the number of random test count to pass the CI. Signed-off-by: Dun Tan Cc: Eric Dong Reviewed-by: Ray Ni Cc: Rahul Kumar Tested-by: Gerd Hoffmann Acked-by: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c = | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUni= tTestHost.c b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUn= itTestHost.c index d3fb9e2fcb..dad106008e 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c @@ -9,11 +9,11 @@ #include "CpuPageTableLibUnitTest.h" =20 // -----------------------------------------------------------------------= PageMode--TestCount-TestRangeCount---RandomOptions -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPagingPae = =3D { PagingPae, 100, 20, USE_RANDOM_ARRAY }; -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging4Level = =3D { Paging4Level, 100, 20, USE_RANDOM_ARRAY }; -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging4Level1GB= =3D { Paging4Level1GB, 100, 20, USE_RANDOM_ARRAY }; -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging5Level = =3D { Paging5Level, 100, 20, USE_RANDOM_ARRAY }; -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging5Level1GB= =3D { Paging5Level1GB, 100, 20, USE_RANDOM_ARRAY }; +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPagingPae = =3D { PagingPae, 30, 20, USE_RANDOM_ARRAY }; +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging4Level = =3D { Paging4Level, 30, 20, USE_RANDOM_ARRAY }; +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging4Level1GB= =3D { Paging4Level1GB, 30, 20, USE_RANDOM_ARRAY }; +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging5Level = =3D { Paging5Level, 30, 20, USE_RANDOM_ARRAY }; +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging5Level1GB= =3D { Paging5Level1GB, 30, 20, USE_RANDOM_ARRAY }; =20 /** Check if the input parameters are not supported. --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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