From nobody Mon Sep 16 19:28:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101646+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101646+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679557317; cv=none; d=zohomail.com; s=zohoarc; b=SU3c5PXjezsHec6XY0grqsAl9lPJo1id326SbJJbtF2Eze1sHExZQovMm26MX4MS2nXL8FVItOyzsoixx7ji9GBuhNsFDFB/5yGNY2E1gN0ykrr/fpgrboq7IyBMAvZWGLmyGWzPJX/0SuVdzuiN8DOOoITb/Lm34IaLd392scg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679557317; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=+qN+JLQp8ykvDPSsVI19kDju4JIMHP2lT7D8yZmah20=; b=ABm3NthOkC9zBs/4CBJx0rpUsF7dtS1BlDIhs53r8xYLM3EURAaADz/VjVIceAcIjcpwF+jN967cWNc1zbmeqbHeO+4fjaCqAUDALV5emeej+ujiyv8tXwE4o8ipP+HhcJb36KNaJrHEQYJurglHpEn7YYR04M6Yxu8v1ZgaVLY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101646+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679557317473799.6921945211985; Thu, 23 Mar 2023 00:41:57 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id A29mYY1788612xGbJM3PYCeQ; Thu, 23 Mar 2023 00:41:57 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.66779.1679557305298569223 for ; Thu, 23 Mar 2023 00:41:56 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="425699856" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="425699856" X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="684616891" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="684616891" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:54 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V4 18/21] UefiCpuPkg: Combine branch for non-present and leaf ParentEntry Date: Thu, 23 Mar 2023 15:40:54 +0800 Message-Id: <20230323074057.549-19-dun.tan@intel.com> In-Reply-To: <20230323074057.549-1-dun.tan@intel.com> References: <20230323074057.549-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: o9ZXMK2rVjnw8cpLVCk8vKClx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679557317; bh=BK/Um7jOD4bv5b0O4P1Y4sazTX/TdXJHA/5JB5r77Uw=; h=Cc:Date:From:Reply-To:Subject:To; b=i168Drh/o80+RabtXeHikK9lWKf+2FjxlRcLzdqR1MC1Zda0QHQlw5uenQ2/jzKwKxW LEO1tYC16K6GRjPI3Nie7ySCDPac8pNzH+Hz187ajJNpGbzI+ci1yXjF3xPOxYBlLO3vR CDpcBcmlt87afbfXjlPbDD6dEvyPvLBqDt0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679557317766100022 Content-Type: text/plain; charset="utf-8" Combine 'if' condition branch for non-present and leaf Parent Entry in PageTableLibMapInLevel. Most steps of these two condition are the same. This commit doesn't change any functionality. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 83 ++++++++++++++++= +++++++++++++++---------------------------------------------------- 1 file changed, 31 insertions(+), 52 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 55a756ad90..773948349e 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -348,68 +348,45 @@ PageTableLibMapInLevel ( // ParentPagingEntry ONLY is deferenced for checking Present and MustBeO= ne bits // when Modify is FALSE. // - - if (ParentPagingEntry->Pce.Present =3D=3D 0) { - // - // [LinearAddress, LinearAddress + Length] contains non-present range. - // - Status =3D IsAttributesAndMaskValidForNonPresentEntry (Attribute, Mask= ); - if (RETURN_ERROR (Status)) { - return Status; - } - + if ((ParentPagingEntry->Pce.Present =3D=3D 0) || IsPle (ParentPagingEntr= y, Level + 1)) { // - // Check the attribute in ParentPagingEntry is equal to attribute calc= ulated by input Attribue and Mask. - // - PleBAttribute.Uint64 =3D PageTableLibGetPleBMapAttribute (&ParentPagin= gEntry->PleB, ParentAttribute); - if ((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRIBU= TE_ATTRIBUTES (Mask)) - =3D=3D (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATTRI= BUTE_ATTRIBUTES (Mask))) - { - return RETURN_SUCCESS; - } - - // - // The parent entry is CR3 or PML5E/PML4E/PDPTE/PDE. + // When ParentPagingEntry is non-present, parent entry is CR3 or PML5E= /PML4E/PDPTE/PDE. // It does NOT point to an existing page directory. + // When ParentPagingEntry is present, parent entry is leaf PDPTE_1G or= PDE_2M. Split to 2M or 4K pages. + // Note: it's impossible the parent entry is a PTE_4K. // - ASSERT (Buffer =3D=3D NULL || *BufferSize >=3D SIZE_4KB); - CreateNew =3D TRUE; - *BufferSize -=3D SIZE_4KB; + OneOfPagingEntry.Pnle.Uint64 =3D 0; + PleBAttribute.Uint64 =3D PageTableLibGetPleBMapAttribute (&Par= entPagingEntry->PleB, ParentAttribute); =20 - if (Modify) { - ParentPagingEntry->Uintn =3D (UINTN)Buffer + *BufferSize; - ZeroMem ((VOID *)ParentPagingEntry->Uintn, SIZE_4KB); + if (ParentPagingEntry->Pce.Present =3D=3D 0) { // - // Set default attribute bits for PML5E/PML4E/PDPTE/PDE. + // [LinearAddress, LinearAddress + Length] contains non-present rang= e. // - PageTableLibSetPnle (&ParentPagingEntry->Pnle, &NopAttribute, &AllOn= eMask); + Status =3D IsAttributesAndMaskValidForNonPresentEntry (Attribute, Ma= sk); + if (RETURN_ERROR (Status)) { + return Status; + } } else { - // - // Just make sure Present and MustBeZero (PageSize) bits are accurat= e. - // - OneOfPagingEntry.Pnle.Uint64 =3D 0; + PageTableLibSetPle (Level, &OneOfPagingEntry, 0, &PleBAttribute, &Al= lOneMask); } - } else if (IsPle (ParentPagingEntry, Level + 1)) { - // - // The parent entry is a PDPTE_1G or PDE_2M. Split to 2M or 4K pages. - // Note: it's impossible the parent entry is a PTE_4K. - // + // - // Use NOP attributes as the attribute of grand-parents because CPU wi= ll consider - // the actual attributes of grand-parents when determing the memory ty= pe. + // Check if the attribute, the physical address calculated by ParentPa= gingEntry is equal to + // the attribute, the physical address calculated by input Attribue an= d Mask. // - PleBAttribute.Uint64 =3D PageTableLibGetPleBMapAttribute (&ParentPagin= gEntry->PleB, ParentAttribute); if ((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRIBU= TE_ATTRIBUTES (Mask)) =3D=3D (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATTRI= BUTE_ATTRIBUTES (Mask))) { - // - // This function is called when the memory length is less than the r= egion length of the parent level. - // No need to split the page when the attributes equal. - // if ((Mask->Bits.PageTableBaseAddressLow =3D=3D 0) && (Mask->Bits.Pag= eTableBaseAddressHigh =3D=3D 0)) { return RETURN_SUCCESS; } =20 + // + // Non-present entry won't reach there since: + // 1.When map non-present entry to present, the attribute must be di= fferent. + // 2.When still map non-present entry to non-present, PageTableBaseA= ddressLow and High in Mask must be 0. + // + ASSERT (ParentPagingEntry->Pce.Present =3D=3D 1); PhysicalAddrInEntry =3D IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (= &PleBAttribute) + PagingEntryIndex * RegionLength; PhysicalAddrInAttr =3D (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS = (Attribute) + Offset) & (~RegionMask); if (PhysicalAddrInEntry =3D=3D PhysicalAddrInAttr) { @@ -420,17 +397,19 @@ PageTableLibMapInLevel ( ASSERT (Buffer =3D=3D NULL || *BufferSize >=3D SIZE_4KB); CreateNew =3D TRUE; *BufferSize -=3D SIZE_4KB; - PageTableLibSetPle (Level, &OneOfPagingEntry, 0, &PleBAttribute, &AllO= neMask); + if (Modify) { - // - // Create 512 child-level entries that map to 2M/4K. - // PagingEntry =3D (IA32_PAGING_ENTRY *)((UINTN)Buffer + *BufferSize); ZeroMem (PagingEntry, SIZE_4KB); =20 - for (SubOffset =3D 0, Index =3D 0; Index < 512; Index++) { - PagingEntry[Index].Uint64 =3D OneOfPagingEntry.Uint64 + SubOffset; - SubOffset +=3D RegionLength; + if (ParentPagingEntry->Pce.Present) { + // + // Create 512 child-level entries that map to 2M/4K. + // + for (SubOffset =3D 0, Index =3D 0; Index < 512; Index++) { + PagingEntry[Index].Uint64 =3D OneOfPagingEntry.Uint64 + SubOffse= t; + SubOffset +=3D RegionLength; + } } =20 // --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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