From nobody Mon Sep 16 19:39:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101644+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101644+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679557312; cv=none; d=zohomail.com; s=zohoarc; b=HGgXChS95ZRQ6GVWGXo+4XtHewTi8+8nPAas4XGp7+x1jRmdQnUmUJ6nFxygtj4FMRgICjG332YND19J+yxRD+/OFnJXoOWBThU4oLRE5UkV2bkw4N8Holy6HgH0TveiCKh+nBvoPl8fxkJ8hlSUla9i+L6dshqoRKa4aaCWA1s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679557312; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=NesqCWs2EPEjF+UyIOphUIbMpX4vvOi8TuA5C3+bUjo=; b=CGFM9X0MwquG0Wp1Q2wBOqKzJ/QPCgo1UkTzMpFmyzFL55QJPvouS4BmBw+GJTuLk6rTgh0NoRE5p6/aSKtnMCvgSt56AxNZzb/NfPy0t9rIGOjyAZwFEuZx2mYy9h1VrOZ2cqcOQEeTg6UZDt5YX41DDNwK6ETjaeV8kBcBdzs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101644+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679557312904238.61222413075677; Thu, 23 Mar 2023 00:41:52 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 28hJYY1788612xxQ94s64ZNo; Thu, 23 Mar 2023 00:41:52 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.66779.1679557305298569223 for ; Thu, 23 Mar 2023 00:41:52 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="425699812" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="425699812" X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="684616880" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="684616880" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:50 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar Subject: [edk2-devel] [Patch V4 16/21] UefiCpuPkg: Modify UnitTest code since tested API is changed Date: Thu, 23 Mar 2023 15:40:52 +0800 Message-Id: <20230323074057.549-17-dun.tan@intel.com> In-Reply-To: <20230323074057.549-1-dun.tan@intel.com> References: <20230323074057.549-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: IF9K02H6Mg61rmiunhvsaSZpx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679557312; bh=ZFZ9zAPK2eM+mkiBQ8wbJzQRjIaTlryl/pXwN1F5R4o=; h=Cc:Date:From:Reply-To:Subject:To; b=vlNlVhQGSbGZpHL1RX1Y7N6Be6sejn75Or0Zmz+tWIHJL4Wbor6DdXoc2D4flBEWFjn aKjySnJDmKVLvFoAH2T9a9q3bj1hII3nsdrkrrVX+xsAjKhD5Al0NMf8z8NxBvH2dfL8P KysV0DzEs8m9on6s1GC/WUfTQn/L9UOu1Ng= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679557317057100015 Content-Type: text/plain; charset="utf-8" From: Zhiguang Liu Last commit changed the CpuPageTableLib API PageTableMap, unit test code should also be modified. Cc: Eric Dong Reviewed-by: Ray Ni Cc: Rahul Kumar Signed-off-by: Zhiguang Liu --- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c = | 38 ++++++++++++++++++-------------------- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c = | 84 +++++++++++++++++++++++++++++++++++++++++++++++-----------------------= -------------- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c = | 4 ++-- 3 files changed, 67 insertions(+), 59 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUni= tTestHost.c b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUn= itTestHost.c index 6343b56c2f..e1efc84c82 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c @@ -422,15 +422,14 @@ TestCaseManualSizeNotMatch ( UINTN MapCount; IA32_PAGING_ENTRY *PagingEntry; =20 - PagingMode =3D Paging4Level; - PageTableBufferSize =3D 0; - PageTable =3D 0; - Buffer =3D NULL; - MapAttribute.Uint64 =3D 0; - MapMask.Uint64 =3D MAX_UINT64; - MapAttribute.Bits.Present =3D 1; - MapAttribute.Bits.ReadWrite =3D 1; - MapAttribute.Bits.PageTableBaseAddress =3D (SIZE_2MB - SIZE_4KB) >> 12; + PagingMode =3D Paging4Level; + PageTableBufferSize =3D 0; + PageTable =3D 0; + Buffer =3D NULL; + MapMask.Uint64 =3D MAX_UINT64; + MapAttribute.Uint64 =3D (SIZE_2MB - SIZE_4KB); + MapAttribute.Bits.Present =3D 1; + MapAttribute.Bits.ReadWrite =3D 1; // // Create Page table to cover [2M-4K, 4M], with ReadWrite =3D 1 // @@ -460,9 +459,9 @@ TestCaseManualSizeNotMatch ( // [2M-4K,2M], R/W =3D 0 // [2M ,4M], R/W =3D 1 // - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)PageTable; = // Get 4 level entry - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(PagingEntry->Pnle.B= its.PageTableBaseAddress << 12); // Get 3 level entry - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(PagingEntry->Pnle.B= its.PageTableBaseAddress << 12); // Get 2 level entry + PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)PageTable; = // Get 4 level entry + PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE= _BASE_ADDRESS (PagingEntry); // Get 3 level entry + PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE= _BASE_ADDRESS (PagingEntry); // Get 2 level entry PagingEntry->Uint64 =3D PagingEntry->Uint64 & (~(UINT64)0x2); MapCount =3D 0; Status =3D PageTableParse (PageTable, PagingMode, NULL, &Ma= pCount); @@ -480,20 +479,19 @@ TestCaseManualSizeNotMatch ( =20 UT_ASSERT_EQUAL (Map[1].LinearAddress, SIZE_2MB); UT_ASSERT_EQUAL (Map[1].Length, SIZE_2MB); - ExpectedMapAttribute.Uint64 =3D MapAttribute.Uint64; - ExpectedMapAttribute.Bits.ReadWrite =3D 1; - ExpectedMapAttribute.Bits.PageTableBaseAddress =3D SIZE_2MB >> 12; + ExpectedMapAttribute.Uint64 =3D MapAttribute.Uint64 + SIZE_4KB; + ExpectedMapAttribute.Bits.ReadWrite =3D 1; UT_ASSERT_EQUAL (Map[1].Attribute.Uint64, ExpectedMapAttribute.Uint64); =20 // // Set Page table [2M-4K, 2M+4K]'s ReadWrite =3D 1, [2M,2M+4K]'s ReadWri= te is already 1 // Just need to set [2M-4K,2M], won't need extra size, so the status sho= uld be success // - MapAttribute.Bits.Present =3D 1; - MapAttribute.Bits.ReadWrite =3D 1; - PageTableBufferSize =3D 0; - MapAttribute.Bits.PageTableBaseAddress =3D (SIZE_2MB - SIZE_4KB) >> 12; - Status =3D PageTableMap (&PageTable, Pag= ingMode, Buffer, &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB * 2, &= MapAttribute, &MapMask, NULL); + MapAttribute.Uint64 =3D SIZE_2MB - SIZE_4KB; + MapAttribute.Bits.Present =3D 1; + MapAttribute.Bits.ReadWrite =3D 1; + PageTableBufferSize =3D 0; + Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB * 2, &MapAttribut= e, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); return UNIT_TEST_PASSED; } diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c index 6f1485976a..18a5010c30 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c @@ -157,7 +157,8 @@ ValidateAndRandomeModifyPageTablePageTableEntry ( ) { UINT64 Index; - UINT64 TempPhysicalBase; + UINT32 PageTableBaseAddressLow; + UINT32 PageTableBaseAddressHigh; IA32_PAGING_ENTRY *ChildPageEntry; UNIT_TEST_STATUS Status; =20 @@ -180,17 +181,21 @@ ValidateAndRandomeModifyPageTablePageTableEntry ( if ((RandomNumber < 100) && RandomBoolean (50)) { RandomNumber++; if (Level =3D=3D 1) { - TempPhysicalBase =3D PagingEntry->Pte4K.Bits.PageTableBaseAddress; + PageTableBaseAddressLow =3D PagingEntry->Pte4K.Bits.PageTableBase= AddressLow; + PageTableBaseAddressHigh =3D PagingEntry->Pte4K.Bits.PageTableBase= AddressHigh; } else { - TempPhysicalBase =3D PagingEntry->PleB.Bits.PageTableBaseAddress; + PageTableBaseAddressLow =3D PagingEntry->PleB.Bits.PageTableBaseA= ddressLow; + PageTableBaseAddressHigh =3D PagingEntry->PleB.Bits.PageTableBaseA= ddressHigh; } =20 PagingEntry->Uint64 =3D (Random64 (0, MAX_UINT64) & mVal= idMaskLeaf[Level].Uint64) | mValidMaskLeafFlag[Level].Uint64; PagingEntry->Pte4K.Bits.Present =3D 1; if (Level =3D=3D 1) { - PagingEntry->Pte4K.Bits.PageTableBaseAddress =3D TempPhysicalBase; + PagingEntry->Pte4K.Bits.PageTableBaseAddressLow =3D PageTableBase= AddressLow; + PagingEntry->Pte4K.Bits.PageTableBaseAddressHigh =3D PageTableBase= AddressHigh; } else { - PagingEntry->PleB.Bits.PageTableBaseAddress =3D TempPhysicalBase; + PagingEntry->PleB.Bits.PageTableBaseAddressLow =3D PageTableBaseA= ddressLow; + PagingEntry->PleB.Bits.PageTableBaseAddressHigh =3D PageTableBaseA= ddressHigh; } =20 if ((PagingEntry->Uint64 & mValidMaskLeaf[Level].Uint64) !=3D Paging= Entry->Uint64) { @@ -212,15 +217,17 @@ ValidateAndRandomeModifyPageTablePageTableEntry ( =20 if ((RandomNumber < 100) && RandomBoolean (50)) { RandomNumber++; - TempPhysicalBase =3D PagingEntry->Pnle.Bits.PageTableBaseAddress; + PageTableBaseAddressLow =3D PagingEntry->PleB.Bits.PageTableBaseAddre= ssLow; + PageTableBaseAddressHigh =3D PagingEntry->PleB.Bits.PageTableBaseAddre= ssHigh; =20 - PagingEntry->Uint64 =3D Random64 (0, MAX_UINT6= 4) & mValidMaskNoLeaf[Level].Uint64; - PagingEntry->Pnle.Bits.Present =3D 1; - PagingEntry->Pnle.Bits.PageTableBaseAddress =3D TempPhysicalBase; + PagingEntry->Uint64 =3D Random64 (0, MAX_U= INT64) & mValidMaskNoLeaf[Level].Uint64; + PagingEntry->Pnle.Bits.Present =3D 1; + PagingEntry->PleB.Bits.PageTableBaseAddressLow =3D PageTableBaseAddre= ssLow; + PagingEntry->PleB.Bits.PageTableBaseAddressHigh =3D PageTableBaseAddre= ssHigh; ASSERT ((PagingEntry->Uint64 & mValidMaskLeafFlag[Level].Uint64) !=3D = mValidMaskLeafFlag[Level].Uint64); } =20 - ChildPageEntry =3D (IA32_PAGING_ENTRY *)(UINTN)((PagingEntry->Pnle.Bits= .PageTableBaseAddress) << 12); + ChildPageEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(IA32_PNLE_PAGE_TABLE_BA= SE_ADDRESS (&PagingEntry->Pnle)); for (Index =3D 0; Index < 512; Index++) { Status =3D ValidateAndRandomeModifyPageTablePageTableEntry (&ChildPage= Entry[Index], Level-1, MaxLeafLevel, Address + (Index<<(9*(Level-1) + 3))); if (Status !=3D UNIT_TEST_PASSED) { @@ -364,10 +371,12 @@ GenerateSingleRandomMapEntry ( } =20 if (mRandomOption & ONLY_ONE_ONE_MAPPING) { - MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress =3D Map= Entrys->Maps[MapsIndex].LinearAddress >> 12; - MapEntrys->Maps[MapsIndex].Mask.Bits.PageTableBaseAddress =3D 0xF= FFFFFFFFF; + MapEntrys->Maps[MapsIndex].Attribute.Uint64 &=3D (~IA32_MAP_ATTRIBUTE_= PAGE_TABLE_BASE_ADDRESS_MASK); + MapEntrys->Maps[MapsIndex].Attribute.Uint64 |=3D MapEntrys->Maps[MapsI= ndex].LinearAddress; + MapEntrys->Maps[MapsIndex].Mask.Uint64 |=3D IA32_MAP_ATTRIBUTE_PA= GE_TABLE_BASE_ADDRESS_MASK; } else { - MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress =3D (Ra= ndom64 (0, (((UINT64)1)<<52) - 1) & AlignedTable[Random32 (0, ARRAY_SIZE (A= lignedTable) -1)])>> 12; + MapEntrys->Maps[MapsIndex].Attribute.Uint64 &=3D (~IA32_MAP_ATTRIBUTE_= PAGE_TABLE_BASE_ADDRESS_MASK); + MapEntrys->Maps[MapsIndex].Attribute.Uint64 |=3D (Random64 (0, (((UINT= 64)1)<<52) - 1) & AlignedTable[Random32 (0, ARRAY_SIZE (AlignedTable) -1)]); } =20 MapEntrys->Count +=3D 1; @@ -414,8 +423,9 @@ CompareEntrysforOnePoint ( // for (Index =3D 0; Index < MapCount; Index++) { if ((Address >=3D Map[Index].LinearAddress) && (Address < (Map[Index].= LinearAddress + Map[Index].Length))) { - AttributeInMap.Uint64 =3D (Map[Index].Attribute.U= int64 & mSupportedBit.Uint64); - AttributeInMap.Bits.PageTableBaseAddress =3D ((Address - Map[Index].= LinearAddress) >> 12) + Map[Index].Attribute.Bits.PageTableBaseAddress; + AttributeInMap.Uint64 =3D (Map[Index].Attribute.Uint64 & mSupported= Bit.Uint64); + AttributeInMap.Uint64 &=3D (~IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDR= ESS_MASK); + AttributeInMap.Uint64 |=3D (Address - Map[Index].LinearAddress + IA3= 2_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&Map[Index].Attribute)) & IA32_MAP= _ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK; break; } } @@ -425,8 +435,10 @@ CompareEntrysforOnePoint ( // for (Index =3D 0; Index < InitMapCount; Index++) { if ((Address >=3D InitMap[Index].LinearAddress) && (Address < (InitMap= [Index].LinearAddress + InitMap[Index].Length))) { - AttributeInInitMap.Uint64 =3D (InitMap[Index].Att= ribute.Uint64 & mSupportedBit.Uint64); - AttributeInInitMap.Bits.PageTableBaseAddress =3D ((Address - InitMap= [Index].LinearAddress) >> 12) + InitMap[Index].Attribute.Bits.PageTableBase= Address; + AttributeInInitMap.Uint64 =3D (InitMap[Index].Attribute.Uint64 & mS= upportedBit.Uint64); + AttributeInInitMap.Uint64 &=3D (~IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_= ADDRESS_MASK); + AttributeInInitMap.Uint64 |=3D (Address - InitMap[Index].LinearAddre= ss + IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&InitMap[Index].Attribute)= ) & IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK; + break; } } @@ -443,8 +455,9 @@ CompareEntrysforOnePoint ( MaskInMapEntrys.Uint64 |=3D MapEntrys->Maps[Index].Mask.Uint64; AttributeInMapEntrys.Uint64 &=3D (~MapEntrys->Maps[Index].Mask.Uint6= 4); AttributeInMapEntrys.Uint64 |=3D (MapEntrys->Maps[Index].Attribute.= Uint64 & MapEntrys->Maps[Index].Mask.Uint64); - if (MapEntrys->Maps[Index].Mask.Bits.PageTableBaseAddress !=3D 0) { - AttributeInMapEntrys.Bits.PageTableBaseAddress =3D ((Address - Map= Entrys->Maps[Index].LinearAddress) >> 12) + MapEntrys->Maps[Index].Attribut= e.Bits.PageTableBaseAddress; + if (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&MapEntrys->Maps[Ind= ex].Mask) !=3D 0) { + AttributeInMapEntrys.Uint64 &=3D (~IA32_MAP_ATTRIBUTE_PAGE_TABLE_B= ASE_ADDRESS_MASK); + AttributeInMapEntrys.Uint64 |=3D (Address - MapEntrys->Maps[Index]= .LinearAddress + IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&MapEntrys->Ma= ps[Index].Attribute)) & IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK; } } } @@ -458,8 +471,8 @@ CompareEntrysforOnePoint ( if ((AttributeInMap.Uint64 & MaskInMapEntrys.Uint64) !=3D (AttributeInMa= pEntrys.Uint64 & MaskInMapEntrys.Uint64)) { DEBUG ((DEBUG_INFO, "=3D=3D=3D=3D=3D=3Ddetailed information begin=3D= =3D=3D=3D=3D\n")); DEBUG ((DEBUG_INFO, "\nError: Detect different attribute on a point wi= th linear address: 0x%lx\n", Address)); - DEBUG ((DEBUG_INFO, "By parsing page table, the point has Attribute 0x= %lx, and map to physical address 0x%lx\n", IA32_MAP_ATTRIBUTE_ATTRIBUTES (&= AttributeInMap) & MaskInMapEntrys.Uint64, AttributeInMap.Bits.PageTableBase= Address)); - DEBUG ((DEBUG_INFO, "While according to inputs, the point should Attri= bute 0x%lx, and should map to physical address 0x%lx\n", IA32_MAP_ATTRIBUTE= _ATTRIBUTES (&AttributeInMapEntrys) & MaskInMapEntrys.Uint64, AttributeInMa= pEntrys.Bits.PageTableBaseAddress)); + DEBUG ((DEBUG_INFO, "By parsing page table, the point has Attribute 0x= %lx, and map to physical address 0x%lx\n", IA32_MAP_ATTRIBUTE_ATTRIBUTES (&= AttributeInMap) & MaskInMapEntrys.Uint64, IA32_MAP_ATTRIBUTE_PAGE_TABLE_BAS= E_ADDRESS (&AttributeInMap))); + DEBUG ((DEBUG_INFO, "While according to inputs, the point should Attri= bute 0x%lx, and should map to physical address 0x%lx\n", IA32_MAP_ATTRIBUTE= _ATTRIBUTES (&AttributeInMapEntrys) & MaskInMapEntrys.Uint64, IA32_MAP_ATTR= IBUTE_PAGE_TABLE_BASE_ADDRESS (&AttributeInMapEntrys))); DEBUG ((DEBUG_INFO, "The total Mask is 0x%lx\n", MaskInMapEntrys.Uint6= 4)); =20 if (MapEntrys->InitCount !=3D 0) { @@ -728,7 +741,7 @@ SingleMapEntryTest ( // if ((Mask->Bits.ReadWrite =3D=3D 0) || (Mask->Bits.UserSupervisor = =3D=3D 0) || (Mask->Bits.WriteThrough =3D=3D 0) || (Mask->Bits.CacheDisable= d =3D=3D 0) || (Mask->Bits.Accessed =3D=3D 0) || (Mask->Bits.Dirty =3D=3D 0) ||= (Mask->Bits.Pat =3D=3D 0) || (Mask->Bits.Global =3D=3D 0) || - (Mask->Bits.PageTableBaseAddress =3D=3D 0) || (Mask->Bits.Protec= tionKey =3D=3D 0) || (Mask->Bits.Nx =3D=3D 0)) + ((Mask->Bits.PageTableBaseAddressLow =3D=3D 0) && (Mask->Bits.Pa= geTableBaseAddressHigh =3D=3D 0)) || (Mask->Bits.ProtectionKey =3D=3D 0) ||= (Mask->Bits.Nx =3D=3D 0)) { RemoveLastMapEntry (MapEntrys); UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); @@ -1013,21 +1026,18 @@ TestCaseforRandomTest ( UT_ASSERT_EQUAL (Random64 (100, 100), 100); UT_ASSERT_TRUE ((Random32 (9, 10) >=3D 9) & (Random32 (9, 10) <=3D 10)); UT_ASSERT_TRUE ((Random64 (9, 10) >=3D 9) & (Random64 (9, 10) <=3D 10)); - - mSupportedBit.Bits.Present =3D 1; - mSupportedBit.Bits.ReadWrite =3D 1; - mSupportedBit.Bits.UserSupervisor =3D 1; - mSupportedBit.Bits.WriteThrough =3D 1; - mSupportedBit.Bits.CacheDisabled =3D 1; - mSupportedBit.Bits.Accessed =3D 1; - mSupportedBit.Bits.Dirty =3D 1; - mSupportedBit.Bits.Pat =3D 1; - mSupportedBit.Bits.Global =3D 1; - mSupportedBit.Bits.Reserved1 =3D 0; - mSupportedBit.Bits.PageTableBaseAddress =3D 0; - mSupportedBit.Bits.Reserved2 =3D 0; - mSupportedBit.Bits.ProtectionKey =3D 0xF; - mSupportedBit.Bits.Nx =3D 1; + mSupportedBit.Uint64 =3D 0; + mSupportedBit.Bits.Present =3D 1; + mSupportedBit.Bits.ReadWrite =3D 1; + mSupportedBit.Bits.UserSupervisor =3D 1; + mSupportedBit.Bits.WriteThrough =3D 1; + mSupportedBit.Bits.CacheDisabled =3D 1; + mSupportedBit.Bits.Accessed =3D 1; + mSupportedBit.Bits.Dirty =3D 1; + mSupportedBit.Bits.Pat =3D 1; + mSupportedBit.Bits.Global =3D 1; + mSupportedBit.Bits.ProtectionKey =3D 0xF; + mSupportedBit.Bits.Nx =3D 1; =20 mRandomOption =3D ((CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT *)Context)->R= andomOption; mNumberIndex =3D 0; diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c index 10fdee2f94..22f179c21f 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c @@ -140,7 +140,7 @@ IsPageTableEntryValid ( UT_ASSERT_EQUAL ((PagingEntry->Uint64 & mValidMaskNoLeaf[Level].Uint64= ), PagingEntry->Uint64); } =20 - ChildPageEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(((UINTN)(PagingEntry->P= nle.Bits.PageTableBaseAddress)) << 12); + ChildPageEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(IA32_PNLE_PAGE_TABLE_BA= SE_ADDRESS (&PagingEntry->Pnle)); for (Index =3D 0; Index < 512; Index++) { Status =3D IsPageTableEntryValid (&ChildPageEntry[Index], Level-1, Max= LeafLevel, Address + (Index<<(9*(Level-1) + 3))); if (Status !=3D UNIT_TEST_PASSED) { @@ -233,7 +233,7 @@ GetEntryFromSubPageTable ( // // Not a leaf // - ChildPageEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(((UINTN)(PagingEntry->P= nle.Bits.PageTableBaseAddress)) << 12); + ChildPageEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(IA32_PNLE_PAGE_TABLE_BA= SE_ADDRESS (&PagingEntry->Pnle)); *Level =3D *Level -1; Index =3D Address >> (*Level * 9 + 3); ASSERT (Index =3D=3D (Index & ((1<< 9) - 1))); --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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