From nobody Sat Apr 20 10:58:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101629+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101629+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679557272; cv=none; d=zohomail.com; s=zohoarc; b=HNuPQb828XE59k/23ViOSBDAVXyTkV1Pq/LkWFdQAdJh9JX5WTFzQpc0V/SkU4EOfZt/XxZTeGot8fNtRZYqJkOM6RkIlGslmJ/YDEuOpiMIz3hScTTPAIgdFLWRtS6qVbNitqXTUGNWdF610RXsoV5S7k5W0PbzgzIpsUgb/as= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679557272; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=oCSaTcku02DZyUfhmKFL81QPxWLwe+3LFIruYTfISV8=; b=VpnWTEIU2tP3xJXjX/xUUZ1vmrTLVt87Uu81vNgiufenMIT1YnNdufpYITgi7ebuWNxFHJYf6vw7ePYtULHjXvr3MITJDMhEKJvXstP8wQ4QO7Odh6cR/b6BR2qsJRoJvBuvvRsuueHKxpIeeYefudStbtySMxi+MokIOymI61k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101629+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679557271997821.6572537737801; Thu, 23 Mar 2023 00:41:11 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id FJU5YY1788612xOFzLEWfZM3; Thu, 23 Mar 2023 00:41:11 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.67098.1679557268568440146 for ; Thu, 23 Mar 2023 00:41:10 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="425699461" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="425699461" X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="684616804" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="684616804" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:09 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V4 01/21] UefiCpuPkg/CpuPageTableLib: Remove unneeded 'if' condition Date: Thu, 23 Mar 2023 15:40:37 +0800 Message-Id: <20230323074057.549-2-dun.tan@intel.com> In-Reply-To: <20230323074057.549-1-dun.tan@intel.com> References: <20230323074057.549-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: D8jYszMtpFdIyAP3ZaNEiTDnx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679557271; bh=4AQDVLMcWPAb2IfyhVR56Z0bgp9CfVbDhh11o99GGHA=; h=Cc:Date:From:Reply-To:Subject:To; b=qIkztn+pj3gu/ae82ikTA/aXdY1KFxfgOfgOiDykbQReM0FL2yZwPW6Pc0vAlZKwhkZ mhrne/0RIwdYNU5Yz2YvqQ2XogN0JAJ2Yz0glP2wjb6RE4/zJLil3mMryOvobhTrNHP6T XUfz50vFLP2G/fL8/zPGlAAblK8mdnYpsY4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679557272189100006 Content-Type: text/plain; charset="utf-8" Remove unneeded 'if' condition in CpuPageTableLib code. The deleted code is in the code branch for present non-leaf parent entry. So the 'if' check for (ParentPagingEntry->Pnle.Bits.Present =3D=3D 0) is always FALSE. Signed-off-by: Dun Tan Cc: Eric Dong Reviewed-by: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Tested-by: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 37713ec659..52535e5a8d 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -1,7 +1,7 @@ /** @file This library implements CpuPageTableLib that are generic for IA32 family= CPU. =20 - Copyright (c) 2022, Intel Corporation. All rights reserved.
+ Copyright (c) 2022 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -375,15 +375,6 @@ PageTableLibMapInLevel ( // we need to change PDPTE[0].ReadWrite =3D 1 and let all P= DE[0-255].ReadWrite =3D 0 in this step. // when PDPTE[0].Nx =3D 1 but caller wants to map [0-2MB] as Nx = =3D 0 (PDT[0].Nx =3D 0) // we need to change PDPTE[0].Nx =3D 0 and let all PDE[0-25= 5].Nx =3D 1 in this step. - if ((ParentPagingEntry->Pnle.Bits.Present =3D=3D 0) && (Mask->Bits.Pre= sent =3D=3D 1) && (Attribute->Bits.Present =3D=3D 1)) { - if (Modify) { - ParentPagingEntry->Pnle.Bits.Present =3D 1; - } - - ChildAttribute.Bits.Present =3D 0; - ChildMask.Bits.Present =3D 1; - } - if ((ParentPagingEntry->Pnle.Bits.ReadWrite =3D=3D 0) && (Mask->Bits.R= eadWrite =3D=3D 1) && (Attribute->Bits.ReadWrite =3D=3D 1)) { if (Modify) { ParentPagingEntry->Pnle.Bits.ReadWrite =3D 1; --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101629): https://edk2.groups.io/g/devel/message/101629 Mute This Topic: https://groups.io/mt/97796373/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 10:58:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101630+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101630+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679557274; cv=none; d=zohomail.com; s=zohoarc; b=h8PX3BSOBsDhFdEa0u5X2dVeK3YLSqDjq1EU+Kp9WhwXjQ6+YAXMGpFObvLSBOtrrKSI1Z+stQFKpWPdsd6UCs34suuGAmYIILnMHYQ2XE/u4e8siaBp2ZnKNNGp+MOtCrRXLUhnLmarWDLa4V/2KvkzLOQ4a5qgz6ck/4XSlSI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679557274; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=2FURtc8ZkL2VVZUdQRGC4EVoL/8nIqJE2DiiRN7ZlEs=; b=PN77JG4xpZCmLi567F4TtdXsVGtJt54uNA+DNfhJJ6wFugPcIhRQXM+R0Vm3WC36In/Csqo/v4VO0Pi46GXVwtKWG4h1DbkoIPrEMBzQZaUpVtoR+a3iDLnTtfXZ7op0gzS3B5i/icW3IilsGAhat1VxrFkEeyxW/ZrPfni9J4g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101630+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679557274438190.89269593523738; Thu, 23 Mar 2023 00:41:14 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id gjhSYY1788612xsmVPDPUpz1; Thu, 23 Mar 2023 00:41:14 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.67098.1679557268568440146 for ; Thu, 23 Mar 2023 00:41:13 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="425699490" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="425699490" X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="684616809" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="684616809" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:11 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V4 02/21] UefiCpuPkg/CpuPageTableLib: Add check for input Length Date: Thu, 23 Mar 2023 15:40:38 +0800 Message-Id: <20230323074057.549-3-dun.tan@intel.com> In-Reply-To: <20230323074057.549-1-dun.tan@intel.com> References: <20230323074057.549-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: mvuAIMcpRpXaOuaV7b7WIHLdx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679557274; bh=Rt7yXJ134d7PUJPyfWrdRcM/OjA3MoK0MWP/E4J1Sz0=; h=Cc:Date:From:Reply-To:Subject:To; b=bYe/TEQrIQYsqzgfeurvwxk49Lu4WJVcf+TVkp6TpDw+CeLG/3qXUpav/QTl2j2lNEA aCbbvtuJKQ9rg/N+wKBsKGioJg6i8LuKDpIbzH+Q5dxZcGHsGGU0yD4vO4iD3UDFiSqjK nu0ncOivkEZgjyYsrPeLdDHfNqYSf62yASA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679557276236100002 Content-Type: text/plain; charset="utf-8" Add check for input Length in PageTableMap (). Return RETURN_SUCCESS when input Length is 0. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Reviewed-by: Ray Ni Tested-by: Gerd Hoffmann --- UefiCpuPkg/Include/Library/CpuPageTableLib.h | 4 ++-- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 6 +++++- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/UefiCpuPkg/Include/Library/CpuPageTableLib.h b/UefiCpuPkg/Incl= ude/Library/CpuPageTableLib.h index 2dc9b7d18e..5f44ece548 100644 --- a/UefiCpuPkg/Include/Library/CpuPageTableLib.h +++ b/UefiCpuPkg/Include/Library/CpuPageTableLib.h @@ -1,7 +1,7 @@ /** @file Public include file for PageTableLib library. =20 - Copyright (c) 2022, Intel Corporation. All rights reserved.
+ Copyright (c) 2022 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -81,7 +81,7 @@ typedef enum { @retval RETURN_BUFFER_TOO_SMALL The buffer is too small for page table= creation/updating. BufferSize is updated to indicate the = expected buffer size. Caller may still get RETURN_BUFFER_TOO= _SMALL with the new BufferSize. - @retval RETURN_SUCCESS PageTable is created/updated successfu= lly. + @retval RETURN_SUCCESS PageTable is created/updated successfu= lly or the input Length is 0. **/ RETURN_STATUS EFIAPI diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 52535e5a8d..218068a3e1 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -544,7 +544,7 @@ PageTableLibMapInLevel ( @retval RETURN_BUFFER_TOO_SMALL The buffer is too small for page table= creation/updating. BufferSize is updated to indicate the = expected buffer size. Caller may still get RETURN_BUFFER_TOO= _SMALL with the new BufferSize. - @retval RETURN_SUCCESS PageTable is created/updated successfu= lly. + @retval RETURN_SUCCESS PageTable is created/updated successfu= lly or the input Length is 0. **/ RETURN_STATUS EFIAPI @@ -567,6 +567,10 @@ PageTableMap ( IA32_PAGE_LEVEL MaxLeafLevel; IA32_MAP_ATTRIBUTE ParentAttribute; =20 + if (Length =3D=3D 0) { + return RETURN_SUCCESS; + } + if ((PagingMode =3D=3D Paging32bit) || (PagingMode =3D=3D PagingPae) || = (PagingMode >=3D PagingModeMax)) { // // 32bit paging is never supported. --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101630): https://edk2.groups.io/g/devel/message/101630 Mute This Topic: https://groups.io/mt/97796375/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 10:58:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101631+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101631+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679557276; cv=none; d=zohomail.com; s=zohoarc; b=YIfBqMpL5sh2F96aiTPHqwA5q4dsqqmwQbmVWmZUvuBuRKQpAbMVlzfacYLgJ8rfBVWFcJUNMk2MwUNETsxe977dsl/Iih+mHBjR0IBh3R8JMcujkQSZNF7pIHj0/G6ShK+21eNu2fG0ZzC9P8Vg66h7o4d6cJgx+YVaxnJ88wg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679557276; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=LCw4OHSIDBotkl16z3a93vSItOdaVerGF4F0dz1y6W0=; b=bNmQBk2kguH9Xxy/0oSdVTPL6/Snyzgp9VTlhXNva/vStKyLhu1x4KBVVBPI6La71aqGv+lveSPF/ybFtbodhoIeqkDWKTOkSZilaaQCJ0jbXK1hVHavctJ4V2pHIKLHSUITPfo3NkJfB6uhJ4vH9oAdX43itVOWS133Bnl+igY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101631+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679557276350821.972330092126; Thu, 23 Mar 2023 00:41:16 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id LBCsYY1788612xIxvhHgW1Zx; Thu, 23 Mar 2023 00:41:16 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.67098.1679557268568440146 for ; Thu, 23 Mar 2023 00:41:15 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="425699506" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="425699506" X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="684616818" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="684616818" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:13 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V4 03/21] UefiCpuPkg/CpuPageTableLib:Initialize some LocalVariable at beginning Date: Thu, 23 Mar 2023 15:40:39 +0800 Message-Id: <20230323074057.549-4-dun.tan@intel.com> In-Reply-To: <20230323074057.549-1-dun.tan@intel.com> References: <20230323074057.549-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: Hqjy4A3brJPMQtDsoQUoQoJdx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679557276; bh=P5j0y5mqwOlx+s0Lbokvx28oAMD67F+HyWqY5M3YY6k=; h=Cc:Date:From:Reply-To:Subject:To; b=fsRg4PImS+Q9ik6cHhmsIGfuDiUZroEt8Y6pi/xr3YfIlsb3WqIlSsA6/1/U7FUh9mD 3scNC4fd1JcQ6eTv11RbxAdNDi24lPyLAUccfjmyHZeXH53qnnbfR7I1ZNcu1dzBZfr3P CddxLwg+IQ81tPNH0ufL5sBo4Zmo89b0+L0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679557278263100005 Content-Type: text/plain; charset="utf-8" Move some local variable initialization to the beginning of the function. Also delete duplicated calculation for RegionLength. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Reviewed-by: Ray Ni Tested-by: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 21 ++++++++++++----= ----- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 218068a3e1..127b65183f 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -258,6 +258,7 @@ PageTableLibMapInLevel ( UINTN BitStart; UINTN Index; IA32_PAGING_ENTRY *PagingEntry; + UINTN PagingEntryIndex; IA32_PAGING_ENTRY *CurrentPagingEntry; UINT64 RegionLength; UINT64 SubLength; @@ -288,6 +289,14 @@ PageTableLibMapInLevel ( LocalParentAttribute.Uint64 =3D ParentAttribute->Uint64; ParentAttribute =3D &LocalParentAttribute; =20 + // + // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 << 2= 1) or 4K (1 << 12). + // + BitStart =3D 12 + (Level - 1) * 9; + PagingEntryIndex =3D (UINTN)BitFieldRead64 (LinearAddress + Offset, BitS= tart, BitStart + 9 - 1); + RegionLength =3D REGION_LENGTH (Level); + RegionMask =3D RegionLength - 1; + // // ParentPagingEntry ONLY is deferenced for checking Present and MustBeO= ne bits // when Modify is FALSE. @@ -353,8 +362,7 @@ PageTableLibMapInLevel ( // PageTableLibSetPnle (&ParentPagingEntry->Pnle, &NopAttribute, &AllOn= eMask); =20 - RegionLength =3D REGION_LENGTH (Level); - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BA= SE_ADDRESS (&ParentPagingEntry->Pnle); + PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BAS= E_ADDRESS (&ParentPagingEntry->Pnle); for (SubOffset =3D 0, Index =3D 0; Index < 512; Index++) { PagingEntry[Index].Uint64 =3D OneOfPagingEntry.Uint64 + SubOffset; SubOffset +=3D RegionLength; @@ -425,15 +433,10 @@ PageTableLibMapInLevel ( } =20 // - // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 << 2= 1) or 4K (1 << 12). // RegionStart: points to the linear address that's aligned on RegionLe= ngth and lower than (LinearAddress + Offset). // - BitStart =3D 12 + (Level - 1) * 9; - Index =3D (UINTN)BitFieldRead64 (LinearAddress + Offset, BitStart= , BitStart + 9 - 1); - RegionLength =3D LShiftU64 (1, BitStart); - RegionMask =3D RegionLength - 1; - RegionStart =3D (LinearAddress + Offset) & ~RegionMask; - + Index =3D PagingEntryIndex; + RegionStart =3D (LinearAddress + Offset) & ~RegionMask; ParentAttribute->Uint64 =3D PageTableLibGetPnleMapAttribute (&ParentPagi= ngEntry->Pnle, ParentAttribute); =20 // --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101631): https://edk2.groups.io/g/devel/message/101631 Mute This Topic: https://groups.io/mt/97796376/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 10:58:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101632+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101632+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679557278; cv=none; d=zohomail.com; s=zohoarc; b=CBrVI40jXzCMZB6q419OkEY5GsJUqRVtrsgr3vqGbNPdDStiwEZfO+mJkTxUpNBASFlxx0mnCNXD+gPLz8HP2EwRh867DLqiSjXng9xn21d+B2tFsQKIvjqGaiTKY/i2o3fSscJbSgzbaqbvTQGGwCZbSiVrsZhpBhEuSvLgmFM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679557278; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=S68bXkj3CvqPOPXiv5hUJ8uuAIvcBvVf2rYB4IjGhcU=; b=TUFIG+dd63xFazoemTNCS3kXUJxc5UuNsQXgHtXlyBVxR+WWNGayBccLQIHz86+nJzsfh0eBREvnMuiKKzKeffUi5V7gLDjfq9G5alEjplpdcPt7W44qqM7tWBhm0ImGTKxlBfNMc9RXbrM8Ps2ZbQntDyTN1+ppXmq4/i6WkVc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101632+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679557278540858.8698472186617; Thu, 23 Mar 2023 00:41:18 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id KYHWYY1788612xlR8daG0qQk; Thu, 23 Mar 2023 00:41:18 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.67098.1679557268568440146 for ; Thu, 23 Mar 2023 00:41:17 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="425699537" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="425699537" X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="684616823" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="684616823" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:15 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V4 04/21] UefiCpuPkg/CpuPageTableLib: Fix the non-1:1 mapping issue Date: Thu, 23 Mar 2023 15:40:40 +0800 Message-Id: <20230323074057.549-5-dun.tan@intel.com> In-Reply-To: <20230323074057.549-1-dun.tan@intel.com> References: <20230323074057.549-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: Fz950JUFfWZUm4FgTgIqmZ91x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679557278; bh=SvuboyWtAH60/fSTqxVeHBZgX24PoLIfGTe3dsqBU4Y=; h=Cc:Date:From:Reply-To:Subject:To; b=NTWIjPcf8OzESZYT2yegXN06TjShhJKujpjRxys9xmkSH89E1bzOUtrnTDBjuYl0+ig VlJYo0uIFq05xYDReGUewZxDzEPSg7i7dYKR2qdwRipXH2LDcWIL02hJvbOkbPoQQQK4A 0v7RdNq7S0NnVeU7+KPo+Bfar5vicJxfrFY= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679557280250100009 Content-Type: text/plain; charset="utf-8" In previous code logic, when splitting a leaf parent entry to smaller granularity child page table, if the parent entry Attribute&Mask(without PageTableBaseAddress field) is equal to the input attribute&mask(without PageTableBaseAddress field), the split process won't happen. This may lead to failure in non-1:1 mapping. For example, there is a page table in which [0, 1G] is mapped(Lv4[0] ,Lv3[0,0], a non-leaf level4 entry and a leaf level3 entry). And we want to remap [0, 2M] linear address range to [1G, 1G + 2M] with the same attibute. The expected behaviour should be: split Lv3[0,0] entry into 512 level2 entries and remap the first level2 entry to cover [0, 2M]. But the split won't happen in previous code since PageTableBaseAddress of input Attribute is not checked. So, when checking if a leaf parent entry needs to be splitted, we should also check if PageTableBaseAddress calculated by parent entry is equal to the value caculated by input attribute. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Tested-by: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 127b65183f..ad68792ca8 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -274,6 +274,8 @@ PageTableLibMapInLevel ( IA32_MAP_ATTRIBUTE ChildMask; IA32_MAP_ATTRIBUTE CurrentMask; IA32_MAP_ATTRIBUTE LocalParentAttribute; + UINT64 PhysicalAddrInEntry; + UINT64 PhysicalAddrInAttr; =20 ASSERT (Level !=3D 0); ASSERT ((Attribute !=3D NULL) && (Mask !=3D NULL)); @@ -341,7 +343,15 @@ PageTableLibMapInLevel ( // This function is called when the memory length is less than the r= egion length of the parent level. // No need to split the page when the attributes equal. // - return RETURN_SUCCESS; + if (Mask->Bits.PageTableBaseAddress =3D=3D 0) { + return RETURN_SUCCESS; + } + + PhysicalAddrInEntry =3D IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (= &PleBAttribute) + PagingEntryIndex * RegionLength; + PhysicalAddrInAttr =3D (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS = (Attribute) + Offset) & (~RegionMask); + if (PhysicalAddrInEntry =3D=3D PhysicalAddrInAttr) { + return RETURN_SUCCESS; + } } =20 ASSERT (Buffer =3D=3D NULL || *BufferSize >=3D SIZE_4KB); --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101632): https://edk2.groups.io/g/devel/message/101632 Mute This Topic: https://groups.io/mt/97796377/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 10:58:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101633+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101633+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679557281; cv=none; d=zohomail.com; s=zohoarc; b=iKo98jAkDv1bQYjLL1EJqKpTNgdYvEPRlveYPUyb3fuLFkRMWTh7TDFo7PVEPaIT4dNPbs5Ea5/XpdKaG3ZCJ5mC6Y21fuX2eLBfiQKuc8XBl7cMNEboFoIRlGgKB0lDK24nTlTnjLBT9WMdHbkeiVpDAeCHx9H0MF1rHZEuw5g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679557281; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=bU14e0xT0VeivlPhcqSEqqJk3RLjtYr0b7NUWHJzkOk=; b=WRaeCvwg5YvrcKvJqOCeu+FkTFbvlx/Iyapbut4lxpWKFmAoJDX43gUCoWcoGw/9Nr8jRxVfa9ZaPIwmlcwtcqk3cUfMJ/fJF3IujcpLOtSbzXIN1aKRcgakgT+XA99dWVEj9L0lZZx/7T4BPpVVYMdxhHBMCJCKtd4dGPE9dQw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101633+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679557281594328.0117728656419; Thu, 23 Mar 2023 00:41:21 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id aBn6YY1788612xbDmlYI8MXc; Thu, 23 Mar 2023 00:41:21 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.67098.1679557268568440146 for ; Thu, 23 Mar 2023 00:41:20 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="425699555" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="425699555" X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="684616828" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="684616828" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:18 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V4 05/21] UefiCpuPkg/CpuPageTableLib:Clear PageSize bit(Bit7) for non-leaf Date: Thu, 23 Mar 2023 15:40:41 +0800 Message-Id: <20230323074057.549-6-dun.tan@intel.com> In-Reply-To: <20230323074057.549-1-dun.tan@intel.com> References: <20230323074057.549-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: TYl4cxU1HdAc5SfoUdKVJB02x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679557281; bh=wh+IKTN+vjzAJ3XA6SDMMPJRsZJcPGDyd0vbGgClpJQ=; h=Cc:Date:From:Reply-To:Subject:To; b=kApOWJDXtwGFT2Iykx6u7UIR3SERbUqe7ovmTT+2OoDH5IuG2B+yhPQMK9QbXNOPU8p 1dZOvcwyVGdgx0peo/fi5OHDeB8aZHXc6cBg5O8TXIUfI4BhTjS0rFaNoTYst7wq7xm5P DVoRH5XkD7oxB0IJmPen3NPBcvGWOp2LdaM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679557282299100013 Content-Type: text/plain; charset="utf-8" Clear PageSize bit(Bit7) for non-leaf entry in PageTableLibSetPnle. This function is used to set non-leaf entry attributes so it should make sure that the PageSize bit of the entry should be 0. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Reviewed-by: Ray Ni Tested-by: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index ad68792ca8..cf0cfeca77 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -202,7 +202,8 @@ PageTableLibSetPnle ( Pnle->Bits.Nx =3D Attribute->Bits.Nx; } =20 - Pnle->Bits.Accessed =3D 0; + Pnle->Bits.Accessed =3D 0; + Pnle->Bits.MustBeZero =3D 0; =20 // // Set the attributes (WT, CD, A) to 0. --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101633): https://edk2.groups.io/g/devel/message/101633 Mute This Topic: https://groups.io/mt/97796378/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 10:58:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101634+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101634+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679557283; cv=none; d=zohomail.com; s=zohoarc; b=eivbN5W6cHth0VHX+2JM/7KD/EauOphjHH4uchBaBk40unJLnONMUOSIXOBZQSqTsOiGK1YvC5LwdLheTgP2IQyS/RtmcPfbKC3LWDNzF1d5gBubE55LDRmmw7s5BEMbpTZkl4Bh25SwuH1OQZLfS87dpYU+cGupem3MQwmN1OY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679557283; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=HLAZdgZ/f5zYCbQVnBUW7nPMMoDZPkdOLQNhwVx+qjw=; b=PCU65F5prG+ZKyx9wcALLvd9plcVCsRvWChOiWbK25+INK0ZQXeTgqCrl49fHTZePiqnO8pEgFCXSugNG0/IbdmXPDWiMJ3Kk53TZKZfb9hwHmgBdJrQyD+HRLnQSpiWMJGH9n+Qt+u9BcVTHwOLD4nMGooKBayp3qg3DlwAFaQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101634+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679557283786357.1284438002597; Thu, 23 Mar 2023 00:41:23 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id Zm1eYY1788612xSa54SPgKEg; Thu, 23 Mar 2023 00:41:23 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.67098.1679557268568440146 for ; Thu, 23 Mar 2023 00:41:22 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="425699572" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="425699572" X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="684616831" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="684616831" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:21 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V4 06/21] UefiCpuPkg/CpuPageTableLib: Fix issue when splitting leaf entry Date: Thu, 23 Mar 2023 15:40:42 +0800 Message-Id: <20230323074057.549-7-dun.tan@intel.com> In-Reply-To: <20230323074057.549-1-dun.tan@intel.com> References: <20230323074057.549-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: xj2aC3dJKDsccwOx5uecfbxmx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679557283; bh=O9Ae5/7F2dzTqr1duUZ9IAKPEiDUfNDliLxM6ldeT/I=; h=Cc:Date:From:Reply-To:Subject:To; b=Qe/k90lzJISE5IDZkujECSTz9P1TpnXuFc1k3Au3POmXAOqO7pr9eID0FJYfh1tDGPo J1+izpnFFzlk8eR0beCef4tfLM28yjDmmN0bN0ZXLhDIkIUeD7IOwzy9ljYJblx0LtVg8 GZt6GuOjHqLVthHMe2YtmOAeG3ey4/PkQm8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679557284280100017 Content-Type: text/plain; charset="utf-8" When splitting leaf parent entry to smaller granularity, create child page table before modifing parent entry. In previous code logic, when splitting a leaf parent entry, parent entry will point to a null 4k memory before child page table is created in this 4k memory. When the page table to be modified is the page table in CR3, if the executed CpuPageTableLib code is in the range mapped by the modified leaf parent entry, then issue will happen. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Tested-by: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index cf0cfeca77..76febdd42d 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -363,8 +363,13 @@ PageTableLibMapInLevel ( // // Create 512 child-level entries that map to 2M/4K. // - ParentPagingEntry->Uintn =3D (UINTN)Buffer + *BufferSize; - ZeroMem ((VOID *)ParentPagingEntry->Uintn, SIZE_4KB); + PagingEntry =3D (IA32_PAGING_ENTRY *)((UINTN)Buffer + *BufferSize); + ZeroMem (PagingEntry, SIZE_4KB); + + for (SubOffset =3D 0, Index =3D 0; Index < 512; Index++) { + PagingEntry[Index].Uint64 =3D OneOfPagingEntry.Uint64 + SubOffset; + SubOffset +=3D RegionLength; + } =20 // // Set NOP attributes @@ -372,12 +377,7 @@ PageTableLibMapInLevel ( // will make the entire region read-only even the child entrie= s set the RW bit. // PageTableLibSetPnle (&ParentPagingEntry->Pnle, &NopAttribute, &AllOn= eMask); - - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BAS= E_ADDRESS (&ParentPagingEntry->Pnle); - for (SubOffset =3D 0, Index =3D 0; Index < 512; Index++) { - PagingEntry[Index].Uint64 =3D OneOfPagingEntry.Uint64 + SubOffset; - SubOffset +=3D RegionLength; - } + ParentPagingEntry->Uint64 =3D ((UINTN)(VOID *)PagingEntry) | (Parent= PagingEntry->Uint64 & (~IA32_PE_BASE_ADDRESS_MASK_40)); } } else { // --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101634): https://edk2.groups.io/g/devel/message/101634 Mute This Topic: https://groups.io/mt/97796379/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 10:58:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101635+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101635+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679557286; cv=none; d=zohomail.com; s=zohoarc; b=JJ4WEMqtLPD7NgrfkXKgX5puTeJTg5jg6F90Bpc1LYC/KiGAP/FJiKbfF0EezFDM6ojmLcg5CIDzbTDrz8W+T5sz/+CfSG/NfShcDG3z3jeGnLe0tQ5D3gz9FWLktnUzvaRGvDH3FBA/B28F6+y3OKC5QVYtA/dO7jPj/5jF7kA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679557286; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=8n9oflamnDVRj266gkgIx3nbvrNWujryUZxV/d2ACHI=; b=ENElJRkZroY0W+FG761YTugkmH/Ub3OCh2kaEupA9rT0JDsSZf+DzofuwKIWplIfw/8jSIF+Z8KVOpKIDVeX2mlceVkHh5YpCqIJg2x0A8zks4R5+YzkxQKoE0OodaKrc2PoSSYYTtyzZSPQHAJdSGVz8CUZ3XoF79bPYOmRco8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101635+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679557286548827.4386018881647; Thu, 23 Mar 2023 00:41:26 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id V4fsYY1788612xjcdVEAkCfa; Thu, 23 Mar 2023 00:41:26 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.67098.1679557268568440146 for ; Thu, 23 Mar 2023 00:41:25 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="425699593" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="425699593" X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="684616835" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="684616835" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:23 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V4 07/21] UefiCpuPkg/MpInitLib: Add code to initialize MapMask Date: Thu, 23 Mar 2023 15:40:43 +0800 Message-Id: <20230323074057.549-8-dun.tan@intel.com> In-Reply-To: <20230323074057.549-1-dun.tan@intel.com> References: <20230323074057.549-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: mF3lqXzLVl4jId4BFGe8oSiux1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679557286; bh=+u7vqbORBjGQoy4B3+02K1CsRbL1XAy7XiMbHdJDcJk=; h=Cc:Date:From:Reply-To:Subject:To; b=uoaIySixvMX0riTj+Ic5xX4hZpDUieJxdYDkoKvvUokj+Z5UYgTOubiJAhW0neR8Wjf iUm0wnXktHJOQz5vjG3NSvTtVEAzkMPbe2ck4EOvQ0BaYf/YmK0piXIfEhXOxFp7BZ0/E UocvAUKhyN5de0+n+bzdahUOiJjAMTuyfG8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679557288279100001 Content-Type: text/plain; charset="utf-8" In function CreatePageTable(), add code to initialize MapMask to MAX_UINT64. When creating new page table or map non-present range to present, all attributes should be provided. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Reviewed-by: Ray Ni Tested-by: Gerd Hoffmann --- UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c b/UefiCpuPk= g/Library/MpInitLib/X64/CreatePageTable.c index 7cf91ed9c4..f20068152b 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c +++ b/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c @@ -36,10 +36,7 @@ CreatePageTable ( MapAttribute.Uint64 =3D Address; MapAttribute.Bits.Present =3D 1; MapAttribute.Bits.ReadWrite =3D 1; - - MapMask.Bits.PageTableBaseAddress =3D 1; - MapMask.Bits.Present =3D 1; - MapMask.Bits.ReadWrite =3D 1; + MapMask.Uint64 =3D MAX_UINT64; =20 PageTable =3D 0; PageTableBufferSize =3D 0; --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101635): https://edk2.groups.io/g/devel/message/101635 Mute This Topic: https://groups.io/mt/97796381/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 10:58:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101636+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101636+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679557288; cv=none; d=zohomail.com; s=zohoarc; b=Bv4z01De112MWYuNIBFlhkvBxtwpvewdsjiXATe0esOzhXxV4g8kj++uKL7tlr4/ilwiZQTuJpk5oeLtu0cAEsXD/xk2eGPKtukJ9LGc4cJ4I/QdjIThdoOtaXCyLKDjlBoyYxN//QnnhX1QNXrPaBIrLvHIl9lUG1mMFMF9/Kg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679557288; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Wmq9m/tvLq6ELSY64605+Dk/yrVXG8ODX5qQNDH1CFQ=; b=huFhzjJVzItReX0VfBoPv6kkGM5s9/N/VO4OcxbIglSxv2UJ8XtlhRAQIEg+FlWscI6sEgPKtxIui783UREkWC5tpKxyZT+kTc0xroewjIKF/2dQxhKXS/X0zBhJI72E+wRtHPUUkcmZGNt0UH+Qtgnr5/VQaDWnnKyYfgA+f5c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101636+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 167955728862590.1975566575087; Thu, 23 Mar 2023 00:41:28 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 7ff7YY1788612xhSmMAqQl7F; Thu, 23 Mar 2023 00:41:28 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.67098.1679557268568440146 for ; Thu, 23 Mar 2023 00:41:27 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="425699621" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="425699621" X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="684616838" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="684616838" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:26 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V4 08/21] UefiCpuPkg/CpuPageTableLib:Add check for Mask and Attr Date: Thu, 23 Mar 2023 15:40:44 +0800 Message-Id: <20230323074057.549-9-dun.tan@intel.com> In-Reply-To: <20230323074057.549-1-dun.tan@intel.com> References: <20230323074057.549-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: FGXfJA9WhoeC68TsOlsSCLlEx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679557288; bh=+lVbbb96Lim2yLOedlOVix5yxCDu0pyU4Hck/DNj6dg=; h=Cc:Date:From:Reply-To:Subject:To; b=m3CvRiYP9Fl98fnX0YXabRbqvoWXQyief4Da66jhQaBNzdGJP/2NXqFLaLtwBYbhig9 f18B5SXCN2pO5USktLqlybEBOGKhYsOv5wnRhA8KYdF5/H73vmv5zE5/X/6FsMFzMLGQ1 Rkvmj5EAe+WFqkMkCgVpIjU0l8uIT6BZFcM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679557290421100001 Content-Type: text/plain; charset="utf-8" For different usage, check if the combination for Mask and Attr is valid when creating or updating page table. 1.For non-present range 1.1Mask.Present is 0 but some other attributes is provided. This case is invalid. 1.2Mask.Present is 1 and Attr.Present is 0. In this case,all other attributes should not be provided. 1.3Mask.Present is 1 and Attr.Present is 1. In this case,all attributes should be provided to intialize the attribute. 2.For present range 2.1Mask.Present is 1 and Attr.Present is 0.In this case, all other attributes should not be provided. All other usage for present range is permitted. In the mentioned cases, 1.2 and 2.1 can be merged into 1 check. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Tested-by: Gerd Hoffmann --- UefiCpuPkg/Include/Library/CpuPageTableLib.h | 2 +- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 79 ++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 78 insertions(+), 3 deletions(-) diff --git a/UefiCpuPkg/Include/Library/CpuPageTableLib.h b/UefiCpuPkg/Incl= ude/Library/CpuPageTableLib.h index 5f44ece548..6bda15b5bc 100644 --- a/UefiCpuPkg/Include/Library/CpuPageTableLib.h +++ b/UefiCpuPkg/Include/Library/CpuPageTableLib.h @@ -76,7 +76,7 @@ typedef enum { @param[in] Mask The mask used for attribute. The correspo= nding field in Attribute is ignored if that in Mask is 0. =20 @retval RETURN_UNSUPPORTED PagingMode is not supported. - @retval RETURN_INVALID_PARAMETER PageTable, BufferSize, Attribute or Ma= sk is NULL. + @retval RETURN_INVALID_PARAMETER PageTable, BufferSize, Attribute or Ma= sk is NULL or the combination of Attribute and Mask is invalid. @retval RETURN_INVALID_PARAMETER *BufferSize is not multiple of 4KB. @retval RETURN_BUFFER_TOO_SMALL The buffer is too small for page table= creation/updating. BufferSize is updated to indicate the = expected buffer size. diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 76febdd42d..2ad22b333d 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -215,6 +215,43 @@ PageTableLibSetPnle ( Pnle->Bits.CacheDisabled =3D 0; } =20 +/** + Check if the combination for Attribute and Mask is valid for non-present= entry. + 1.Mask.Present is 0 but some other attributes is provided. This case sho= uld be invalid. + 2.Map non-present range to present. In this case, all attributes should = be provided. + + @param[in] Attribute The attribute of the linear address range. + @param[in] Mask The mask used for attribute to check. + + @retval RETURN_INVALID_PARAMETER The combination for Attribute and Ma= sk is invalid. + @retval RETURN_SUCCESS The combination for Attribute and Ma= sk is valid. +**/ +RETURN_STATUS +IsAttributesAndMaskValidForNonPresentEntry ( + IN IA32_MAP_ATTRIBUTE *Attribute, + IN IA32_MAP_ATTRIBUTE *Mask + ) +{ + if ((Mask->Bits.Present =3D=3D 1) && (Attribute->Bits.Present =3D=3D 1))= { + // + // Creating new page table or remapping non-present range to present. + // + if ((Mask->Bits.ReadWrite =3D=3D 0) || (Mask->Bits.UserSupervisor =3D= =3D 0) || (Mask->Bits.WriteThrough =3D=3D 0) || (Mask->Bits.CacheDisabled = =3D=3D 0) || + (Mask->Bits.Accessed =3D=3D 0) || (Mask->Bits.Dirty =3D=3D 0) || (= Mask->Bits.Pat =3D=3D 0) || (Mask->Bits.Global =3D=3D 0) || + (Mask->Bits.PageTableBaseAddress =3D=3D 0) || (Mask->Bits.Protecti= onKey =3D=3D 0) || (Mask->Bits.Nx =3D=3D 0)) + { + return RETURN_INVALID_PARAMETER; + } + } else if ((Mask->Bits.Present =3D=3D 0) && (Mask->Uint64 > 1)) { + // + // Only change other attributes for non-present range is not permitted. + // + return RETURN_INVALID_PARAMETER; + } + + return RETURN_SUCCESS; +} + /** Update page table to map [LinearAddress, LinearAddress + Length) with sp= ecified attribute in the specified level. =20 @@ -237,6 +274,7 @@ PageTableLibSetPnle ( when a new physical base address is se= t. @param[in] Mask The mask used for attribute. The corre= sponding field in Attribute is ignored if that in Mask is 0. =20 + @retval RETURN_INVALID_PARAMETER The combination of Attribute and Mask = for non-present entry is invalid. @retval RETURN_SUCCESS PageTable is created/updated successfu= lly. **/ RETURN_STATUS @@ -260,6 +298,7 @@ PageTableLibMapInLevel ( UINTN Index; IA32_PAGING_ENTRY *PagingEntry; UINTN PagingEntryIndex; + UINTN PagingEntryIndexEnd; IA32_PAGING_ENTRY *CurrentPagingEntry; UINT64 RegionLength; UINT64 SubLength; @@ -306,6 +345,14 @@ PageTableLibMapInLevel ( // =20 if (ParentPagingEntry->Pce.Present =3D=3D 0) { + // + // [LinearAddress, LinearAddress + Length] contains non-present range. + // + Status =3D IsAttributesAndMaskValidForNonPresentEntry (Attribute, Mask= ); + if (RETURN_ERROR (Status)) { + return Status; + } + // // The parent entry is CR3 or PML5E/PML4E/PDPTE/PDE. // It does NOT point to an existing page directory. @@ -380,6 +427,27 @@ PageTableLibMapInLevel ( ParentPagingEntry->Uint64 =3D ((UINTN)(VOID *)PagingEntry) | (Parent= PagingEntry->Uint64 & (~IA32_PE_BASE_ADDRESS_MASK_40)); } } else { + // + // If (LinearAddress + Length - 1) is not in the same ParentPagingEntr= y with (LinearAddress + Offset), then the remaining child PagingEntry + // starting from PagingEntryIndex of ParentPagingEntry is all covered = by [LinearAddress + Offset, LinearAddress + Length - 1]. + // + PagingEntryIndexEnd =3D (BitFieldRead64 (LinearAddress + Length - 1, B= itStart + 9, 63) !=3D BitFieldRead64 (LinearAddress + Offset, BitStart + 9,= 63)) ? 511 : + (UINTN)BitFieldRead64 (LinearAddress + Length - = 1, BitStart, BitStart + 9 - 1); + PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_= ADDRESS (&ParentPagingEntry->Pnle); + for (Index =3D PagingEntryIndex; Index <=3D PagingEntryIndexEnd; Index= ++) { + if (PagingEntry[Index].Pce.Present =3D=3D 0) { + // + // [LinearAddress, LinearAddress + Length] contains non-present ra= nge. + // + Status =3D IsAttributesAndMaskValidForNonPresentEntry (Attribute, = Mask); + if (RETURN_ERROR (Status)) { + return Status; + } + + break; + } + } + // // It's a non-leaf entry // @@ -427,7 +495,6 @@ PageTableLibMapInLevel ( // Update child entries to use restrictive attribute inherited fro= m parent. // e.g.: Set PDE[0-255].ReadWrite =3D 0 // - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_B= ASE_ADDRESS (&ParentPagingEntry->Pnle); for (Index =3D 0; Index < 512; Index++) { if (PagingEntry[Index].Pce.Present =3D=3D 0) { continue; @@ -553,7 +620,7 @@ PageTableLibMapInLevel ( @param[in] Mask The mask used for attribute. The correspo= nding field in Attribute is ignored if that in Mask is 0. =20 @retval RETURN_UNSUPPORTED PagingMode is not supported. - @retval RETURN_INVALID_PARAMETER PageTable, BufferSize, Attribute or Ma= sk is NULL. + @retval RETURN_INVALID_PARAMETER PageTable, BufferSize, Attribute or Ma= sk is NULL or the combination of Attribute and Mask is invalid. @retval RETURN_INVALID_PARAMETER *BufferSize is not multiple of 4KB. @retval RETURN_BUFFER_TOO_SMALL The buffer is too small for page table= creation/updating. BufferSize is updated to indicate the = expected buffer size. @@ -615,6 +682,14 @@ PageTableMap ( return RETURN_INVALID_PARAMETER; } =20 + // + // If to map [LinearAddress, LinearAddress + Length] as non-present, + // all attributes except Present should not be provided. + // + if ((Attribute->Bits.Present =3D=3D 0) && (Mask->Bits.Present =3D=3D 1) = && (Mask->Uint64 > 1)) { + return RETURN_INVALID_PARAMETER; + } + MaxLeafLevel =3D (IA32_PAGE_LEVEL)(UINT8)PagingMode; MaxLevel =3D (IA32_PAGE_LEVEL)(UINT8)(PagingMode >> 8); MaxLinearAddress =3D LShiftU64 (1, 12 + MaxLevel * 9); --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101636): https://edk2.groups.io/g/devel/message/101636 Mute This Topic: https://groups.io/mt/97796382/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 10:58:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101637+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101637+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679557291; cv=none; d=zohomail.com; s=zohoarc; b=nn8sSml+9bPLQMozAZdsa2Or4m3hNvKXhhFb+DN6/5eWf1dz8KfF0LWaR0McULmm02B68ZFZdcWjstfmD/B4c6UtivJEBS2C8eBbKomlC2Qsz4GbqrZ4Y9fgx9/iWq+0W7Z8X931ah7LZVwAkFYlHMh5fucGaFKYlb9Y0ZcUJCk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679557291; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=OL1oNiKMW6nHP5qTxfmEn5lyejWzc11/oZcuykqoag8=; b=FxDWC32nPfGGkNYmDsSy+sk7h/9qLDP8gmafjWY/lbMjeppd1usbFDaYcgys9ZDiv4i+TQd5nvE7+AswylUxorsnlKKxe6FWTTb/mXuIKM+me7Y5bpxJB6+OYsA795TKdO8Ox5RvyNIopMP4/KA0XDFRqP52le4PKL8sRAmu2fg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101637+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679557291035238.76750595153055; Thu, 23 Mar 2023 00:41:31 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 3Wj0YY1788612xaiEF9MgGqC; Thu, 23 Mar 2023 00:41:30 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.67098.1679557268568440146 for ; Thu, 23 Mar 2023 00:41:30 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="425699643" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="425699643" X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="684616842" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="684616842" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:28 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V4 09/21] UefiCpuPkg/CpuPageTableLib: Add manual test to check Mask and Attr Date: Thu, 23 Mar 2023 15:40:45 +0800 Message-Id: <20230323074057.549-10-dun.tan@intel.com> In-Reply-To: <20230323074057.549-1-dun.tan@intel.com> References: <20230323074057.549-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: UJ66qFR6pjY9LSWk8PthMPUOx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679557290; bh=fjgmHjne3MWAprW+SJg6I+SMCk7m4HFzFXhZJvhv66U=; h=Cc:Date:From:Reply-To:Subject:To; b=rbU01O3o66iBIGlIygcktuAgwXz76GTby5yyB2OIzAF+3poj4E19gFRRHXF9ZdO2XaZ FgGcvDtkVeuF32k/d73MiCSLWNzbsEQ/mefxiya4Lbjcy8yqU/nnMqghlsz7Jq5r5yVGY gWEo6znUkZi20tAF1x4I/pYtgK7qtnZQFDo= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679557292352100005 Content-Type: text/plain; charset="utf-8" Add manual test case to check input Mask and Attribute. The check steps are: 1.Create Page table to cover [0, 2G]. All fields of MapMask should be set. 2.Update Page table to set [2G - 8K,2G] from present to non-present. All fields of MapMask except present should not be set. 3.Still set [2G - 8K, 2G] as not present, this case is permitted. But set [2G - 8K, 2G] as RW is not permitted. 4.Update Page table to set [2G - 8K, 2G] as present and RW. All fields of MapMask should be set. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Tested-by: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c = | 129 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 127 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUni= tTestHost.c b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUn= itTestHost.c index 3014a03243..3e84e2ba11 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c @@ -1,7 +1,7 @@ /** @file Unit tests of the CpuPageTableLib instance of the CpuPageTableLib class =20 - Copyright (c) 2022, Intel Corporation. All rights reserved.
+ Copyright (c) 2022 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -697,6 +697,131 @@ TestCaseManualChangeNx ( return UNIT_TEST_PASSED; } =20 +/** + Check if the input Mask and Attribute is as expected when creating new p= age table or + updating existing page table. + + @param[in] Context [Optional] An optional parameter that enables: + 1) test-case reuse with varied parameters and + 2) test-case re-entry for Target tests that need a + reboot. This parameter is a VOID* and it is the + responsibility of the test author to ensure that = the + contents are well understood by all test cases th= at may + consume it. + + @retval UNIT_TEST_PASSED The Unit test has completed and th= e test + case was successful. + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. +**/ +UNIT_TEST_STATUS +EFIAPI +TestCaseToCheckMapMaskAndAttr ( + IN UNIT_TEST_CONTEXT Context + ) +{ + UINTN PageTable; + PAGING_MODE PagingMode; + VOID *Buffer; + UINTN PageTableBufferSize; + IA32_MAP_ATTRIBUTE MapAttribute; + IA32_MAP_ATTRIBUTE ExpectedMapAttribute; + IA32_MAP_ATTRIBUTE MapMask; + RETURN_STATUS Status; + IA32_MAP_ENTRY *Map; + UINTN MapCount; + + PagingMode =3D Paging4Level; + PageTableBufferSize =3D 0; + PageTable =3D 0; + Buffer =3D NULL; + MapAttribute.Uint64 =3D 0; + MapAttribute.Bits.Present =3D 1; + MapMask.Uint64 =3D 0; + MapMask.Bits.Present =3D 1; + // + // Create Page table to cover [0, 2G]. All fields of MapMask should be s= et. + // + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); + MapMask.Uint64 =3D MAX_UINT64; + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTa= bleBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); + Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); + + // + // Update Page table to set [2G - 8K, 2G] from present to non-present. A= ll fields of MapMask except present should be set. + // + PageTableBufferSize =3D 0; + MapAttribute.Uint64 =3D SIZE_2GB - SIZE_8KB; + MapMask.Uint64 =3D 0; + MapMask.Bits.Present =3D 1; + MapMask.Bits.ReadWrite =3D 1; + Status =3D PageTableMap (&PageTable, PagingMode, Buffer,= &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMa= sk); + UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); + MapMask.Bits.ReadWrite =3D 0; + Status =3D PageTableMap (&PageTable, PagingMode, Buffer,= &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMa= sk); + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); + Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); + + // + // Still set [2G - 8K, 2G] as not present, this case is permitted. But s= et [2G - 8K, 2G] as RW is not permitted. + // + PageTableBufferSize =3D 0; + MapAttribute.Uint64 =3D 0; + MapMask.Uint64 =3D 0; + MapMask.Bits.Present =3D 1; + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &= PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMask= ); + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); + MapAttribute.Bits.ReadWrite =3D 1; + MapMask.Bits.ReadWrite =3D 1; + Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &= MapMask); + UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); + + // + // Update Page table to set [2G - 8K, 2G] as present and RW. All fields = of MapMask should not be set. + // + PageTableBufferSize =3D 0; + MapAttribute.Uint64 =3D SIZE_2GB - SIZE_8KB; + MapAttribute.Bits.ReadWrite =3D 1; + MapAttribute.Bits.Present =3D 1; + MapMask.Uint64 =3D 0; + MapMask.Bits.ReadWrite =3D 1; + MapMask.Bits.Present =3D 1; + Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &= MapMask); + UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); + MapMask.Uint64 =3D MAX_UINT64; + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTa= bleBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMask); + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); + + MapCount =3D 0; + Status =3D PageTableParse (PageTable, PagingMode, NULL, &MapCount); + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); + Map =3D AllocatePages (EFI_SIZE_TO_PAGES (MapCount* sizeof (IA32_MAP_= ENTRY))); + Status =3D PageTableParse (PageTable, PagingMode, Map, &MapCount); + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); + + // + // There should be two ranges [0, 2G-8k] with RW =3D 0 and [2G-8k, 2G] w= ith RW =3D 1 + // + UT_ASSERT_EQUAL (MapCount, 2); + UT_ASSERT_EQUAL (Map[0].LinearAddress, 0); + UT_ASSERT_EQUAL (Map[0].Length, SIZE_2GB - SIZE_8KB); + ExpectedMapAttribute.Uint64 =3D 0; + ExpectedMapAttribute.Bits.Present =3D 1; + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, ExpectedMapAttribute.Uint64); + UT_ASSERT_EQUAL (Map[1].LinearAddress, SIZE_2GB - SIZE_8KB); + UT_ASSERT_EQUAL (Map[1].Length, SIZE_8KB); + ExpectedMapAttribute.Uint64 =3D SIZE_2GB - SIZE_8KB; + ExpectedMapAttribute.Bits.Present =3D 1; + ExpectedMapAttribute.Bits.ReadWrite =3D 1; + UT_ASSERT_EQUAL (Map[1].Attribute.Uint64, ExpectedMapAttribute.Uint64); + return UNIT_TEST_PASSED; +} + /** Initialize the unit test framework, suite, and unit tests for the sample unit tests and run the unit tests. @@ -746,7 +871,7 @@ UefiTestMain ( AddTestCase (ManualTestCase, "Check if the parent entry has different Re= adWrite attribute", "Manual Test Case5", TestCaseManualChangeReadWrite, NUL= L, NULL, NULL); AddTestCase (ManualTestCase, "Check if the parent entry has different Nx= attribute", "Manual Test Case6", TestCaseManualChangeNx, NULL, NULL, NULL); AddTestCase (ManualTestCase, "Check if the needed size is expected", "Ma= nual Test Case7", TestCaseManualSizeNotMatch, NULL, NULL, NULL); - + AddTestCase (ManualTestCase, "Check MapMask when creating new page table= or mapping not-present range", "Manual Test Case8", TestCaseToCheckMapMask= AndAttr, NULL, NULL, NULL); // // Populate the Random Test Cases. // --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101637): https://edk2.groups.io/g/devel/message/101637 Mute This Topic: https://groups.io/mt/97796385/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 10:58:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101638+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101638+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679557293; cv=none; d=zohomail.com; s=zohoarc; b=kKVncLwB1jHNWw0ZGNuzANWXKVOX7uA9ldssz47DwlV1gEQdU7JsAhb9qpmLlMIxngt2vz0RMSQSGaaJ0s87YIFoutMMQspaLAFU8F3nAHHX3S+iqiaGpxBMujnP5kZifB9RPOViECl4yyCSgV/kB8z+9EPivTcTA/2lcPyuiAU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679557293; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=zjm0hQNw8XeAzCS+SykC1RcBR+tJJ27Jh4oYq9OewK8=; b=cN4x7riVcjt6dBkoHsaAVYJJgvyKKz9eoD57tPJm8vuuwZ0tA0Sg8qpQeAESC31VEz2dcLsnVX/bjJoGJqWvTbd8NuWyJgh8jCnsw1S/EW0kSiUATuslxrUxg4VetJjyIjtyKgjFw1OboP5g6R80EzuIlAlPgTB6tpXPUoEywnM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101638+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679557293441400.1304603253558; Thu, 23 Mar 2023 00:41:33 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id AYLUYY1788612xSeB2INyDNW; Thu, 23 Mar 2023 00:41:33 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.67098.1679557268568440146 for ; Thu, 23 Mar 2023 00:41:32 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="425699673" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="425699673" X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="684616847" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="684616847" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:30 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V4 10/21] UefiCpuPkg/CpuPageTableLib:Modify RandomBoolean() in RandomTest Date: Thu, 23 Mar 2023 15:40:46 +0800 Message-Id: <20230323074057.549-11-dun.tan@intel.com> In-Reply-To: <20230323074057.549-1-dun.tan@intel.com> References: <20230323074057.549-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: 2P9TBFxIT1tOp1ykFLt4WyLKx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679557293; bh=ey8pL1PFq5V/ieqguQN4utkrnBZRXwTcgxk9BweNLQU=; h=Cc:Date:From:Reply-To:Subject:To; b=RJawTRtird4iXJaQjh3wnzoA+qv5GRL28JVQGemh79Jvta/2/pXeZuUJOjvokqDTgeP //CN7MTwH1HvFghWyscQSNJh5+q/qSvXpB6hAcrDjflXWTcYvQ6EABpdgn11gO9td1gLt tmK32cKIEPuqCiT/S+IONUedbiA5LumNiAQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679557294338100010 Content-Type: text/plain; charset="utf-8" Add an input parameter to control the probability of returning true. Change RandomBoolean() in RandomTest from 50% chance returning true to returning true with the percentage of input Probability. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Reviewed-by: Ray Ni Tested-by: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c | 43 ++++++++++++= +++++++++---------------------- 1 file changed, 21 insertions(+), 22 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c index 97a388ca1c..52eb9daa10 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c @@ -1,7 +1,7 @@ /** @file Random test case for Unit tests of the CpuPageTableLib instance of the C= puPageTableLib class =20 - Copyright (c) 2022, Intel Corporation. All rights reserved.
+ Copyright (c) 2022 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -81,22 +81,6 @@ LocalRandomBytes ( } } =20 -/** - Return a random boolean. - - @return boolean -**/ -BOOLEAN -RandomBoolean ( - VOID - ) -{ - BOOLEAN Value; - - LocalRandomBytes ((UINT8 *)&Value, sizeof (BOOLEAN)); - return Value%2; -} - /** Return a 32bit random number. =20 @@ -139,6 +123,21 @@ Random64 ( return (UINT64)(Value % (Limit - Start + 1)) + Start; } =20 +/** + Returns true with the percentage of input Probability. + + @param[in] Probability The percentage to return true. + + @return boolean +**/ +BOOLEAN +RandomBoolean ( + UINT8 Probability + ) +{ + return ((Probability > ((UINT8)Random64 (0, 100))) ? TRUE : FALSE); +} + /** Check if the Page table entry is valid =20 @@ -178,7 +177,7 @@ ValidateAndRandomeModifyPageTablePageTableEntry ( UT_ASSERT_EQUAL ((PagingEntry->Uint64 & mValidMaskLeaf[Level].Uint64= ), PagingEntry->Uint64); } =20 - if ((RandomNumber < 100) && RandomBoolean ()) { + if ((RandomNumber < 100) && RandomBoolean (50)) { RandomNumber++; if (Level =3D=3D 1) { TempPhysicalBase =3D PagingEntry->Pte4K.Bits.PageTableBaseAddress; @@ -211,7 +210,7 @@ ValidateAndRandomeModifyPageTablePageTableEntry ( UT_ASSERT_EQUAL ((PagingEntry->Uint64 & mValidMaskNoLeaf[Level].Uint64= ), PagingEntry->Uint64); } =20 - if ((RandomNumber < 100) && RandomBoolean ()) { + if ((RandomNumber < 100) && RandomBoolean (50)) { RandomNumber++; TempPhysicalBase =3D PagingEntry->Pnle.Bits.PageTableBaseAddress; =20 @@ -299,7 +298,7 @@ GenerateSingleRandomMapEntry ( // // use AlignedTable to avoid that a random number can be very hard to be= 1G or 2M aligned // - if ((MapsIndex !=3D 0) && (RandomBoolean ())) { + if ((MapsIndex !=3D 0) && (RandomBoolean (50))) { FormerLinearAddress =3D MapEntrys->Maps[Random32 (0, (UINT32)MapsIndex= -1)].LinearAddress; if (FormerLinearAddress < 2 * (UINT64)SIZE_1GB) { FormerLinearAddressBottom =3D 0; @@ -323,7 +322,7 @@ GenerateSingleRandomMapEntry ( // MapEntrys->Maps[MapsIndex].Length =3D Random64 (0, MIN (MaxAddress - Map= Entrys->Maps[MapsIndex].LinearAddress, 10 * (UINT64)SIZE_1GB)) & AlignedTab= le[Random32 (0, ARRAY_SIZE (AlignedTable) -1)]; =20 - if ((MapsIndex !=3D 0) && (RandomBoolean ())) { + if ((MapsIndex !=3D 0) && (RandomBoolean (50))) { MapEntrys->Maps[MapsIndex].Attribute.Uint64 =3D MapEntrys->Maps[Random= 32 (0, (UINT32)MapsIndex-1)].Attribute.Uint64; MapEntrys->Maps[MapsIndex].Mask.Uint64 =3D MapEntrys->Maps[Random= 32 (0, (UINT32)MapsIndex-1)].Mask.Uint64; } else { @@ -344,7 +343,7 @@ GenerateSingleRandomMapEntry ( // Need to avoid such case when remove the Random option ONLY_ON= E_ONE_MAPPING // MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress =3D (Ra= ndom64 (0, (((UINT64)1)<<52) - 1) & AlignedTable[Random32 (0, ARRAY_SIZE (A= lignedTable) -1)])>> 12; - if (RandomBoolean ()) { + if (RandomBoolean (50)) { MapEntrys->Maps[MapsIndex].Mask.Bits.PageTableBaseAddress =3D 0; } } --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101638): https://edk2.groups.io/g/devel/message/101638 Mute This Topic: https://groups.io/mt/97796386/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 10:58:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101639+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101639+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679557296; cv=none; d=zohomail.com; s=zohoarc; b=Roj+R/CgUW+O6gkxhRkrjniVgs+ItgH054QTS0rJzj2JP47DfCuBHCQgUFX0XbicW7YgDugAZz6sZyOW5DDWKy2dnJKV5jF6CMmThbsbQSRQfqwE2cJeOeKwdbfwVYBUWxJba+obCM51r1tN/3gfnRmFwr7JfqqShJTMSg3knzU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679557296; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Wf+PDjpnBBKo6BIwBG9fjHkpxk5CLQmUtY6Ejn1yEYg=; b=aS6GPYKulQBHyRcNe4oJsKadG957E8h++7NuL5Cz3KQMb2lbFapce5BCzHDPXjCAhVTQ+5oFsGpZZJLaQRZtVCp/Vl5JN4rU0GuZ3g/T1WLhkKmuQ6GjYCMgZHgxhrgaDPEsb1MyrHP3K3K1r4o5l4wfig6YTRCjONLiPqW8sx8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101639+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679557296048904.4422575640831; Thu, 23 Mar 2023 00:41:36 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id G0dIYY1788612xk3bmyoJIxv; Thu, 23 Mar 2023 00:41:35 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.67098.1679557268568440146 for ; Thu, 23 Mar 2023 00:41:35 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="425699695" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="425699695" X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="684616852" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="684616852" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:33 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann , Zhiguang Liu Subject: [edk2-devel] [Patch V4 11/21] UefiCpuPkg/CpuPageTableLib:Modify RandomTest to check Mask/Attr Date: Thu, 23 Mar 2023 15:40:47 +0800 Message-Id: <20230323074057.549-12-dun.tan@intel.com> In-Reply-To: <20230323074057.549-1-dun.tan@intel.com> References: <20230323074057.549-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: vLtRKNZeL5dkGHgMtI5ulBTlx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679557295; bh=WKrs8NIsJqKc+A1gAgtJS0OJL8xd45rktIgXoR5S+aA=; h=Cc:Date:From:Reply-To:Subject:To; b=JSkXB2Igu79C1O3yH6Wki/gSNa0DSaDaQ4e2JFfFnjjdfwlCZwxMDpB0YDa4bITEmMY 0Ux9oGx6l9UWk1h949WOccuywRObfhGri130uW6Es11jTsBIGKJ9AyjzL1uMenCnQpUlK nMcpbxYg0dOqI91O7AicdI5mSZgFov2p6tw= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679557296402100014 Content-Type: text/plain; charset="utf-8" Modify RandomTest to check invalid input. When creating new page table or updating exsiting page table: 1.If set [LinearAddress, LinearAddress+Length] to non-preset, all other attributes should not be provided. 2.If [LinearAddress, LinearAddress+Length] contain non-present range, the Returnstatus of PageTableMap() should be InvalidParameter when: 2.1Some of attributes are not provided when mapping non-present range to present. 2.2Set any other attribute without setting the non-present range to Present. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Zhiguang Liu Acked-by: Gerd Hoffmann Tested-by: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c | 150 +++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++------------------------ UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c | 6 +++++- 2 files changed, 131 insertions(+), 25 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c index 52eb9daa10..b99e31f4c8 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c @@ -273,6 +273,27 @@ ValidateAndRandomeModifyPageTable ( return Status; } =20 +/** + Remove the last MAP_ENTRY in MapEntrys. + + @param MapEntrys Pointer to MapEntrys buffer +**/ +VOID +RemoveLastMapEntry ( + IN OUT MAP_ENTRYS *MapEntrys + ) +{ + UINTN MapsIndex; + + if (MapEntrys->Count =3D=3D 0) { + return; + } + + MapsIndex =3D MapEntrys->Count - 1; + ZeroMem (&(MapEntrys->Maps[MapsIndex]), sizeof (MAP_ENTRY)); + MapEntrys->Count =3D MapsIndex; +} + /** Generate single random map entry. The map entry can be the input of function PageTableMap @@ -327,7 +348,16 @@ GenerateSingleRandomMapEntry ( MapEntrys->Maps[MapsIndex].Mask.Uint64 =3D MapEntrys->Maps[Random= 32 (0, (UINT32)MapsIndex-1)].Mask.Uint64; } else { MapEntrys->Maps[MapsIndex].Attribute.Uint64 =3D Random64 (0, MAX_UINT6= 4) & mSupportedBit.Uint64; - MapEntrys->Maps[MapsIndex].Mask.Uint64 =3D Random64 (0, MAX_UINT6= 4) & mSupportedBit.Uint64; + if (RandomBoolean (5)) { + // + // The probability to get random Mask should be small since all bits= of a random number + // have a high probability of containing 0, which may be a invalid i= nput. + // + MapEntrys->Maps[MapsIndex].Mask.Uint64 =3D Random64 (0, MAX_UINT64) = & mSupportedBit.Uint64; + } else { + MapEntrys->Maps[MapsIndex].Mask.Uint64 =3D MAX_UINT64; + } + if (MapEntrys->Maps[MapsIndex].Mask.Bits.ProtectionKey !=3D 0) { MapEntrys->Maps[MapsIndex].Mask.Bits.ProtectionKey =3D 0xF; } @@ -337,15 +367,7 @@ GenerateSingleRandomMapEntry ( MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress =3D Map= Entrys->Maps[MapsIndex].LinearAddress >> 12; MapEntrys->Maps[MapsIndex].Mask.Bits.PageTableBaseAddress =3D 0xF= FFFFFFFFF; } else { - // - // Todo: If the mask bit for base address is zero, when dump the paget= able, every entry mapping to physical address zeor. - // This means the map count will be a large number, and impossib= le to finish in proper time. - // Need to avoid such case when remove the Random option ONLY_ON= E_ONE_MAPPING - // MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress =3D (Ra= ndom64 (0, (((UINT64)1)<<52) - 1) & AlignedTable[Random32 (0, ARRAY_SIZE (A= lignedTable) -1)])>> 12; - if (RandomBoolean (50)) { - MapEntrys->Maps[MapsIndex].Mask.Bits.PageTableBaseAddress =3D 0; - } } =20 MapEntrys->Count +=3D 1; @@ -608,23 +630,62 @@ SingleMapEntryTest ( IN UINTN InitMapCount ) { - UINTN MapsIndex; - RETURN_STATUS Status; - UINTN PageTableBufferSize; - VOID *Buffer; - IA32_MAP_ENTRY *Map; - UINTN MapCount; - UINTN Index; - UINTN KeyPointCount; - UINTN NewKeyPointCount; - UINT64 *KeyPointBuffer; - UINTN Level; - UINT64 Value; - UNIT_TEST_STATUS TestStatus; - - MapsIndex =3D MapEntrys->Count; + UINTN MapsIndex; + RETURN_STATUS Status; + UINTN PageTableBufferSize; + VOID *Buffer; + IA32_MAP_ENTRY *Map; + UINTN MapCount; + UINTN Index; + UINTN KeyPointCount; + UINTN NewKeyPointCount; + UINT64 *KeyPointBuffer; + UINTN Level; + UINT64 Value; + UNIT_TEST_STATUS TestStatus; + IA32_MAP_ATTRIBUTE *Mask; + IA32_MAP_ATTRIBUTE *Attribute; + UINT64 PreviousAddress; + UINT64 RangeLimit; + BOOLEAN IsNotPresent; + + MapsIndex =3D MapEntrys->Count; + MapCount =3D 0; + PreviousAddress =3D 0; + IsNotPresent =3D FALSE; =20 GenerateSingleRandomMapEntry (MaxAddress, MapEntrys); + RangeLimit =3D MapEntrys->Maps[MapsIndex].LinearAddress + MapEntrys->Map= s[MapsIndex].Length; + Status =3D PageTableParse (*PageTable, PagingMode, NULL, &MapCount); + + if (MapCount !=3D 0) { + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); + Map =3D AllocatePages (EFI_SIZE_TO_PAGES (MapCount * sizeof (IA32_MAP_= ENTRY))); + ASSERT (Map !=3D NULL); + Status =3D PageTableParse (*PageTable, PagingMode, Map, &MapCount); + } + + // + // Check if the generated MapEntrys->Maps[MapsIndex] contains not-presen= t range. + // + if (MapEntrys->Maps[MapsIndex].Length > 0) { + for (Index =3D 0; Index < MapCount; Index++) { + if ((PreviousAddress < Map[Index].LinearAddress) && + (MapEntrys->Maps[MapsIndex].LinearAddress < Map[Index].LinearAdd= ress) && (RangeLimit > PreviousAddress)) + { + // + // MapEntrys->Maps[MapsIndex] contains not-present range in exsiti= ng page table. + // + break; + } + + PreviousAddress =3D Map[Index].LinearAddress + Map[Index].Length; + } + + if (PreviousAddress < RangeLimit) { + IsNotPresent =3D TRUE; + } + } =20 PageTableBufferSize =3D 0; Status =3D PageTableMap ( @@ -637,6 +698,47 @@ SingleMapEntryTest ( &MapEntrys->Maps[MapsIndex].Attribute, &MapEntrys->Maps[MapsIndex].Mask ); + + Attribute =3D &MapEntrys->Maps[MapsIndex].Attribute; + Mask =3D &MapEntrys->Maps[MapsIndex].Mask; + // + // If set [LinearAddress, LinearAddress+Attribute] to not preset, all + // other attributes should not be provided. + // + if ((MapEntrys->Maps[MapsIndex].Length > 0) && (Attribute->Bits.Present = =3D=3D 0) && (Mask->Bits.Present =3D=3D 1) && (Mask->Uint64 > 1)) { + RemoveLastMapEntry (MapEntrys); + UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); + return UNIT_TEST_PASSED; + } + + // + // Return Status for non-present range also should be InvalidParameter w= hen: + // 1. Some of attributes are not provided when mapping non-present range= to present. + // 2. Set any other attribute without setting the non-present range to P= resent. + // + if (IsNotPresent) { + if ((Mask->Bits.Present =3D=3D 1) && (Attribute->Bits.Present =3D=3D 1= )) { + // + // Creating new page table or remapping non-present range to present. + // + if ((Mask->Bits.ReadWrite =3D=3D 0) || (Mask->Bits.UserSupervisor = =3D=3D 0) || (Mask->Bits.WriteThrough =3D=3D 0) || (Mask->Bits.CacheDisable= d =3D=3D 0) || + (Mask->Bits.Accessed =3D=3D 0) || (Mask->Bits.Dirty =3D=3D 0) ||= (Mask->Bits.Pat =3D=3D 0) || (Mask->Bits.Global =3D=3D 0) || + (Mask->Bits.PageTableBaseAddress =3D=3D 0) || (Mask->Bits.Protec= tionKey =3D=3D 0) || (Mask->Bits.Nx =3D=3D 0)) + { + RemoveLastMapEntry (MapEntrys); + UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); + return UNIT_TEST_PASSED; + } + } else if ((Mask->Bits.Present =3D=3D 0) && (Mask->Uint64 > 1)) { + // + // Only change other attributes for non-present range is not permitt= ed. + // + RemoveLastMapEntry (MapEntrys); + UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); + return UNIT_TEST_PASSED; + } + } + if (PageTableBufferSize !=3D 0) { UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); =20 diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c index 5bd70c0f65..10fdee2f94 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c @@ -1,7 +1,7 @@ /** @file helper file for Unit tests of the CpuPageTableLib instance of the CpuPag= eTableLib class =20 - Copyright (c) 2022, Intel Corporation. All rights reserved.
+ Copyright (c) 2022 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -171,6 +171,10 @@ IsPageTableValid ( UNIT_TEST_STATUS Status; IA32_PAGING_ENTRY *PagingEntry; =20 + if (PageTable =3D=3D 0) { + return UNIT_TEST_PASSED; + } + if ((PagingMode =3D=3D Paging32bit) || (PagingMode =3D=3D PagingPae) || = (PagingMode >=3D PagingModeMax)) { // // 32bit paging is never supported. --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101639): https://edk2.groups.io/g/devel/message/101639 Mute This Topic: https://groups.io/mt/97796388/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 10:58:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101640+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101640+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679557298; cv=none; d=zohomail.com; s=zohoarc; b=MsrUU7cTjPKGjxGoCv05DvWXG4iV1V20hC3Sqa2SNyiono2CN8ve21CVkg60Ljwv4zENteFKrDAs0TI/8Zf2aOS5sqYe8UI7iONkgdQT32YuiYon89GAoTnD2eBHBKSrkpGf9QW/asAM2eUEfHZjVvENVS0JR/q7wWQYwddMQkg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679557298; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=6t2dc6wDLx73d8WblAFU5iC9QXhLJI9lXey3Sigi1zk=; b=KNBtXLRl2haZkodGImAoqE3qZYhQfNaXZ980f05++ZoMYD/GorIW1WapN3oO/doufu8prR1AhddHtEDvRmyKThDQxn75g0ytWvuS34jww97/ObWI0Yaia3YSGxyEbVEuJ7TxeZbHuUJGq7reyWYt0nPeeBibUqEjQbhGlA+QYz0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101640+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679557298616965.3173672861443; Thu, 23 Mar 2023 00:41:38 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id rytoYY1788612xpvmYMpoM2J; Thu, 23 Mar 2023 00:41:38 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.67098.1679557268568440146 for ; Thu, 23 Mar 2023 00:41:37 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="425699716" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="425699716" X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="684616857" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="684616857" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:35 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V4 12/21] UefiCpuPkg/CpuPageTableLib: Enable non-1:1 mapping in random test Date: Thu, 23 Mar 2023 15:40:48 +0800 Message-Id: <20230323074057.549-13-dun.tan@intel.com> In-Reply-To: <20230323074057.549-1-dun.tan@intel.com> References: <20230323074057.549-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: jXwU66DlAfzMccxmbznppm1wx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679557298; bh=W5onN+JbGTxnEeX7fh2YULazetM8oVp7d+yaaM6OIFk=; h=Cc:Date:From:Reply-To:Subject:To; b=KdDVFvXTJJzgCbxqUhaisTdLMOcrFYvZd58KUYLO8Tfxv5bvdN5Npncfrxt6vV8+1II p10ZObKQUehaJyeUoeBvijuXuncH/tBPlnMmJQtImn4BRAqc1U3gNp2YojCFqStR6vlFn QPl9mNUd90joJdSobZcDaK+sB8JeDbP7t8A= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679557300345100001 Content-Type: text/plain; charset="utf-8" Enable non-1:1 mapping in random test. In previous test, non-1:1 test will fail due to the non-1:1 mapping issue in CpuPageTableLib and invalid Input Mask when creating new page table or mapping not-present range. Now these issue have been fixed. Signed-off-by: Dun Tan Cc: Eric Dong Reviewed-by: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Tested-by: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c = | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUni= tTestHost.c b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUn= itTestHost.c index 3e84e2ba11..d37cae9fbd 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c @@ -9,10 +9,10 @@ #include "CpuPageTableLibUnitTest.h" =20 // -----------------------------------------------------------------------= PageMode--TestCount-TestRangeCount---RandomOptions -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging4Level = =3D { Paging4Level, 100, 20, ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY }; -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging4Level1GB= =3D { Paging4Level1GB, 100, 20, ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY }; -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging5Level = =3D { Paging5Level, 100, 20, ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY }; -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging5Level1GB= =3D { Paging5Level1GB, 100, 20, ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY }; +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging4Level = =3D { Paging4Level, 100, 20, USE_RANDOM_ARRAY }; +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging4Level1GB= =3D { Paging4Level1GB, 100, 20, USE_RANDOM_ARRAY }; +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging5Level = =3D { Paging5Level, 100, 20, USE_RANDOM_ARRAY }; +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging5Level1GB= =3D { Paging5Level1GB, 100, 20, USE_RANDOM_ARRAY }; =20 /** Check if the input parameters are not supported. --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101640): https://edk2.groups.io/g/devel/message/101640 Mute This Topic: https://groups.io/mt/97796389/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 10:58:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101641+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101641+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679557306; cv=none; d=zohomail.com; s=zohoarc; b=ZP15v6aFFMqa3eT0prBN+6ffyqsZpiss+LkJ+4JrhyqdnNzbAC9JLhwfZCESOygGGfJKEG/bKe5CfAewssYGOaFXoB/mxhpbP6i9FHl+IeWfQUqaEr3RihkT511JPu8FFMMbF0QBUh/rXfq1Rvj7yROKDA86xFyLsWt5sv5qSxk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679557306; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=1fLVUw98ek+9v1xBweYF1Xx4ByrA4dDGI+YZrN3qC3E=; b=nHmIhb7o5+dqGGmHOZLNuHj8+SSAe3sQ2Kb6gnaxXRto5MzlOAAFJCIz78moacBLstLTO7YhCvAigtonrZzQ5vSFUqlat2mRF4c/woRP+ZV9drtlXa0CEWE5dn3L+Ai8ul3/lFAp9fLMjcUOKrbDMg1ouq5QFbHfk8d2h8S52+o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101641+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679557306375795.11515753225; Thu, 23 Mar 2023 00:41:46 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id UsoAYY1788612xtPi3WVspF3; Thu, 23 Mar 2023 00:41:46 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.66779.1679557305298569223 for ; Thu, 23 Mar 2023 00:41:45 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="425699746" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="425699746" X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="684616864" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="684616864" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:43 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V4 13/21] UefiCpuPkg/CpuPageTableLib: Add OUTPUT IsModified parameter. Date: Thu, 23 Mar 2023 15:40:49 +0800 Message-Id: <20230323074057.549-14-dun.tan@intel.com> In-Reply-To: <20230323074057.549-1-dun.tan@intel.com> References: <20230323074057.549-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: g5VQfk6ng5en7CIocn5MqCqJx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679557306; bh=3LPHUmINkCJlPj499HabXX/GXAZLxjD4+EPGZAi9so4=; h=Cc:Date:From:Reply-To:Subject:To; b=D8Cr0jNArv/P7+UywezHLnZMP7S13A/ok7sQBEJYMrg9usvGsj5qzljNFufB6TBNxSM /nPF7ycjFgkp8vQnRvhHRt6jStBNTA625owLMlNIUIZwcr3oDeZ8o3NfLpiqu954eWTXs KTCuKswNbCsCptr7bagiI7uRkBBeY7oGegY= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679557315624100001 Content-Type: text/plain; charset="utf-8" Add OUTPUT IsModified parameter in PageTableMap() to indicate if page table has been modified. With this parameter, caller can know if need to call FlushTlb when the page table is in CR3. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Tested-by: Gerd Hoffmann --- UefiCpuPkg/Include/Library/CpuPageTableLib.h = | 4 +++- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c = | 50 +++++++++++++++++++++++++++++++++++++++++++------- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c = | 72 ++++++++++++++++++++++++++++++++++++----------------------------------= -- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c = | 6 ++++-- UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c = | 6 ++++-- 5 files changed, 90 insertions(+), 48 deletions(-) diff --git a/UefiCpuPkg/Include/Library/CpuPageTableLib.h b/UefiCpuPkg/Incl= ude/Library/CpuPageTableLib.h index 6bda15b5bc..c94d82ea65 100644 --- a/UefiCpuPkg/Include/Library/CpuPageTableLib.h +++ b/UefiCpuPkg/Include/Library/CpuPageTableLib.h @@ -74,6 +74,7 @@ typedef enum { Page table entries that map the linear ad= dress range are reset to 0 before set to the new attribute when a new physical base address is set. @param[in] Mask The mask used for attribute. The correspo= nding field in Attribute is ignored if that in Mask is 0. + @param[out] IsModified TRUE means page table is modified. FALSE = means page table is not modified. =20 @retval RETURN_UNSUPPORTED PagingMode is not supported. @retval RETURN_INVALID_PARAMETER PageTable, BufferSize, Attribute or Ma= sk is NULL or the combination of Attribute and Mask is invalid. @@ -93,7 +94,8 @@ PageTableMap ( IN UINT64 LinearAddress, IN UINT64 Length, IN IA32_MAP_ATTRIBUTE *Attribute, - IN IA32_MAP_ATTRIBUTE *Mask + IN IA32_MAP_ATTRIBUTE *Mask, + OUT BOOLEAN *IsModified OPTIONAL ); =20 typedef struct { diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 2ad22b333d..797fc2f600 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -273,6 +273,7 @@ IsAttributesAndMaskValidForNonPresentEntry ( Page table entries that map the linear= address range are reset to 0 before set to the new attribute when a new physical base address is se= t. @param[in] Mask The mask used for attribute. The corre= sponding field in Attribute is ignored if that in Mask is 0. + @param[out] IsModified TRUE means page table is modified. FAL= SE means page table is not modified. =20 @retval RETURN_INVALID_PARAMETER The combination of Attribute and Mask = for non-present entry is invalid. @retval RETURN_SUCCESS PageTable is created/updated successfu= lly. @@ -290,7 +291,8 @@ PageTableLibMapInLevel ( IN UINT64 Length, IN UINT64 Offset, IN IA32_MAP_ATTRIBUTE *Attribute, - IN IA32_MAP_ATTRIBUTE *Mask + IN IA32_MAP_ATTRIBUTE *Mask, + OUT BOOLEAN *IsModified ) { RETURN_STATUS Status; @@ -316,6 +318,8 @@ PageTableLibMapInLevel ( IA32_MAP_ATTRIBUTE LocalParentAttribute; UINT64 PhysicalAddrInEntry; UINT64 PhysicalAddrInAttr; + IA32_PAGING_ENTRY OriginalParentPagingEntry; + IA32_PAGING_ENTRY OriginalCurrentPagingEntry; =20 ASSERT (Level !=3D 0); ASSERT ((Attribute !=3D NULL) && (Mask !=3D NULL)); @@ -328,8 +332,9 @@ PageTableLibMapInLevel ( NopAttribute.Bits.ReadWrite =3D 1; NopAttribute.Bits.UserSupervisor =3D 1; =20 - LocalParentAttribute.Uint64 =3D ParentAttribute->Uint64; - ParentAttribute =3D &LocalParentAttribute; + LocalParentAttribute.Uint64 =3D ParentAttribute->Uint64; + ParentAttribute =3D &LocalParentAttribute; + OriginalParentPagingEntry.Uint64 =3D ParentPagingEntry->Uint64; =20 // // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 << 2= 1) or 4K (1 << 12). @@ -563,7 +568,15 @@ PageTableLibMapInLevel ( ASSERT (CreateNew || (Mask->Bits.Nx =3D=3D 0) || (Attribute->Bit= s.Nx =3D=3D 1)); } =20 + // + // Check if any leaf PagingEntry is modified. + // + OriginalCurrentPagingEntry.Uint64 =3D CurrentPagingEntry->Uint64; PageTableLibSetPle (Level, CurrentPagingEntry, Offset, Attribute, = &CurrentMask); + + if (OriginalCurrentPagingEntry.Uint64 !=3D CurrentPagingEntry->Uin= t64) { + *IsModified =3D TRUE; + } } } else { // @@ -586,7 +599,8 @@ PageTableLibMapInLevel ( Length, Offset, Attribute, - Mask + Mask, + IsModified ); if (RETURN_ERROR (Status)) { return Status; @@ -598,6 +612,14 @@ PageTableLibMapInLevel ( Index++; } =20 + // + // Check if ParentPagingEntry entry is modified here is enough. Except t= he changes happen in leaf PagingEntry during + // the while loop, if there is any other change happens in page table, t= he ParentPagingEntry must has been modified. + // + if (OriginalParentPagingEntry.Uint64 !=3D ParentPagingEntry->Uint64) { + *IsModified =3D TRUE; + } + return RETURN_SUCCESS; } =20 @@ -618,6 +640,7 @@ PageTableLibMapInLevel ( Page table entries that map the linear ad= dress range are reset to 0 before set to the new attribute when a new physical base address is set. @param[in] Mask The mask used for attribute. The correspo= nding field in Attribute is ignored if that in Mask is 0. + @param[out] IsModified TRUE means page table is modified. FALSE = means page table is not modified. =20 @retval RETURN_UNSUPPORTED PagingMode is not supported. @retval RETURN_INVALID_PARAMETER PageTable, BufferSize, Attribute or Ma= sk is NULL or the combination of Attribute and Mask is invalid. @@ -637,7 +660,8 @@ PageTableMap ( IN UINT64 LinearAddress, IN UINT64 Length, IN IA32_MAP_ATTRIBUTE *Attribute, - IN IA32_MAP_ATTRIBUTE *Mask + IN IA32_MAP_ATTRIBUTE *Mask, + OUT BOOLEAN *IsModified OPTIONAL ) { RETURN_STATUS Status; @@ -647,6 +671,7 @@ PageTableMap ( IA32_PAGE_LEVEL MaxLevel; IA32_PAGE_LEVEL MaxLeafLevel; IA32_MAP_ATTRIBUTE ParentAttribute; + BOOLEAN LocalIsModified; =20 if (Length =3D=3D 0) { return RETURN_SUCCESS; @@ -709,6 +734,10 @@ PageTableMap ( TopPagingEntry.Pce.Nx =3D 0; } =20 + if (IsModified !=3D NULL) { + *IsModified =3D FALSE; + } + ParentAttribute.Uint64 =3D 0; ParentAttribute.Bits.PageTableBaseAddress =3D 1; ParentAttribute.Bits.Present =3D 1; @@ -732,7 +761,8 @@ PageTableMap ( Length, 0, Attribute, - Mask + Mask, + &LocalIsModified ); if (RETURN_ERROR (Status)) { return Status; @@ -749,6 +779,7 @@ PageTableMap ( return RETURN_INVALID_PARAMETER; } =20 + LocalIsModified =3D FALSE; // // Update the page table when the supplied buffer is sufficient. // @@ -764,8 +795,13 @@ PageTableMap ( Length, 0, Attribute, - Mask + Mask, + &LocalIsModified ); + if (IsModified !=3D NULL) { + *IsModified =3D LocalIsModified; + } + if (!RETURN_ERROR (Status)) { *PageTable =3D (UINTN)(TopPagingEntry.Uintn & IA32_PE_BASE_ADDRESS_MAS= K_40); } diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUni= tTestHost.c b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUn= itTestHost.c index d37cae9fbd..6343b56c2f 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c @@ -51,26 +51,26 @@ TestCaseForParameter ( // // If the input linear address is not 4K align, it should return invalid= parameter // - UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 1, SIZE_4KB, &MapAttribute, &MapMask), RETURN_INVALID_PARAMET= ER); + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 1, SIZE_4KB, &MapAttribute, &MapMask, NULL), RETURN_INVALID_P= ARAMETER); =20 // // If the input PageTableBufferSize is not 4K align, it should return in= valid parameter // PageTableBufferSize =3D 10; - UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 0, SIZE_4KB, &MapAttribute, &MapMask), RETURN_INVALID_PARAMET= ER); + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 0, SIZE_4KB, &MapAttribute, &MapMask, NULL), RETURN_INVALID_P= ARAMETER); =20 // // If the input PagingMode is Paging32bit, it should return invalid para= meter // PageTableBufferSize =3D 0; PagingMode =3D Paging32bit; - UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 1, SIZE_4KB, &MapAttribute, &MapMask), RETURN_UNSUPPORTED); + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 1, SIZE_4KB, &MapAttribute, &MapMask, NULL), RETURN_UNSUPPORT= ED); =20 // // If the input MapMask is NULL, it should return invalid parameter // PagingMode =3D Paging5Level1GB; - UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 1, SIZE_4KB, &MapAttribute, NULL), RETURN_INVALID_PARAMETER); + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 1, SIZE_4KB, &MapAttribute, NULL, NULL), RETURN_INVALID_PARAM= ETER); =20 return UNIT_TEST_PASSED; } @@ -119,10 +119,10 @@ TestCaseWhichNoNeedExtraSize ( // // Create page table to cover [0, 10M], it should have 5 PTE // - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, (UINT64)SIZE_2MB * 5, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, (UINT64)SIZE_2MB * 5, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, (UINT64)SIZE_2MB * 5, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, (UINT64)SIZE_2MB * 5, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); TestStatus =3D IsPageTableValid (PageTable, PagingMode); if (TestStatus !=3D UNIT_TEST_PASSED) { @@ -134,7 +134,7 @@ TestCaseWhichNoNeedExtraSize ( // We assume the fucntion doesn't need to change page table, return succ= ess and output BufferSize is 0 // Buffer =3D NULL; - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, (UINT64)SIZE_4KB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, (UINT64)SIZE_4KB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (PageTableBufferSize, 0); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); TestStatus =3D IsPageTableValid (PageTable, PagingMode); @@ -148,7 +148,7 @@ TestCaseWhichNoNeedExtraSize ( // MapMask.Bits.Nx =3D 0; PageTableBufferSize =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, NULL, &Pag= eTableBufferSize, 0, (UINT64)SIZE_4KB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, NULL, &Pag= eTableBufferSize, 0, (UINT64)SIZE_4KB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); UT_ASSERT_EQUAL (PageTableBufferSize, 0); TestStatus =3D IsPageTableValid (PageTable, PagingMode); @@ -164,7 +164,7 @@ TestCaseWhichNoNeedExtraSize ( MapAttribute.Bits.Accessed =3D 1; MapMask.Bits.Accessed =3D 1; PageTableBufferSize =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, NUL= L, &PageTableBufferSize, (UINT64)SIZE_2MB, (UINT64)SIZE_2MB, &MapAttribute,= &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, NUL= L, &PageTableBufferSize, (UINT64)SIZE_2MB, (UINT64)SIZE_2MB, &MapAttribute,= &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); UT_ASSERT_EQUAL (PageTableBufferSize, 0); TestStatus =3D IsPageTableValid (PageTable, PagingMode); @@ -217,10 +217,10 @@ TestCase1Gmapto4K ( MapAttribute.Bits.Present =3D 1; MapMask.Bits.Present =3D 1; MapMask.Uint64 =3D MAX_UINT64; - Status =3D PageTableMap (&PageTable, PagingMode, Buff= er, &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapM= ask); + Status =3D PageTableMap (&PageTable, PagingMode, Buff= er, &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapM= ask, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); =20 // @@ -281,11 +281,11 @@ TestCaseManualChangeReadWrite ( // // Create Page table to cover [0,2G], with ReadWrite =3D 1 // - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); BackupPageTableBufferSize =3D PageTableBufferSize; Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTabl= eBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buff= er, &PageTableBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buff= er, &PageTableBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); IsPageTableValid (PageTable, PagingMode); =20 @@ -331,7 +331,7 @@ TestCaseManualChangeReadWrite ( // Call library to change ReadWrite to 0 for [0,2M] // MapAttribute.Bits.ReadWrite =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, NU= LL, &PageTableBufferSize, 0, SIZE_2MB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, NU= LL, &PageTableBufferSize, 0, SIZE_2MB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); IsPageTableValid (PageTable, PagingMode); MapCount =3D 0; @@ -360,7 +360,7 @@ TestCaseManualChangeReadWrite ( // MapAttribute.Bits.ReadWrite =3D 1; PageTableBufferSize =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, NU= LL, &PageTableBufferSize, 0, SIZE_2MB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, NU= LL, &PageTableBufferSize, 0, SIZE_2MB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); IsPageTableValid (PageTable, PagingMode); MapCount =3D 0; @@ -434,10 +434,10 @@ TestCaseManualSizeNotMatch ( // // Create Page table to cover [2M-4K, 4M], with ReadWrite =3D 1 // - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, SIZE_2MB - SIZE_4KB, SIZE_4KB + SIZE_2MB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, SIZE_2MB - SIZE_4KB, SIZE_4KB + SIZE_2MB, &MapAttribute, &MapMask, N= ULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, SIZE_2MB - SIZE_4KB, SIZE_4KB + SIZE_2MB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, SIZE_2MB - SIZE_4KB, SIZE_4KB + SIZE_2MB, &MapAttribute, &MapMask, N= ULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); IsPageTableValid (PageTable, PagingMode); =20 @@ -493,7 +493,7 @@ TestCaseManualSizeNotMatch ( MapAttribute.Bits.ReadWrite =3D 1; PageTableBufferSize =3D 0; MapAttribute.Bits.PageTableBaseAddress =3D (SIZE_2MB - SIZE_4KB) >> 12; - Status =3D PageTableMap (&PageTable, Pag= ingMode, Buffer, &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB * 2, &= MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, Pag= ingMode, Buffer, &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB * 2, &= MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); return UNIT_TEST_PASSED; } @@ -540,10 +540,10 @@ TestCaseManualNotMergeEntry ( // // Create Page table to cover [0,4M], and [4M, 1G] is not present // - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_2MB * 2, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_2MB * 2, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_2MB * 2, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_2MB * 2, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); TestStatus =3D IsPageTableValid (PageTable, PagingMode); if (TestStatus !=3D UNIT_TEST_PASSED) { @@ -555,7 +555,7 @@ TestCaseManualNotMergeEntry ( // It looks like the chioce is not bad, but sometime, we need to keep so= me small entry // PageTableBufferSize =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, NULL, &Pag= eTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, NULL, &Pag= eTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapMask, NUL= L); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); TestStatus =3D IsPageTableValid (PageTable, PagingMode); if (TestStatus !=3D UNIT_TEST_PASSED) { @@ -564,7 +564,7 @@ TestCaseManualNotMergeEntry ( =20 MapAttribute.Bits.Accessed =3D 1; PageTableBufferSize =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, NUL= L, &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_2MB, &MapAttribute, &MapMa= sk); + Status =3D PageTableMap (&PageTable, PagingMode, NUL= L, &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_2MB, &MapAttribute, &MapMa= sk, NULL); // // If it didn't use a big 1G entry to cover whole range, only change [0,= 2M] for some attribute won't need extra memory // @@ -619,10 +619,10 @@ TestCaseManualChangeNx ( // // Create Page table to cover [0,2G], with Nx =3D 0 // - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_1GB * 2, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_1GB * 2, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_1GB * 2, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_1GB * 2, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); TestStatus =3D IsPageTableValid (PageTable, PagingMode); if (TestStatus !=3D UNIT_TEST_PASSED) { @@ -666,7 +666,7 @@ TestCaseManualChangeNx ( // // Call library to change Nx to 0 for [0,1G] // - Status =3D PageTableMap (&PageTable, PagingMode, NULL, &PageTableBufferS= ize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, NULL, &PageTableBufferS= ize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); TestStatus =3D IsPageTableValid (PageTable, PagingMode); if (TestStatus !=3D UNIT_TEST_PASSED) { @@ -741,30 +741,30 @@ TestCaseToCheckMapMaskAndAttr ( // // Create Page table to cover [0, 2G]. All fields of MapMask should be s= et. // - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); MapMask.Uint64 =3D MAX_UINT64; - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTa= bleBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTa= bleBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); =20 // // Update Page table to set [2G - 8K, 2G] from present to non-present. A= ll fields of MapMask except present should be set. // PageTableBufferSize =3D 0; - MapAttribute.Uint64 =3D SIZE_2GB - SIZE_8KB; + MapAttribute.Uint64 =3D 0; MapMask.Uint64 =3D 0; MapMask.Bits.Present =3D 1; MapMask.Bits.ReadWrite =3D 1; - Status =3D PageTableMap (&PageTable, PagingMode, Buffer,= &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMa= sk); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer,= &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMa= sk, NULL); UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); MapMask.Bits.ReadWrite =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, Buffer,= &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMa= sk); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer,= &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMa= sk, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); =20 // @@ -774,11 +774,11 @@ TestCaseToCheckMapMaskAndAttr ( MapAttribute.Uint64 =3D 0; MapMask.Uint64 =3D 0; MapMask.Bits.Present =3D 1; - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &= PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMask= ); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &= PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMask= , NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); MapAttribute.Bits.ReadWrite =3D 1; MapMask.Bits.ReadWrite =3D 1; - Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &= MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &= MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); =20 // @@ -791,10 +791,10 @@ TestCaseToCheckMapMaskAndAttr ( MapMask.Uint64 =3D 0; MapMask.Bits.ReadWrite =3D 1; MapMask.Bits.Present =3D 1; - Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &= MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &= MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); MapMask.Uint64 =3D MAX_UINT64; - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTa= bleBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTa= bleBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMask, NULL= ); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); =20 MapCount =3D 0; diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c index b99e31f4c8..816fd7b446 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c @@ -696,7 +696,8 @@ SingleMapEntryTest ( MapEntrys->Maps[MapsIndex].LinearAddress, MapEntrys->Maps[MapsIndex].Length, &MapEntrys->Maps[MapsIndex].Attribute, - &MapEntrys->Maps[MapsIndex].Mask + &MapEntrys->Maps[MapsIndex].Mask, + NULL ); =20 Attribute =3D &MapEntrys->Maps[MapsIndex].Attribute; @@ -756,7 +757,8 @@ SingleMapEntryTest ( MapEntrys->Maps[MapsIndex].LinearAddress, MapEntrys->Maps[MapsIndex].Length, &MapEntrys->Maps[MapsIndex].Attribute, - &MapEntrys->Maps[MapsIndex].Mask + &MapEntrys->Maps[MapsIndex].Mask, + NULL ); } =20 diff --git a/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c b/UefiCpuPk= g/Library/MpInitLib/X64/CreatePageTable.c index f20068152b..da8729e752 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c +++ b/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c @@ -57,7 +57,8 @@ CreatePageTable ( Address, Length, &MapAttribute, - &MapMask + &MapMask, + NULL ); ASSERT (Status =3D=3D EFI_BUFFER_TOO_SMALL); DEBUG ((DEBUG_INFO, "AP Page Table Buffer Size =3D %x\n", PageTableBuffe= rSize)); @@ -72,7 +73,8 @@ CreatePageTable ( Address, Length, &MapAttribute, - &MapMask + &MapMask, + NULL ); ASSERT_EFI_ERROR (Status); return PageTable; --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101641): https://edk2.groups.io/g/devel/message/101641 Mute This Topic: https://groups.io/mt/97796390/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 10:58:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101642+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101642+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679557309; cv=none; d=zohomail.com; s=zohoarc; b=Oqv40c6Y+bFHPMoQUQEsVGQXXgWjhd1P8Z0oNUKQ6qWlZh0vRrA4s04oLPTBNAWKmgucpHniRb8JxR6M0U6+Tfllj04uY3RN9eCdCq6Rb/4yr+iJ1+cxtypwne/Kq6ggEj9ZEaa5hAroxhPA5Zy22CJZaoa1wRhO2sYOln+LHRg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679557309; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=WmS4vGsHoqRhZeca76byfs44CG03QR96WsKu5SJMPQc=; b=Bxwm9NfSlwqD6fdQMqKamKXr9ygzPr6ODOoH2mBzXvFBAiNkXHKh1DvhUakthi7wTUOraQxNaI/ux3MwLZR71rtHaU2IIgVW+ZKZ6B9CT8Ldg36uot3e5lXNAFHwGgaPL15Cs9Fyf/jLqU8eWurClJhDpQ7f+yehXyrPU82PJsw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101642+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679557309738489.0024738483214; Thu, 23 Mar 2023 00:41:49 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id QkvbYY1788612xNftpMi8ZyJ; Thu, 23 Mar 2023 00:41:48 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.66779.1679557305298569223 for ; Thu, 23 Mar 2023 00:41:47 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="425699764" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="425699764" X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="684616868" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="684616868" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:45 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann , Zhiguang Liu Subject: [edk2-devel] [Patch V4 14/21] UefiCpuPkg/CpuPageTableLib: Modify RandomTest to check IsModified Date: Thu, 23 Mar 2023 15:40:50 +0800 Message-Id: <20230323074057.549-15-dun.tan@intel.com> In-Reply-To: <20230323074057.549-1-dun.tan@intel.com> References: <20230323074057.549-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: mjDHYcTWSWqBGmp8VzBxZj1qx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679557308; bh=DsZv+zcEys4AsUj5sxILw19BAQ4q8cGlVIXFDddKFKE=; h=Cc:Date:From:Reply-To:Subject:To; b=FMbi5B5JYKXG/RWybMBww741KOK0fEnEVcusTZ3UU0+uVnVRfUlRHT6tsMCYfgItb6I 0yjmErDA+sVvpvWkEtO/JtzGGyL9aEthArS4HMMLhe5SEoEFxQ6E1UrUiPCRVFlBYcaCc 85U0ESRQwfHQI6mHIIhuTg9vImwc2NtoAiY= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679557315871100004 Content-Type: text/plain; charset="utf-8" Modify RandomTest to check if parameter IsModified of PageTableMap() correctlly indicates whether input page table is modified or not. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Zhiguang Liu Acked-by: Gerd Hoffmann Reviewed-by: Ray Ni Tested-by: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c | 45 ++++++++++++= +++++++++++++++++++++------------ 1 file changed, 33 insertions(+), 12 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c index 816fd7b446..6f1485976a 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c @@ -636,6 +636,8 @@ SingleMapEntryTest ( VOID *Buffer; IA32_MAP_ENTRY *Map; UINTN MapCount; + IA32_MAP_ENTRY *Map2; + UINTN MapCount2; UINTN Index; UINTN KeyPointCount; UINTN NewKeyPointCount; @@ -648,11 +650,13 @@ SingleMapEntryTest ( UINT64 PreviousAddress; UINT64 RangeLimit; BOOLEAN IsNotPresent; + BOOLEAN IsModified; =20 MapsIndex =3D MapEntrys->Count; MapCount =3D 0; PreviousAddress =3D 0; IsNotPresent =3D FALSE; + IsModified =3D FALSE; =20 GenerateSingleRandomMapEntry (MaxAddress, MapEntrys); RangeLimit =3D MapEntrys->Maps[MapsIndex].LinearAddress + MapEntrys->Map= s[MapsIndex].Length; @@ -697,7 +701,7 @@ SingleMapEntryTest ( MapEntrys->Maps[MapsIndex].Length, &MapEntrys->Maps[MapsIndex].Attribute, &MapEntrys->Maps[MapsIndex].Mask, - NULL + &IsModified ); =20 Attribute =3D &MapEntrys->Maps[MapsIndex].Attribute; @@ -758,7 +762,7 @@ SingleMapEntryTest ( MapEntrys->Maps[MapsIndex].Length, &MapEntrys->Maps[MapsIndex].Attribute, &MapEntrys->Maps[MapsIndex].Mask, - NULL + &IsModified ); } =20 @@ -772,18 +776,31 @@ SingleMapEntryTest ( return TestStatus; } =20 - MapCount =3D 0; - Status =3D PageTableParse (*PageTable, PagingMode, NULL, &MapCount); - if (MapCount !=3D 0) { + MapCount2 =3D 0; + Status =3D PageTableParse (*PageTable, PagingMode, NULL, &MapCount2); + if (MapCount2 !=3D 0) { UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); =20 // - // Allocate memory for Maps + // Allocate memory for Map2 // Note the memory is only used in this one Single MapEntry Test // - Map =3D AllocatePages (EFI_SIZE_TO_PAGES (MapCount * sizeof (IA32_MAP_= ENTRY))); - ASSERT (Map !=3D NULL); - Status =3D PageTableParse (*PageTable, PagingMode, Map, &MapCount); + Map2 =3D AllocatePages (EFI_SIZE_TO_PAGES (MapCount2 * sizeof (IA32_MA= P_ENTRY))); + ASSERT (Map2 !=3D NULL); + Status =3D PageTableParse (*PageTable, PagingMode, Map2, &MapCount2); + } + + // + // Check if PageTable has been modified. + // + if (MapCount2 !=3D MapCount) { + UT_ASSERT_EQUAL (IsModified, TRUE); + } else { + if (CompareMem (Map, Map2, MapCount2 * sizeof (IA32_MAP_ENTRY)) !=3D 0= ) { + UT_ASSERT_EQUAL (IsModified, TRUE); + } else { + UT_ASSERT_EQUAL (IsModified, FALSE); + } } =20 UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); @@ -793,17 +810,17 @@ SingleMapEntryTest ( // Note the memory is only used in this one Single MapEntry Test // KeyPointCount =3D 0; - GetKeyPointList (MapEntrys, Map, MapCount, NULL, &KeyPointCount); + GetKeyPointList (MapEntrys, Map2, MapCount2, NULL, &KeyPointCount); KeyPointBuffer =3D AllocatePages (EFI_SIZE_TO_PAGES (KeyPointCount * siz= eof (UINT64))); ASSERT (KeyPointBuffer !=3D NULL); NewKeyPointCount =3D 0; - GetKeyPointList (MapEntrys, Map, MapCount, KeyPointBuffer, &NewKeyPointC= ount); + GetKeyPointList (MapEntrys, Map2, MapCount2, KeyPointBuffer, &NewKeyPoin= tCount); =20 // // Compare all key point's attribute // for (Index =3D 0; Index < NewKeyPointCount; Index++) { - if (!CompareEntrysforOnePoint (KeyPointBuffer[Index], MapEntrys, Map, = MapCount, InitMap, InitMapCount)) { + if (!CompareEntrysforOnePoint (KeyPointBuffer[Index], MapEntrys, Map2,= MapCount2, InitMap, InitMapCount)) { DEBUG ((DEBUG_INFO, "Error happens at below key point\n")); DEBUG ((DEBUG_INFO, "Index =3D %d KeyPointBuffer[Index] =3D 0x%lx\n"= , Index, KeyPointBuffer[Index])); Value =3D GetEntryFromPageTable (*PageTable, PagingMode, KeyPointBuf= fer[Index], &Level); @@ -817,6 +834,10 @@ SingleMapEntryTest ( FreePages (Map, EFI_SIZE_TO_PAGES (MapCount * sizeof (IA32_MAP_ENTRY))= ); } =20 + if (MapCount2 !=3D 0) { + FreePages (Map2, EFI_SIZE_TO_PAGES (MapCount2 * sizeof (IA32_MAP_ENTRY= ))); + } + return UNIT_TEST_PASSED; } =20 --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101642): https://edk2.groups.io/g/devel/message/101642 Mute This Topic: https://groups.io/mt/97796391/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 10:58:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101643+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101643+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679557310; cv=none; d=zohomail.com; s=zohoarc; b=WlD3rYnkd/FjjHzTWXhcjaPvNHtP+kgdGTn6AXVt0VXsodN1tW+X2RRsW8HaZv0imgGkxjdC21CeYHJdn9aTN01q0Y6na3TkPahc13+kl2lHJzDhnXjPIhKmBdCV7W0yj4DGQF9qgQB08QEDuvdkOwJiw+sRXA0K65/TRR/VsJg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679557310; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=mlVjTgTO+NtoA+3jcZfQHAbGT9Ho42B/I4VkVHmPKnQ=; b=J65+ok7Y5iXcCKJP86HuBDPT37y5fhIWND4i3rgXcRVUi4adKna9THHjJj0utCXFOM9UjSJyVycCcQE/V7ZsJtjAUsvDevk0hXU30TCTtdH6skkwYtVneplghlFrMi09bySSwU0FZP9AeKxOSEdzlkcH4vS903Ro0VZRULZhsJg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101643+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679557310951641.2151143779541; Thu, 23 Mar 2023 00:41:50 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id TzdXYY1788612x3QVODB4cwa; Thu, 23 Mar 2023 00:41:50 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.66779.1679557305298569223 for ; Thu, 23 Mar 2023 00:41:49 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="425699792" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="425699792" X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="684616873" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="684616873" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:47 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar Subject: [edk2-devel] [Patch V4 15/21] UefiCpuPkg: Fix IA32 build failure in CpuPageTableLib.inf Date: Thu, 23 Mar 2023 15:40:51 +0800 Message-Id: <20230323074057.549-16-dun.tan@intel.com> In-Reply-To: <20230323074057.549-1-dun.tan@intel.com> References: <20230323074057.549-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: a230EHmeymrrlrun8H5T1nxdx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679557310; bh=t+pmsinVN8o0CutYXeiX4FF/qbHEnZ61k0rW8gPRAhs=; h=Cc:Date:From:Reply-To:Subject:To; b=BNK99WCxIpL1CF87k0EWRnAmSKYyJbTgtTigVu/L0t9UEaqZFbHM/utR1JD05MY/xPK qtT635e3OMAJLYxLDohGaRfJxBsT7OWkBoWAII/cyYRAPTZiD9Rx1T4kSowaLV5gC6dPO S3/dBJ5CzRrDMDbHde/CDSf8z199a3/IYvw= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679557316631100011 Content-Type: text/plain; charset="utf-8" From: Zhiguang Liu The definition of IA32_MAP_ATTRIBUTE has 64 bits, and one of the bit field PageTableBaseAddress is from bit 12 to bit 52. This means if the compiler treats the 64bits value as two UINT32 value, the field PageTableBaseAddress spans two UINT32 value. That's why when building in NOOPT mode in IA32, the below issue is noticed: unresolved external symbol __allshl This patch fix the build failure by seperate field PageTableBaseAddress into two fields, make sure no field spans two UINT32 value. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Signed-off-by: Zhiguang Liu Signed-off-by: Ray Ni Acked-by: Gerd Hoffmann Reviewed-by: Ray Ni Tested-by: Gerd Hoffmann --- UefiCpuPkg/Include/Library/CpuPageTableLib.h | 32 +++++++++++++++= +---------------- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h | 125 +++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++---------------------------= ----------------------------------- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 22 +++++++++++----= ------- 3 files changed, 90 insertions(+), 89 deletions(-) diff --git a/UefiCpuPkg/Include/Library/CpuPageTableLib.h b/UefiCpuPkg/Incl= ude/Library/CpuPageTableLib.h index c94d82ea65..5e545a35f6 100644 --- a/UefiCpuPkg/Include/Library/CpuPageTableLib.h +++ b/UefiCpuPkg/Include/Library/CpuPageTableLib.h @@ -11,22 +11,22 @@ =20 typedef union { struct { - UINT64 Present : 1; // 0 =3D Not present in memory, 1 = =3D Present in memory - UINT64 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Write - UINT64 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser - UINT64 WriteThrough : 1; // 0 =3D Write-Back caching, 1=3DW= rite-Through caching - UINT64 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cached - UINT64 Accessed : 1; // 0 =3D Not accessed, 1 =3D Acces= sed (set by CPU) - UINT64 Dirty : 1; // 0 =3D Not dirty, 1 =3D Dirty (s= et by CPU) - UINT64 Pat : 1; // PAT - - UINT64 Global : 1; // 0 =3D Not global, 1 =3D Global = (if CR4.PGE =3D 1) - UINT64 Reserved1 : 3; // Ignored - - UINT64 PageTableBaseAddress : 40; // Page Table Base Address - UINT64 Reserved2 : 7; // Ignored - UINT64 ProtectionKey : 4; // Protection key - UINT64 Nx : 1; // No Execute bit + UINT32 Present : 1; // 0 =3D Not present in memor= y, 1 =3D Present in memory + UINT32 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read= /Write + UINT32 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser + UINT32 WriteThrough : 1; // 0 =3D Write-Back caching, = 1=3DWrite-Through caching + UINT32 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cach= ed + UINT32 Accessed : 1; // 0 =3D Not accessed, 1 =3D = Accessed (set by CPU) + UINT32 Dirty : 1; // 0 =3D Not dirty, 1 =3D Dir= ty (set by CPU) + UINT32 Pat : 1; // PAT + UINT32 Global : 1; // 0 =3D Not global, 1 =3D Gl= obal (if CR4.PGE =3D 1) + UINT32 Reserved1 : 3; // Ignored + UINT32 PageTableBaseAddressLow : 20; // Page Table Base Address Low + + UINT32 PageTableBaseAddressHigh : 20; // Page Table Base Address Hi= gh + UINT32 Reserved2 : 7; // Ignored + UINT32 ProtectionKey : 4; // Protection key + UINT32 Nx : 1; // No Execute bit } Bits; UINT64 Uint64; } IA32_MAP_ATTRIBUTE; diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h b/UefiCpuPkg= /Library/CpuPageTableLib/CpuPageTable.h index 8d856d7c7e..2c67ecb469 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h @@ -29,11 +29,12 @@ typedef enum { } IA32_PAGE_LEVEL; =20 typedef struct { - UINT64 Present : 1; // 0 =3D Not present in memory, 1 = =3D Present in memory - UINT64 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Write - UINT64 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser - UINT64 Reserved : 58; - UINT64 Nx : 1; // No Execute bit + UINT32 Present : 1; // 0 =3D Not present in memory, 1 = =3D Present in memory + UINT32 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Write + UINT32 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser + UINT32 Reserved0 : 29; + UINT32 Reserved1 : 31; + UINT32 Nx : 1; // No Execute bit } IA32_PAGE_COMMON_ENTRY; =20 /// @@ -41,20 +42,20 @@ typedef struct { /// typedef union { struct { - UINT64 Present : 1; // 0 =3D Not present in memory, 1 = =3D Present in memory - UINT64 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Write - UINT64 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser - UINT64 WriteThrough : 1; // 0 =3D Write-Back caching, 1=3DW= rite-Through caching - UINT64 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cached - UINT64 Accessed : 1; // 0 =3D Not accessed, 1 =3D Acces= sed (set by CPU) - UINT64 Available0 : 1; // Ignored - UINT64 MustBeZero : 1; // Must Be Zero - - UINT64 Available2 : 4; // Ignored - - UINT64 PageTableBaseAddress : 40; // Page Table Base Address - UINT64 Available3 : 11; // Ignored - UINT64 Nx : 1; // No Execute bit + UINT32 Present : 1; // 0 =3D Not present in memor= y, 1 =3D Present in memory + UINT32 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read= /Write + UINT32 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser + UINT32 WriteThrough : 1; // 0 =3D Write-Back caching, = 1=3DWrite-Through caching + UINT32 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cach= ed + UINT32 Accessed : 1; // 0 =3D Not accessed, 1 =3D = Accessed (set by CPU) + UINT32 Available0 : 1; // Ignored + UINT32 MustBeZero : 1; // Must Be Zero + UINT32 Available2 : 4; // Ignored + UINT32 PageTableBaseAddressLow : 20; // Page Table Base Address Low + + UINT32 PageTableBaseAddressHigh : 20; // Page Table Base Address Hi= gh + UINT32 Available3 : 11; // Ignored + UINT32 Nx : 1; // No Execute bit } Bits; UINT64 Uint64; } IA32_PAGE_NON_LEAF_ENTRY; @@ -86,23 +87,23 @@ typedef IA32_PAGE_NON_LEAF_ENTRY IA32_PDE; /// typedef union { struct { - UINT64 Present : 1; // 0 =3D Not present in memory, 1 = =3D Present in memory - UINT64 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Write - UINT64 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser - UINT64 WriteThrough : 1; // 0 =3D Write-Back caching, 1=3DW= rite-Through caching - UINT64 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cached - UINT64 Accessed : 1; // 0 =3D Not accessed, 1 =3D Acces= sed (set by CPU) - UINT64 Dirty : 1; // 0 =3D Not dirty, 1 =3D Dirty (s= et by CPU) - UINT64 MustBeOne : 1; // Page Size. Must Be One - - UINT64 Global : 1; // 0 =3D Not global, 1 =3D Global = (if CR4.PGE =3D 1) - UINT64 Available1 : 3; // Ignored - UINT64 Pat : 1; // PAT - - UINT64 PageTableBaseAddress : 39; // Page Table Base Address - UINT64 Available3 : 7; // Ignored - UINT64 ProtectionKey : 4; // Protection key - UINT64 Nx : 1; // No Execute bit + UINT32 Present : 1; // 0 =3D Not present in memor= y, 1 =3D Present in memory + UINT32 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read= /Write + UINT32 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser + UINT32 WriteThrough : 1; // 0 =3D Write-Back caching, = 1=3DWrite-Through caching + UINT32 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cach= ed + UINT32 Accessed : 1; // 0 =3D Not accessed, 1 =3D = Accessed (set by CPU) + UINT32 Dirty : 1; // 0 =3D Not dirty, 1 =3D Dir= ty (set by CPU) + UINT32 MustBeOne : 1; // Page Size. Must Be One + UINT32 Global : 1; // 0 =3D Not global, 1 =3D Gl= obal (if CR4.PGE =3D 1) + UINT32 Available1 : 3; // Ignored + UINT32 Pat : 1; // PAT + UINT32 PageTableBaseAddressLow : 19; // Page Table Base Address Low + + UINT32 PageTableBaseAddressHigh : 20; // Page Table Base Address Hi= gh + UINT32 Available3 : 7; // Ignored + UINT32 ProtectionKey : 4; // Protection key + UINT32 Nx : 1; // No Execute bit } Bits; UINT64 Uint64; } IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE; @@ -123,22 +124,22 @@ typedef IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE IA32_PDPTE_= 1G; /// typedef union { struct { - UINT64 Present : 1; // 0 =3D Not present in memory, 1 = =3D Present in memory - UINT64 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Write - UINT64 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser - UINT64 WriteThrough : 1; // 0 =3D Write-Back caching, 1=3DW= rite-Through caching - UINT64 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cached - UINT64 Accessed : 1; // 0 =3D Not accessed, 1 =3D Acces= sed (set by CPU) - UINT64 Dirty : 1; // 0 =3D Not dirty, 1 =3D Dirty (s= et by CPU) - UINT64 Pat : 1; // PAT - - UINT64 Global : 1; // 0 =3D Not global, 1 =3D Global = (if CR4.PGE =3D 1) - UINT64 Available1 : 3; // Ignored - - UINT64 PageTableBaseAddress : 40; // Page Table Base Address - UINT64 Available3 : 7; // Ignored - UINT64 ProtectionKey : 4; // Protection key - UINT64 Nx : 1; // No Execute bit + UINT32 Present : 1; // 0 =3D Not present in memor= y, 1 =3D Present in memory + UINT32 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read= /Write + UINT32 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser + UINT32 WriteThrough : 1; // 0 =3D Write-Back caching, = 1=3DWrite-Through caching + UINT32 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cach= ed + UINT32 Accessed : 1; // 0 =3D Not accessed, 1 =3D = Accessed (set by CPU) + UINT32 Dirty : 1; // 0 =3D Not dirty, 1 =3D Dir= ty (set by CPU) + UINT32 Pat : 1; // PAT + UINT32 Global : 1; // 0 =3D Not global, 1 =3D Gl= obal (if CR4.PGE =3D 1) + UINT32 Available1 : 3; // Ignored + UINT32 PageTableBaseAddressLow : 20; // Page Table Base Address Low + + UINT32 PageTableBaseAddressHigh : 20; // Page Table Base Address Hi= gh + UINT32 Available3 : 7; // Ignored + UINT32 ProtectionKey : 4; // Protection key + UINT32 Nx : 1; // No Execute bit } Bits; UINT64 Uint64; } IA32_PTE_4K; @@ -149,16 +150,16 @@ typedef union { /// typedef union { struct { - UINT64 Present : 1; // 0 =3D Not present in memory, 1 = =3D Present in memory - UINT64 MustBeZero : 2; // Must Be Zero - UINT64 WriteThrough : 1; // 0 =3D Write-Back caching, 1=3DW= rite-Through caching - UINT64 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cached - UINT64 MustBeZero2 : 4; // Must Be Zero - - UINT64 Available : 3; // Ignored - - UINT64 PageTableBaseAddress : 40; // Page Table Base Address - UINT64 MustBeZero3 : 12; // Must Be Zero + UINT32 Present : 1; // 0 =3D Not present in memor= y, 1 =3D Present in memory + UINT32 MustBeZero : 2; // Must Be Zero + UINT32 WriteThrough : 1; // 0 =3D Write-Back caching, = 1=3DWrite-Through caching + UINT32 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cach= ed + UINT32 MustBeZero2 : 4; // Must Be Zero + UINT32 Available : 3; // Ignored + UINT32 PageTableBaseAddressLow : 20; // Page Table Base Address Low + + UINT32 PageTableBaseAddressHigh : 20; // Page Table Base Address Hi= gh + UINT32 MustBeZero3 : 12; // Must Be Zero } Bits; UINT64 Uint64; } IA32_PDPTE_PAE; diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 797fc2f600..982652b58b 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -26,7 +26,7 @@ PageTableLibSetPte4K ( IN IA32_MAP_ATTRIBUTE *Mask ) { - if (Mask->Bits.PageTableBaseAddress) { + if (Mask->Bits.PageTableBaseAddressLow || Mask->Bits.PageTableBaseAddres= sHigh) { Pte4K->Uint64 =3D (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribu= te) + Offset) | (Pte4K->Uint64 & ~IA32_PE_BASE_ADDRESS_MASK_40); } =20 @@ -93,7 +93,7 @@ PageTableLibSetPleB ( IN IA32_MAP_ATTRIBUTE *Mask ) { - if (Mask->Bits.PageTableBaseAddress) { + if (Mask->Bits.PageTableBaseAddressLow || Mask->Bits.PageTableBaseAddres= sHigh) { PleB->Uint64 =3D (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribut= e) + Offset) | (PleB->Uint64 & ~IA32_PE_BASE_ADDRESS_MASK_39); } =20 @@ -238,7 +238,7 @@ IsAttributesAndMaskValidForNonPresentEntry ( // if ((Mask->Bits.ReadWrite =3D=3D 0) || (Mask->Bits.UserSupervisor =3D= =3D 0) || (Mask->Bits.WriteThrough =3D=3D 0) || (Mask->Bits.CacheDisabled = =3D=3D 0) || (Mask->Bits.Accessed =3D=3D 0) || (Mask->Bits.Dirty =3D=3D 0) || (= Mask->Bits.Pat =3D=3D 0) || (Mask->Bits.Global =3D=3D 0) || - (Mask->Bits.PageTableBaseAddress =3D=3D 0) || (Mask->Bits.Protecti= onKey =3D=3D 0) || (Mask->Bits.Nx =3D=3D 0)) + ((Mask->Bits.PageTableBaseAddressLow =3D=3D 0) && (Mask->Bits.Page= TableBaseAddressHigh =3D=3D 0)) || (Mask->Bits.ProtectionKey =3D=3D 0) || (= Mask->Bits.Nx =3D=3D 0)) { return RETURN_INVALID_PARAMETER; } @@ -396,7 +396,7 @@ PageTableLibMapInLevel ( // This function is called when the memory length is less than the r= egion length of the parent level. // No need to split the page when the attributes equal. // - if (Mask->Bits.PageTableBaseAddress =3D=3D 0) { + if ((Mask->Bits.PageTableBaseAddressLow =3D=3D 0) && (Mask->Bits.Pag= eTableBaseAddressHigh =3D=3D 0)) { return RETURN_SUCCESS; } =20 @@ -696,7 +696,7 @@ PageTableMap ( return RETURN_INVALID_PARAMETER; } =20 - if ((LinearAddress % SIZE_4KB !=3D 0) || (Length % SIZE_4KB !=3D 0)) { + if (((UINTN)LinearAddress % SIZE_4KB !=3D 0) || ((UINTN)Length % SIZE_4K= B !=3D 0)) { // // LinearAddress and Length should be multiple of 4K. // @@ -738,12 +738,12 @@ PageTableMap ( *IsModified =3D FALSE; } =20 - ParentAttribute.Uint64 =3D 0; - ParentAttribute.Bits.PageTableBaseAddress =3D 1; - ParentAttribute.Bits.Present =3D 1; - ParentAttribute.Bits.ReadWrite =3D 1; - ParentAttribute.Bits.UserSupervisor =3D 1; - ParentAttribute.Bits.Nx =3D 0; + ParentAttribute.Uint64 =3D 0; + ParentAttribute.Bits.PageTableBaseAddressLow =3D 1; + ParentAttribute.Bits.Present =3D 1; + ParentAttribute.Bits.ReadWrite =3D 1; + ParentAttribute.Bits.UserSupervisor =3D 1; + ParentAttribute.Bits.Nx =3D 0; =20 // // Query the required buffer size without modifying the page table. --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101643): https://edk2.groups.io/g/devel/message/101643 Mute This Topic: https://groups.io/mt/97796393/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 10:58:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101644+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101644+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679557312; cv=none; d=zohomail.com; s=zohoarc; b=HGgXChS95ZRQ6GVWGXo+4XtHewTi8+8nPAas4XGp7+x1jRmdQnUmUJ6nFxygtj4FMRgICjG332YND19J+yxRD+/OFnJXoOWBThU4oLRE5UkV2bkw4N8Holy6HgH0TveiCKh+nBvoPl8fxkJ8hlSUla9i+L6dshqoRKa4aaCWA1s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679557312; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=NesqCWs2EPEjF+UyIOphUIbMpX4vvOi8TuA5C3+bUjo=; b=CGFM9X0MwquG0Wp1Q2wBOqKzJ/QPCgo1UkTzMpFmyzFL55QJPvouS4BmBw+GJTuLk6rTgh0NoRE5p6/aSKtnMCvgSt56AxNZzb/NfPy0t9rIGOjyAZwFEuZx2mYy9h1VrOZ2cqcOQEeTg6UZDt5YX41DDNwK6ETjaeV8kBcBdzs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101644+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679557312904238.61222413075677; Thu, 23 Mar 2023 00:41:52 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 28hJYY1788612xxQ94s64ZNo; Thu, 23 Mar 2023 00:41:52 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.66779.1679557305298569223 for ; Thu, 23 Mar 2023 00:41:52 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="425699812" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="425699812" X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="684616880" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="684616880" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:50 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar Subject: [edk2-devel] [Patch V4 16/21] UefiCpuPkg: Modify UnitTest code since tested API is changed Date: Thu, 23 Mar 2023 15:40:52 +0800 Message-Id: <20230323074057.549-17-dun.tan@intel.com> In-Reply-To: <20230323074057.549-1-dun.tan@intel.com> References: <20230323074057.549-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: IF9K02H6Mg61rmiunhvsaSZpx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679557312; bh=ZFZ9zAPK2eM+mkiBQ8wbJzQRjIaTlryl/pXwN1F5R4o=; h=Cc:Date:From:Reply-To:Subject:To; b=vlNlVhQGSbGZpHL1RX1Y7N6Be6sejn75Or0Zmz+tWIHJL4Wbor6DdXoc2D4flBEWFjn aKjySnJDmKVLvFoAH2T9a9q3bj1hII3nsdrkrrVX+xsAjKhD5Al0NMf8z8NxBvH2dfL8P KysV0DzEs8m9on6s1GC/WUfTQn/L9UOu1Ng= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679557317057100015 Content-Type: text/plain; charset="utf-8" From: Zhiguang Liu Last commit changed the CpuPageTableLib API PageTableMap, unit test code should also be modified. Cc: Eric Dong Reviewed-by: Ray Ni Cc: Rahul Kumar Signed-off-by: Zhiguang Liu Acked-by: Gerd Hoffmann Tested-by: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c = | 38 ++++++++++++++++++-------------------- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c = | 84 +++++++++++++++++++++++++++++++++++++++++++++++-----------------------= -------------- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c = | 4 ++-- 3 files changed, 67 insertions(+), 59 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUni= tTestHost.c b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUn= itTestHost.c index 6343b56c2f..e1efc84c82 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c @@ -422,15 +422,14 @@ TestCaseManualSizeNotMatch ( UINTN MapCount; IA32_PAGING_ENTRY *PagingEntry; =20 - PagingMode =3D Paging4Level; - PageTableBufferSize =3D 0; - PageTable =3D 0; - Buffer =3D NULL; - MapAttribute.Uint64 =3D 0; - MapMask.Uint64 =3D MAX_UINT64; - MapAttribute.Bits.Present =3D 1; - MapAttribute.Bits.ReadWrite =3D 1; - MapAttribute.Bits.PageTableBaseAddress =3D (SIZE_2MB - SIZE_4KB) >> 12; + PagingMode =3D Paging4Level; + PageTableBufferSize =3D 0; + PageTable =3D 0; + Buffer =3D NULL; + MapMask.Uint64 =3D MAX_UINT64; + MapAttribute.Uint64 =3D (SIZE_2MB - SIZE_4KB); + MapAttribute.Bits.Present =3D 1; + MapAttribute.Bits.ReadWrite =3D 1; // // Create Page table to cover [2M-4K, 4M], with ReadWrite =3D 1 // @@ -460,9 +459,9 @@ TestCaseManualSizeNotMatch ( // [2M-4K,2M], R/W =3D 0 // [2M ,4M], R/W =3D 1 // - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)PageTable; = // Get 4 level entry - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(PagingEntry->Pnle.B= its.PageTableBaseAddress << 12); // Get 3 level entry - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(PagingEntry->Pnle.B= its.PageTableBaseAddress << 12); // Get 2 level entry + PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)PageTable; = // Get 4 level entry + PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE= _BASE_ADDRESS (PagingEntry); // Get 3 level entry + PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE= _BASE_ADDRESS (PagingEntry); // Get 2 level entry PagingEntry->Uint64 =3D PagingEntry->Uint64 & (~(UINT64)0x2); MapCount =3D 0; Status =3D PageTableParse (PageTable, PagingMode, NULL, &Ma= pCount); @@ -480,20 +479,19 @@ TestCaseManualSizeNotMatch ( =20 UT_ASSERT_EQUAL (Map[1].LinearAddress, SIZE_2MB); UT_ASSERT_EQUAL (Map[1].Length, SIZE_2MB); - ExpectedMapAttribute.Uint64 =3D MapAttribute.Uint64; - ExpectedMapAttribute.Bits.ReadWrite =3D 1; - ExpectedMapAttribute.Bits.PageTableBaseAddress =3D SIZE_2MB >> 12; + ExpectedMapAttribute.Uint64 =3D MapAttribute.Uint64 + SIZE_4KB; + ExpectedMapAttribute.Bits.ReadWrite =3D 1; UT_ASSERT_EQUAL (Map[1].Attribute.Uint64, ExpectedMapAttribute.Uint64); =20 // // Set Page table [2M-4K, 2M+4K]'s ReadWrite =3D 1, [2M,2M+4K]'s ReadWri= te is already 1 // Just need to set [2M-4K,2M], won't need extra size, so the status sho= uld be success // - MapAttribute.Bits.Present =3D 1; - MapAttribute.Bits.ReadWrite =3D 1; - PageTableBufferSize =3D 0; - MapAttribute.Bits.PageTableBaseAddress =3D (SIZE_2MB - SIZE_4KB) >> 12; - Status =3D PageTableMap (&PageTable, Pag= ingMode, Buffer, &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB * 2, &= MapAttribute, &MapMask, NULL); + MapAttribute.Uint64 =3D SIZE_2MB - SIZE_4KB; + MapAttribute.Bits.Present =3D 1; + MapAttribute.Bits.ReadWrite =3D 1; + PageTableBufferSize =3D 0; + Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB * 2, &MapAttribut= e, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); return UNIT_TEST_PASSED; } diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c index 6f1485976a..18a5010c30 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c @@ -157,7 +157,8 @@ ValidateAndRandomeModifyPageTablePageTableEntry ( ) { UINT64 Index; - UINT64 TempPhysicalBase; + UINT32 PageTableBaseAddressLow; + UINT32 PageTableBaseAddressHigh; IA32_PAGING_ENTRY *ChildPageEntry; UNIT_TEST_STATUS Status; =20 @@ -180,17 +181,21 @@ ValidateAndRandomeModifyPageTablePageTableEntry ( if ((RandomNumber < 100) && RandomBoolean (50)) { RandomNumber++; if (Level =3D=3D 1) { - TempPhysicalBase =3D PagingEntry->Pte4K.Bits.PageTableBaseAddress; + PageTableBaseAddressLow =3D PagingEntry->Pte4K.Bits.PageTableBase= AddressLow; + PageTableBaseAddressHigh =3D PagingEntry->Pte4K.Bits.PageTableBase= AddressHigh; } else { - TempPhysicalBase =3D PagingEntry->PleB.Bits.PageTableBaseAddress; + PageTableBaseAddressLow =3D PagingEntry->PleB.Bits.PageTableBaseA= ddressLow; + PageTableBaseAddressHigh =3D PagingEntry->PleB.Bits.PageTableBaseA= ddressHigh; } =20 PagingEntry->Uint64 =3D (Random64 (0, MAX_UINT64) & mVal= idMaskLeaf[Level].Uint64) | mValidMaskLeafFlag[Level].Uint64; PagingEntry->Pte4K.Bits.Present =3D 1; if (Level =3D=3D 1) { - PagingEntry->Pte4K.Bits.PageTableBaseAddress =3D TempPhysicalBase; + PagingEntry->Pte4K.Bits.PageTableBaseAddressLow =3D PageTableBase= AddressLow; + PagingEntry->Pte4K.Bits.PageTableBaseAddressHigh =3D PageTableBase= AddressHigh; } else { - PagingEntry->PleB.Bits.PageTableBaseAddress =3D TempPhysicalBase; + PagingEntry->PleB.Bits.PageTableBaseAddressLow =3D PageTableBaseA= ddressLow; + PagingEntry->PleB.Bits.PageTableBaseAddressHigh =3D PageTableBaseA= ddressHigh; } =20 if ((PagingEntry->Uint64 & mValidMaskLeaf[Level].Uint64) !=3D Paging= Entry->Uint64) { @@ -212,15 +217,17 @@ ValidateAndRandomeModifyPageTablePageTableEntry ( =20 if ((RandomNumber < 100) && RandomBoolean (50)) { RandomNumber++; - TempPhysicalBase =3D PagingEntry->Pnle.Bits.PageTableBaseAddress; + PageTableBaseAddressLow =3D PagingEntry->PleB.Bits.PageTableBaseAddre= ssLow; + PageTableBaseAddressHigh =3D PagingEntry->PleB.Bits.PageTableBaseAddre= ssHigh; =20 - PagingEntry->Uint64 =3D Random64 (0, MAX_UINT6= 4) & mValidMaskNoLeaf[Level].Uint64; - PagingEntry->Pnle.Bits.Present =3D 1; - PagingEntry->Pnle.Bits.PageTableBaseAddress =3D TempPhysicalBase; + PagingEntry->Uint64 =3D Random64 (0, MAX_U= INT64) & mValidMaskNoLeaf[Level].Uint64; + PagingEntry->Pnle.Bits.Present =3D 1; + PagingEntry->PleB.Bits.PageTableBaseAddressLow =3D PageTableBaseAddre= ssLow; + PagingEntry->PleB.Bits.PageTableBaseAddressHigh =3D PageTableBaseAddre= ssHigh; ASSERT ((PagingEntry->Uint64 & mValidMaskLeafFlag[Level].Uint64) !=3D = mValidMaskLeafFlag[Level].Uint64); } =20 - ChildPageEntry =3D (IA32_PAGING_ENTRY *)(UINTN)((PagingEntry->Pnle.Bits= .PageTableBaseAddress) << 12); + ChildPageEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(IA32_PNLE_PAGE_TABLE_BA= SE_ADDRESS (&PagingEntry->Pnle)); for (Index =3D 0; Index < 512; Index++) { Status =3D ValidateAndRandomeModifyPageTablePageTableEntry (&ChildPage= Entry[Index], Level-1, MaxLeafLevel, Address + (Index<<(9*(Level-1) + 3))); if (Status !=3D UNIT_TEST_PASSED) { @@ -364,10 +371,12 @@ GenerateSingleRandomMapEntry ( } =20 if (mRandomOption & ONLY_ONE_ONE_MAPPING) { - MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress =3D Map= Entrys->Maps[MapsIndex].LinearAddress >> 12; - MapEntrys->Maps[MapsIndex].Mask.Bits.PageTableBaseAddress =3D 0xF= FFFFFFFFF; + MapEntrys->Maps[MapsIndex].Attribute.Uint64 &=3D (~IA32_MAP_ATTRIBUTE_= PAGE_TABLE_BASE_ADDRESS_MASK); + MapEntrys->Maps[MapsIndex].Attribute.Uint64 |=3D MapEntrys->Maps[MapsI= ndex].LinearAddress; + MapEntrys->Maps[MapsIndex].Mask.Uint64 |=3D IA32_MAP_ATTRIBUTE_PA= GE_TABLE_BASE_ADDRESS_MASK; } else { - MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress =3D (Ra= ndom64 (0, (((UINT64)1)<<52) - 1) & AlignedTable[Random32 (0, ARRAY_SIZE (A= lignedTable) -1)])>> 12; + MapEntrys->Maps[MapsIndex].Attribute.Uint64 &=3D (~IA32_MAP_ATTRIBUTE_= PAGE_TABLE_BASE_ADDRESS_MASK); + MapEntrys->Maps[MapsIndex].Attribute.Uint64 |=3D (Random64 (0, (((UINT= 64)1)<<52) - 1) & AlignedTable[Random32 (0, ARRAY_SIZE (AlignedTable) -1)]); } =20 MapEntrys->Count +=3D 1; @@ -414,8 +423,9 @@ CompareEntrysforOnePoint ( // for (Index =3D 0; Index < MapCount; Index++) { if ((Address >=3D Map[Index].LinearAddress) && (Address < (Map[Index].= LinearAddress + Map[Index].Length))) { - AttributeInMap.Uint64 =3D (Map[Index].Attribute.U= int64 & mSupportedBit.Uint64); - AttributeInMap.Bits.PageTableBaseAddress =3D ((Address - Map[Index].= LinearAddress) >> 12) + Map[Index].Attribute.Bits.PageTableBaseAddress; + AttributeInMap.Uint64 =3D (Map[Index].Attribute.Uint64 & mSupported= Bit.Uint64); + AttributeInMap.Uint64 &=3D (~IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDR= ESS_MASK); + AttributeInMap.Uint64 |=3D (Address - Map[Index].LinearAddress + IA3= 2_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&Map[Index].Attribute)) & IA32_MAP= _ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK; break; } } @@ -425,8 +435,10 @@ CompareEntrysforOnePoint ( // for (Index =3D 0; Index < InitMapCount; Index++) { if ((Address >=3D InitMap[Index].LinearAddress) && (Address < (InitMap= [Index].LinearAddress + InitMap[Index].Length))) { - AttributeInInitMap.Uint64 =3D (InitMap[Index].Att= ribute.Uint64 & mSupportedBit.Uint64); - AttributeInInitMap.Bits.PageTableBaseAddress =3D ((Address - InitMap= [Index].LinearAddress) >> 12) + InitMap[Index].Attribute.Bits.PageTableBase= Address; + AttributeInInitMap.Uint64 =3D (InitMap[Index].Attribute.Uint64 & mS= upportedBit.Uint64); + AttributeInInitMap.Uint64 &=3D (~IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_= ADDRESS_MASK); + AttributeInInitMap.Uint64 |=3D (Address - InitMap[Index].LinearAddre= ss + IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&InitMap[Index].Attribute)= ) & IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK; + break; } } @@ -443,8 +455,9 @@ CompareEntrysforOnePoint ( MaskInMapEntrys.Uint64 |=3D MapEntrys->Maps[Index].Mask.Uint64; AttributeInMapEntrys.Uint64 &=3D (~MapEntrys->Maps[Index].Mask.Uint6= 4); AttributeInMapEntrys.Uint64 |=3D (MapEntrys->Maps[Index].Attribute.= Uint64 & MapEntrys->Maps[Index].Mask.Uint64); - if (MapEntrys->Maps[Index].Mask.Bits.PageTableBaseAddress !=3D 0) { - AttributeInMapEntrys.Bits.PageTableBaseAddress =3D ((Address - Map= Entrys->Maps[Index].LinearAddress) >> 12) + MapEntrys->Maps[Index].Attribut= e.Bits.PageTableBaseAddress; + if (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&MapEntrys->Maps[Ind= ex].Mask) !=3D 0) { + AttributeInMapEntrys.Uint64 &=3D (~IA32_MAP_ATTRIBUTE_PAGE_TABLE_B= ASE_ADDRESS_MASK); + AttributeInMapEntrys.Uint64 |=3D (Address - MapEntrys->Maps[Index]= .LinearAddress + IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&MapEntrys->Ma= ps[Index].Attribute)) & IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK; } } } @@ -458,8 +471,8 @@ CompareEntrysforOnePoint ( if ((AttributeInMap.Uint64 & MaskInMapEntrys.Uint64) !=3D (AttributeInMa= pEntrys.Uint64 & MaskInMapEntrys.Uint64)) { DEBUG ((DEBUG_INFO, "=3D=3D=3D=3D=3D=3Ddetailed information begin=3D= =3D=3D=3D=3D\n")); DEBUG ((DEBUG_INFO, "\nError: Detect different attribute on a point wi= th linear address: 0x%lx\n", Address)); - DEBUG ((DEBUG_INFO, "By parsing page table, the point has Attribute 0x= %lx, and map to physical address 0x%lx\n", IA32_MAP_ATTRIBUTE_ATTRIBUTES (&= AttributeInMap) & MaskInMapEntrys.Uint64, AttributeInMap.Bits.PageTableBase= Address)); - DEBUG ((DEBUG_INFO, "While according to inputs, the point should Attri= bute 0x%lx, and should map to physical address 0x%lx\n", IA32_MAP_ATTRIBUTE= _ATTRIBUTES (&AttributeInMapEntrys) & MaskInMapEntrys.Uint64, AttributeInMa= pEntrys.Bits.PageTableBaseAddress)); + DEBUG ((DEBUG_INFO, "By parsing page table, the point has Attribute 0x= %lx, and map to physical address 0x%lx\n", IA32_MAP_ATTRIBUTE_ATTRIBUTES (&= AttributeInMap) & MaskInMapEntrys.Uint64, IA32_MAP_ATTRIBUTE_PAGE_TABLE_BAS= E_ADDRESS (&AttributeInMap))); + DEBUG ((DEBUG_INFO, "While according to inputs, the point should Attri= bute 0x%lx, and should map to physical address 0x%lx\n", IA32_MAP_ATTRIBUTE= _ATTRIBUTES (&AttributeInMapEntrys) & MaskInMapEntrys.Uint64, IA32_MAP_ATTR= IBUTE_PAGE_TABLE_BASE_ADDRESS (&AttributeInMapEntrys))); DEBUG ((DEBUG_INFO, "The total Mask is 0x%lx\n", MaskInMapEntrys.Uint6= 4)); =20 if (MapEntrys->InitCount !=3D 0) { @@ -728,7 +741,7 @@ SingleMapEntryTest ( // if ((Mask->Bits.ReadWrite =3D=3D 0) || (Mask->Bits.UserSupervisor = =3D=3D 0) || (Mask->Bits.WriteThrough =3D=3D 0) || (Mask->Bits.CacheDisable= d =3D=3D 0) || (Mask->Bits.Accessed =3D=3D 0) || (Mask->Bits.Dirty =3D=3D 0) ||= (Mask->Bits.Pat =3D=3D 0) || (Mask->Bits.Global =3D=3D 0) || - (Mask->Bits.PageTableBaseAddress =3D=3D 0) || (Mask->Bits.Protec= tionKey =3D=3D 0) || (Mask->Bits.Nx =3D=3D 0)) + ((Mask->Bits.PageTableBaseAddressLow =3D=3D 0) && (Mask->Bits.Pa= geTableBaseAddressHigh =3D=3D 0)) || (Mask->Bits.ProtectionKey =3D=3D 0) ||= (Mask->Bits.Nx =3D=3D 0)) { RemoveLastMapEntry (MapEntrys); UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); @@ -1013,21 +1026,18 @@ TestCaseforRandomTest ( UT_ASSERT_EQUAL (Random64 (100, 100), 100); UT_ASSERT_TRUE ((Random32 (9, 10) >=3D 9) & (Random32 (9, 10) <=3D 10)); UT_ASSERT_TRUE ((Random64 (9, 10) >=3D 9) & (Random64 (9, 10) <=3D 10)); - - mSupportedBit.Bits.Present =3D 1; - mSupportedBit.Bits.ReadWrite =3D 1; - mSupportedBit.Bits.UserSupervisor =3D 1; - mSupportedBit.Bits.WriteThrough =3D 1; - mSupportedBit.Bits.CacheDisabled =3D 1; - mSupportedBit.Bits.Accessed =3D 1; - mSupportedBit.Bits.Dirty =3D 1; - mSupportedBit.Bits.Pat =3D 1; - mSupportedBit.Bits.Global =3D 1; - mSupportedBit.Bits.Reserved1 =3D 0; - mSupportedBit.Bits.PageTableBaseAddress =3D 0; - mSupportedBit.Bits.Reserved2 =3D 0; - mSupportedBit.Bits.ProtectionKey =3D 0xF; - mSupportedBit.Bits.Nx =3D 1; + mSupportedBit.Uint64 =3D 0; + mSupportedBit.Bits.Present =3D 1; + mSupportedBit.Bits.ReadWrite =3D 1; + mSupportedBit.Bits.UserSupervisor =3D 1; + mSupportedBit.Bits.WriteThrough =3D 1; + mSupportedBit.Bits.CacheDisabled =3D 1; + mSupportedBit.Bits.Accessed =3D 1; + mSupportedBit.Bits.Dirty =3D 1; + mSupportedBit.Bits.Pat =3D 1; + mSupportedBit.Bits.Global =3D 1; + mSupportedBit.Bits.ProtectionKey =3D 0xF; + mSupportedBit.Bits.Nx =3D 1; =20 mRandomOption =3D ((CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT *)Context)->R= andomOption; mNumberIndex =3D 0; diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c index 10fdee2f94..22f179c21f 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c @@ -140,7 +140,7 @@ IsPageTableEntryValid ( UT_ASSERT_EQUAL ((PagingEntry->Uint64 & mValidMaskNoLeaf[Level].Uint64= ), PagingEntry->Uint64); } =20 - ChildPageEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(((UINTN)(PagingEntry->P= nle.Bits.PageTableBaseAddress)) << 12); + ChildPageEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(IA32_PNLE_PAGE_TABLE_BA= SE_ADDRESS (&PagingEntry->Pnle)); for (Index =3D 0; Index < 512; Index++) { Status =3D IsPageTableEntryValid (&ChildPageEntry[Index], Level-1, Max= LeafLevel, Address + (Index<<(9*(Level-1) + 3))); if (Status !=3D UNIT_TEST_PASSED) { @@ -233,7 +233,7 @@ GetEntryFromSubPageTable ( // // Not a leaf // - ChildPageEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(((UINTN)(PagingEntry->P= nle.Bits.PageTableBaseAddress)) << 12); + ChildPageEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(IA32_PNLE_PAGE_TABLE_BA= SE_ADDRESS (&PagingEntry->Pnle)); *Level =3D *Level -1; Index =3D Address >> (*Level * 9 + 3); ASSERT (Index =3D=3D (Index & ((1<< 9) - 1))); --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101644): https://edk2.groups.io/g/devel/message/101644 Mute This Topic: https://groups.io/mt/97796394/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 10:58:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101645+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101645+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679557315; cv=none; d=zohomail.com; s=zohoarc; b=evYZAUVsfsJm9vntb16Yx2MtXQw77mmJOfCU/69el5e6gurMJ5Yyhb0TRh0JwaJWF+rn2McdK57i7/5XdOBR3OehUL6fbg5/DWBoKSuSZ+UaXFFcOUBi7dLBmSnYvvsJZwaowlaQkQERBiUslRm5OJ8ABdeEPxRvNbulZpjn/o8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679557315; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=CPH39Gyo/k+BzZDWCKOJJkOplAfXo/dW2omgzwHg3qk=; b=dt+d0MZf9eBk8DmoSo9pF41RxW9JBwFi+g5tdBtStiLsOwnNRkpfXldN90mlrcQCoycMqeJgzkjK1L3oChnim/G2Qoks2rUWAgfaC6K4fwicWzyEjRelq93y/nEqw2k8NbSUK0h9N3vRg5Q5bcMBBc/PMLWTAA6xUBLoMpnxQJY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101645+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679557315243831.7487394764036; Thu, 23 Mar 2023 00:41:55 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id hZSgYY1788612x4UE37MEPJm; Thu, 23 Mar 2023 00:41:54 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.66779.1679557305298569223 for ; Thu, 23 Mar 2023 00:41:54 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="425699834" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="425699834" X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="684616886" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="684616886" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:52 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V4 17/21] UefiCpuPkg/CpuPageTableLib: Add check for page table creation Date: Thu, 23 Mar 2023 15:40:53 +0800 Message-Id: <20230323074057.549-18-dun.tan@intel.com> In-Reply-To: <20230323074057.549-1-dun.tan@intel.com> References: <20230323074057.549-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: 89jCvtvOoxQo5Y9PlwPmSW9ax1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679557314; bh=qMOm9k3YMc7y3kNUln/K+qToN2kWor91+fKXeci4PLM=; h=Cc:Date:From:Reply-To:Subject:To; b=hWk7Mrj4caCpaIQ0w+4/V0R1G/zsfaw+wpQZWuA2PVQhxUhXD8x0m2MheA4iBx45FEa EsImZHGb2wTgFfNYayfUH9KtREPBtmacgw5YCtwrCF1mwoks/aHp04D/IB+hWaZtcG5yE wieE7MTIt+id0tM9rDMw3+pcadVFvBSILh8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679557317058100016 Content-Type: text/plain; charset="utf-8" Add code to compare ParentPagingEntry Attribute&Mask and input Attribute&Mask to decide if new next level page table is needed in non-present ParentPagingEntry condition. This can help avoid unneccessary page table creation. For example, there is a page table in which [0, 1G] is mapped(Lv4[0] ,Lv3[0,0], a non-leaf level4 entry and a leaf level3 entry).And we only want to map [1G, 1G+2M] linear address still as non-present. The expected behaviour should be nothing happens in the process. However, previous code logic doesn't check if ParentPagingEntry Attribute&Mask and input Attribute&Mask are the same in non-present ParentPagingEntry condition. Then a new 4K memory is allocated for Lv2 since 1G+2M is not 1G-aligned. So when ParentPagingEntry is non-present, before allocate 4K memory for next level paging, we also check if ParentPagingEntry Attribute& Mask and input Attribute&Mask are the same. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Reviewed-by: Ray Ni Tested-by: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 982652b58b..55a756ad90 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -358,6 +358,16 @@ PageTableLibMapInLevel ( return Status; } =20 + // + // Check the attribute in ParentPagingEntry is equal to attribute calc= ulated by input Attribue and Mask. + // + PleBAttribute.Uint64 =3D PageTableLibGetPleBMapAttribute (&ParentPagin= gEntry->PleB, ParentAttribute); + if ((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRIBU= TE_ATTRIBUTES (Mask)) + =3D=3D (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATTRI= BUTE_ATTRIBUTES (Mask))) + { + return RETURN_SUCCESS; + } + // // The parent entry is CR3 or PML5E/PML4E/PDPTE/PDE. // It does NOT point to an existing page directory. --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101645): https://edk2.groups.io/g/devel/message/101645 Mute This Topic: https://groups.io/mt/97796395/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 10:58:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101646+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101646+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679557317; cv=none; d=zohomail.com; s=zohoarc; b=SU3c5PXjezsHec6XY0grqsAl9lPJo1id326SbJJbtF2Eze1sHExZQovMm26MX4MS2nXL8FVItOyzsoixx7ji9GBuhNsFDFB/5yGNY2E1gN0ykrr/fpgrboq7IyBMAvZWGLmyGWzPJX/0SuVdzuiN8DOOoITb/Lm34IaLd392scg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679557317; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=+qN+JLQp8ykvDPSsVI19kDju4JIMHP2lT7D8yZmah20=; b=ABm3NthOkC9zBs/4CBJx0rpUsF7dtS1BlDIhs53r8xYLM3EURAaADz/VjVIceAcIjcpwF+jN967cWNc1zbmeqbHeO+4fjaCqAUDALV5emeej+ujiyv8tXwE4o8ipP+HhcJb36KNaJrHEQYJurglHpEn7YYR04M6Yxu8v1ZgaVLY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101646+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679557317473799.6921945211985; Thu, 23 Mar 2023 00:41:57 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id A29mYY1788612xGbJM3PYCeQ; Thu, 23 Mar 2023 00:41:57 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.66779.1679557305298569223 for ; Thu, 23 Mar 2023 00:41:56 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="425699856" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="425699856" X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="684616891" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="684616891" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:54 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V4 18/21] UefiCpuPkg: Combine branch for non-present and leaf ParentEntry Date: Thu, 23 Mar 2023 15:40:54 +0800 Message-Id: <20230323074057.549-19-dun.tan@intel.com> In-Reply-To: <20230323074057.549-1-dun.tan@intel.com> References: <20230323074057.549-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: o9ZXMK2rVjnw8cpLVCk8vKClx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679557317; bh=BK/Um7jOD4bv5b0O4P1Y4sazTX/TdXJHA/5JB5r77Uw=; h=Cc:Date:From:Reply-To:Subject:To; b=i168Drh/o80+RabtXeHikK9lWKf+2FjxlRcLzdqR1MC1Zda0QHQlw5uenQ2/jzKwKxW LEO1tYC16K6GRjPI3Nie7ySCDPac8pNzH+Hz187ajJNpGbzI+ci1yXjF3xPOxYBlLO3vR CDpcBcmlt87afbfXjlPbDD6dEvyPvLBqDt0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679557317766100022 Content-Type: text/plain; charset="utf-8" Combine 'if' condition branch for non-present and leaf Parent Entry in PageTableLibMapInLevel. Most steps of these two condition are the same. This commit doesn't change any functionality. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Tested-by: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 83 ++++++++++++++++= +++++++++++++++---------------------------------------------------- 1 file changed, 31 insertions(+), 52 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 55a756ad90..773948349e 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -348,68 +348,45 @@ PageTableLibMapInLevel ( // ParentPagingEntry ONLY is deferenced for checking Present and MustBeO= ne bits // when Modify is FALSE. // - - if (ParentPagingEntry->Pce.Present =3D=3D 0) { - // - // [LinearAddress, LinearAddress + Length] contains non-present range. - // - Status =3D IsAttributesAndMaskValidForNonPresentEntry (Attribute, Mask= ); - if (RETURN_ERROR (Status)) { - return Status; - } - + if ((ParentPagingEntry->Pce.Present =3D=3D 0) || IsPle (ParentPagingEntr= y, Level + 1)) { // - // Check the attribute in ParentPagingEntry is equal to attribute calc= ulated by input Attribue and Mask. - // - PleBAttribute.Uint64 =3D PageTableLibGetPleBMapAttribute (&ParentPagin= gEntry->PleB, ParentAttribute); - if ((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRIBU= TE_ATTRIBUTES (Mask)) - =3D=3D (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATTRI= BUTE_ATTRIBUTES (Mask))) - { - return RETURN_SUCCESS; - } - - // - // The parent entry is CR3 or PML5E/PML4E/PDPTE/PDE. + // When ParentPagingEntry is non-present, parent entry is CR3 or PML5E= /PML4E/PDPTE/PDE. // It does NOT point to an existing page directory. + // When ParentPagingEntry is present, parent entry is leaf PDPTE_1G or= PDE_2M. Split to 2M or 4K pages. + // Note: it's impossible the parent entry is a PTE_4K. // - ASSERT (Buffer =3D=3D NULL || *BufferSize >=3D SIZE_4KB); - CreateNew =3D TRUE; - *BufferSize -=3D SIZE_4KB; + OneOfPagingEntry.Pnle.Uint64 =3D 0; + PleBAttribute.Uint64 =3D PageTableLibGetPleBMapAttribute (&Par= entPagingEntry->PleB, ParentAttribute); =20 - if (Modify) { - ParentPagingEntry->Uintn =3D (UINTN)Buffer + *BufferSize; - ZeroMem ((VOID *)ParentPagingEntry->Uintn, SIZE_4KB); + if (ParentPagingEntry->Pce.Present =3D=3D 0) { // - // Set default attribute bits for PML5E/PML4E/PDPTE/PDE. + // [LinearAddress, LinearAddress + Length] contains non-present rang= e. // - PageTableLibSetPnle (&ParentPagingEntry->Pnle, &NopAttribute, &AllOn= eMask); + Status =3D IsAttributesAndMaskValidForNonPresentEntry (Attribute, Ma= sk); + if (RETURN_ERROR (Status)) { + return Status; + } } else { - // - // Just make sure Present and MustBeZero (PageSize) bits are accurat= e. - // - OneOfPagingEntry.Pnle.Uint64 =3D 0; + PageTableLibSetPle (Level, &OneOfPagingEntry, 0, &PleBAttribute, &Al= lOneMask); } - } else if (IsPle (ParentPagingEntry, Level + 1)) { - // - // The parent entry is a PDPTE_1G or PDE_2M. Split to 2M or 4K pages. - // Note: it's impossible the parent entry is a PTE_4K. - // + // - // Use NOP attributes as the attribute of grand-parents because CPU wi= ll consider - // the actual attributes of grand-parents when determing the memory ty= pe. + // Check if the attribute, the physical address calculated by ParentPa= gingEntry is equal to + // the attribute, the physical address calculated by input Attribue an= d Mask. // - PleBAttribute.Uint64 =3D PageTableLibGetPleBMapAttribute (&ParentPagin= gEntry->PleB, ParentAttribute); if ((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRIBU= TE_ATTRIBUTES (Mask)) =3D=3D (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATTRI= BUTE_ATTRIBUTES (Mask))) { - // - // This function is called when the memory length is less than the r= egion length of the parent level. - // No need to split the page when the attributes equal. - // if ((Mask->Bits.PageTableBaseAddressLow =3D=3D 0) && (Mask->Bits.Pag= eTableBaseAddressHigh =3D=3D 0)) { return RETURN_SUCCESS; } =20 + // + // Non-present entry won't reach there since: + // 1.When map non-present entry to present, the attribute must be di= fferent. + // 2.When still map non-present entry to non-present, PageTableBaseA= ddressLow and High in Mask must be 0. + // + ASSERT (ParentPagingEntry->Pce.Present =3D=3D 1); PhysicalAddrInEntry =3D IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (= &PleBAttribute) + PagingEntryIndex * RegionLength; PhysicalAddrInAttr =3D (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS = (Attribute) + Offset) & (~RegionMask); if (PhysicalAddrInEntry =3D=3D PhysicalAddrInAttr) { @@ -420,17 +397,19 @@ PageTableLibMapInLevel ( ASSERT (Buffer =3D=3D NULL || *BufferSize >=3D SIZE_4KB); CreateNew =3D TRUE; *BufferSize -=3D SIZE_4KB; - PageTableLibSetPle (Level, &OneOfPagingEntry, 0, &PleBAttribute, &AllO= neMask); + if (Modify) { - // - // Create 512 child-level entries that map to 2M/4K. - // PagingEntry =3D (IA32_PAGING_ENTRY *)((UINTN)Buffer + *BufferSize); ZeroMem (PagingEntry, SIZE_4KB); =20 - for (SubOffset =3D 0, Index =3D 0; Index < 512; Index++) { - PagingEntry[Index].Uint64 =3D OneOfPagingEntry.Uint64 + SubOffset; - SubOffset +=3D RegionLength; + if (ParentPagingEntry->Pce.Present) { + // + // Create 512 child-level entries that map to 2M/4K. + // + for (SubOffset =3D 0, Index =3D 0; Index < 512; Index++) { + PagingEntry[Index].Uint64 =3D OneOfPagingEntry.Uint64 + SubOffse= t; + SubOffset +=3D RegionLength; + } } =20 // --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101646): https://edk2.groups.io/g/devel/message/101646 Mute This Topic: https://groups.io/mt/97796396/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 10:58:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101647+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101647+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679557319; cv=none; d=zohomail.com; s=zohoarc; b=KpB8wDbpf4+cfLsG5MIj7lnLB5EW0A4Q2U2Dqq22Oy0SzjaLhogekXYPeO05MjJR5GN9mlU+y5YVNY/0vB/OZV3x9aDv7u5UHfj3TFl8pOXFJfoXhYljcEA7fiJ5uhXuMWCdZxE+z7btYpbx2uZkM+3/mHRrC7+fRygkxzJO/Jk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679557319; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Vv1zb7w4iCQH+4dQDo+uJGQduKVDr0AOmukr6ISW1gA=; b=U6ic5PILwqRPR7iNLnRODDWgv904LXU7a2qR6gV508F2mG0NvW0y+hEanIURwX9ktcz27Su/V4TZCLR+1SBrZ3C2eDX3BQnNWEwN0ZOFUDW+kLVzPLvrZ1D9F9Lq5jYmFrKUkLZifdkomIRTI1F5cennLS8ZFq/MHtloLS30CBY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101647+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679557319802814.0833398832239; Thu, 23 Mar 2023 00:41:59 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id sW6SYY1788612xYvuQN1IfCU; Thu, 23 Mar 2023 00:41:59 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.66779.1679557305298569223 for ; Thu, 23 Mar 2023 00:41:58 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="425699875" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="425699875" X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="684616900" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="684616900" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:57 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V4 19/21] UefiCpuPkg/CpuPageTableLib: Enable PAE paging Date: Thu, 23 Mar 2023 15:40:55 +0800 Message-Id: <20230323074057.549-20-dun.tan@intel.com> In-Reply-To: <20230323074057.549-1-dun.tan@intel.com> References: <20230323074057.549-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: L1XWOSAQlgOcti0doxfJXTrUx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679557319; bh=5oipK0eWtlailr0wnHUkRXud9bpdkqcywL8MU9IrheY=; h=Cc:Date:From:Reply-To:Subject:To; b=cGPgTgWOPBt+RF2TfKqusBOhNdOXcPsqwXfRduGWzauFt9nzWjk7kxVexZBRZRl6FUz WqmzSmmC1bGTA53xjDu4pdpVzJJoIQsPPy4Z2kEv7YM2w7LqiMwJlGyEYrG+QEBqOldBQ MGqXiNLxSuc6eGfqU0oKmMZYxZHKQSPsO3Y= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679557321802100002 Content-Type: text/plain; charset="utf-8" Modify CpuPageTableLib code to enable PAE paging. In PageTableMap() API: When creating new PAE page table, after creating page table, set all MustBeZero fields of 4 PDPTE to 0. The MustBeZero fields are treated as RW and other attributes by the common map logic. So they might be set to 1. When updating exsiting PAE page table, the special steps are: 1.Prepare 4K-aligned 32bytes memory in stack for 4 temp PDPTE. 2.Copy original 4 PDPTE to the 4 temp PDPTE and set the RW, UserSupervisor to 1 and set Nx of 4 temp PDPTE to 0. 4.After updating the page table, set the MustBeZero fields of 4 temp PDPTE to 0. 5.Copy the temp PDPTE to original PDPTE. In PageTableParse() API, also create 4 temp PDPTE in stack. Copy original 4 PDPTE to the 4 temp PDPTE. Then set the RW, UserSupervisor to 1 and set Nx of 4 temp PDPTE to 0. Finally use the address of temp PDPTE as the page table address. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Tested-by: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h | 10 +++++++--- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 53 ++++++++++++++= ++++++++++++++++++++++++++++++++++----- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableParse.c | 25 ++++++++++++++= +++++++---- 3 files changed, 76 insertions(+), 12 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h b/UefiCpuPkg= /Library/CpuPageTableLib/CpuPageTable.h index 2c67ecb469..521d56c148 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h @@ -15,11 +15,14 @@ #include #include =20 -#define IA32_PE_BASE_ADDRESS_MASK_40 0xFFFFFFFFFF000ull -#define IA32_PE_BASE_ADDRESS_MASK_39 0xFFFFFFFFFE000ull +#define IA32_PE_BASE_ADDRESS_MASK_40 0xFFFFFFFFFF000ull +#define IA32_PE_BASE_ADDRESS_MASK_39 0xFFFFFFFFFE000ull +#define IA32_PE_BASE_ADDRESS_MASK_PAE_PDPTE 0xFFFFFFFFFFFE0ull =20 #define REGION_LENGTH(l) LShiftU64 (1, (l) * 9 + 3) =20 +#define MAX_PAE_PDPTE_NUM 4 + typedef enum { Pte =3D 1, Pde =3D 2, @@ -60,7 +63,8 @@ typedef union { UINT64 Uint64; } IA32_PAGE_NON_LEAF_ENTRY; =20 -#define IA32_PNLE_PAGE_TABLE_BASE_ADDRESS(pa) ((pa)->Uint64 & IA32_PE_BAS= E_ADDRESS_MASK_40) +#define IA32_PNLE_PAGE_TABLE_BASE_ADDRESS(pa) ((pa)->Uint64 & IA32_P= E_BASE_ADDRESS_MASK_40) +#define IA32_PAE_PDPTE_PAGE_TABLE_BASE_ADDRESS(pa) ((pa)->Uint64 & IA32_P= E_BASE_ADDRESS_MASK_PAE_PDPTE) =20 /// /// Format of a PML5 Entry (PML5E) that References a PML4 Table diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 773948349e..8769e45f25 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -661,15 +661,17 @@ PageTableMap ( IA32_PAGE_LEVEL MaxLeafLevel; IA32_MAP_ATTRIBUTE ParentAttribute; BOOLEAN LocalIsModified; + UINTN Index; + IA32_PAGING_ENTRY *PagingEntry; + UINT8 BufferInStack[SIZE_4KB - 1 + MAX_PAE_PDPTE_NUM * siz= eof (IA32_PAGING_ENTRY)]; =20 if (Length =3D=3D 0) { return RETURN_SUCCESS; } =20 - if ((PagingMode =3D=3D Paging32bit) || (PagingMode =3D=3D PagingPae) || = (PagingMode >=3D PagingModeMax)) { + if ((PagingMode =3D=3D Paging32bit) || (PagingMode >=3D PagingModeMax)) { // // 32bit paging is never supported. - // PAE paging will be supported later. // return RETURN_UNSUPPORTED; } @@ -706,17 +708,32 @@ PageTableMap ( =20 MaxLeafLevel =3D (IA32_PAGE_LEVEL)(UINT8)PagingMode; MaxLevel =3D (IA32_PAGE_LEVEL)(UINT8)(PagingMode >> 8); - MaxLinearAddress =3D LShiftU64 (1, 12 + MaxLevel * 9); + MaxLinearAddress =3D (PagingMode =3D=3D PagingPae) ? LShiftU64 (1, 32) := LShiftU64 (1, 12 + MaxLevel * 9); =20 if ((LinearAddress > MaxLinearAddress) || (Length > MaxLinearAddress - L= inearAddress)) { // - // Maximum linear address is (1 << 48) or (1 << 57) + // Maximum linear address is (1 << 32), (1 << 48) or (1 << 57) // return RETURN_INVALID_PARAMETER; } =20 TopPagingEntry.Uintn =3D *PageTable; if (TopPagingEntry.Uintn !=3D 0) { + if (PagingMode =3D=3D PagingPae) { + // + // Create 4 temporary PDPTE at a 4k-aligned address. + // Copy the original PDPTE content and set ReadWrite, UserSupervisor= to 1, set Nx to 0. + // + TopPagingEntry.Uintn =3D ALIGN_VALUE ((UINTN)BufferInStack, BASE_4KB= ); + PagingEntry =3D (IA32_PAGING_ENTRY *)(TopPagingEntry.Uintn); + CopyMem (PagingEntry, (VOID *)(*PageTable), MAX_PAE_PDPTE_NUM * size= of (IA32_PAGING_ENTRY)); + for (Index =3D 0; Index < MAX_PAE_PDPTE_NUM; Index++) { + PagingEntry[Index].Pnle.Bits.ReadWrite =3D 1; + PagingEntry[Index].Pnle.Bits.UserSupervisor =3D 1; + PagingEntry[Index].Pnle.Bits.Nx =3D 0; + } + } + TopPagingEntry.Pce.Present =3D 1; TopPagingEntry.Pce.ReadWrite =3D 1; TopPagingEntry.Pce.UserSupervisor =3D 1; @@ -792,7 +809,33 @@ PageTableMap ( } =20 if (!RETURN_ERROR (Status)) { - *PageTable =3D (UINTN)(TopPagingEntry.Uintn & IA32_PE_BASE_ADDRESS_MAS= K_40); + PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(TopPagingEntry.Uintn & IA= 32_PE_BASE_ADDRESS_MASK_40); + + if (PagingMode =3D=3D PagingPae) { + // + // These MustBeZero fields are treated as RW and other attributes by= the common map logic. So they might be set to 1. + // + for (Index =3D 0; Index < MAX_PAE_PDPTE_NUM; Index++) { + PagingEntry[Index].PdptePae.Bits.MustBeZero =3D 0; + PagingEntry[Index].PdptePae.Bits.MustBeZero2 =3D 0; + PagingEntry[Index].PdptePae.Bits.MustBeZero3 =3D 0; + } + + if (*PageTable !=3D 0) { + // + // Copy temp PDPTE to original PDPTE. + // + CopyMem ((VOID *)(*PageTable), PagingEntry, MAX_PAE_PDPTE_NUM * si= zeof (IA32_PAGING_ENTRY)); + } + } + + if (*PageTable =3D=3D 0) { + // + // Do not assign the *PageTable when it's an existing page table. + // If it's an existing PAE page table, PagingEntry is the temp buffe= r in stack. + // + *PageTable =3D (UINTN)PagingEntry; + } } =20 return Status; diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableParse.c b/UefiC= puPkg/Library/CpuPageTableLib/CpuPageTableParse.c index 65490751ab..f6d7b9bb4c 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableParse.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableParse.c @@ -158,6 +158,7 @@ VOID PageTableLibParsePnle ( IN UINT64 PageTableBaseAddress, IN UINTN Level, + IN UINTN MaxLevel, IN UINT64 RegionStart, IN IA32_MAP_ATTRIBUTE *ParentMapAttribute, IN OUT IA32_MAP_ENTRY *Map, @@ -171,13 +172,15 @@ PageTableLibParsePnle ( UINTN Index; IA32_MAP_ATTRIBUTE MapAttribute; UINT64 RegionLength; + UINTN PagingEntryNumber; =20 ASSERT (OneEntry !=3D NULL); =20 - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)PageTableBaseAddress; - RegionLength =3D REGION_LENGTH (Level); + PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)PageTableBaseAddress; + RegionLength =3D REGION_LENGTH (Level); + PagingEntryNumber =3D ((MaxLevel =3D=3D 3) && (Level =3D=3D 3)) ? MAX_PA= E_PDPTE_NUM : 512; =20 - for (Index =3D 0; Index < 512; Index++, RegionStart +=3D RegionLength) { + for (Index =3D 0; Index < PagingEntryNumber; Index++, RegionStart +=3D R= egionLength) { if (PagingEntry[Index].Pce.Present =3D=3D 0) { continue; } @@ -228,6 +231,7 @@ PageTableLibParsePnle ( PageTableLibParsePnle ( IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&PagingEntry[Index].Pnle), Level - 1, + MaxLevel, RegionStart, &MapAttribute, Map, @@ -269,6 +273,8 @@ PageTableParse ( IA32_MAP_ENTRY *LastEntry; IA32_MAP_ENTRY OneEntry; UINTN MaxLevel; + UINTN Index; + IA32_PAGING_ENTRY BufferInStack[MAX_PAE_PDPTE_NUM]; =20 if ((PagingMode =3D=3D Paging32bit) || (PagingMode >=3D PagingModeMax)) { // @@ -290,6 +296,17 @@ PageTableParse ( return RETURN_SUCCESS; } =20 + if (PagingMode =3D=3D PagingPae) { + CopyMem (BufferInStack, (VOID *)PageTable, sizeof (BufferInStack)); + for (Index =3D 0; Index < MAX_PAE_PDPTE_NUM; Index++) { + BufferInStack[Index].Pnle.Bits.ReadWrite =3D 1; + BufferInStack[Index].Pnle.Bits.UserSupervisor =3D 1; + BufferInStack[Index].Pnle.Bits.Nx =3D 0; + } + + PageTable =3D (UINTN)BufferInStack; + } + // // Page table layout is as below: // @@ -319,7 +336,7 @@ PageTableParse ( MapCapacity =3D *MapCount; *MapCount =3D 0; LastEntry =3D NULL; - PageTableLibParsePnle ((UINT64)PageTable, MaxLevel, 0, &NopAttribute, Ma= p, MapCount, MapCapacity, &LastEntry, &OneEntry); + PageTableLibParsePnle ((UINT64)PageTable, MaxLevel, MaxLevel, 0, &NopAtt= ribute, Map, MapCount, MapCapacity, &LastEntry, &OneEntry); =20 if (*MapCount > MapCapacity) { return RETURN_BUFFER_TOO_SMALL; --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101647): https://edk2.groups.io/g/devel/message/101647 Mute This Topic: https://groups.io/mt/97796397/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 10:58:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101648+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101648+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679557322; cv=none; d=zohomail.com; s=zohoarc; b=aiHvLhVbZrmJyw0QsZqF1OkQcV9IyStKZQQpperDLUlgQbp54+PTIQuOXxyMTELcqL5VSAZnnp+AzkmrUwepQbefIwfJ4b0m7wOYIWov+GxJiPJ7TUMCVmIAsHdkCgP5OsY+EceA7hU//xqWdpx4F/dNhPgPmTJb12NZpeuMib0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679557322; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Tll1J4N2CLZemHfwV1RJc/kDT+rWE7QeCdG5i83Sobs=; b=fdKCxUSdD/48nEIJF9eFbi8E7VRJSfWkCVJ6yFplO5fHxX28iKlIc1002ZV8md4IJmrnpjQNteGzlslLzPwQ37vaRBeG9lPbilSukAsxKxVr1zO4ot/RkOigVyObWJOKrAPVpZcHq+RGI/KPNFUsRHyRhJkiq783lWuycqPeKrM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101648+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679557322898456.59558065176054; Thu, 23 Mar 2023 00:42:02 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id UjiNYY1788612xaMnw5JbRXe; Thu, 23 Mar 2023 00:42:01 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.66779.1679557305298569223 for ; Thu, 23 Mar 2023 00:42:01 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="425699901" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="425699901" X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:42:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="684616906" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="684616906" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:41:59 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V4 20/21] UefiCpuPkg/CpuPageTableLib: Add RandomTest for PAE paging Date: Thu, 23 Mar 2023 15:40:56 +0800 Message-Id: <20230323074057.549-21-dun.tan@intel.com> In-Reply-To: <20230323074057.549-1-dun.tan@intel.com> References: <20230323074057.549-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: 8R2OdEQztpgtnHkrFa1HQB77x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679557321; bh=wxaNzZ5hGZx60kLbg6HF4QxNUWTAnzTpV2NIQPzpHao=; h=Cc:Date:From:Reply-To:Subject:To; b=qMYYrJM+43wK+TgZkoZipKN7H5KUqnQxzT32C1R+ugJveluyb/S+RA/FI+eeHu53BIq AYTDqAkTTmhcK5wFt/vQPwsoDgqZ/rj2Xy8cWx82buysCoI57cZYr3r9kJ8ilP3J47TfR px+ZRWrn7b92H71ZnGBJoOoRetdSlujmP78= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679557325763100009 Content-Type: text/plain; charset="utf-8" Add RandomTest for PAE paging. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Reviewed-by: Ray Ni Tested-by: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c = | 2 ++ UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c = | 3 +-- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c = | 12 ++++++++---- 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUni= tTestHost.c b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUn= itTestHost.c index e1efc84c82..8554eefa39 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c @@ -9,6 +9,7 @@ #include "CpuPageTableLibUnitTest.h" =20 // -----------------------------------------------------------------------= PageMode--TestCount-TestRangeCount---RandomOptions +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPagingPae = =3D { PagingPae, 100, 20, USE_RANDOM_ARRAY }; static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging4Level = =3D { Paging4Level, 100, 20, USE_RANDOM_ARRAY }; static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging4Level1GB= =3D { Paging4Level1GB, 100, 20, USE_RANDOM_ARRAY }; static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging5Level = =3D { Paging5Level, 100, 20, USE_RANDOM_ARRAY }; @@ -880,6 +881,7 @@ UefiTestMain ( goto EXIT; } =20 + AddTestCase (RandomTestCase, "Random Test for PagingPae", "Random Test C= ase1", TestCaseforRandomTest, NULL, NULL, &mTestContextPagingPae); AddTestCase (RandomTestCase, "Random Test for Paging4Level", "Random Tes= t Case1", TestCaseforRandomTest, NULL, NULL, &mTestContextPaging4Level); AddTestCase (RandomTestCase, "Random Test for Paging4Level1G", "Random T= est Case2", TestCaseforRandomTest, NULL, NULL, &mTestContextPaging4Level1GB= ); AddTestCase (RandomTestCase, "Random Test for Paging5Level", "Random Tes= t Case3", TestCaseforRandomTest, NULL, NULL, &mTestContextPaging5Level); diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c index 18a5010c30..7e79b01823 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c @@ -258,10 +258,9 @@ ValidateAndRandomeModifyPageTable ( UNIT_TEST_STATUS Status; IA32_PAGING_ENTRY *PagingEntry; =20 - if ((PagingMode =3D=3D Paging32bit) || (PagingMode =3D=3D PagingPae) || = (PagingMode >=3D PagingModeMax)) { + if ((PagingMode =3D=3D Paging32bit) || (PagingMode >=3D PagingModeMax)) { // // 32bit paging is never supported. - // PAE paging will be supported later. // return UNIT_TEST_ERROR_TEST_FAILED; } diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c index 22f179c21f..67776255c2 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c @@ -175,10 +175,9 @@ IsPageTableValid ( return UNIT_TEST_PASSED; } =20 - if ((PagingMode =3D=3D Paging32bit) || (PagingMode =3D=3D PagingPae) || = (PagingMode >=3D PagingModeMax)) { + if ((PagingMode =3D=3D Paging32bit) || (PagingMode >=3D PagingModeMax)) { // // 32bit paging is never supported. - // PAE paging will be supported later. // return UNIT_TEST_ERROR_TEST_FAILED; } @@ -187,7 +186,12 @@ IsPageTableValid ( MaxLevel =3D (UINT8)(PagingMode >> 8); =20 PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)PageTable; - for (Index =3D 0; Index < 512; Index++) { + for (Index =3D 0; Index < ((PagingMode =3D=3D PagingPae) ? 4 : 512); Ind= ex++) { + if (PagingMode =3D=3D PagingPae) { + UT_ASSERT_EQUAL (PagingEntry[Index].PdptePae.Bits.MustBeZero, 0); + UT_ASSERT_EQUAL (PagingEntry[Index].PdptePae.Bits.MustBeZero2, 0); + } + Status =3D IsPageTableEntryValid (&PagingEntry[Index], MaxLevel, MaxLe= afLevel, Index << (9 * MaxLevel + 3)); if (Status !=3D UNIT_TEST_PASSED) { return Status; @@ -264,7 +268,7 @@ GetEntryFromPageTable ( UINT64 Index; IA32_PAGING_ENTRY *PagingEntry; =20 - if ((PagingMode =3D=3D Paging32bit) || (PagingMode =3D=3D PagingPae) || = (PagingMode >=3D PagingModeMax)) { + if ((PagingMode =3D=3D Paging32bit) || (PagingMode >=3D PagingModeMax)) { // // 32bit paging is never supported. // PAE paging will be supported later. --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101648): https://edk2.groups.io/g/devel/message/101648 Mute This Topic: https://groups.io/mt/97796399/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat Apr 20 10:58:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101649+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101649+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679557326; cv=none; d=zohomail.com; s=zohoarc; b=SSwv8IyPpVDpFETxRm9PJfZ2JoLd+erRefCKmgoGWCqH6ZHcU56vj2IsehihGbxr6sX5aWiibemTsoTD/OLCGOS86yb2PE6tFoyKYp/LCUrJxTCmLZ6kdPUDM/wiHoG68d2gcspBiv6pA5e/0oQ4S2hDRk3p32CJlaVWO7L02YI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679557326; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=ajhvg3U/uPGqONhh1mdH/0pq/oTqiLBOQIrc+3wRhAI=; b=fifRgB5DkfzLOReYjFqF5nilaQFVgMFJhvWouNkjPJhOV6/FLxDEQQboyK4VUdcuRN5MC9zg0Rl1e++Y+jk/E/ig6tMrMd2+Gp5nhghYHMTP0W5R3/xqgBzBlBb7Yy3wL+KCRj5DCC4TeP/UlHB9kgWzbiG2mnGXKjI6Sgm1Hxw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101649+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679557326736758.4301114657816; Thu, 23 Mar 2023 00:42:06 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id qk1wYY1788612xnpAH47ob4k; Thu, 23 Mar 2023 00:42:06 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.66779.1679557305298569223 for ; Thu, 23 Mar 2023 00:42:03 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="425699918" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="425699918" X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:42:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="684616912" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="684616912" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2023 00:42:01 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V4 21/21] UefiCpuPkg/CpuPageTableLib: Reduce the number of random tests Date: Thu, 23 Mar 2023 15:40:57 +0800 Message-Id: <20230323074057.549-22-dun.tan@intel.com> In-Reply-To: <20230323074057.549-1-dun.tan@intel.com> References: <20230323074057.549-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: o2UFG9dmJQzp6qdSIjrd5dIcx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679557326; bh=jerfz92LqcBZ+0sUFDQ3ln/Zb/1ly3nw6y/6tFBmRuc=; h=Cc:Date:From:Reply-To:Subject:To; b=XzuqI8BoIYRRDAG0uQltraiDndjW8SJfdq3m971wdqOkb19M6Mq4Gga9VVuWMR2OWbN bcwrlOPxvPoeN1h2c5m1oXIABgI4fkyCvs/3T+10XC43HynbYYNww3g+enMqgHE9QSGMi duvNNWx02LhBWrtBmGZOqKbiarj+1wveVjs= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679557327774100011 Content-Type: text/plain; charset="utf-8" Reduce the number of random tests. In previous patch, non-1:1 mapping is enbaled and it may need more than an hour and a half for the CI test, which may lead to CI timeout. Reduce the number of random test count to pass the CI. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Reviewed-by: Ray Ni Tested-by: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c = | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUni= tTestHost.c b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUn= itTestHost.c index 8554eefa39..c60302eeac 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c @@ -9,11 +9,11 @@ #include "CpuPageTableLibUnitTest.h" =20 // -----------------------------------------------------------------------= PageMode--TestCount-TestRangeCount---RandomOptions -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPagingPae = =3D { PagingPae, 100, 20, USE_RANDOM_ARRAY }; -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging4Level = =3D { Paging4Level, 100, 20, USE_RANDOM_ARRAY }; -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging4Level1GB= =3D { Paging4Level1GB, 100, 20, USE_RANDOM_ARRAY }; -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging5Level = =3D { Paging5Level, 100, 20, USE_RANDOM_ARRAY }; -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging5Level1GB= =3D { Paging5Level1GB, 100, 20, USE_RANDOM_ARRAY }; +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPagingPae = =3D { PagingPae, 30, 20, USE_RANDOM_ARRAY }; +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging4Level = =3D { Paging4Level, 30, 20, USE_RANDOM_ARRAY }; +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging4Level1GB= =3D { Paging4Level1GB, 30, 20, USE_RANDOM_ARRAY }; +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging5Level = =3D { Paging5Level, 30, 20, USE_RANDOM_ARRAY }; +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging5Level1GB= =3D { Paging5Level1GB, 30, 20, USE_RANDOM_ARRAY }; =20 /** Check if the input parameters are not supported. --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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