From nobody Mon Sep 16 19:00:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101524+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101524+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679443044; cv=none; d=zohomail.com; s=zohoarc; b=Zem5W56xeYT7SdB8AfR6dfWsl0rn4s+wxIiGxmiVcjAguHSiV5ijZD6RLducuKfiIc/1//ikwftBEdM631mdSijz4DAyjuKWAp7RkESn70n4QtakbRavwWoxYDeAtHMUjbtHSnbZQnR/q0vgMimmHjGSRFNVBY4FvRzRIcauIws= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679443044; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=QOrV1SMpFK+Q/ScUPzZrZNF0TpzpD6tUEdUZzBXM4Dc=; b=Y2MIM3Kg2zh4lkdI+RHdDp/qaoaeewJcYpQRV6NmitQ8UKbyj7Q4q7E1dt/Vq+wDgfH1O0hGv4dC4Ea/ilA+2WV7pDvFUo3ysR7e52dmIr15VW9KuChRG4da8Ue2VuE0sHiSadSCOlylmbWcu0/eVxm3b7uRI4K/OWQCFbvVlz0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101524+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679443044834807.0844789571074; Tue, 21 Mar 2023 16:57:24 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 6yV6YY1788612xQ1Wh2MyRIn; Tue, 21 Mar 2023 16:57:24 -0700 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.30797.1679443043224909338 for ; Tue, 21 Mar 2023 16:57:23 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10656"; a="341441547" X-IronPort-AV: E=Sophos;i="5.98,280,1673942400"; d="scan'208";a="341441547" X-Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Mar 2023 16:57:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10656"; a="805627780" X-IronPort-AV: E=Sophos;i="5.98,280,1673942400"; d="scan'208";a="805627780" X-Received: from shwdeopenlab706.ccr.corp.intel.com ([10.239.55.95]) by orsmga004.jf.intel.com with ESMTP; 21 Mar 2023 16:57:04 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Eric Dong , Rahul Kumar , Gerd Hoffmann , Michael D Kinney , Ahmad Anadani Subject: [edk2-devel] [PATCH 6/6] UefiCpuPkg/MtrrTest: Add test cases for TME-MK enable case Date: Wed, 22 Mar 2023 07:56:50 +0800 Message-Id: <20230321235650.675-7-ray.ni@intel.com> In-Reply-To: <20230321235650.675-1-ray.ni@intel.com> References: <20230321235650.675-1-ray.ni@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com X-Gm-Message-State: G2SzQPRYiuOzx4uTPOfcBi1zx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679443044; bh=D3zXABrrh2tL4WGApijMus1V7/RV6IO7LghpYpbfnJQ=; h=Cc:Date:From:Reply-To:Subject:To; b=F6sJe25BVfAsg9wHkxsrxX+6uxkBQGjoFOvKVHYkbhdEFl49wLIf2/AiZcheWUPiK4c Jx56qjn7QX7FetLU4dU2ftuVTn+WkuBJKp9HxYFTxBF0ERh8QxjihNTueM6Hn/wlRVgKc FlSfsb5AQ/KKO3lon8hhwcRrL6FrQ4Dude8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679443047078100001 Content-Type: text/plain; charset="utf-8" When TME-MK is enabled, the MtrrLib should substract the TME-MK reserved bits from the max PA returned from CPUID instruction. The new test case guarantees such behavior in MtrrLib. Signed-off-by: Ray Ni Cc: Eric Dong Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Michael D Kinney Cc: Ahmad Anadani Reviewed-by: Michael D Kinney --- .../MtrrLib/UnitTest/MtrrLibUnitTest.c | 18 +-- .../MtrrLib/UnitTest/MtrrLibUnitTest.h | 3 +- UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c | 119 ++++++++++++++---- 3 files changed, 107 insertions(+), 33 deletions(-) diff --git a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c b/UefiCp= uPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c index b9a97dee09..1409ae27bb 100644 --- a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c +++ b/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c @@ -1,7 +1,7 @@ /** @file Unit tests of the MtrrLib instance of the MtrrLib class =20 - Copyright (c) 2020, Intel Corporation. All rights reserved.
+ Copyright (c) 2020 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -30,6 +30,8 @@ STATIC MTRR_LIB_SYSTEM_PARAMETER mSystemParameters[] =3D= { { 48, TRUE, TRUE, CacheWriteThrough, 12 }, { 48, TRUE, TRUE, CacheWriteProtected, 12 }, { 48, TRUE, TRUE, CacheWriteCombining, 12 }, + + { 48, TRUE, TRUE, CacheWriteBack, 12, 7}, // 7 bits for MKTME }; =20 UINT32 mFixedMtrrsIndex[] =3D { @@ -219,7 +221,7 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings ( &WcCount ); GenerateValidAndConfigurableMtrrPairs ( - SystemParameter->PhysicalAddressBits, + SystemParameter->PhysicalAddressBits - SystemParameter->MkTmeKeyidBits, RawMtrrRange, UcCount, WtCount, @@ -232,7 +234,7 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings ( ExpectedMemoryRangesCount =3D ARRAY_SIZE (ExpectedMemoryRanges); GetEffectiveMemoryRanges ( SystemParameter->DefaultCacheType, - SystemParameter->PhysicalAddressBits, + SystemParameter->PhysicalAddressBits - SystemParameter->MkTmeKeyidBits, RawMtrrRange, ExpectedVariableMtrrUsage, ExpectedMemoryRanges, @@ -278,7 +280,7 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings ( ActualMemoryRangesCount =3D ARRAY_SIZE (ActualMemoryRanges); CollectTestResult ( SystemParameter->DefaultCacheType, - SystemParameter->PhysicalAddressBits, + SystemParameter->PhysicalAddressBits - SystemParameter->MkTmeKeyidBi= ts, SystemParameter->VariableMtrrCount, &LocalMtrrs, ActualMemoryRanges, @@ -325,7 +327,7 @@ UnitTestInvalidMemoryLayouts ( SystemParameter =3D (MTRR_LIB_SYSTEM_PARAMETER *)Context; =20 RangeCount =3D Random32 (1, ARRAY_SIZE (Ranges)); - MaxAddress =3D 1ull << SystemParameter->PhysicalAddressBits; + MaxAddress =3D 1ull << (SystemParameter->PhysicalAddressBits - SystemPar= ameter->MkTmeKeyidBits); =20 for (Index =3D 0; Index < RangeCount; Index++) { do { @@ -967,7 +969,7 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings ( &WcCount ); GenerateValidAndConfigurableMtrrPairs ( - SystemParameter->PhysicalAddressBits, + SystemParameter->PhysicalAddressBits - SystemParameter->MkTmeKeyidBits, RawMtrrRange, UcCount, WtCount, @@ -980,7 +982,7 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings ( ExpectedMemoryRangesCount =3D ARRAY_SIZE (ExpectedMemoryRanges); GetEffectiveMemoryRanges ( SystemParameter->DefaultCacheType, - SystemParameter->PhysicalAddressBits, + SystemParameter->PhysicalAddressBits - SystemParameter->MkTmeKeyidBits, RawMtrrRange, ExpectedVariableMtrrUsage, ExpectedMemoryRanges, @@ -1019,7 +1021,7 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings ( ActualMemoryRangesCount =3D ARRAY_SIZE (ActualMemoryRanges); CollectTestResult ( SystemParameter->DefaultCacheType, - SystemParameter->PhysicalAddressBits, + SystemParameter->PhysicalAddressBits - SystemParameter->MkTmeKeyidBi= ts, SystemParameter->VariableMtrrCount, &LocalMtrrs, ActualMemoryRanges, diff --git a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h b/UefiCp= uPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h index 57e656c555..4471c1dcf7 100644 --- a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h +++ b/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2020, Intel Corporation. All rights reserved.
+ Copyright (c) 2020 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -40,6 +40,7 @@ typedef struct { BOOLEAN FixedMtrrSupported; MTRR_MEMORY_CACHE_TYPE DefaultCacheType; UINT32 VariableMtrrCount; + UINT8 MkTmeKeyidBits; } MTRR_LIB_SYSTEM_PARAMETER; =20 extern UINT32 mFixedMtrrsIndex[]; diff --git a/UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c b/UefiCpuPkg/Lib= rary/MtrrLib/UnitTest/Support.c index 260966e7b6..ba1de10034 100644 --- a/UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c +++ b/UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c @@ -12,13 +12,15 @@ MTRR_MEMORY_CACHE_TYPE mMemoryCacheTypes[] =3D { CacheUncacheable, CacheWriteCombining, CacheWriteThrough, CacheWriteProt= ected, CacheWriteBack }; =20 -UINT64 mFixedMtrrsValue[MTRR_NUMBER_OF_FIXED_MTR= R]; -MSR_IA32_MTRR_PHYSBASE_REGISTER mVariableMtrrsPhysBase[MTRR_NUMBER_OF_VAR= IABLE_MTRR]; -MSR_IA32_MTRR_PHYSMASK_REGISTER mVariableMtrrsPhysMask[MTRR_NUMBER_OF_VAR= IABLE_MTRR]; -MSR_IA32_MTRR_DEF_TYPE_REGISTER mDefTypeMsr; -MSR_IA32_MTRRCAP_REGISTER mMtrrCapMsr; -CPUID_VERSION_INFO_EDX mCpuidVersionInfoEdx; -CPUID_VIR_PHY_ADDRESS_SIZE_EAX mCpuidVirPhyAddressSizeEax; +UINT64 mFixedMtrrsValue[MTRR_NUMBER_= OF_FIXED_MTRR]; +MSR_IA32_MTRR_PHYSBASE_REGISTER mVariableMtrrsPhysBase[MTRR_N= UMBER_OF_VARIABLE_MTRR]; +MSR_IA32_MTRR_PHYSMASK_REGISTER mVariableMtrrsPhysMask[MTRR_N= UMBER_OF_VARIABLE_MTRR]; +MSR_IA32_MTRR_DEF_TYPE_REGISTER mDefTypeMsr; +MSR_IA32_MTRRCAP_REGISTER mMtrrCapMsr; +MSR_IA32_TME_ACTIVATE_REGISTER mTmeActivateMsr; +CPUID_VERSION_INFO_EDX mCpuidVersionInfoEdx; +CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX mCpuidExtendedFeatureFlagsEcx; +CPUID_VIR_PHY_ADDRESS_SIZE_EAX mCpuidVirPhyAddressSizeEax; =20 BOOLEAN mRandomInput; UINTN mNumberIndex =3D 0; @@ -87,34 +89,42 @@ GenerateRandomNumbers ( } =20 /** - Retrieves CPUID information. + Retrieves CPUID information using an extended leaf identifier. + + Executes the CPUID instruction with EAX set to the value specified by In= dex + and ECX set to the value specified by SubIndex. This function always ret= urns + Index. This function is only available on IA-32 and x64. =20 - Executes the CPUID instruction with EAX set to the value specified by In= dex. - This function always returns Index. If Eax is not NULL, then the value of EAX after CPUID is returned in Eax. If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx. If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx. If Edx is not NULL, then the value of EDX after CPUID is returned in Edx. - This function is only available on IA-32 and x64. =20 - @param Index The 32-bit value to load into EAX prior to invoking the CP= UID - instruction. - @param Eax The pointer to the 32-bit EAX value returned by the CPUID - instruction. This is an optional parameter that may be NUL= L. - @param Ebx The pointer to the 32-bit EBX value returned by the CPUID - instruction. This is an optional parameter that may be NUL= L. - @param Ecx The pointer to the 32-bit ECX value returned by the CPUID - instruction. This is an optional parameter that may be NUL= L. - @param Edx The pointer to the 32-bit EDX value returned by the CPUID - instruction. This is an optional parameter that may be NUL= L. + @param Index The 32-bit value to load into EAX prior to invoking the + CPUID instruction. + @param SubIndex The 32-bit value to load into ECX prior to invoking the + CPUID instruction. + @param Eax The pointer to the 32-bit EAX value returned by the CP= UID + instruction. This is an optional parameter that may be + NULL. + @param Ebx The pointer to the 32-bit EBX value returned by the CP= UID + instruction. This is an optional parameter that may be + NULL. + @param Ecx The pointer to the 32-bit ECX value returned by the CP= UID + instruction. This is an optional parameter that may be + NULL. + @param Edx The pointer to the 32-bit EDX value returned by the CP= UID + instruction. This is an optional parameter that may be + NULL. =20 @return Index. =20 **/ UINT32 EFIAPI -UnitTestMtrrLibAsmCpuid ( +UnitTestMtrrLibAsmCpuidEx ( IN UINT32 Index, + IN UINT32 SubIndex, OUT UINT32 *Eax OPTIONAL, OUT UINT32 *Ebx OPTIONAL, OUT UINT32 *Ecx OPTIONAL, @@ -124,7 +134,7 @@ UnitTestMtrrLibAsmCpuid ( switch (Index) { case CPUID_SIGNATURE: if (Eax !=3D NULL) { - *Eax =3D CPUID_VERSION_INFO; + *Eax =3D CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS; } =20 return Index; @@ -134,6 +144,13 @@ UnitTestMtrrLibAsmCpuid ( *Edx =3D mCpuidVersionInfoEdx.Uint32; } =20 + return Index; + break; + case CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS: + if (Ecx !=3D NULL) { + *Ecx =3D mCpuidExtendedFeatureFlagsEcx.Uint32; + } + return Index; break; case CPUID_EXTENDED_FUNCTION: @@ -159,6 +176,44 @@ UnitTestMtrrLibAsmCpuid ( return Index; } =20 +/** + Retrieves CPUID information. + + Executes the CPUID instruction with EAX set to the value specified by In= dex. + This function always returns Index. + If Eax is not NULL, then the value of EAX after CPUID is returned in Eax. + If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx. + If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx. + If Edx is not NULL, then the value of EDX after CPUID is returned in Edx. + This function is only available on IA-32 and x64. + + @param Index The 32-bit value to load into EAX prior to invoking the CP= UID + instruction. + @param Eax The pointer to the 32-bit EAX value returned by the CPUID + instruction. This is an optional parameter that may be NUL= L. + @param Ebx The pointer to the 32-bit EBX value returned by the CPUID + instruction. This is an optional parameter that may be NUL= L. + @param Ecx The pointer to the 32-bit ECX value returned by the CPUID + instruction. This is an optional parameter that may be NUL= L. + @param Edx The pointer to the 32-bit EDX value returned by the CPUID + instruction. This is an optional parameter that may be NUL= L. + + @return Index. + +**/ +UINT32 +EFIAPI +UnitTestMtrrLibAsmCpuid ( + IN UINT32 Index, + OUT UINT32 *Eax OPTIONAL, + OUT UINT32 *Ebx OPTIONAL, + OUT UINT32 *Ecx OPTIONAL, + OUT UINT32 *Edx OPTIONAL + ) +{ + return UnitTestMtrrLibAsmCpuidEx (Index, 0, Eax, Ebx, Ecx, Edx); +} + /** Returns a 64-bit Machine Specific Register(MSR). =20 @@ -207,6 +262,10 @@ UnitTestMtrrLibAsmReadMsr64 ( return mMtrrCapMsr.Uint64; } =20 + if (MsrIndex =3D=3D MSR_IA32_TME_ACTIVATE) { + return mTmeActivateMsr.Uint64; + } + // // Should never fall through to here // @@ -324,10 +383,22 @@ InitializeMtrrRegs ( // // Hook BaseLib functions used by MtrrLib that require some emulation. // - gUnitTestHostBaseLib.X86->AsmCpuid =3D UnitTestMtrrLibAsmCpuid; + gUnitTestHostBaseLib.X86->AsmCpuid =3D UnitTestMtrrLibAsmCpuid; + gUnitTestHostBaseLib.X86->AsmCpuidEx =3D UnitTestMtrrLibAsmCpuidEx; + gUnitTestHostBaseLib.X86->AsmReadMsr64 =3D UnitTestMtrrLibAsmReadMsr64; gUnitTestHostBaseLib.X86->AsmWriteMsr64 =3D UnitTestMtrrLibAsmWriteMsr64; =20 + if (SystemParameter->MkTmeKeyidBits !=3D 0) { + mCpuidExtendedFeatureFlagsEcx.Bits.TME_EN =3D 1; + mTmeActivateMsr.Bits.TmeEnable =3D 1; + mTmeActivateMsr.Bits.MkTmeKeyidBits =3D SystemParameter->MkTmeKe= yidBits; + } else { + mCpuidExtendedFeatureFlagsEcx.Bits.TME_EN =3D 0; + mTmeActivateMsr.Bits.TmeEnable =3D 0; + mTmeActivateMsr.Bits.MkTmeKeyidBits =3D 0; + } + return UNIT_TEST_PASSED; } =20 --=20 2.39.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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