From nobody Thu Apr 18 23:09:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101519+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101519+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679443024; cv=none; d=zohomail.com; s=zohoarc; b=M4ZH0XOYX7dEiz90ArjcJ7O8jV+db13hfVj6poTzbx57ROjXXYuP6YH8NMbpv4DBBnQDfV4xLd0cZ8IqFD85fkjosD2FRGTRDVZRfF3XI8MJ02SaIRpkH8jd+N1g9ABs/6zZaU1SNHClO1rjE84s7OWLTHMF1L/vqokKc4TcXMk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679443024; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=YAtN06aw3ztv5Eg6N9MkS7EUjwCeBlrtyjvObGGJms0=; b=YH0TJ34No16cxroPPlZRdhcFXMgVNRdUNqGdhhl3Q3hRfWWObHyX+0uIr1HvN/7Jp/qsYSzBBIByfC9BVzVvH67K1SuA0r0nbfaVVFmZHWMuicZhdFl2BIFV6i9+07oUPdaWaQKujMO/2HFDkYr3NqBaSeEKfEjovBsgmLqEuKc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101519+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 16794430244501019.3491538756157; Tue, 21 Mar 2023 16:57:04 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id BrQGYY1788612xlFvFWAdo6K; Tue, 21 Mar 2023 16:57:04 -0700 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.30789.1679443023007772831 for ; Tue, 21 Mar 2023 16:57:03 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10656"; a="341441496" X-IronPort-AV: E=Sophos;i="5.98,280,1673942400"; d="scan'208";a="341441496" X-Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Mar 2023 16:56:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10656"; a="805627723" X-IronPort-AV: E=Sophos;i="5.98,280,1673942400"; d="scan'208";a="805627723" X-Received: from shwdeopenlab706.ccr.corp.intel.com ([10.239.55.95]) by orsmga004.jf.intel.com with ESMTP; 21 Mar 2023 16:56:55 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu Subject: [edk2-devel] [PATCH 1/6] MdePkg: Add TME-MK related CPUID and MSR definitions Date: Wed, 22 Mar 2023 07:56:45 +0800 Message-Id: <20230321235650.675-2-ray.ni@intel.com> In-Reply-To: <20230321235650.675-1-ray.ni@intel.com> References: <20230321235650.675-1-ray.ni@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com X-Gm-Message-State: Dvtd6mtlbtFHJcu3aTiSzzO4x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679443024; bh=BGvCha8X15X/QpjX1XCEX4eCTdJshv8ZLpw7iNiiA9g=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=Q7NqtPvtysKIIu8SYZl/hoH3CXBKYH+XxE6SOjCtRC9ma/tZjvrNIj1+EIK/Xb3eS1N RH7+mdfBhZroIH9xZJfUqwmnHbXDIc+O5IO9XbqSUnHE9yRA3uA6Kq8YWzCseE8eQ8uuT 4ELetJP5A2ma+zrGbpgsgNrh+98tdhrdXD4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679443024951100002 Content-Type: text/plain; charset="utf-8" TME (Total Memory Encryption) is the capability to encrypt the entirety of physical memory of a system. TME-MK (Total Memory Encryption-Multi-Key) builds on TME and adds support for multiple encryption keys. The patch adds some necessary CPUID/MSR definitions for TME-MK. Signed-off-by: Ray Ni Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Reviewed-by: Michael D Kinney --- .../Include/Register/Intel/ArchitecturalMsr.h | 106 +++++++++++++++++- MdePkg/Include/Register/Intel/Cpuid.h | 9 +- 2 files changed, 112 insertions(+), 3 deletions(-) diff --git a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h b/MdePkg/Incl= ude/Register/Intel/ArchitecturalMsr.h index 071a8c689c..76d80660da 100644 --- a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h +++ b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h @@ -6,7 +6,7 @@ returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR. =20 - Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 @par Specification Reference: @@ -5679,6 +5679,110 @@ typedef union { **/ #define MSR_IA32_X2APIC_SELF_IPI 0x0000083F =20 +/** + Memory Encryption Activation MSR. If CPUID.07H:ECX.[13] =3D 1. + + @param ECX MSR_IA32_TME_ACTIVATE (0x00000982) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_TME_ACTIVATE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_TME_ACTIVATE_REGISTER. + + Example usage + @code + MSR_IA32_TME_ACTIVATE_REGISTER Msr; + + Msr.Uint64 =3D AsmReadMsr64 (MSR_IA32_TME_ACTIVATE); + AsmWriteMsr64 (MSR_IA32_TME_ACTIVATE, Msr.Uint64); + @endcode + @note MSR_IA32_TME_ACTIVATE is defined as IA32_TME_ACTIVATE in SDM. +**/ +#define MSR_IA32_TME_ACTIVATE 0x00000982 + +/** + MSR information returned for MSR index #MSR_IA32_TME_ACTIVATE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Lock R/O: Will be set upon successful WRMSR (or first SMI); + /// written value ignored.. + /// + UINT32 Lock : 1; + /// + /// [Bit 1] Hardware Encryption Enable: This bit also enables MKTME; M= KTME + /// cannot be enabled without enabling encryption hardware. + /// + UINT32 TmeEnable : 1; + /// + /// [Bit 2] Key Select: + /// 0: Create a new TME key (expected cold/warm boot). + /// 1: Restore the TME key from storage (Expected when resume from sta= ndby). + /// + UINT32 KeySelect : 1; + /// + /// [Bit 3] Save TME Key for Standby: Save key into storage to be used= when + /// resume from standby. + /// Note: This may not be supported in all processors. + /// + UINT32 SaveKeyForStandby : 1; + /// + /// [Bit 7:4] TME Policy/Encryption Algorithm: Only algorithms enumera= ted in + /// IA32_TME_CAPABILITY are allowed. + /// For example: + /// 0000 =E2=80=93 AES-XTS-128. + /// 0001 =E2=80=93 AES-XTS-128 with integrity. + /// 0010 =E2=80=93 AES-XTS-256. + /// Other values are invalid. + /// + UINT32 TmePolicy : 4; + UINT32 Reserved : 23; + /// + /// [Bit 31] TME Encryption Bypass Enable: When encryption hardware is= enabled: + /// * Total Memory Encryption is enabled using a CPU generated ephemer= al key + /// based on a hardware random number generator when this bit is set= to 0. + /// * Total Memory Encryption is bypassed (no encryption/decryption fo= r KeyID0) + /// when this bit is set to 1. + /// Software must inspect Hardware Encryption Enable (bit 1) and TME e= ncryption + /// bypass Enable (bit 31) to determine if TME encryption is enabled. + /// + UINT32 TmeBypassMode : 1; + /// + /// [Bit 35:32] MK_TME_KEYID_BITS: Reserved if MKTME is not enumerated= , otherwise: + /// The number of key identifier bits to allocate to MKTME usage. + /// Similar to enumeration, this is an encoded value. + /// Writing a value greater than MK_TME_MAX_KEYID_BITS will result in = #GP. + /// Writing a non-zero value to this field will #GP if bit 1 of EAX (H= ardware + /// Encryption Enable) is not also set to =E2=80=981, as encryption ha= rdware must be + /// enabled to use MKTME. + /// Example: To support 255 keys, this field would be set to a value o= f 8. + /// + UINT32 MkTmeKeyidBits : 4; + UINT32 Reserved2 : 12; + /// + /// [Bit 63:48] MK_TME_CRYPTO_ALGS: Reserved if MKTME is not enumerate= d, otherwise: + /// Bit 48: AES-XTS 128. + /// Bit 49: AES-XTS 128 with integrity. + /// Bit 50: AES-XTS 256. + /// Bit 63:51: Reserved (#GP) + /// Bitmask for BIOS to set which encryption algorithms are allowed fo= r MKTME, would + /// be later enforced by the key loading ISA ('1=3D allowed) + /// + UINT32 MkTmeCryptoAlgs : 16; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_TME_ACTIVATE_REGISTER; + /** Silicon Debug Feature Control (R/W). If CPUID.01H:ECX.[11] =3D 1. =20 diff --git a/MdePkg/Include/Register/Intel/Cpuid.h b/MdePkg/Include/Registe= r/Intel/Cpuid.h index 350bf60252..1fb880c85c 100644 --- a/MdePkg/Include/Register/Intel/Cpuid.h +++ b/MdePkg/Include/Register/Intel/Cpuid.h @@ -6,7 +6,7 @@ If a register returned is a single 32-bit value, then a data structure is not provided for that register. =20 - Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 @par Specification Reference: @@ -1490,7 +1490,12 @@ typedef union { /// RDPKRU/WRPKRU instructions). /// UINT32 OSPKE : 1; - UINT32 Reserved5 : 9; + UINT32 Reserved8 : 8; + /// + /// [Bit 13] If 1, the following MSRs are supported: IA32_TME_CAPABILI= TY, IA32_TME_ACTIVATE, + /// IA32_TME_EXCLUDE_MASK, and IA32_TME_EXCLUDE_BASE. + /// + UINT32 TME_EN : 1; /// /// [Bits 14] AVX512_VPOPCNTDQ. (Intel Xeon Phi only.). /// --=20 2.39.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101519): https://edk2.groups.io/g/devel/message/101519 Mute This Topic: https://groups.io/mt/97767966/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/3901457/1787277/102458076= /xyzzy [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Apr 18 23:09:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101521+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101521+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679443024; cv=none; d=zohomail.com; s=zohoarc; b=DnlTkuouN9COw+Tz8lwHR51ud6Htg4KduzjyOiecXwlUUkGxtouXQGM1uwMnZgdzenHKoQEid5YIGMBmUUJzxOisEe0FteXDkApSrcXSfFcvNrGjv+EkFM+QTulMothGXQsJbEm0I7BhHfZeqvaNpAt7ZUNQ9tqhSkMpCDzmW/Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679443024; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=fSCq26xCm0RYZorQmkCYqt+/XfNy+uRJH1Zcfx0V0Y8=; b=j7QwQQPX2Y2JI0S6TnyMXaJN4SV1Lx7kf3W0s1tTnD6S9whERQ8og3heDUlp6gdkvN51awDypujXIvoLf4CF/Zkg5q1Q0++Fxqi1DHWC1eglVUBysJ2oNGJIoZ7gUna124ucPoTwujAzz7/+vDQrMCTUOkxf7sFkF+KL9TjEn3c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101521+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679443024944869.5529641137537; Tue, 21 Mar 2023 16:57:04 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id ZlukYY1788612xmxvjPcPxKL; Tue, 21 Mar 2023 16:57:04 -0700 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.30790.1679443023738136787 for ; Tue, 21 Mar 2023 16:57:03 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10656"; a="341441508" X-IronPort-AV: E=Sophos;i="5.98,280,1673942400"; d="scan'208";a="341441508" X-Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Mar 2023 16:56:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10656"; a="805627733" X-IronPort-AV: E=Sophos;i="5.98,280,1673942400"; d="scan'208";a="805627733" X-Received: from shwdeopenlab706.ccr.corp.intel.com ([10.239.55.95]) by orsmga004.jf.intel.com with ESMTP; 21 Mar 2023 16:56:56 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Eric Dong , Rahul Kumar , Gerd Hoffmann , Michael D Kinney , Ahmad Anadani Subject: [edk2-devel] [PATCH 2/6] UefiCpuPkg/MtrrTest: Only claim CPUID max leaf as 1 Date: Wed, 22 Mar 2023 07:56:46 +0800 Message-Id: <20230321235650.675-3-ray.ni@intel.com> In-Reply-To: <20230321235650.675-1-ray.ni@intel.com> References: <20230321235650.675-1-ray.ni@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com X-Gm-Message-State: 9JCxnTiy7OMAzSYxoTegGNf5x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679443024; bh=dTYD02bZuPnI6eorS6NqAm8/uK25wLWZqQHuih98Rdk=; h=Cc:Date:From:Reply-To:Subject:To; b=f45ZU9+gEvVRnV0d50Zf0wzgVfoL0ZjbzvKbKFpipeow4hMZY/XlN/vtZdC63C7PC4b 5cTM0ReezqpMWqHCiULbeZWJWULm+kiIHzGhgq63a0zPlRA1HfpUTfSx/I4Nq8s6K/3j7 D/YtkXkfz9GnergEjatbtIs2IyoCU6xdZjg= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679443026866100006 Content-Type: text/plain; charset="utf-8" MtrrLib code queries the CPUID leaf 7h result if support. Update Test code temporary to claim the CPUID only supports max leaf as 1 so MtrrLib skips to query CPUID leaf 7h. Signed-off-by: Ray Ni Cc: Eric Dong Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Michael D Kinney Cc: Ahmad Anadani Reviewed-by: Michael D Kinney --- UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c b/UefiCpuPkg/Lib= rary/MtrrLib/UnitTest/Support.c index 748c403281..260966e7b6 100644 --- a/UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c +++ b/UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c @@ -1,7 +1,7 @@ /** @file Unit tests of the MtrrLib instance of the MtrrLib class =20 - Copyright (c) 2018 - 2020, Intel Corporation. All rights reserved.
+ Copyright (c) 2018 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -122,6 +122,13 @@ UnitTestMtrrLibAsmCpuid ( ) { switch (Index) { + case CPUID_SIGNATURE: + if (Eax !=3D NULL) { + *Eax =3D CPUID_VERSION_INFO; + } + + return Index; + break; case CPUID_VERSION_INFO: if (Edx !=3D NULL) { *Edx =3D mCpuidVersionInfoEdx.Uint32; --=20 2.39.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101521): https://edk2.groups.io/g/devel/message/101521 Mute This Topic: https://groups.io/mt/97767968/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/3901457/1787277/102458076= /xyzzy [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Apr 18 23:09:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101520+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101520+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679443025; cv=none; d=zohomail.com; s=zohoarc; b=F4rVCoOoCUriFMVnscju2TJ8u8fKgo25CORFnIFNlbe36Q6ck/YCw0SiqYp2ALfedN3ZB5c9TSX67I/gU5q0v6kSWv2/XBasMJqdEHe4m0Xjy3EBEadJGo9ELWlVfK/E8ggO120QcVzeaShbeXi7OenuCcg546ayjNiTfrsofMc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679443025; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=nUKJ3fiPzaQIkhu90Vt4jzuJ0NBSW7PobeYL2d+MQbs=; b=B6ooIV6kgubkvLaMys2BcZJp6Hx0LyHxJc9k8yvKE/71Sf9xN+khtjI+eN3XMhULxWfifgZrzRLztIJkHMc8g6x6p9WCz65ZoKbrWx7L7hrjx7pogJ8hfs8eh8uIHzDBpzEXavsr31bBf7qUmRjsY5WxipdugCUTmda9mN2EQH8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101520+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679443025756299.79690945954917; Tue, 21 Mar 2023 16:57:05 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id Mea3YY1788612xwgB7bXdE9p; Tue, 21 Mar 2023 16:57:05 -0700 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.30789.1679443023007772831 for ; Tue, 21 Mar 2023 16:57:03 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10656"; a="341441514" X-IronPort-AV: E=Sophos;i="5.98,280,1673942400"; d="scan'208";a="341441514" X-Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Mar 2023 16:57:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10656"; a="805627742" X-IronPort-AV: E=Sophos;i="5.98,280,1673942400"; d="scan'208";a="805627742" X-Received: from shwdeopenlab706.ccr.corp.intel.com ([10.239.55.95]) by orsmga004.jf.intel.com with ESMTP; 21 Mar 2023 16:56:58 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Eric Dong , Rahul Kumar , Gerd Hoffmann , Michael D Kinney , Ahmad Anadani Subject: [edk2-devel] [PATCH 3/6] UefiCpuPkg/MtrrLib: Substract TME-MK KEY_ID_BITS from CPU max PA Date: Wed, 22 Mar 2023 07:56:47 +0800 Message-Id: <20230321235650.675-4-ray.ni@intel.com> In-Reply-To: <20230321235650.675-1-ray.ni@intel.com> References: <20230321235650.675-1-ray.ni@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com X-Gm-Message-State: SPbNepFQE59QeqgPC1z2biLux1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679443025; bh=gHz14572Qd6Ujm4TK5Cd36buA+ETyUaZya5ykJ0FTSo=; h=Cc:Date:From:Reply-To:Subject:To; b=MB0A7dD6A8YrZ5gMjAH/xX7mIyFz6mz8zz9UlAdYAonNijDrGu8+h10AA++O+k9pLBt O4S+AsWK5h1C5UMKU3eCb7tZbjEGC+l60kmVMxSVzxs/mKYm+nXf89AaRMgsFVUy51yec ZSbSP0qFea3W0JRfUXxpXCXLS0PnxZNB7Ow= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679443026867100007 Content-Type: text/plain; charset="utf-8" CPUID enumeration of MAX_PA is unaffected by TME-MK activation and will continue to report the maximum physical address bits available for software to use, irrespective of the number of KeyID bits. So, we need to check if TME is enabled and adjust the PA size accordingly. Signed-off-by: Ray Ni Cc: Eric Dong Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Michael D Kinney Cc: Ahmad Anadani Reviewed-by: Michael D Kinney --- UefiCpuPkg/Library/MtrrLib/MtrrLib.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c b/UefiCpuPkg/Library/Mtrr= Lib/MtrrLib.c index e5c862c83d..a66357e305 100644 --- a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c +++ b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c @@ -756,8 +756,11 @@ MtrrLibInitializeMtrrMask ( OUT UINT64 *MtrrValidAddressMask ) { - UINT32 MaxExtendedFunction; - CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize; + UINT32 MaxExtendedFunction; + CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize; + UINT32 MaxFunction; + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX ExtendedFeatureFlagsEcx; + MSR_IA32_TME_ACTIVATE_REGISTER TmeActivate; =20 AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunction, NULL, NULL, NUL= L); =20 @@ -767,6 +770,23 @@ MtrrLibInitializeMtrrMask ( VirPhyAddressSize.Bits.PhysicalAddressBits =3D 36; } =20 + // + // CPUID enumeration of MAX_PA is unaffected by TME-MK activation and wi= ll continue + // to report the maximum physical address bits available for software to= use, + // irrespective of the number of KeyID bits. + // So, we need to check if TME is enabled and adjust the PA size accordi= ngly. + // + AsmCpuid (CPUID_SIGNATURE, &MaxFunction, NULL, NULL, NULL); + if (MaxFunction >=3D CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS) { + AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 0, NULL, NULL, &E= xtendedFeatureFlagsEcx.Uint32, NULL); + if (ExtendedFeatureFlagsEcx.Bits.TME_EN =3D=3D 1) { + TmeActivate.Uint64 =3D AsmReadMsr64 (MSR_IA32_TME_ACTIVATE); + if (TmeActivate.Bits.TmeEnable =3D=3D 1) { + VirPhyAddressSize.Bits.PhysicalAddressBits -=3D TmeActivate.Bits.M= kTmeKeyidBits; + } + } + } + *MtrrValidBitsMask =3D LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalA= ddressBits) - 1; *MtrrValidAddressMask =3D *MtrrValidBitsMask & 0xfffffffffffff000ULL; } --=20 2.39.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101520): https://edk2.groups.io/g/devel/message/101520 Mute This Topic: https://groups.io/mt/97767967/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/3901457/1787277/102458076= /xyzzy [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Apr 18 23:09:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101522+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101522+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679443026; cv=none; d=zohomail.com; s=zohoarc; b=JqzutBLPRrIcPoKy4Q32dCtFYh9lvZXDl5sn/+xYW+d6jdrLsrMG38vcs5kv62TeX9wgS9+Y2pUUI1MpQdMykhDFCI7YoqJXT/Wk6rWfe9egIIU0x5sEklX+mEZXJDbF3yftyl68bQMrN24mc66LA6le/432KZa6d7QLZ82IK/M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679443026; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=ubDlzQXMiG/Utd6W+ANE0XGD9OFnnJHMlkpUW/HcDSk=; b=eM6Kiga2kEfx8WQhzsbWJ35GX9mQFkxIUgqkviUUF5YZ/ObgoWcbTqy6sNeE3oGjNLs5KCl3qb0YW7rZBdRrwTnd7aZVA/IF7Ol4POyUt9CiVO5jeQS2isOcrhLMdPOnZv0WGh9TWFFO+xvOYQq59aNMW9qSCqPmGMwtB+baRgU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101522+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679443026193459.82514652401267; Tue, 21 Mar 2023 16:57:06 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id rveNYY1788612x1MUgOr4rHj; Tue, 21 Mar 2023 16:57:05 -0700 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.30789.1679443023007772831 for ; Tue, 21 Mar 2023 16:57:03 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10656"; a="341441518" X-IronPort-AV: E=Sophos;i="5.98,280,1673942400"; d="scan'208";a="341441518" X-Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Mar 2023 16:57:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10656"; a="805627764" X-IronPort-AV: E=Sophos;i="5.98,280,1673942400"; d="scan'208";a="805627764" X-Received: from shwdeopenlab706.ccr.corp.intel.com ([10.239.55.95]) by orsmga004.jf.intel.com with ESMTP; 21 Mar 2023 16:57:00 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Eric Dong , Rahul Kumar , Gerd Hoffmann , Michael D Kinney , Ahmad Anadani Subject: [edk2-devel] [PATCH 4/6] UefiCpuPkg/CpuDxe: Refactor to use CPUID definitions Date: Wed, 22 Mar 2023 07:56:48 +0800 Message-Id: <20230321235650.675-5-ray.ni@intel.com> In-Reply-To: <20230321235650.675-1-ray.ni@intel.com> References: <20230321235650.675-1-ray.ni@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com X-Gm-Message-State: 9dTF2nKHKRB5Sax8vD7KGorEx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679443025; bh=hYAl/J7JMW2EEiTQlYes3VjP2Pz4y5iHEVOso868Dts=; h=Cc:Date:From:Reply-To:Subject:To; b=e5zGaeBGWi8FBcwp2x5B31/bC+6hNm1a1La+mMJc4aRmGyxHYkgJOQ+RIq8gehZv8KG 4jpLwD9dpqmZjIfQu/Y08XM9DTHXb2KFKvkEIlVXy/RtxK2ConVxcvmoqt6IIyGoM2CyV I1iaLJS2cQ6DR7ZFsi658O7bS2Mz2ZyovSI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679443026878100011 Content-Type: text/plain; charset="utf-8" The patch does not change any code behavior but only refactors by: * replaces the hardcode 0x80000000 with CPUID_EXTENDED_FUNCTION * replaces the hardcode 0x80000008 with CPUID_VIR_PHY_ADDRESS_SIZE * replace "UINT32 Eax" with "CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize" Signed-off-by: Ray Ni Cc: Eric Dong Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Michael D Kinney Cc: Ahmad Anadani Reviewed-by: Michael D Kinney --- UefiCpuPkg/CpuDxe/CpuDxe.c | 18 ++++++++---------- UefiCpuPkg/CpuDxe/CpuDxe.h | 3 ++- 2 files changed, 10 insertions(+), 11 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.c b/UefiCpuPkg/CpuDxe/CpuDxe.c index a6a91507f6..920976c576 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.c +++ b/UefiCpuPkg/CpuDxe/CpuDxe.c @@ -1,7 +1,7 @@ /** @file CPU DXE Module to produce CPU ARCH Protocol. =20 - Copyright (c) 2008 - 2022, Intel Corporation. All rights reserved.
+ Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -505,20 +505,18 @@ InitializeMtrrMask ( VOID ) { - UINT32 RegEax; - UINT8 PhysicalAddressBits; + UINT32 MaxExtendedFunction; + CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize; =20 - AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); + AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunction, NULL, NULL, NUL= L); =20 - if (RegEax >=3D 0x80000008) { - AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); - - PhysicalAddressBits =3D (UINT8)RegEax; + if (MaxExtendedFunction >=3D CPUID_VIR_PHY_ADDRESS_SIZE) { + AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &VirPhyAddressSize.Uint32, NULL,= NULL, NULL); } else { - PhysicalAddressBits =3D 36; + VirPhyAddressSize.Bits.PhysicalAddressBits =3D 36; } =20 - mValidMtrrBitsMask =3D LShiftU64 (1, PhysicalAddressBits) - 1; + mValidMtrrBitsMask =3D LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalA= ddressBits) - 1; mValidMtrrAddressMask =3D mValidMtrrBitsMask & 0xfffffffffffff000ULL; } =20 diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.h b/UefiCpuPkg/CpuDxe/CpuDxe.h index 49a390b4c4..0e7d88dd35 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.h +++ b/UefiCpuPkg/CpuDxe/CpuDxe.h @@ -1,7 +1,7 @@ /** @file CPU DXE Module to produce CPU ARCH Protocol and CPU MP Protocol. =20 - Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -13,6 +13,7 @@ =20 #include #include +#include #include =20 #include --=20 2.39.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101522): https://edk2.groups.io/g/devel/message/101522 Mute This Topic: https://groups.io/mt/97767969/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/3901457/1787277/102458076= /xyzzy [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Apr 18 23:09:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101523+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101523+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679443044; cv=none; d=zohomail.com; s=zohoarc; b=n/5gxpb/1zqm34CMCUmb/wlbB4K4l5JM722bXUsU0J3IQevQyNJ149fFQ8W4wjWlglAj8edD/lu+AtRm2DS9Z1Y7E05tsUn8R5tv8BQ561/oHLFTAMK4CiamxcofTHvVhaANvFirXdId22WQHbClaW/VLy2LNC7z5CxjoZexusQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679443044; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=QdyVxKQarLqhTN7+b2AegM8HlKunxdvwznRUpMmJ7/w=; b=Ms82esQhfeuSeIT6YRnqqvL0Q3xsqkfJRcoRifaRE4Sc5xz5g/a1ie0p8lyAE/ZB4Z78IPTz/a358dRjHpTkVoh6jVt4tGAHaeSl80COQBb0t0VfwNWDjWdSM5GU9qsWBdjhF7eOqZe+YX3ICcynQ05HZ57gMA9bI/Rx3DFqciE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101523+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679443044372301.42092410072814; Tue, 21 Mar 2023 16:57:24 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id izHVYY1788612xILdpFUV7FE; Tue, 21 Mar 2023 16:57:24 -0700 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.30797.1679443043224909338 for ; Tue, 21 Mar 2023 16:57:23 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10656"; a="341441528" X-IronPort-AV: E=Sophos;i="5.98,280,1673942400"; d="scan'208";a="341441528" X-Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Mar 2023 16:57:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10656"; a="805627777" X-IronPort-AV: E=Sophos;i="5.98,280,1673942400"; d="scan'208";a="805627777" X-Received: from shwdeopenlab706.ccr.corp.intel.com ([10.239.55.95]) by orsmga004.jf.intel.com with ESMTP; 21 Mar 2023 16:57:02 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Eric Dong , Rahul Kumar , Gerd Hoffmann , Michael D Kinney , Ahmad Anadani Subject: [edk2-devel] [PATCH 5/6] UefiCpuPkg/CpuDxe: Substract TME-MK KEY_ID_BITS from CPU max PA Date: Wed, 22 Mar 2023 07:56:49 +0800 Message-Id: <20230321235650.675-6-ray.ni@intel.com> In-Reply-To: <20230321235650.675-1-ray.ni@intel.com> References: <20230321235650.675-1-ray.ni@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com X-Gm-Message-State: 9NSdoxjskCpYSxMknXKxFyQbx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679443044; bh=gFE8rZJFLdVCeMKKhc8UhnVtO983XjvdCyo1eIKTkJ8=; h=Cc:Date:From:Reply-To:Subject:To; b=qQJLKtNF3wT3+zN+F668pUqN42uW89IubgodfUpAz09FLb7DDamAnkxW0AA7YwblKDZ thBedRKQzxowL/cc2u8QqigcObm7zucSH/HjKLI0EPdMZ3CvoBGg5UMGu3O/CubNnQw2z VBE91R/expWuLCOBpEuPfHMRxFX+bug112k= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679443044946100002 Content-Type: text/plain; charset="utf-8" CPUID enumeration of MAX_PA is unaffected by TME-MK activation and will continue to report the maximum physical address bits available for software to use, irrespective of the number of KeyID bits. So, we need to check if TME is enabled and adjust the PA size accordingly. Signed-off-by: Ray Ni Cc: Eric Dong Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Michael D Kinney Cc: Ahmad Anadani Reviewed-by: Michael D Kinney --- UefiCpuPkg/CpuDxe/CpuDxe.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.c b/UefiCpuPkg/CpuDxe/CpuDxe.c index 920976c576..3febd59d99 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.c +++ b/UefiCpuPkg/CpuDxe/CpuDxe.c @@ -505,8 +505,11 @@ InitializeMtrrMask ( VOID ) { - UINT32 MaxExtendedFunction; - CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize; + UINT32 MaxExtendedFunction; + CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize; + UINT32 MaxFunction; + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX ExtendedFeatureFlagsEcx; + MSR_IA32_TME_ACTIVATE_REGISTER TmeActivate; =20 AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunction, NULL, NULL, NUL= L); =20 @@ -516,6 +519,23 @@ InitializeMtrrMask ( VirPhyAddressSize.Bits.PhysicalAddressBits =3D 36; } =20 + // + // CPUID enumeration of MAX_PA is unaffected by TME-MK activation and wi= ll continue + // to report the maximum physical address bits available for software to= use, + // irrespective of the number of KeyID bits. + // So, we need to check if TME is enabled and adjust the PA size accordi= ngly. + // + AsmCpuid (CPUID_SIGNATURE, &MaxFunction, NULL, NULL, NULL); + if (MaxFunction >=3D CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS) { + AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 0, NULL, NULL, &E= xtendedFeatureFlagsEcx.Uint32, NULL); + if (ExtendedFeatureFlagsEcx.Bits.TME_EN =3D=3D 1) { + TmeActivate.Uint64 =3D AsmReadMsr64 (MSR_IA32_TME_ACTIVATE); + if (TmeActivate.Bits.TmeEnable =3D=3D 1) { + VirPhyAddressSize.Bits.PhysicalAddressBits -=3D TmeActivate.Bits.M= kTmeKeyidBits; + } + } + } + mValidMtrrBitsMask =3D LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalA= ddressBits) - 1; mValidMtrrAddressMask =3D mValidMtrrBitsMask & 0xfffffffffffff000ULL; } --=20 2.39.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101523): https://edk2.groups.io/g/devel/message/101523 Mute This Topic: https://groups.io/mt/97767975/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/3901457/1787277/102458076= /xyzzy [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Apr 18 23:09:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101524+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101524+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679443044; cv=none; d=zohomail.com; s=zohoarc; b=Zem5W56xeYT7SdB8AfR6dfWsl0rn4s+wxIiGxmiVcjAguHSiV5ijZD6RLducuKfiIc/1//ikwftBEdM631mdSijz4DAyjuKWAp7RkESn70n4QtakbRavwWoxYDeAtHMUjbtHSnbZQnR/q0vgMimmHjGSRFNVBY4FvRzRIcauIws= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679443044; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=QOrV1SMpFK+Q/ScUPzZrZNF0TpzpD6tUEdUZzBXM4Dc=; b=Y2MIM3Kg2zh4lkdI+RHdDp/qaoaeewJcYpQRV6NmitQ8UKbyj7Q4q7E1dt/Vq+wDgfH1O0hGv4dC4Ea/ilA+2WV7pDvFUo3ysR7e52dmIr15VW9KuChRG4da8Ue2VuE0sHiSadSCOlylmbWcu0/eVxm3b7uRI4K/OWQCFbvVlz0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101524+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679443044834807.0844789571074; Tue, 21 Mar 2023 16:57:24 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 6yV6YY1788612xQ1Wh2MyRIn; Tue, 21 Mar 2023 16:57:24 -0700 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.30797.1679443043224909338 for ; Tue, 21 Mar 2023 16:57:23 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10656"; a="341441547" X-IronPort-AV: E=Sophos;i="5.98,280,1673942400"; d="scan'208";a="341441547" X-Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Mar 2023 16:57:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10656"; a="805627780" X-IronPort-AV: E=Sophos;i="5.98,280,1673942400"; d="scan'208";a="805627780" X-Received: from shwdeopenlab706.ccr.corp.intel.com ([10.239.55.95]) by orsmga004.jf.intel.com with ESMTP; 21 Mar 2023 16:57:04 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Eric Dong , Rahul Kumar , Gerd Hoffmann , Michael D Kinney , Ahmad Anadani Subject: [edk2-devel] [PATCH 6/6] UefiCpuPkg/MtrrTest: Add test cases for TME-MK enable case Date: Wed, 22 Mar 2023 07:56:50 +0800 Message-Id: <20230321235650.675-7-ray.ni@intel.com> In-Reply-To: <20230321235650.675-1-ray.ni@intel.com> References: <20230321235650.675-1-ray.ni@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com X-Gm-Message-State: G2SzQPRYiuOzx4uTPOfcBi1zx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679443044; bh=D3zXABrrh2tL4WGApijMus1V7/RV6IO7LghpYpbfnJQ=; h=Cc:Date:From:Reply-To:Subject:To; b=F6sJe25BVfAsg9wHkxsrxX+6uxkBQGjoFOvKVHYkbhdEFl49wLIf2/AiZcheWUPiK4c Jx56qjn7QX7FetLU4dU2ftuVTn+WkuBJKp9HxYFTxBF0ERh8QxjihNTueM6Hn/wlRVgKc FlSfsb5AQ/KKO3lon8hhwcRrL6FrQ4Dude8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679443047078100001 Content-Type: text/plain; charset="utf-8" When TME-MK is enabled, the MtrrLib should substract the TME-MK reserved bits from the max PA returned from CPUID instruction. The new test case guarantees such behavior in MtrrLib. Signed-off-by: Ray Ni Cc: Eric Dong Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Michael D Kinney Cc: Ahmad Anadani Reviewed-by: Michael D Kinney --- .../MtrrLib/UnitTest/MtrrLibUnitTest.c | 18 +-- .../MtrrLib/UnitTest/MtrrLibUnitTest.h | 3 +- UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c | 119 ++++++++++++++---- 3 files changed, 107 insertions(+), 33 deletions(-) diff --git a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c b/UefiCp= uPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c index b9a97dee09..1409ae27bb 100644 --- a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c +++ b/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c @@ -1,7 +1,7 @@ /** @file Unit tests of the MtrrLib instance of the MtrrLib class =20 - Copyright (c) 2020, Intel Corporation. All rights reserved.
+ Copyright (c) 2020 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -30,6 +30,8 @@ STATIC MTRR_LIB_SYSTEM_PARAMETER mSystemParameters[] =3D= { { 48, TRUE, TRUE, CacheWriteThrough, 12 }, { 48, TRUE, TRUE, CacheWriteProtected, 12 }, { 48, TRUE, TRUE, CacheWriteCombining, 12 }, + + { 48, TRUE, TRUE, CacheWriteBack, 12, 7}, // 7 bits for MKTME }; =20 UINT32 mFixedMtrrsIndex[] =3D { @@ -219,7 +221,7 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings ( &WcCount ); GenerateValidAndConfigurableMtrrPairs ( - SystemParameter->PhysicalAddressBits, + SystemParameter->PhysicalAddressBits - SystemParameter->MkTmeKeyidBits, RawMtrrRange, UcCount, WtCount, @@ -232,7 +234,7 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings ( ExpectedMemoryRangesCount =3D ARRAY_SIZE (ExpectedMemoryRanges); GetEffectiveMemoryRanges ( SystemParameter->DefaultCacheType, - SystemParameter->PhysicalAddressBits, + SystemParameter->PhysicalAddressBits - SystemParameter->MkTmeKeyidBits, RawMtrrRange, ExpectedVariableMtrrUsage, ExpectedMemoryRanges, @@ -278,7 +280,7 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings ( ActualMemoryRangesCount =3D ARRAY_SIZE (ActualMemoryRanges); CollectTestResult ( SystemParameter->DefaultCacheType, - SystemParameter->PhysicalAddressBits, + SystemParameter->PhysicalAddressBits - SystemParameter->MkTmeKeyidBi= ts, SystemParameter->VariableMtrrCount, &LocalMtrrs, ActualMemoryRanges, @@ -325,7 +327,7 @@ UnitTestInvalidMemoryLayouts ( SystemParameter =3D (MTRR_LIB_SYSTEM_PARAMETER *)Context; =20 RangeCount =3D Random32 (1, ARRAY_SIZE (Ranges)); - MaxAddress =3D 1ull << SystemParameter->PhysicalAddressBits; + MaxAddress =3D 1ull << (SystemParameter->PhysicalAddressBits - SystemPar= ameter->MkTmeKeyidBits); =20 for (Index =3D 0; Index < RangeCount; Index++) { do { @@ -967,7 +969,7 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings ( &WcCount ); GenerateValidAndConfigurableMtrrPairs ( - SystemParameter->PhysicalAddressBits, + SystemParameter->PhysicalAddressBits - SystemParameter->MkTmeKeyidBits, RawMtrrRange, UcCount, WtCount, @@ -980,7 +982,7 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings ( ExpectedMemoryRangesCount =3D ARRAY_SIZE (ExpectedMemoryRanges); GetEffectiveMemoryRanges ( SystemParameter->DefaultCacheType, - SystemParameter->PhysicalAddressBits, + SystemParameter->PhysicalAddressBits - SystemParameter->MkTmeKeyidBits, RawMtrrRange, ExpectedVariableMtrrUsage, ExpectedMemoryRanges, @@ -1019,7 +1021,7 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings ( ActualMemoryRangesCount =3D ARRAY_SIZE (ActualMemoryRanges); CollectTestResult ( SystemParameter->DefaultCacheType, - SystemParameter->PhysicalAddressBits, + SystemParameter->PhysicalAddressBits - SystemParameter->MkTmeKeyidBi= ts, SystemParameter->VariableMtrrCount, &LocalMtrrs, ActualMemoryRanges, diff --git a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h b/UefiCp= uPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h index 57e656c555..4471c1dcf7 100644 --- a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h +++ b/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2020, Intel Corporation. All rights reserved.
+ Copyright (c) 2020 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -40,6 +40,7 @@ typedef struct { BOOLEAN FixedMtrrSupported; MTRR_MEMORY_CACHE_TYPE DefaultCacheType; UINT32 VariableMtrrCount; + UINT8 MkTmeKeyidBits; } MTRR_LIB_SYSTEM_PARAMETER; =20 extern UINT32 mFixedMtrrsIndex[]; diff --git a/UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c b/UefiCpuPkg/Lib= rary/MtrrLib/UnitTest/Support.c index 260966e7b6..ba1de10034 100644 --- a/UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c +++ b/UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c @@ -12,13 +12,15 @@ MTRR_MEMORY_CACHE_TYPE mMemoryCacheTypes[] =3D { CacheUncacheable, CacheWriteCombining, CacheWriteThrough, CacheWriteProt= ected, CacheWriteBack }; =20 -UINT64 mFixedMtrrsValue[MTRR_NUMBER_OF_FIXED_MTR= R]; -MSR_IA32_MTRR_PHYSBASE_REGISTER mVariableMtrrsPhysBase[MTRR_NUMBER_OF_VAR= IABLE_MTRR]; -MSR_IA32_MTRR_PHYSMASK_REGISTER mVariableMtrrsPhysMask[MTRR_NUMBER_OF_VAR= IABLE_MTRR]; -MSR_IA32_MTRR_DEF_TYPE_REGISTER mDefTypeMsr; -MSR_IA32_MTRRCAP_REGISTER mMtrrCapMsr; -CPUID_VERSION_INFO_EDX mCpuidVersionInfoEdx; -CPUID_VIR_PHY_ADDRESS_SIZE_EAX mCpuidVirPhyAddressSizeEax; +UINT64 mFixedMtrrsValue[MTRR_NUMBER_= OF_FIXED_MTRR]; +MSR_IA32_MTRR_PHYSBASE_REGISTER mVariableMtrrsPhysBase[MTRR_N= UMBER_OF_VARIABLE_MTRR]; +MSR_IA32_MTRR_PHYSMASK_REGISTER mVariableMtrrsPhysMask[MTRR_N= UMBER_OF_VARIABLE_MTRR]; +MSR_IA32_MTRR_DEF_TYPE_REGISTER mDefTypeMsr; +MSR_IA32_MTRRCAP_REGISTER mMtrrCapMsr; +MSR_IA32_TME_ACTIVATE_REGISTER mTmeActivateMsr; +CPUID_VERSION_INFO_EDX mCpuidVersionInfoEdx; +CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX mCpuidExtendedFeatureFlagsEcx; +CPUID_VIR_PHY_ADDRESS_SIZE_EAX mCpuidVirPhyAddressSizeEax; =20 BOOLEAN mRandomInput; UINTN mNumberIndex =3D 0; @@ -87,34 +89,42 @@ GenerateRandomNumbers ( } =20 /** - Retrieves CPUID information. + Retrieves CPUID information using an extended leaf identifier. + + Executes the CPUID instruction with EAX set to the value specified by In= dex + and ECX set to the value specified by SubIndex. This function always ret= urns + Index. This function is only available on IA-32 and x64. =20 - Executes the CPUID instruction with EAX set to the value specified by In= dex. - This function always returns Index. If Eax is not NULL, then the value of EAX after CPUID is returned in Eax. If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx. If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx. If Edx is not NULL, then the value of EDX after CPUID is returned in Edx. - This function is only available on IA-32 and x64. =20 - @param Index The 32-bit value to load into EAX prior to invoking the CP= UID - instruction. - @param Eax The pointer to the 32-bit EAX value returned by the CPUID - instruction. This is an optional parameter that may be NUL= L. - @param Ebx The pointer to the 32-bit EBX value returned by the CPUID - instruction. This is an optional parameter that may be NUL= L. - @param Ecx The pointer to the 32-bit ECX value returned by the CPUID - instruction. This is an optional parameter that may be NUL= L. - @param Edx The pointer to the 32-bit EDX value returned by the CPUID - instruction. This is an optional parameter that may be NUL= L. + @param Index The 32-bit value to load into EAX prior to invoking the + CPUID instruction. + @param SubIndex The 32-bit value to load into ECX prior to invoking the + CPUID instruction. + @param Eax The pointer to the 32-bit EAX value returned by the CP= UID + instruction. This is an optional parameter that may be + NULL. + @param Ebx The pointer to the 32-bit EBX value returned by the CP= UID + instruction. This is an optional parameter that may be + NULL. + @param Ecx The pointer to the 32-bit ECX value returned by the CP= UID + instruction. This is an optional parameter that may be + NULL. + @param Edx The pointer to the 32-bit EDX value returned by the CP= UID + instruction. This is an optional parameter that may be + NULL. =20 @return Index. =20 **/ UINT32 EFIAPI -UnitTestMtrrLibAsmCpuid ( +UnitTestMtrrLibAsmCpuidEx ( IN UINT32 Index, + IN UINT32 SubIndex, OUT UINT32 *Eax OPTIONAL, OUT UINT32 *Ebx OPTIONAL, OUT UINT32 *Ecx OPTIONAL, @@ -124,7 +134,7 @@ UnitTestMtrrLibAsmCpuid ( switch (Index) { case CPUID_SIGNATURE: if (Eax !=3D NULL) { - *Eax =3D CPUID_VERSION_INFO; + *Eax =3D CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS; } =20 return Index; @@ -134,6 +144,13 @@ UnitTestMtrrLibAsmCpuid ( *Edx =3D mCpuidVersionInfoEdx.Uint32; } =20 + return Index; + break; + case CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS: + if (Ecx !=3D NULL) { + *Ecx =3D mCpuidExtendedFeatureFlagsEcx.Uint32; + } + return Index; break; case CPUID_EXTENDED_FUNCTION: @@ -159,6 +176,44 @@ UnitTestMtrrLibAsmCpuid ( return Index; } =20 +/** + Retrieves CPUID information. + + Executes the CPUID instruction with EAX set to the value specified by In= dex. + This function always returns Index. + If Eax is not NULL, then the value of EAX after CPUID is returned in Eax. + If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx. + If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx. + If Edx is not NULL, then the value of EDX after CPUID is returned in Edx. + This function is only available on IA-32 and x64. + + @param Index The 32-bit value to load into EAX prior to invoking the CP= UID + instruction. + @param Eax The pointer to the 32-bit EAX value returned by the CPUID + instruction. This is an optional parameter that may be NUL= L. + @param Ebx The pointer to the 32-bit EBX value returned by the CPUID + instruction. This is an optional parameter that may be NUL= L. + @param Ecx The pointer to the 32-bit ECX value returned by the CPUID + instruction. This is an optional parameter that may be NUL= L. + @param Edx The pointer to the 32-bit EDX value returned by the CPUID + instruction. This is an optional parameter that may be NUL= L. + + @return Index. + +**/ +UINT32 +EFIAPI +UnitTestMtrrLibAsmCpuid ( + IN UINT32 Index, + OUT UINT32 *Eax OPTIONAL, + OUT UINT32 *Ebx OPTIONAL, + OUT UINT32 *Ecx OPTIONAL, + OUT UINT32 *Edx OPTIONAL + ) +{ + return UnitTestMtrrLibAsmCpuidEx (Index, 0, Eax, Ebx, Ecx, Edx); +} + /** Returns a 64-bit Machine Specific Register(MSR). =20 @@ -207,6 +262,10 @@ UnitTestMtrrLibAsmReadMsr64 ( return mMtrrCapMsr.Uint64; } =20 + if (MsrIndex =3D=3D MSR_IA32_TME_ACTIVATE) { + return mTmeActivateMsr.Uint64; + } + // // Should never fall through to here // @@ -324,10 +383,22 @@ InitializeMtrrRegs ( // // Hook BaseLib functions used by MtrrLib that require some emulation. // - gUnitTestHostBaseLib.X86->AsmCpuid =3D UnitTestMtrrLibAsmCpuid; + gUnitTestHostBaseLib.X86->AsmCpuid =3D UnitTestMtrrLibAsmCpuid; + gUnitTestHostBaseLib.X86->AsmCpuidEx =3D UnitTestMtrrLibAsmCpuidEx; + gUnitTestHostBaseLib.X86->AsmReadMsr64 =3D UnitTestMtrrLibAsmReadMsr64; gUnitTestHostBaseLib.X86->AsmWriteMsr64 =3D UnitTestMtrrLibAsmWriteMsr64; =20 + if (SystemParameter->MkTmeKeyidBits !=3D 0) { + mCpuidExtendedFeatureFlagsEcx.Bits.TME_EN =3D 1; + mTmeActivateMsr.Bits.TmeEnable =3D 1; + mTmeActivateMsr.Bits.MkTmeKeyidBits =3D SystemParameter->MkTmeKe= yidBits; + } else { + mCpuidExtendedFeatureFlagsEcx.Bits.TME_EN =3D 0; + mTmeActivateMsr.Bits.TmeEnable =3D 0; + mTmeActivateMsr.Bits.MkTmeKeyidBits =3D 0; + } + return UNIT_TEST_PASSED; } =20 --=20 2.39.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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