From nobody Fri Apr 26 15:40:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101381+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101381+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679290464; cv=none; d=zohomail.com; s=zohoarc; b=dQsmKSdD18ZMSL3MLFoWuVcn+syM25TnYs+lbxZe9t5AQSDmqbRTBCSJn22HclB1KOVnCM2vbicOn4hefkqzoav/8Gg8Y+AAyTLO3KGO2r3PS6wTeCUr5P4CG90zQP2IRn2CIgNFL+o/i6AJoa53MbOGACs9WlOSW8wj0b321GY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679290464; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Qt9Myaov1YKu4vMKxss508pYhKzjXsdYxV9gfTDxbac=; b=aP6X6hUHE0shRzP/Q6JjN4UoYCmgIqEd/uyA2DSMB6aquIY61ko5GlpyrRXQkNnh62uKlk7IcD4QG3CsfbpYLRppqqqbLJIb+YRvFGFUEfMjhgjAnmGyIJr2MnFai5Z7DYI+yKOLgdSVuy4c+5JNi9c2LTTaxImjA3hN8ed0vtc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101381+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679290464883797.3251437805925; Sun, 19 Mar 2023 22:34:24 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id Y8XOYY1788612xHdJRIDffPV; Sun, 19 Mar 2023 22:34:24 -0700 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web11.7469.1679290461311870555 for ; Sun, 19 Mar 2023 22:34:23 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="401155411" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="401155411" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:34:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="770059307" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="770059307" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:34:22 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V3 01/18] UefiCpuPkg/CpuPageTableLib: Remove unneeded 'if' condition Date: Mon, 20 Mar 2023 13:33:12 +0800 Message-Id: <20230320053329.410-2-dun.tan@intel.com> In-Reply-To: <20230320053329.410-1-dun.tan@intel.com> References: <20230320053329.410-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: 2a041pirhT33OAsvc50IcECzx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679290464; bh=sDDOBvbTVGIukOlFz5EkweiF+4MUI6WHANaUZZGRfyU=; h=Cc:Date:From:Reply-To:Subject:To; b=kxwKaq24sHXyFx5OfcghqCC8Akyp2elTah3v0foQqW7hMeslaMIsi/JIab25XmG2Kks Fc7l3maDJDpke5MVvPSVUM0zVrL92utL8sOyu6NG8gUDPDCGh5hmwY6jWSr2oLPEVwVps WPC8qX5dy2IY/Oo7YcX4Mfz+s44BXVjfmNw= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679290466407100005 Content-Type: text/plain; charset="utf-8" Remove unneeded 'if' condition in CpuPageTableLib code. The deleted code is in the code branch for present non-leaf parent entry. So the 'if' check for (ParentPagingEntry->Pnle.Bits.Present =3D=3D 0) is always FALSE. Signed-off-by: Dun Tan Cc: Eric Dong Reviewed-by: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 37713ec659..52535e5a8d 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -1,7 +1,7 @@ /** @file This library implements CpuPageTableLib that are generic for IA32 family= CPU. =20 - Copyright (c) 2022, Intel Corporation. All rights reserved.
+ Copyright (c) 2022 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -375,15 +375,6 @@ PageTableLibMapInLevel ( // we need to change PDPTE[0].ReadWrite =3D 1 and let all P= DE[0-255].ReadWrite =3D 0 in this step. // when PDPTE[0].Nx =3D 1 but caller wants to map [0-2MB] as Nx = =3D 0 (PDT[0].Nx =3D 0) // we need to change PDPTE[0].Nx =3D 0 and let all PDE[0-25= 5].Nx =3D 1 in this step. - if ((ParentPagingEntry->Pnle.Bits.Present =3D=3D 0) && (Mask->Bits.Pre= sent =3D=3D 1) && (Attribute->Bits.Present =3D=3D 1)) { - if (Modify) { - ParentPagingEntry->Pnle.Bits.Present =3D 1; - } - - ChildAttribute.Bits.Present =3D 0; - ChildMask.Bits.Present =3D 1; - } - if ((ParentPagingEntry->Pnle.Bits.ReadWrite =3D=3D 0) && (Mask->Bits.R= eadWrite =3D=3D 1) && (Attribute->Bits.ReadWrite =3D=3D 1)) { if (Modify) { ParentPagingEntry->Pnle.Bits.ReadWrite =3D 1; --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101381): https://edk2.groups.io/g/devel/message/101381 Mute This Topic: https://groups.io/mt/97725694/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 26 15:40:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101382+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101382+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679290467; cv=none; d=zohomail.com; s=zohoarc; b=VQZg2KhRSsS/cf3YNvf6a3TmRiJRCCabFb8d3h2DqAQEY8JOsjqQryd7RXKyrdMomPTs+hnNINA/8hc32NbzbgDXA8e51p3mmXWMC+PWhkYA6oJpMD54/StUwOJ7lLsUhMqq15iw/jLgwCkl+8mvjDchr0t7p6D3RQKqBHD+Gr0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679290467; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=K7v+GOgRSfvGVvlZyZFSwZqr/fQ1XbZxr/lrtYv1B0o=; b=RLlEM69bf4wviXLzUAi90jyiUpSpFaQFezDRwLQY2QiMtXeONClDPij8N2VegZHWf2CCczr+ABqHuyDV/VSb2zdhB2pJmliZrb1LtFoa6r5ASy2r90AZn6n+usov+XU5hvAuO8zDkhpC9u1EDhYa0tAQx3oXO9x80UyilZM/3l4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101382+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679290467426625.8007282181223; Sun, 19 Mar 2023 22:34:27 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id kWe3YY1788612xeYdkWyXq9L; Sun, 19 Mar 2023 22:34:27 -0700 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web11.7469.1679290461311870555 for ; Sun, 19 Mar 2023 22:34:26 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="401155436" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="401155436" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:34:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="770059313" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="770059313" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:34:24 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V3 02/18] UefiCpuPkg/CpuPageTableLib: Add check for input Length Date: Mon, 20 Mar 2023 13:33:13 +0800 Message-Id: <20230320053329.410-3-dun.tan@intel.com> In-Reply-To: <20230320053329.410-1-dun.tan@intel.com> References: <20230320053329.410-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: RNUhNlni8y3XGAHpuTI8mYVbx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679290467; bh=Kj6Nf561/+AkqDsrYoP9TVfO3XYmqTbhCqjvs92/RAA=; h=Cc:Date:From:Reply-To:Subject:To; b=woqEBNzwMsc3DcWElUiTPiG6FsjAjnx//ST2YMcPW0YAXq4oFqjKlXAdhjDol2z4PII Xccs44ijxlt3JTr9WFUlY+N3lSgpOq0OusxDUdBHo8v5waqZ4hFcGGltDSXG9x+EPuzHc K99N7z+QyOMYF/ec7RoqgBYSkBUKckVIJXI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679290468419100009 Content-Type: text/plain; charset="utf-8" Add check for input Length in PageTableMap (). Return RETURN_SUCCESS when input Length is 0. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Include/Library/CpuPageTableLib.h | 4 ++-- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 6 +++++- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/UefiCpuPkg/Include/Library/CpuPageTableLib.h b/UefiCpuPkg/Incl= ude/Library/CpuPageTableLib.h index 2dc9b7d18e..5f44ece548 100644 --- a/UefiCpuPkg/Include/Library/CpuPageTableLib.h +++ b/UefiCpuPkg/Include/Library/CpuPageTableLib.h @@ -1,7 +1,7 @@ /** @file Public include file for PageTableLib library. =20 - Copyright (c) 2022, Intel Corporation. All rights reserved.
+ Copyright (c) 2022 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -81,7 +81,7 @@ typedef enum { @retval RETURN_BUFFER_TOO_SMALL The buffer is too small for page table= creation/updating. BufferSize is updated to indicate the = expected buffer size. Caller may still get RETURN_BUFFER_TOO= _SMALL with the new BufferSize. - @retval RETURN_SUCCESS PageTable is created/updated successfu= lly. + @retval RETURN_SUCCESS PageTable is created/updated successfu= lly or the input Length is 0. **/ RETURN_STATUS EFIAPI diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 52535e5a8d..218068a3e1 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -544,7 +544,7 @@ PageTableLibMapInLevel ( @retval RETURN_BUFFER_TOO_SMALL The buffer is too small for page table= creation/updating. BufferSize is updated to indicate the = expected buffer size. Caller may still get RETURN_BUFFER_TOO= _SMALL with the new BufferSize. - @retval RETURN_SUCCESS PageTable is created/updated successfu= lly. + @retval RETURN_SUCCESS PageTable is created/updated successfu= lly or the input Length is 0. **/ RETURN_STATUS EFIAPI @@ -567,6 +567,10 @@ PageTableMap ( IA32_PAGE_LEVEL MaxLeafLevel; IA32_MAP_ATTRIBUTE ParentAttribute; =20 + if (Length =3D=3D 0) { + return RETURN_SUCCESS; + } + if ((PagingMode =3D=3D Paging32bit) || (PagingMode =3D=3D PagingPae) || = (PagingMode >=3D PagingModeMax)) { // // 32bit paging is never supported. --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101382): https://edk2.groups.io/g/devel/message/101382 Mute This Topic: https://groups.io/mt/97725695/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 26 15:40:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101383+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101383+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679290476; cv=none; d=zohomail.com; s=zohoarc; b=W1XWwGJmHPtr2Jx42WJDNcbeCoymA9Qcrxo0q2h6Hs1ID7Ac63Bbc0b4k1tke1LazizIOkU4uU9SDP3hMhhUgcuJ/op2oCNHOQKQkxhtoILDb9KyvY1zLKtGYTIU8KCytI3YSWpvvWQkKCuOobgO7USePnhLanxJV8fTljO44U0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679290476; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=HLl42OK0tn1lGSVlSE3UJI5eSqLkxTDkhwjI5VFertc=; b=ZKkA+rKPogz641R/cQJUpjUMHHw0lj7eodeiByyAhfvkMIoVF6hd1CGAKmdp3NtKOP6dVVGVCNIX8d1GOGbHgMhWelnSi1cXHvIfsrYCWtcawfIVFP4W/wvL7RNdYM7YKF1fUbCN4qjO+JuzosMKEW0rqrtcUJM9dKuJG/kG8NU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101383+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679290476076733.0816544839613; Sun, 19 Mar 2023 22:34:36 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id FNP7YY1788612xqkbwl1qOP6; Sun, 19 Mar 2023 22:34:35 -0700 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web11.7471.1679290475232002420 for ; Sun, 19 Mar 2023 22:34:35 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="401155476" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="401155476" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:34:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="770059374" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="770059374" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:34:32 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V3 03/18] UefiCpuPkg/CpuPageTableLib:Initialize some LocalVariable at beginning Date: Mon, 20 Mar 2023 13:33:14 +0800 Message-Id: <20230320053329.410-4-dun.tan@intel.com> In-Reply-To: <20230320053329.410-1-dun.tan@intel.com> References: <20230320053329.410-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: WoFVzCktCnyYe1Lq9K3KfJAMx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679290475; bh=irWOcM91X1GsPHfgMxWEMbR7eGOvbHthK8qwSi0HJxc=; h=Cc:Date:From:Reply-To:Subject:To; b=IATkE+O1iEOVwA3mShyj95uS+zmGCSFzUuVnOnjlm0hfoAJ90XQh/Ov+Z5jwX8fUv2K cCa0FsiBbkwrdtTLyTVtht6Jju/bLf8xesNhXZHr3ozh9red6V9ZVbygbk7/pyBtCgzQr TvjkQOa1eN8edxSyXhIz0A6tLQTN6kifkAQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679290476420100002 Content-Type: text/plain; charset="utf-8" Move some local variable initialization to the beginning of the function. Also delete duplicated calculation for RegionLength. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 20 ++++++++++++----= ---- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 218068a3e1..a6414778a7 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -258,6 +258,7 @@ PageTableLibMapInLevel ( UINTN BitStart; UINTN Index; IA32_PAGING_ENTRY *PagingEntry; + UINTN PagingEntryIndex; IA32_PAGING_ENTRY *CurrentPagingEntry; UINT64 RegionLength; UINT64 SubLength; @@ -288,6 +289,13 @@ PageTableLibMapInLevel ( LocalParentAttribute.Uint64 =3D ParentAttribute->Uint64; ParentAttribute =3D &LocalParentAttribute; =20 + // + // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 << 2= 1) or 4K (1 << 12). + // + BitStart =3D 12 + (Level - 1) * 9; + PagingEntryIndex =3D (UINTN)BitFieldRead64 (LinearAddress + Offset, BitS= tart, BitStart + 9 - 1); + RegionLength =3D REGION_LENGTH (Level); + // // ParentPagingEntry ONLY is deferenced for checking Present and MustBeO= ne bits // when Modify is FALSE. @@ -353,8 +361,7 @@ PageTableLibMapInLevel ( // PageTableLibSetPnle (&ParentPagingEntry->Pnle, &NopAttribute, &AllOn= eMask); =20 - RegionLength =3D REGION_LENGTH (Level); - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BA= SE_ADDRESS (&ParentPagingEntry->Pnle); + PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BAS= E_ADDRESS (&ParentPagingEntry->Pnle); for (SubOffset =3D 0, Index =3D 0; Index < 512; Index++) { PagingEntry[Index].Uint64 =3D OneOfPagingEntry.Uint64 + SubOffset; SubOffset +=3D RegionLength; @@ -425,14 +432,11 @@ PageTableLibMapInLevel ( } =20 // - // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 << 2= 1) or 4K (1 << 12). // RegionStart: points to the linear address that's aligned on RegionLe= ngth and lower than (LinearAddress + Offset). // - BitStart =3D 12 + (Level - 1) * 9; - Index =3D (UINTN)BitFieldRead64 (LinearAddress + Offset, BitStart= , BitStart + 9 - 1); - RegionLength =3D LShiftU64 (1, BitStart); - RegionMask =3D RegionLength - 1; - RegionStart =3D (LinearAddress + Offset) & ~RegionMask; + Index =3D PagingEntryIndex; + RegionMask =3D RegionLength - 1; + RegionStart =3D (LinearAddress + Offset) & ~RegionMask; =20 ParentAttribute->Uint64 =3D PageTableLibGetPnleMapAttribute (&ParentPagi= ngEntry->Pnle, ParentAttribute); =20 --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101383): https://edk2.groups.io/g/devel/message/101383 Mute This Topic: https://groups.io/mt/97725697/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 26 15:40:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101384+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101384+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679290478; cv=none; d=zohomail.com; s=zohoarc; b=K8TVR0QDfm+QbWcvqUqxKrZQLle0uLS2ICNnUVMZsveRPayXBFEAWczh0CP2P6s6Pj6chrgfgWbmOGuwtXIR8jPyTWKfU1lVjjEDgF+x9Ft1sxTk+WRhX6IP2/YHzj6+PeANMkgXh9v/hIZRmGnxNtgcyJYquwmj0nUN+wBdB8o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679290478; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=EhmEUXfPGmwwwCD65n9TehNR9FDCFlNzgQylDAc4A8k=; b=KCZMm+6qoCUQ2gaUcoOHt3r6wiRQAPZ62zHp5jibomBfNs9ADhGTu/X2Puct3nNyUDoKUQUhM/dlvIWYy0XxF6TSNSvpQ0Mgvgo7tI2thto1T+9J7oypAxiYktL5vzKZ+CMyooDrp/Rokjkm1LYFT9CkD/xIb9AcHNORUYna5cY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101384+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679290478197575.8240471134168; Sun, 19 Mar 2023 22:34:38 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id BSEOYY1788612xgglR7yGea9; Sun, 19 Mar 2023 22:34:37 -0700 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web11.7471.1679290475232002420 for ; Sun, 19 Mar 2023 22:34:37 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="401155493" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="401155493" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:34:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="770059386" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="770059386" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:34:35 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V3 04/18] UefiCpuPkg/CpuPageTableLib: Fix the non-1:1 mapping issue Date: Mon, 20 Mar 2023 13:33:15 +0800 Message-Id: <20230320053329.410-5-dun.tan@intel.com> In-Reply-To: <20230320053329.410-1-dun.tan@intel.com> References: <20230320053329.410-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: cfaHltrk7zwKzK8OjQgXdtnEx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679290477; bh=WK4gUs7re1hwuerlaGc/jiCiVdHpU+l0wFz84f9jNK4=; h=Cc:Date:From:Reply-To:Subject:To; b=kf8RwhNyIJLvpnfbNPX18QSmlgwOzezt4DEFoVfKsLnh2nly+QUw7s8wbz+gJ0Uy3PL lnpOEBFbM2DLWJUVyRCwHU3TMfeV34IjjARQgT3ROLs8bQyM6s7kktUjwuy0zHPhOfLC/ dxk8bQti1OzVyvMoUirlTARxyJhcOHacLek= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679290480447100002 Content-Type: text/plain; charset="utf-8" In previous code logic, when splitting a leaf parent entry to smaller granularity child page table, if the parent entry Attribute&Mask(without PageTableBaseAddress field) is equal to the input attribute&mask(without PageTableBaseAddress field), the split process won't happen. This may lead to failure in non-1:1 mapping. For example, there is a page table in which [0, 1G] is mapped(Lv4[0] ,Lv3[0,0], a non-leaf level4 entry and a leaf level3 entry). And we want to remap [0, 2M] linear address range to [1G, 1G + 2M] with the same attibute. The expected behaviour should be: split Lv3[0,0] entry into 512 level2 entries and remap the first level2 entry to cover [0, 2M]. But the split won't happen in previous code since PageTableBaseAddress of input Attribute is not checked. So, when checking if a leaf parent entry needs to be splitted, we should also check if PageTableBaseAddress calculated by parent entry is equal to the value caculated by input attribute. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index a6414778a7..1f17d8a6d4 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -333,8 +333,11 @@ PageTableLibMapInLevel ( // the actual attributes of grand-parents when determing the memory ty= pe. // PleBAttribute.Uint64 =3D PageTableLibGetPleBMapAttribute (&ParentPagin= gEntry->PleB, ParentAttribute); - if ((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRIBU= TE_ATTRIBUTES (Mask)) - =3D=3D (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATTRI= BUTE_ATTRIBUTES (Mask))) + if ((((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRI= BUTE_ATTRIBUTES (Mask)) + =3D=3D (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATT= RIBUTE_ATTRIBUTES (Mask)))) && + ( (Mask->Bits.PageTableBaseAddress =3D=3D 0) + || ((IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&PleBAttribute) += PagingEntryIndex * RegionLength) + =3D=3D (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute)= + Offset)))) { // // This function is called when the memory length is less than the r= egion length of the parent level. --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101384): https://edk2.groups.io/g/devel/message/101384 Mute This Topic: https://groups.io/mt/97725698/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 26 15:40:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101385+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101385+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679290480; cv=none; d=zohomail.com; s=zohoarc; b=D9Rhe2MbiDl3/Kby+zxPUCMmy+NHdP+Fg49AojTPC1ZKxkUfm32FXj4YuQyvmKCbgmBgWGaincWRlpJOgEu9MpSpg73r54kThF8CNOOj6zb2YuhS7uhPnY4gw4lmhOUSHy6NgOKsVk5F1KvZ6CCmw6zsjOKYlrotsocoNuY7pkY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679290480; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=WIrI20dUMKzNS/ygN/EESTklIa6JUlHe1YjGYaMwwGs=; b=katjVG2efAzU9gHlJtwerhuPNUq3K0UK8Qrkz2uj8x+oUU6adHMF7ty+WKACliB7dEaDlXrRtXQyU6ZgY+pAMBI5b0lfZusQwnw7+NQ21ddD0HRd46gXgxOz6r8ETcpgaKRYhgt7p1QPiY4QIW0JsGPyxgPaTP6BBgjgF8mm6I4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101385+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679290480488861.5663615313332; Sun, 19 Mar 2023 22:34:40 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 4lpwYY1788612xCZa36xFib9; Sun, 19 Mar 2023 22:34:40 -0700 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web11.7471.1679290475232002420 for ; Sun, 19 Mar 2023 22:34:39 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="401155505" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="401155505" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:34:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="770059412" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="770059412" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:34:37 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V3 05/18] UefiCpuPkg/CpuPageTableLib:Clear PageSize bit(Bit7) for non-leaf Date: Mon, 20 Mar 2023 13:33:16 +0800 Message-Id: <20230320053329.410-6-dun.tan@intel.com> In-Reply-To: <20230320053329.410-1-dun.tan@intel.com> References: <20230320053329.410-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: aK5xmSmJKPjxoauoi6Imb661x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679290480; bh=VdtlSiXnWeVdugWWNsOLFge53ea0gpJj7cWXF45lEso=; h=Cc:Date:From:Reply-To:Subject:To; b=PK+JPw9jQciRTd2HOgjManT0lYKhXPVLSqdlim2jB2Z3fE6u8JrtEiTa7t7eftWvfIB 4xPg5lgdXpbaZGRa3Vg4HODG1oMqYS9nUyPfv63zf/mBLjUuzkAQBjMgwJElGVjT+hB6B lns4cQntg6Gy4mPJ4ZACbWejNkyyRwsOeLI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679290482441100005 Content-Type: text/plain; charset="utf-8" Clear PageSize bit(Bit7) for non-leaf entry in PageTableLibSetPnle. This function is used to set non-leaf entry attributes so it should make sure that the PageSize bit of the entry should be 0. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 1f17d8a6d4..d623b62401 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -202,7 +202,8 @@ PageTableLibSetPnle ( Pnle->Bits.Nx =3D Attribute->Bits.Nx; } =20 - Pnle->Bits.Accessed =3D 0; + Pnle->Bits.Accessed =3D 0; + Pnle->Bits.MustBeZero =3D 0; =20 // // Set the attributes (WT, CD, A) to 0. --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101385): https://edk2.groups.io/g/devel/message/101385 Mute This Topic: https://groups.io/mt/97725700/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 26 15:40:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101386+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101386+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679290482; cv=none; d=zohomail.com; s=zohoarc; b=FkO5Y+88BRe/JCh52YybxMw6ykW79ZI3c2XjzSX/l7AMcPgGLFgHZtgLoUwMu/8BW0TgDYGED5g78ghIN6z8UvyVdNMFmVR1tJ3FgI1XtLRYAEIGMdN3cocMpLTKuQ0VuiTdBeMbakAOk6/tS6e0zb6lNMeu5UuwZ4hlDgPK7AQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679290482; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=bVRBh2jzMHgqRzfr9QLUQcI/hzBmbFGeHVF9RgVj+iI=; b=bJcTGtr9Nq/LLAlAHe5GFFRtV0Ifxzgzn3BW7Z/2VpsvQrFL60QksgAy2gPIVNUofuyWk56yFJ9mDX6qFuvX0XI0nET1i7K3NQAJAwKdpslgSngMPEtBsaTv34TjSuq/ww09hhRLkA05XtGacoO5BggX1u8ezAUGiQVzX2Cq2fs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101386+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679290482470358.4002464959066; Sun, 19 Mar 2023 22:34:42 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id FdyJYY1788612xhUgiUSjhhL; Sun, 19 Mar 2023 22:34:42 -0700 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web11.7471.1679290475232002420 for ; Sun, 19 Mar 2023 22:34:41 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="401155536" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="401155536" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:34:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="770059433" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="770059433" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:34:39 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V3 06/18] UefiCpuPkg/CpuPageTableLib: Fix issue when splitting leaf entry Date: Mon, 20 Mar 2023 13:33:17 +0800 Message-Id: <20230320053329.410-7-dun.tan@intel.com> In-Reply-To: <20230320053329.410-1-dun.tan@intel.com> References: <20230320053329.410-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: v9dQqN4iFF5hpIsHcoJ0Munax1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679290482; bh=9gkAkTP5YDaH3z6DRg0JSEGiM5SYuy3L5WMvXva28T4=; h=Cc:Date:From:Reply-To:Subject:To; b=sUDDusaZ18liocLnWzhsh6mqBsSgEfJhylYZNL6J+qmq9dU0bAevJeiYfqpmtbReNsv 7zBnpjRrAryXnljGgdKTrm32QXPoaYGK8FVlEzSK3eMMNrjLG39Qx1sS5Ub8vaBraXSKw iqEV1dg+XZ/JZ9N9zCXm6JGyAWxM0j+TFIk= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679290484472100009 Content-Type: text/plain; charset="utf-8" When splitting leaf parent entry to smaller granularity, create child page table before modifing parent entry. In previous code logic, when splitting a leaf parent entry, parent entry will point to a null 4k memory before child page table is created in this 4k memory. When the page table to be modified is the page table in CR3, if the executed CpuPageTableLib code is in the range mapped by the modified leaf parent entry, then issue will happen. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index d623b62401..1fc696f572 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -355,8 +355,13 @@ PageTableLibMapInLevel ( // // Create 512 child-level entries that map to 2M/4K. // - ParentPagingEntry->Uintn =3D (UINTN)Buffer + *BufferSize; - ZeroMem ((VOID *)ParentPagingEntry->Uintn, SIZE_4KB); + PagingEntry =3D (IA32_PAGING_ENTRY *)((UINTN)Buffer + *BufferSize); + ZeroMem (PagingEntry, SIZE_4KB); + + for (SubOffset =3D 0, Index =3D 0; Index < 512; Index++) { + PagingEntry[Index].Uint64 =3D OneOfPagingEntry.Uint64 + SubOffset; + SubOffset +=3D RegionLength; + } =20 // // Set NOP attributes @@ -364,12 +369,7 @@ PageTableLibMapInLevel ( // will make the entire region read-only even the child entrie= s set the RW bit. // PageTableLibSetPnle (&ParentPagingEntry->Pnle, &NopAttribute, &AllOn= eMask); - - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BAS= E_ADDRESS (&ParentPagingEntry->Pnle); - for (SubOffset =3D 0, Index =3D 0; Index < 512; Index++) { - PagingEntry[Index].Uint64 =3D OneOfPagingEntry.Uint64 + SubOffset; - SubOffset +=3D RegionLength; - } + ParentPagingEntry->Uint64 =3D ((UINTN)(VOID *)PagingEntry) | (Parent= PagingEntry->Uint64 & (~IA32_PE_BASE_ADDRESS_MASK_40)); } } else { // --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101386): https://edk2.groups.io/g/devel/message/101386 Mute This Topic: https://groups.io/mt/97725701/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 26 15:40:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101387+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101387+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679290485; cv=none; d=zohomail.com; s=zohoarc; b=jJvTdVNICRqWoD1PAZuu18rD4UdCE+1Gmg/wgjH88gKMK0/azQzTHHH8e9gIe3XZtX0O4io3rd6hbcj9/lqWZLpQZ1BpT9LXiSi6I6KGExUb5xI2WXcCfAy6MljZKShVmXeQPi4jWBouAWnB3/LaWgQo6S+H6BGLlpfCTrYcP6Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679290485; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=INU1gfCsjiolttfT/sLxAL+ymm2XpePE5UAMaEhK+3o=; b=FyYN1mLMugn6ZYPVtH7avri02c2ZBq1JVuQJEuEQf6g62sVRy97eYDN+Bx1SzU3Y4RGo0Cd3mS5Sjnx8LojoJpYlk+iYjoWEmtEu2bJ8xrdovfRCYnxA83WsThiJDtOYLonmq70+6UujmfkZAH0hwBqLMa7epkmfqoJHZ54TR68= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101387+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679290485112731.9837283771371; Sun, 19 Mar 2023 22:34:45 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id LvG4YY1788612xGWA1jqbxN7; Sun, 19 Mar 2023 22:34:44 -0700 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web11.7471.1679290475232002420 for ; Sun, 19 Mar 2023 22:34:44 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="401155570" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="401155570" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:34:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="770059463" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="770059463" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:34:42 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V3 07/18] UefiCpuPkg/CpuPageTableLib:Add check for Mask and Attr Date: Mon, 20 Mar 2023 13:33:18 +0800 Message-Id: <20230320053329.410-8-dun.tan@intel.com> In-Reply-To: <20230320053329.410-1-dun.tan@intel.com> References: <20230320053329.410-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: Tref5od5Dhp6OB9LRXlWRy0rx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679290484; bh=8tfKAW9bUBXWbqahMkv3FI1srdxo82ppDGSf6QlKOHo=; h=Cc:Date:From:Reply-To:Subject:To; b=lpHejuJBQxRnY3o23alUZ+0XnEFaK1DQ16qEOVx+ZP12LfRNIcYSS6ho8KYr4VjAzsa TSGvtXJcvGwFO54XRFnvxAN/pQNBPL/B6/gax00fCEUVl3bnGasvQRGcf5aQ7hv4/AJFx uJDsffGIAhDgQYzQpHDMQSjSAm6b6S/fUqg= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679290486490100013 Content-Type: text/plain; charset="utf-8" For different usage, check if the combination for Mask and Attr is valid when creating or updating page table. 1.For non-present range 1.1Mask.Present is 0 but some other attributes is provided. This case is invalid. 1.2Mask.Present is 1 and Attr.Present is 0. In this case,all other attributes should not be provided. 1.3Mask.Present is 1 and Attr.Present is 1. In this case,all attributes should be provided to intialize the attribute. 2.For present range 2.1Mask.Present is 1 and Attr.Present is 0.In this case, all other attributes should not be provided. All other usage for present range is permitted. In the mentioned cases, 1.2 and 2.1 can be merged into 1 check. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Include/Library/CpuPageTableLib.h | 2 +- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 79 ++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 78 insertions(+), 3 deletions(-) diff --git a/UefiCpuPkg/Include/Library/CpuPageTableLib.h b/UefiCpuPkg/Incl= ude/Library/CpuPageTableLib.h index 5f44ece548..6bda15b5bc 100644 --- a/UefiCpuPkg/Include/Library/CpuPageTableLib.h +++ b/UefiCpuPkg/Include/Library/CpuPageTableLib.h @@ -76,7 +76,7 @@ typedef enum { @param[in] Mask The mask used for attribute. The correspo= nding field in Attribute is ignored if that in Mask is 0. =20 @retval RETURN_UNSUPPORTED PagingMode is not supported. - @retval RETURN_INVALID_PARAMETER PageTable, BufferSize, Attribute or Ma= sk is NULL. + @retval RETURN_INVALID_PARAMETER PageTable, BufferSize, Attribute or Ma= sk is NULL or the combination of Attribute and Mask is invalid. @retval RETURN_INVALID_PARAMETER *BufferSize is not multiple of 4KB. @retval RETURN_BUFFER_TOO_SMALL The buffer is too small for page table= creation/updating. BufferSize is updated to indicate the = expected buffer size. diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 1fc696f572..925dd90f23 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -215,6 +215,43 @@ PageTableLibSetPnle ( Pnle->Bits.CacheDisabled =3D 0; } =20 +/** + Check if the combination for Attribute and Mask is valid for non-present= entry. + 1.Mask.Present is 0 but some other attributes is provided. This case sho= uld be invalid. + 2.Map non-present range to present. In this case, all attributes should = be provided. + + @param[in] Attribute The attribute of the linear address range. + @param[in] Mask The mask used for attribute to check. + + @retval RETURN_INVALID_PARAMETER The combination for Attribute and Ma= sk is invalid. + @retval RETURN_SUCCESS The combination for Attribute and Ma= sk is valid. +**/ +RETURN_STATUS +IsAttributesAndMaskValidForNonPresentEntry ( + IN IA32_MAP_ATTRIBUTE *Attribute, + IN IA32_MAP_ATTRIBUTE *Mask + ) +{ + if ((Mask->Bits.Present =3D=3D 1) && (Attribute->Bits.Present =3D=3D 1))= { + // + // Creating new page table or remapping non-present range to present. + // + if ((Mask->Bits.ReadWrite =3D=3D 0) || (Mask->Bits.UserSupervisor =3D= =3D 0) || (Mask->Bits.WriteThrough =3D=3D 0) || (Mask->Bits.CacheDisabled = =3D=3D 0) || + (Mask->Bits.Accessed =3D=3D 0) || (Mask->Bits.Dirty =3D=3D 0) || (= Mask->Bits.Pat =3D=3D 0) || (Mask->Bits.Global =3D=3D 0) || + (Mask->Bits.PageTableBaseAddress =3D=3D 0) || (Mask->Bits.Protecti= onKey =3D=3D 0) || (Mask->Bits.Nx =3D=3D 0)) + { + return RETURN_INVALID_PARAMETER; + } + } else if ((Mask->Bits.Present =3D=3D 0) && (Mask->Uint64 > 1)) { + // + // Only change other attributes for non-present range is not permitted. + // + return RETURN_INVALID_PARAMETER; + } + + return RETURN_SUCCESS; +} + /** Update page table to map [LinearAddress, LinearAddress + Length) with sp= ecified attribute in the specified level. =20 @@ -237,6 +274,7 @@ PageTableLibSetPnle ( when a new physical base address is se= t. @param[in] Mask The mask used for attribute. The corre= sponding field in Attribute is ignored if that in Mask is 0. =20 + @retval RETURN_INVALID_PARAMETER The combination of Attribute and Mask = for non-present entry is invalid. @retval RETURN_SUCCESS PageTable is created/updated successfu= lly. **/ RETURN_STATUS @@ -260,6 +298,7 @@ PageTableLibMapInLevel ( UINTN Index; IA32_PAGING_ENTRY *PagingEntry; UINTN PagingEntryIndex; + UINTN PagingEntryIndexEnd; IA32_PAGING_ENTRY *CurrentPagingEntry; UINT64 RegionLength; UINT64 SubLength; @@ -303,6 +342,14 @@ PageTableLibMapInLevel ( // =20 if (ParentPagingEntry->Pce.Present =3D=3D 0) { + // + // [LinearAddress, LinearAddress + Length] contains non-present range. + // + Status =3D IsAttributesAndMaskValidForNonPresentEntry (Attribute, Mask= ); + if (RETURN_ERROR (Status)) { + return Status; + } + // // The parent entry is CR3 or PML5E/PML4E/PDPTE/PDE. // It does NOT point to an existing page directory. @@ -372,6 +419,27 @@ PageTableLibMapInLevel ( ParentPagingEntry->Uint64 =3D ((UINTN)(VOID *)PagingEntry) | (Parent= PagingEntry->Uint64 & (~IA32_PE_BASE_ADDRESS_MASK_40)); } } else { + // + // If (LinearAddress + Length - 1) is not in the same ParentPagingEntr= y with (LinearAddress + Offset), then the remaining child PagingEntry + // starting from PagingEntryIndex of ParentPagingEntry is all covered = by [LinearAddress + Offset, LinearAddress + Length - 1]. + // + PagingEntryIndexEnd =3D (BitFieldRead64 (LinearAddress + Length - 1, B= itStart + 9, 63) !=3D BitFieldRead64 (LinearAddress + Offset, BitStart + 9,= 63)) ? 511 : + (UINTN)BitFieldRead64 (LinearAddress + Length - = 1, BitStart, BitStart + 9 - 1); + PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_= ADDRESS (&ParentPagingEntry->Pnle); + for (Index =3D PagingEntryIndex; Index <=3D PagingEntryIndexEnd; Index= ++) { + if (PagingEntry[Index].Pce.Present =3D=3D 0) { + // + // [LinearAddress, LinearAddress + Length] contains non-present ra= nge. + // + Status =3D IsAttributesAndMaskValidForNonPresentEntry (Attribute, = Mask); + if (RETURN_ERROR (Status)) { + return Status; + } + + break; + } + } + // // It's a non-leaf entry // @@ -419,7 +487,6 @@ PageTableLibMapInLevel ( // Update child entries to use restrictive attribute inherited fro= m parent. // e.g.: Set PDE[0-255].ReadWrite =3D 0 // - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_B= ASE_ADDRESS (&ParentPagingEntry->Pnle); for (Index =3D 0; Index < 512; Index++) { if (PagingEntry[Index].Pce.Present =3D=3D 0) { continue; @@ -547,7 +614,7 @@ PageTableLibMapInLevel ( @param[in] Mask The mask used for attribute. The correspo= nding field in Attribute is ignored if that in Mask is 0. =20 @retval RETURN_UNSUPPORTED PagingMode is not supported. - @retval RETURN_INVALID_PARAMETER PageTable, BufferSize, Attribute or Ma= sk is NULL. + @retval RETURN_INVALID_PARAMETER PageTable, BufferSize, Attribute or Ma= sk is NULL or the combination of Attribute and Mask is invalid. @retval RETURN_INVALID_PARAMETER *BufferSize is not multiple of 4KB. @retval RETURN_BUFFER_TOO_SMALL The buffer is too small for page table= creation/updating. BufferSize is updated to indicate the = expected buffer size. @@ -609,6 +676,14 @@ PageTableMap ( return RETURN_INVALID_PARAMETER; } =20 + // + // If to map [LinearAddress, LinearAddress + Length] as non-present, + // all attributes except Present should not be provided. + // + if ((Attribute->Bits.Present =3D=3D 0) && (Mask->Bits.Present =3D=3D 1) = && (Mask->Uint64 > 1)) { + return RETURN_INVALID_PARAMETER; + } + MaxLeafLevel =3D (IA32_PAGE_LEVEL)(UINT8)PagingMode; MaxLevel =3D (IA32_PAGE_LEVEL)(UINT8)(PagingMode >> 8); MaxLinearAddress =3D LShiftU64 (1, 12 + MaxLevel * 9); --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101387): https://edk2.groups.io/g/devel/message/101387 Mute This Topic: https://groups.io/mt/97725704/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 26 15:40:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101388+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101388+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679290487; cv=none; d=zohomail.com; s=zohoarc; b=n8o9F4XZ1XF5DcZjTMG8920Dxc5LwlJf9IEq8oPbhkcTgnTW44BZdSph2I3DofP2LzSAJvHglsJceGqRt76Jmu1YosL4SQbCeLp12zDzDsrCHzY2LktXHlKP9qiv2Ku5Ed8NpYBxP/finjqxkoOTLnOplVRWlq5aKGkZffDcTxg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679290487; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=G1keZ0rO8PhMGSp9Dkq6P/bmcXf1n8s0RiJAm3Ysoh8=; b=LDFWdIDVc6w5irIBT3Gfu/RWFb7ER3Ek220ILVp2/8PLgobyk9jJ+cue8HSUq5YpM02niHIvkgnraIpnOAJy5se7Cf4uXn3y6OHY2VqmZ5VEXD+W++oKvV4jJSAVDEfJJH9R3DAx3OuPZZKxbfhD+RFJNrcandZOAIYWkaNARHY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101388+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679290487379127.21607707819805; Sun, 19 Mar 2023 22:34:47 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id hd8HYY1788612xrquzprEdQg; Sun, 19 Mar 2023 22:34:47 -0700 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web11.7471.1679290475232002420 for ; Sun, 19 Mar 2023 22:34:46 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="401155585" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="401155585" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:34:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="770059491" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="770059491" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:34:44 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V3 08/18] UefiCpuPkg/CpuPageTableLib: Add manual test to check Mask and Attr Date: Mon, 20 Mar 2023 13:33:19 +0800 Message-Id: <20230320053329.410-9-dun.tan@intel.com> In-Reply-To: <20230320053329.410-1-dun.tan@intel.com> References: <20230320053329.410-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: f0C3fMN1ngfxdWHuHkNiQC31x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679290487; bh=nKF6ZMCYyF6T40ERaMISOBiLBo/H72y8102WtWekpRQ=; h=Cc:Date:From:Reply-To:Subject:To; b=NrskMY1XjJH/fJhgvKV6Yd5OPVFFB5mEMfJbaSXpy2whr4hhjKcuU5zmRgp4vF3yATc IVLE4BZbP+jS7/JpxKdr/gLAhlds+xkOVaPw4mZ7trmYzMfLar+j+KrajYOyLTns+HQvV b1TDaJ4MiJ5ZSdRT3TdnhFu9Q033+WVp5Ow= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679290488515100018 Content-Type: text/plain; charset="utf-8" Add manual test case to check input Mask and Attribute. The check steps are: 1.Create Page table to cover [0, 2G]. All fields of MapMask should be set. 2.Update Page table to set [2G - 8K,2G] from present to non-present. All fields of MapMask except present should not be set. 3.Still set [2G - 8K, 2G] as not present, this case is permitted. But set [2G - 8K, 2G] as RW is not permitted. 4.Update Page table to set [2G - 8K, 2G] as present and RW. All fields of MapMask should be set. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c = | 129 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 127 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUni= tTestHost.c b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUn= itTestHost.c index 3014a03243..3e84e2ba11 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c @@ -1,7 +1,7 @@ /** @file Unit tests of the CpuPageTableLib instance of the CpuPageTableLib class =20 - Copyright (c) 2022, Intel Corporation. All rights reserved.
+ Copyright (c) 2022 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -697,6 +697,131 @@ TestCaseManualChangeNx ( return UNIT_TEST_PASSED; } =20 +/** + Check if the input Mask and Attribute is as expected when creating new p= age table or + updating existing page table. + + @param[in] Context [Optional] An optional parameter that enables: + 1) test-case reuse with varied parameters and + 2) test-case re-entry for Target tests that need a + reboot. This parameter is a VOID* and it is the + responsibility of the test author to ensure that = the + contents are well understood by all test cases th= at may + consume it. + + @retval UNIT_TEST_PASSED The Unit test has completed and th= e test + case was successful. + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. +**/ +UNIT_TEST_STATUS +EFIAPI +TestCaseToCheckMapMaskAndAttr ( + IN UNIT_TEST_CONTEXT Context + ) +{ + UINTN PageTable; + PAGING_MODE PagingMode; + VOID *Buffer; + UINTN PageTableBufferSize; + IA32_MAP_ATTRIBUTE MapAttribute; + IA32_MAP_ATTRIBUTE ExpectedMapAttribute; + IA32_MAP_ATTRIBUTE MapMask; + RETURN_STATUS Status; + IA32_MAP_ENTRY *Map; + UINTN MapCount; + + PagingMode =3D Paging4Level; + PageTableBufferSize =3D 0; + PageTable =3D 0; + Buffer =3D NULL; + MapAttribute.Uint64 =3D 0; + MapAttribute.Bits.Present =3D 1; + MapMask.Uint64 =3D 0; + MapMask.Bits.Present =3D 1; + // + // Create Page table to cover [0, 2G]. All fields of MapMask should be s= et. + // + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); + MapMask.Uint64 =3D MAX_UINT64; + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTa= bleBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); + Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); + + // + // Update Page table to set [2G - 8K, 2G] from present to non-present. A= ll fields of MapMask except present should be set. + // + PageTableBufferSize =3D 0; + MapAttribute.Uint64 =3D SIZE_2GB - SIZE_8KB; + MapMask.Uint64 =3D 0; + MapMask.Bits.Present =3D 1; + MapMask.Bits.ReadWrite =3D 1; + Status =3D PageTableMap (&PageTable, PagingMode, Buffer,= &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMa= sk); + UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); + MapMask.Bits.ReadWrite =3D 0; + Status =3D PageTableMap (&PageTable, PagingMode, Buffer,= &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMa= sk); + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); + Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); + + // + // Still set [2G - 8K, 2G] as not present, this case is permitted. But s= et [2G - 8K, 2G] as RW is not permitted. + // + PageTableBufferSize =3D 0; + MapAttribute.Uint64 =3D 0; + MapMask.Uint64 =3D 0; + MapMask.Bits.Present =3D 1; + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &= PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMask= ); + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); + MapAttribute.Bits.ReadWrite =3D 1; + MapMask.Bits.ReadWrite =3D 1; + Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &= MapMask); + UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); + + // + // Update Page table to set [2G - 8K, 2G] as present and RW. All fields = of MapMask should not be set. + // + PageTableBufferSize =3D 0; + MapAttribute.Uint64 =3D SIZE_2GB - SIZE_8KB; + MapAttribute.Bits.ReadWrite =3D 1; + MapAttribute.Bits.Present =3D 1; + MapMask.Uint64 =3D 0; + MapMask.Bits.ReadWrite =3D 1; + MapMask.Bits.Present =3D 1; + Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &= MapMask); + UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); + MapMask.Uint64 =3D MAX_UINT64; + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTa= bleBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMask); + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); + + MapCount =3D 0; + Status =3D PageTableParse (PageTable, PagingMode, NULL, &MapCount); + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); + Map =3D AllocatePages (EFI_SIZE_TO_PAGES (MapCount* sizeof (IA32_MAP_= ENTRY))); + Status =3D PageTableParse (PageTable, PagingMode, Map, &MapCount); + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); + + // + // There should be two ranges [0, 2G-8k] with RW =3D 0 and [2G-8k, 2G] w= ith RW =3D 1 + // + UT_ASSERT_EQUAL (MapCount, 2); + UT_ASSERT_EQUAL (Map[0].LinearAddress, 0); + UT_ASSERT_EQUAL (Map[0].Length, SIZE_2GB - SIZE_8KB); + ExpectedMapAttribute.Uint64 =3D 0; + ExpectedMapAttribute.Bits.Present =3D 1; + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, ExpectedMapAttribute.Uint64); + UT_ASSERT_EQUAL (Map[1].LinearAddress, SIZE_2GB - SIZE_8KB); + UT_ASSERT_EQUAL (Map[1].Length, SIZE_8KB); + ExpectedMapAttribute.Uint64 =3D SIZE_2GB - SIZE_8KB; + ExpectedMapAttribute.Bits.Present =3D 1; + ExpectedMapAttribute.Bits.ReadWrite =3D 1; + UT_ASSERT_EQUAL (Map[1].Attribute.Uint64, ExpectedMapAttribute.Uint64); + return UNIT_TEST_PASSED; +} + /** Initialize the unit test framework, suite, and unit tests for the sample unit tests and run the unit tests. @@ -746,7 +871,7 @@ UefiTestMain ( AddTestCase (ManualTestCase, "Check if the parent entry has different Re= adWrite attribute", "Manual Test Case5", TestCaseManualChangeReadWrite, NUL= L, NULL, NULL); AddTestCase (ManualTestCase, "Check if the parent entry has different Nx= attribute", "Manual Test Case6", TestCaseManualChangeNx, NULL, NULL, NULL); AddTestCase (ManualTestCase, "Check if the needed size is expected", "Ma= nual Test Case7", TestCaseManualSizeNotMatch, NULL, NULL, NULL); - + AddTestCase (ManualTestCase, "Check MapMask when creating new page table= or mapping not-present range", "Manual Test Case8", TestCaseToCheckMapMask= AndAttr, NULL, NULL, NULL); // // Populate the Random Test Cases. // --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101388): https://edk2.groups.io/g/devel/message/101388 Mute This Topic: https://groups.io/mt/97725705/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 26 15:40:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101389+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101389+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679290489; cv=none; d=zohomail.com; s=zohoarc; b=eRY+ljj+QL6kJQyU4qMqSKYftTYoieIWdfeswSyoII5jp1C1t6Tx9PyZv9rWxNrS661M8+ALg2/kieVhh+/RWtpiVHBGzltHtIslmwHhS/g6n8M8NQ9IdGh9jP/xiMNF/arHCYzAhLUY1If9+o/i9R/W8slqmCYBBrfNcivi0No= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679290489; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=+5AFMHuFYIVFsbP4UzRqEFIXBxiLnRthFm/oiJkBaUE=; b=T82U05oTYmsLK6E1yPs1XJy37c6eYokYL+rQjpOorXtDOe2jDBP4UaL3yAd7eleERTgAsJ2JNTfKBCgldM/PDLK7b6FUR19CZ4lDHGisGoxXEVSyPlUohtMhAMuDCk3CjXWSYrRIFDOIFN/IHCuADKNQxVYYJbkhX2gPuZhnpms= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101389+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679290489464833.2007843335443; Sun, 19 Mar 2023 22:34:49 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id imtFYY1788612xceuDdIGp9A; Sun, 19 Mar 2023 22:34:49 -0700 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web11.7471.1679290475232002420 for ; Sun, 19 Mar 2023 22:34:48 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="401155604" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="401155604" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:34:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="770059510" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="770059510" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:34:46 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V3 09/18] UefiCpuPkg/CpuPageTableLib:Modify RandomBoolean() in RandomTest Date: Mon, 20 Mar 2023 13:33:20 +0800 Message-Id: <20230320053329.410-10-dun.tan@intel.com> In-Reply-To: <20230320053329.410-1-dun.tan@intel.com> References: <20230320053329.410-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: BDTmbv6t6fpH1gJAfe9ilaWbx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679290489; bh=5HT0EXDRZwItVwpPdA9RWEf16CDFLhpY/RJjhSF/PYs=; h=Cc:Date:From:Reply-To:Subject:To; b=CkX0AYE2JLqZPNPuRKzykKNt0ibo44ziy39yRLelPTWUiGx68+mmcjuMMArpTZexZxS +l6h3Bt0N4hVxA9YiTdE8/lA1f2wGoCVvw2v3vYJSMURfX5MONEco3Jt2Gtq8OiHZkI/9 2qJH7tXEXFLp0XZHHyeI33nHHOyFo1VwDbk= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679290490486100021 Content-Type: text/plain; charset="utf-8" Add an input parameter to control the probability of returning true. Change RandomBoolean() in RandomTest from 50% chance returning true to returning true with the percentage of input Probability. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c | 43 ++++++++++++= +++++++++---------------------- 1 file changed, 21 insertions(+), 22 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c index 97a388ca1c..52eb9daa10 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c @@ -1,7 +1,7 @@ /** @file Random test case for Unit tests of the CpuPageTableLib instance of the C= puPageTableLib class =20 - Copyright (c) 2022, Intel Corporation. All rights reserved.
+ Copyright (c) 2022 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -81,22 +81,6 @@ LocalRandomBytes ( } } =20 -/** - Return a random boolean. - - @return boolean -**/ -BOOLEAN -RandomBoolean ( - VOID - ) -{ - BOOLEAN Value; - - LocalRandomBytes ((UINT8 *)&Value, sizeof (BOOLEAN)); - return Value%2; -} - /** Return a 32bit random number. =20 @@ -139,6 +123,21 @@ Random64 ( return (UINT64)(Value % (Limit - Start + 1)) + Start; } =20 +/** + Returns true with the percentage of input Probability. + + @param[in] Probability The percentage to return true. + + @return boolean +**/ +BOOLEAN +RandomBoolean ( + UINT8 Probability + ) +{ + return ((Probability > ((UINT8)Random64 (0, 100))) ? TRUE : FALSE); +} + /** Check if the Page table entry is valid =20 @@ -178,7 +177,7 @@ ValidateAndRandomeModifyPageTablePageTableEntry ( UT_ASSERT_EQUAL ((PagingEntry->Uint64 & mValidMaskLeaf[Level].Uint64= ), PagingEntry->Uint64); } =20 - if ((RandomNumber < 100) && RandomBoolean ()) { + if ((RandomNumber < 100) && RandomBoolean (50)) { RandomNumber++; if (Level =3D=3D 1) { TempPhysicalBase =3D PagingEntry->Pte4K.Bits.PageTableBaseAddress; @@ -211,7 +210,7 @@ ValidateAndRandomeModifyPageTablePageTableEntry ( UT_ASSERT_EQUAL ((PagingEntry->Uint64 & mValidMaskNoLeaf[Level].Uint64= ), PagingEntry->Uint64); } =20 - if ((RandomNumber < 100) && RandomBoolean ()) { + if ((RandomNumber < 100) && RandomBoolean (50)) { RandomNumber++; TempPhysicalBase =3D PagingEntry->Pnle.Bits.PageTableBaseAddress; =20 @@ -299,7 +298,7 @@ GenerateSingleRandomMapEntry ( // // use AlignedTable to avoid that a random number can be very hard to be= 1G or 2M aligned // - if ((MapsIndex !=3D 0) && (RandomBoolean ())) { + if ((MapsIndex !=3D 0) && (RandomBoolean (50))) { FormerLinearAddress =3D MapEntrys->Maps[Random32 (0, (UINT32)MapsIndex= -1)].LinearAddress; if (FormerLinearAddress < 2 * (UINT64)SIZE_1GB) { FormerLinearAddressBottom =3D 0; @@ -323,7 +322,7 @@ GenerateSingleRandomMapEntry ( // MapEntrys->Maps[MapsIndex].Length =3D Random64 (0, MIN (MaxAddress - Map= Entrys->Maps[MapsIndex].LinearAddress, 10 * (UINT64)SIZE_1GB)) & AlignedTab= le[Random32 (0, ARRAY_SIZE (AlignedTable) -1)]; =20 - if ((MapsIndex !=3D 0) && (RandomBoolean ())) { + if ((MapsIndex !=3D 0) && (RandomBoolean (50))) { MapEntrys->Maps[MapsIndex].Attribute.Uint64 =3D MapEntrys->Maps[Random= 32 (0, (UINT32)MapsIndex-1)].Attribute.Uint64; MapEntrys->Maps[MapsIndex].Mask.Uint64 =3D MapEntrys->Maps[Random= 32 (0, (UINT32)MapsIndex-1)].Mask.Uint64; } else { @@ -344,7 +343,7 @@ GenerateSingleRandomMapEntry ( // Need to avoid such case when remove the Random option ONLY_ON= E_ONE_MAPPING // MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress =3D (Ra= ndom64 (0, (((UINT64)1)<<52) - 1) & AlignedTable[Random32 (0, ARRAY_SIZE (A= lignedTable) -1)])>> 12; - if (RandomBoolean ()) { + if (RandomBoolean (50)) { MapEntrys->Maps[MapsIndex].Mask.Bits.PageTableBaseAddress =3D 0; } } --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101389): https://edk2.groups.io/g/devel/message/101389 Mute This Topic: https://groups.io/mt/97725706/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 26 15:40:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101390+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101390+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679290492; cv=none; d=zohomail.com; s=zohoarc; b=QkZmCHjyrBB5qaGLtj1V/qnl7Q6yP2KOXBDbdjxV+uOXFIyPIvoRg3g63HDIYsxwDYd0Q00YfpFr380gcp2GGxEbO7mGJFNv+NvLKV5a5a0h6SjXe2PPwZllo+ULXgxidCwl5ZUJOkPplLb7GwK+mCnGegXY9qWScoZDUmxkALc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679290492; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=GFLshngNI345rb9eYJ2mlwQQEvqDsWlvvBwk7XaFpqk=; b=CPZFAG+FPiIWautZONImRZMD18Mz2SDSf7EBhaDpwYK2DMLHjMvjQxsdr0Zk7FT/P6yLaHui/WP5in4053FrKEWkX1zYuUcn3JB5iJDvP6huEQiGSOYdry90lZg87Prb1MMgXjUNMBadRN2e7UCc4BMROH6d8WtPkXIce6zykaM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101390+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679290492223181.8366945317241; Sun, 19 Mar 2023 22:34:52 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id QWpWYY1788612x3gFM5Awhpn; Sun, 19 Mar 2023 22:34:51 -0700 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web11.7471.1679290475232002420 for ; Sun, 19 Mar 2023 22:34:51 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="401155621" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="401155621" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:34:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="770059536" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="770059536" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:34:49 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann , Zhiguang Liu Subject: [edk2-devel] [Patch V3 10/18] UefiCpuPkg/CpuPageTableLib:Modify RandomTest to check Mask/Attr Date: Mon, 20 Mar 2023 13:33:21 +0800 Message-Id: <20230320053329.410-11-dun.tan@intel.com> In-Reply-To: <20230320053329.410-1-dun.tan@intel.com> References: <20230320053329.410-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: 3tNpCPcHCyvF9Qy4YO95U9bpx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679290491; bh=yM4ECEpSXRiPZrZlobgwfoaSYf/3YRbZDJ4Ew5gQNJY=; h=Cc:Date:From:Reply-To:Subject:To; b=u3jZ2asAXYHGLJwQihq3KE63o3NqHwJU80qIH5+sbXApXpMzpxC51vB3lurDHsZMvIf e58g4FMDZ/4CXaUxopWdb9fr7Yk7AR8TNqUXdWNagFdx3GfhbrDDNc3YYgaMc4jhmQ93+ 7Rrc/xrdnM4kqQj16iKbW1nkBS6kGbFyGSE= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679290494576100003 Content-Type: text/plain; charset="utf-8" Modify RandomTest to check invalid input. When creating new page table or updating exsiting page table: 1.If set [LinearAddress, LinearAddress+Length] to non-preset, all other attributes should not be provided. 2.If [LinearAddress, LinearAddress+Length] contain non-present range, the Returnstatus of PageTableMap() should be InvalidParameter when: 2.1Some of attributes are not provided when mapping non-present range to present. 2.2Set any other attribute without setting the non-present range to Present. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Zhiguang Liu --- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c | 149 +++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++------------------------ UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c | 6 +++++- 2 files changed, 130 insertions(+), 25 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c index 52eb9daa10..eb621e6e59 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c @@ -273,6 +273,27 @@ ValidateAndRandomeModifyPageTable ( return Status; } =20 +/** + Remove the last MAP_ENTRY in MapEntrys. + + @param MapEntrys Pointer to MapEntrys buffer +**/ +VOID +RemoveLastMapEntry ( + IN OUT MAP_ENTRYS *MapEntrys + ) +{ + UINTN MapsIndex; + + if (MapEntrys->Count =3D=3D 0) { + return; + } + + MapsIndex =3D MapEntrys->Count - 1; + ZeroMem (&(MapEntrys->Maps[MapsIndex]), sizeof (MAP_ENTRY)); + MapEntrys->Count =3D MapsIndex; +} + /** Generate single random map entry. The map entry can be the input of function PageTableMap @@ -327,7 +348,16 @@ GenerateSingleRandomMapEntry ( MapEntrys->Maps[MapsIndex].Mask.Uint64 =3D MapEntrys->Maps[Random= 32 (0, (UINT32)MapsIndex-1)].Mask.Uint64; } else { MapEntrys->Maps[MapsIndex].Attribute.Uint64 =3D Random64 (0, MAX_UINT6= 4) & mSupportedBit.Uint64; - MapEntrys->Maps[MapsIndex].Mask.Uint64 =3D Random64 (0, MAX_UINT6= 4) & mSupportedBit.Uint64; + if (RandomBoolean (5)) { + // + // The probability to get random Mask should be small since all bits= of a random number + // have a high probability of containing 0, which may be a invalid i= nput. + // + MapEntrys->Maps[MapsIndex].Mask.Uint64 =3D Random64 (0, MAX_UINT64) = & mSupportedBit.Uint64; + } else { + MapEntrys->Maps[MapsIndex].Mask.Uint64 =3D MAX_UINT64; + } + if (MapEntrys->Maps[MapsIndex].Mask.Bits.ProtectionKey !=3D 0) { MapEntrys->Maps[MapsIndex].Mask.Bits.ProtectionKey =3D 0xF; } @@ -337,15 +367,7 @@ GenerateSingleRandomMapEntry ( MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress =3D Map= Entrys->Maps[MapsIndex].LinearAddress >> 12; MapEntrys->Maps[MapsIndex].Mask.Bits.PageTableBaseAddress =3D 0xF= FFFFFFFFF; } else { - // - // Todo: If the mask bit for base address is zero, when dump the paget= able, every entry mapping to physical address zeor. - // This means the map count will be a large number, and impossib= le to finish in proper time. - // Need to avoid such case when remove the Random option ONLY_ON= E_ONE_MAPPING - // MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress =3D (Ra= ndom64 (0, (((UINT64)1)<<52) - 1) & AlignedTable[Random32 (0, ARRAY_SIZE (A= lignedTable) -1)])>> 12; - if (RandomBoolean (50)) { - MapEntrys->Maps[MapsIndex].Mask.Bits.PageTableBaseAddress =3D 0; - } } =20 MapEntrys->Count +=3D 1; @@ -608,23 +630,61 @@ SingleMapEntryTest ( IN UINTN InitMapCount ) { - UINTN MapsIndex; - RETURN_STATUS Status; - UINTN PageTableBufferSize; - VOID *Buffer; - IA32_MAP_ENTRY *Map; - UINTN MapCount; - UINTN Index; - UINTN KeyPointCount; - UINTN NewKeyPointCount; - UINT64 *KeyPointBuffer; - UINTN Level; - UINT64 Value; - UNIT_TEST_STATUS TestStatus; - - MapsIndex =3D MapEntrys->Count; + UINTN MapsIndex; + RETURN_STATUS Status; + UINTN PageTableBufferSize; + VOID *Buffer; + IA32_MAP_ENTRY *Map; + UINTN MapCount; + UINTN Index; + UINTN KeyPointCount; + UINTN NewKeyPointCount; + UINT64 *KeyPointBuffer; + UINTN Level; + UINT64 Value; + UNIT_TEST_STATUS TestStatus; + IA32_MAP_ATTRIBUTE *Mask; + IA32_MAP_ATTRIBUTE *Attribute; + UINT64 PreviousAddress; + UINT64 RangeLimit; + BOOLEAN IsNotPresent; + + MapsIndex =3D MapEntrys->Count; + MapCount =3D 0; + PreviousAddress =3D 0; + IsNotPresent =3D FALSE; =20 GenerateSingleRandomMapEntry (MaxAddress, MapEntrys); + RangeLimit =3D MapEntrys->Maps[MapsIndex].LinearAddress + MapEntrys->Map= s[MapsIndex].Length; + Status =3D PageTableParse (*PageTable, PagingMode, NULL, &MapCount); + + if (MapCount !=3D 0) { + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); + Map =3D AllocatePages (EFI_SIZE_TO_PAGES (MapCount * sizeof (IA32_MAP_= ENTRY))); + ASSERT (Map !=3D NULL); + Status =3D PageTableParse (*PageTable, PagingMode, Map, &MapCount); + } + + // + // Check if the generated MapEntrys->Maps[MapsIndex] contains not-presen= t range. + // + if (MapEntrys->Maps[MapsIndex].Length > 0) { + for (Index =3D 0; Index < MapCount; Index++) { + if ((PreviousAddress < Map[Index].LinearAddress) && + (MapEntrys->Maps[MapsIndex].LinearAddress < Map[Index].LinearAdd= ress) && (RangeLimit > PreviousAddress)) + { + // + // MapEntrys->Maps[MapsIndex] contains not-present range in exsiti= ng page table. + // + break; + } + PreviousAddress =3D Map[Index].LinearAddress + Map[Index].Length; + } + + if (PreviousAddress < RangeLimit) { + IsNotPresent =3D TRUE; + } + } =20 PageTableBufferSize =3D 0; Status =3D PageTableMap ( @@ -637,6 +697,47 @@ SingleMapEntryTest ( &MapEntrys->Maps[MapsIndex].Attribute, &MapEntrys->Maps[MapsIndex].Mask ); + + Attribute =3D &MapEntrys->Maps[MapsIndex].Attribute; + Mask =3D &MapEntrys->Maps[MapsIndex].Mask; + // + // If set [LinearAddress, LinearAddress+Attribute] to not preset, all + // other attributes should not be provided. + // + if ((MapEntrys->Maps[MapsIndex].Length > 0) && (Attribute->Bits.Present = =3D=3D 0) && (Mask->Bits.Present =3D=3D 1) && (Mask->Uint64 > 1)) { + RemoveLastMapEntry (MapEntrys); + UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); + return UNIT_TEST_PASSED; + } + + // + // Return Status for non-present range also should be InvalidParameter w= hen: + // 1. Some of attributes are not provided when mapping non-present range= to present. + // 2. Set any other attribute without setting the non-present range to P= resent. + // + if (IsNotPresent) { + if ((Mask->Bits.Present =3D=3D 1) && (Attribute->Bits.Present =3D=3D 1= )) { + // + // Creating new page table or remapping non-present range to present. + // + if ((Mask->Bits.ReadWrite =3D=3D 0) || (Mask->Bits.UserSupervisor = =3D=3D 0) || (Mask->Bits.WriteThrough =3D=3D 0) || (Mask->Bits.CacheDisable= d =3D=3D 0) || + (Mask->Bits.Accessed =3D=3D 0) || (Mask->Bits.Dirty =3D=3D 0) ||= (Mask->Bits.Pat =3D=3D 0) || (Mask->Bits.Global =3D=3D 0) || + (Mask->Bits.PageTableBaseAddress =3D=3D 0) || (Mask->Bits.Protec= tionKey =3D=3D 0) || (Mask->Bits.Nx =3D=3D 0)) + { + RemoveLastMapEntry (MapEntrys); + UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); + return UNIT_TEST_PASSED; + } + } else if ((Mask->Bits.Present =3D=3D 0) && (Mask->Uint64 > 1)) { + // + // Only change other attributes for non-present range is not permitt= ed. + // + RemoveLastMapEntry (MapEntrys); + UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); + return UNIT_TEST_PASSED; + } + } + if (PageTableBufferSize !=3D 0) { UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); =20 diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c index 5bd70c0f65..10fdee2f94 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c @@ -1,7 +1,7 @@ /** @file helper file for Unit tests of the CpuPageTableLib instance of the CpuPag= eTableLib class =20 - Copyright (c) 2022, Intel Corporation. All rights reserved.
+ Copyright (c) 2022 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -171,6 +171,10 @@ IsPageTableValid ( UNIT_TEST_STATUS Status; IA32_PAGING_ENTRY *PagingEntry; =20 + if (PageTable =3D=3D 0) { + return UNIT_TEST_PASSED; + } + if ((PagingMode =3D=3D Paging32bit) || (PagingMode =3D=3D PagingPae) || = (PagingMode >=3D PagingModeMax)) { // // 32bit paging is never supported. --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101390): https://edk2.groups.io/g/devel/message/101390 Mute This Topic: https://groups.io/mt/97725707/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 26 15:40:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101391+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101391+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679290494; cv=none; d=zohomail.com; s=zohoarc; b=dzigCrqL0f3RarzuRYcpS1ApB4HyE3VginBoKO3gKPoo/fVIVr5oYIb76FhMXM9DjWCUWPjLPrjTHY3KGZMCcovHC4F0LfE+6pElIZiwJW8l+VoZZORJnjLRf8ie38yCHiAKAIOQb+jaB1IAFGMXBTJfJt6yQz2iJNJHVDEBlNM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679290494; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=wvdAHe8wukmeKGIjmNPWj7Zvdhse2/KDOCLlxdVpbEM=; b=IlqUfszBHvvo8JbyDd4L89pGy3bvmXS5xaRxsHXYj3wHeTOmlLGi3iNzl3VhYA1kFh77z3q5I26y4Lq46dAO8gEfMvThyzwWjPKRqEFdGFfD0V5eTuwY7/qlOihCVTfaA07iUFD07SEUd8e3TIteODzshRxzfX1ktQrT38XCbZ4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101391+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679290494267664.3347404252855; Sun, 19 Mar 2023 22:34:54 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id Evv3YY1788612xlHVIpcWtl5; Sun, 19 Mar 2023 22:34:53 -0700 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web11.7471.1679290475232002420 for ; Sun, 19 Mar 2023 22:34:53 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="401155645" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="401155645" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:34:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="770059552" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="770059552" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:34:51 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V3 11/18] UefiCpuPkg/CpuPageTableLib: Enable non-1:1 mapping in random test Date: Mon, 20 Mar 2023 13:33:22 +0800 Message-Id: <20230320053329.410-12-dun.tan@intel.com> In-Reply-To: <20230320053329.410-1-dun.tan@intel.com> References: <20230320053329.410-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: UCTfIU9pobBQftlb53xouIPtx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679290493; bh=aakfvMXCp34VFu/H8vHwSGF5On1ADFjbpJQYyvswpaM=; h=Cc:Date:From:Reply-To:Subject:To; b=tLI6UoTGXs76Glk0p2qxzMgtfBDf2LLeVMzzoOU8/PxpF8jsI6+GzE9wqXWU/63WAgN hrS62YefKw/no/KB2vvc4FUOQNN9QXp1EQTDqCoOQT+AMBeUuDz6MqGoDaVhYCO7FRmyG mEpIRFpuUDvvbHpI9CWrqnHO+eBTofUSshI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679290496521100007 Content-Type: text/plain; charset="utf-8" Enable non-1:1 mapping in random test. In previous test, non-1:1 test will fail due to the non-1:1 mapping issue in CpuPageTableLib and invalid Input Mask when creating new page table or mapping not-present range. Now these issue have been fixed. Signed-off-by: Dun Tan Cc: Eric Dong Reviewed-by: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c = | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUni= tTestHost.c b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUn= itTestHost.c index 3e84e2ba11..d37cae9fbd 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c @@ -9,10 +9,10 @@ #include "CpuPageTableLibUnitTest.h" =20 // -----------------------------------------------------------------------= PageMode--TestCount-TestRangeCount---RandomOptions -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging4Level = =3D { Paging4Level, 100, 20, ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY }; -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging4Level1GB= =3D { Paging4Level1GB, 100, 20, ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY }; -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging5Level = =3D { Paging5Level, 100, 20, ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY }; -static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging5Level1GB= =3D { Paging5Level1GB, 100, 20, ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY }; +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging4Level = =3D { Paging4Level, 100, 20, USE_RANDOM_ARRAY }; +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging4Level1GB= =3D { Paging4Level1GB, 100, 20, USE_RANDOM_ARRAY }; +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging5Level = =3D { Paging5Level, 100, 20, USE_RANDOM_ARRAY }; +static CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT mTestContextPaging5Level1GB= =3D { Paging5Level1GB, 100, 20, USE_RANDOM_ARRAY }; =20 /** Check if the input parameters are not supported. --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101391): https://edk2.groups.io/g/devel/message/101391 Mute This Topic: https://groups.io/mt/97725708/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 26 15:40:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101392+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101392+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679290497; cv=none; d=zohomail.com; s=zohoarc; b=EO8lkw3O1oErObJtbr8m555DnZoL8+7Ph0My7yCAy4v7cZakcmXqFlWDkPf2sY++Mhs/JHlxAGJvU1ZnYroAwmIhd1MlqXLHiNBjmG6gkTnukt/8/A70KFNPovllqYU+V2QWWkf6aOBWkX+egg/bzXuKXD2EwmBkokPHMrrQjbw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679290497; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=lDdhBCzUinq3xyDSyA8PKT+1bY5ydlFcxJmtONXvoLQ=; b=LcZkf8Qh6txp90eWtlxtOxDl4XoevY03MaSAIypFkZgdT8t7S2v2N1iP1hv4JixnAwJRTSFXihE4LPk7GQfiSATqvKKejskOY5zfIIqwzuleOZmj9uwjZ2pPb7meTynMHLh9lI0Bb6THYkHKvtlYYxOfk24DU35j/R8PF4oiMrU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101392+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679290497013372.66150683363367; Sun, 19 Mar 2023 22:34:57 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id KEIhYY1788612x2daD9OOCf2; Sun, 19 Mar 2023 22:34:56 -0700 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web11.7471.1679290475232002420 for ; Sun, 19 Mar 2023 22:34:55 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="401155673" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="401155673" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:34:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="770059576" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="770059576" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:34:53 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V3 12/18] UefiCpuPkg/CpuPageTableLib: Add OUTPUT IsModified parameter. Date: Mon, 20 Mar 2023 13:33:23 +0800 Message-Id: <20230320053329.410-13-dun.tan@intel.com> In-Reply-To: <20230320053329.410-1-dun.tan@intel.com> References: <20230320053329.410-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: B1pGRYTJnOSubyfhAZvBKlALx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679290496; bh=aGCXymSpXIT2BuBv+Hrtc+AX6JwselTGlVPsrtkQeQs=; h=Cc:Date:From:Reply-To:Subject:To; b=uK2Y47kcAgYWDUPxoozLuLfOeGefZEYPFgGwBWMwwqJj18zRuxLBPySRETGkkGyHKu9 hqe4jApkBmls+Evw+SMu0G9FRYhb5IFC9sqc41QyrRQ9z1JjLqYj94tbnS8TH1E8MFJFX rmoRXBr1NVMML47Wi8+4njVgX1a10vPhZyU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679290498581100010 Content-Type: text/plain; charset="utf-8" Add OUTPUT IsModified parameter in PageTableMap() to indicate if page table has been modified. With this parameter, caller can know if need to call FlushTlb when the page table is in CR3. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Include/Library/CpuPageTableLib.h = | 4 +++- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c = | 50 +++++++++++++++++++++++++++++++++++++++++++------- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c = | 72 ++++++++++++++++++++++++++++++++++++----------------------------------= -- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c = | 6 ++++-- UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c = | 6 ++++-- 5 files changed, 90 insertions(+), 48 deletions(-) diff --git a/UefiCpuPkg/Include/Library/CpuPageTableLib.h b/UefiCpuPkg/Incl= ude/Library/CpuPageTableLib.h index 6bda15b5bc..c94d82ea65 100644 --- a/UefiCpuPkg/Include/Library/CpuPageTableLib.h +++ b/UefiCpuPkg/Include/Library/CpuPageTableLib.h @@ -74,6 +74,7 @@ typedef enum { Page table entries that map the linear ad= dress range are reset to 0 before set to the new attribute when a new physical base address is set. @param[in] Mask The mask used for attribute. The correspo= nding field in Attribute is ignored if that in Mask is 0. + @param[out] IsModified TRUE means page table is modified. FALSE = means page table is not modified. =20 @retval RETURN_UNSUPPORTED PagingMode is not supported. @retval RETURN_INVALID_PARAMETER PageTable, BufferSize, Attribute or Ma= sk is NULL or the combination of Attribute and Mask is invalid. @@ -93,7 +94,8 @@ PageTableMap ( IN UINT64 LinearAddress, IN UINT64 Length, IN IA32_MAP_ATTRIBUTE *Attribute, - IN IA32_MAP_ATTRIBUTE *Mask + IN IA32_MAP_ATTRIBUTE *Mask, + OUT BOOLEAN *IsModified OPTIONAL ); =20 typedef struct { diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 925dd90f23..9dda308b00 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -273,6 +273,7 @@ IsAttributesAndMaskValidForNonPresentEntry ( Page table entries that map the linear= address range are reset to 0 before set to the new attribute when a new physical base address is se= t. @param[in] Mask The mask used for attribute. The corre= sponding field in Attribute is ignored if that in Mask is 0. + @param[out] IsModified TRUE means page table is modified. FAL= SE means page table is not modified. =20 @retval RETURN_INVALID_PARAMETER The combination of Attribute and Mask = for non-present entry is invalid. @retval RETURN_SUCCESS PageTable is created/updated successfu= lly. @@ -290,7 +291,8 @@ PageTableLibMapInLevel ( IN UINT64 Length, IN UINT64 Offset, IN IA32_MAP_ATTRIBUTE *Attribute, - IN IA32_MAP_ATTRIBUTE *Mask + IN IA32_MAP_ATTRIBUTE *Mask, + OUT BOOLEAN *IsModified ) { RETURN_STATUS Status; @@ -314,6 +316,8 @@ PageTableLibMapInLevel ( IA32_MAP_ATTRIBUTE ChildMask; IA32_MAP_ATTRIBUTE CurrentMask; IA32_MAP_ATTRIBUTE LocalParentAttribute; + IA32_PAGING_ENTRY OriginalParentPagingEntry; + IA32_PAGING_ENTRY OriginalCurrentPagingEntry; =20 ASSERT (Level !=3D 0); ASSERT ((Attribute !=3D NULL) && (Mask !=3D NULL)); @@ -326,8 +330,9 @@ PageTableLibMapInLevel ( NopAttribute.Bits.ReadWrite =3D 1; NopAttribute.Bits.UserSupervisor =3D 1; =20 - LocalParentAttribute.Uint64 =3D ParentAttribute->Uint64; - ParentAttribute =3D &LocalParentAttribute; + LocalParentAttribute.Uint64 =3D ParentAttribute->Uint64; + ParentAttribute =3D &LocalParentAttribute; + OriginalParentPagingEntry.Uint64 =3D ParentPagingEntry->Uint64; =20 // // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 << 2= 1) or 4K (1 << 12). @@ -557,7 +562,15 @@ PageTableLibMapInLevel ( ASSERT (CreateNew || (Mask->Bits.Nx =3D=3D 0) || (Attribute->Bit= s.Nx =3D=3D 1)); } =20 + // + // Check if any leaf PagingEntry is modified. + // + OriginalCurrentPagingEntry.Uint64 =3D CurrentPagingEntry->Uint64; PageTableLibSetPle (Level, CurrentPagingEntry, Offset, Attribute, = &CurrentMask); + + if (OriginalCurrentPagingEntry.Uint64 !=3D CurrentPagingEntry->Uin= t64) { + *IsModified =3D TRUE; + } } } else { // @@ -580,7 +593,8 @@ PageTableLibMapInLevel ( Length, Offset, Attribute, - Mask + Mask, + IsModified ); if (RETURN_ERROR (Status)) { return Status; @@ -592,6 +606,14 @@ PageTableLibMapInLevel ( Index++; } =20 + // + // Check if ParentPagingEntry entry is modified here is enough. Except t= he changes happen in leaf PagingEntry during + // the while loop, if there is any other change happens in page table, t= he ParentPagingEntry must has been modified. + // + if (OriginalParentPagingEntry.Uint64 !=3D ParentPagingEntry->Uint64) { + *IsModified =3D TRUE; + } + return RETURN_SUCCESS; } =20 @@ -612,6 +634,7 @@ PageTableLibMapInLevel ( Page table entries that map the linear ad= dress range are reset to 0 before set to the new attribute when a new physical base address is set. @param[in] Mask The mask used for attribute. The correspo= nding field in Attribute is ignored if that in Mask is 0. + @param[out] IsModified TRUE means page table is modified. FALSE = means page table is not modified. =20 @retval RETURN_UNSUPPORTED PagingMode is not supported. @retval RETURN_INVALID_PARAMETER PageTable, BufferSize, Attribute or Ma= sk is NULL or the combination of Attribute and Mask is invalid. @@ -631,7 +654,8 @@ PageTableMap ( IN UINT64 LinearAddress, IN UINT64 Length, IN IA32_MAP_ATTRIBUTE *Attribute, - IN IA32_MAP_ATTRIBUTE *Mask + IN IA32_MAP_ATTRIBUTE *Mask, + OUT BOOLEAN *IsModified OPTIONAL ) { RETURN_STATUS Status; @@ -641,6 +665,7 @@ PageTableMap ( IA32_PAGE_LEVEL MaxLevel; IA32_PAGE_LEVEL MaxLeafLevel; IA32_MAP_ATTRIBUTE ParentAttribute; + BOOLEAN LocalIsModified; =20 if (Length =3D=3D 0) { return RETURN_SUCCESS; @@ -703,6 +728,10 @@ PageTableMap ( TopPagingEntry.Pce.Nx =3D 0; } =20 + if (IsModified !=3D NULL) { + *IsModified =3D FALSE; + } + ParentAttribute.Uint64 =3D 0; ParentAttribute.Bits.PageTableBaseAddress =3D 1; ParentAttribute.Bits.Present =3D 1; @@ -726,7 +755,8 @@ PageTableMap ( Length, 0, Attribute, - Mask + Mask, + &LocalIsModified ); if (RETURN_ERROR (Status)) { return Status; @@ -743,6 +773,7 @@ PageTableMap ( return RETURN_INVALID_PARAMETER; } =20 + LocalIsModified =3D FALSE; // // Update the page table when the supplied buffer is sufficient. // @@ -758,8 +789,13 @@ PageTableMap ( Length, 0, Attribute, - Mask + Mask, + &LocalIsModified ); + if (IsModified !=3D NULL) { + *IsModified =3D LocalIsModified; + } + if (!RETURN_ERROR (Status)) { *PageTable =3D (UINTN)(TopPagingEntry.Uintn & IA32_PE_BASE_ADDRESS_MAS= K_40); } diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUni= tTestHost.c b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUn= itTestHost.c index d37cae9fbd..6343b56c2f 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c @@ -51,26 +51,26 @@ TestCaseForParameter ( // // If the input linear address is not 4K align, it should return invalid= parameter // - UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 1, SIZE_4KB, &MapAttribute, &MapMask), RETURN_INVALID_PARAMET= ER); + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 1, SIZE_4KB, &MapAttribute, &MapMask, NULL), RETURN_INVALID_P= ARAMETER); =20 // // If the input PageTableBufferSize is not 4K align, it should return in= valid parameter // PageTableBufferSize =3D 10; - UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 0, SIZE_4KB, &MapAttribute, &MapMask), RETURN_INVALID_PARAMET= ER); + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 0, SIZE_4KB, &MapAttribute, &MapMask, NULL), RETURN_INVALID_P= ARAMETER); =20 // // If the input PagingMode is Paging32bit, it should return invalid para= meter // PageTableBufferSize =3D 0; PagingMode =3D Paging32bit; - UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 1, SIZE_4KB, &MapAttribute, &MapMask), RETURN_UNSUPPORTED); + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 1, SIZE_4KB, &MapAttribute, &MapMask, NULL), RETURN_UNSUPPORT= ED); =20 // // If the input MapMask is NULL, it should return invalid parameter // PagingMode =3D Paging5Level1GB; - UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 1, SIZE_4KB, &MapAttribute, NULL), RETURN_INVALID_PARAMETER); + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, &PageTab= leBufferSize, 1, SIZE_4KB, &MapAttribute, NULL, NULL), RETURN_INVALID_PARAM= ETER); =20 return UNIT_TEST_PASSED; } @@ -119,10 +119,10 @@ TestCaseWhichNoNeedExtraSize ( // // Create page table to cover [0, 10M], it should have 5 PTE // - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, (UINT64)SIZE_2MB * 5, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, (UINT64)SIZE_2MB * 5, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, (UINT64)SIZE_2MB * 5, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, (UINT64)SIZE_2MB * 5, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); TestStatus =3D IsPageTableValid (PageTable, PagingMode); if (TestStatus !=3D UNIT_TEST_PASSED) { @@ -134,7 +134,7 @@ TestCaseWhichNoNeedExtraSize ( // We assume the fucntion doesn't need to change page table, return succ= ess and output BufferSize is 0 // Buffer =3D NULL; - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, (UINT64)SIZE_4KB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, (UINT64)SIZE_4KB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (PageTableBufferSize, 0); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); TestStatus =3D IsPageTableValid (PageTable, PagingMode); @@ -148,7 +148,7 @@ TestCaseWhichNoNeedExtraSize ( // MapMask.Bits.Nx =3D 0; PageTableBufferSize =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, NULL, &Pag= eTableBufferSize, 0, (UINT64)SIZE_4KB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, NULL, &Pag= eTableBufferSize, 0, (UINT64)SIZE_4KB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); UT_ASSERT_EQUAL (PageTableBufferSize, 0); TestStatus =3D IsPageTableValid (PageTable, PagingMode); @@ -164,7 +164,7 @@ TestCaseWhichNoNeedExtraSize ( MapAttribute.Bits.Accessed =3D 1; MapMask.Bits.Accessed =3D 1; PageTableBufferSize =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, NUL= L, &PageTableBufferSize, (UINT64)SIZE_2MB, (UINT64)SIZE_2MB, &MapAttribute,= &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, NUL= L, &PageTableBufferSize, (UINT64)SIZE_2MB, (UINT64)SIZE_2MB, &MapAttribute,= &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); UT_ASSERT_EQUAL (PageTableBufferSize, 0); TestStatus =3D IsPageTableValid (PageTable, PagingMode); @@ -217,10 +217,10 @@ TestCase1Gmapto4K ( MapAttribute.Bits.Present =3D 1; MapMask.Bits.Present =3D 1; MapMask.Uint64 =3D MAX_UINT64; - Status =3D PageTableMap (&PageTable, PagingMode, Buff= er, &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapM= ask); + Status =3D PageTableMap (&PageTable, PagingMode, Buff= er, &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapM= ask, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); =20 // @@ -281,11 +281,11 @@ TestCaseManualChangeReadWrite ( // // Create Page table to cover [0,2G], with ReadWrite =3D 1 // - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); BackupPageTableBufferSize =3D PageTableBufferSize; Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTabl= eBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buff= er, &PageTableBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buff= er, &PageTableBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); IsPageTableValid (PageTable, PagingMode); =20 @@ -331,7 +331,7 @@ TestCaseManualChangeReadWrite ( // Call library to change ReadWrite to 0 for [0,2M] // MapAttribute.Bits.ReadWrite =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, NU= LL, &PageTableBufferSize, 0, SIZE_2MB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, NU= LL, &PageTableBufferSize, 0, SIZE_2MB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); IsPageTableValid (PageTable, PagingMode); MapCount =3D 0; @@ -360,7 +360,7 @@ TestCaseManualChangeReadWrite ( // MapAttribute.Bits.ReadWrite =3D 1; PageTableBufferSize =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, NU= LL, &PageTableBufferSize, 0, SIZE_2MB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, NU= LL, &PageTableBufferSize, 0, SIZE_2MB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); IsPageTableValid (PageTable, PagingMode); MapCount =3D 0; @@ -434,10 +434,10 @@ TestCaseManualSizeNotMatch ( // // Create Page table to cover [2M-4K, 4M], with ReadWrite =3D 1 // - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, SIZE_2MB - SIZE_4KB, SIZE_4KB + SIZE_2MB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, SIZE_2MB - SIZE_4KB, SIZE_4KB + SIZE_2MB, &MapAttribute, &MapMask, N= ULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, SIZE_2MB - SIZE_4KB, SIZE_4KB + SIZE_2MB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, SIZE_2MB - SIZE_4KB, SIZE_4KB + SIZE_2MB, &MapAttribute, &MapMask, N= ULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); IsPageTableValid (PageTable, PagingMode); =20 @@ -493,7 +493,7 @@ TestCaseManualSizeNotMatch ( MapAttribute.Bits.ReadWrite =3D 1; PageTableBufferSize =3D 0; MapAttribute.Bits.PageTableBaseAddress =3D (SIZE_2MB - SIZE_4KB) >> 12; - Status =3D PageTableMap (&PageTable, Pag= ingMode, Buffer, &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB * 2, &= MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, Pag= ingMode, Buffer, &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB * 2, &= MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); return UNIT_TEST_PASSED; } @@ -540,10 +540,10 @@ TestCaseManualNotMergeEntry ( // // Create Page table to cover [0,4M], and [4M, 1G] is not present // - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_2MB * 2, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_2MB * 2, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_2MB * 2, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_2MB * 2, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); TestStatus =3D IsPageTableValid (PageTable, PagingMode); if (TestStatus !=3D UNIT_TEST_PASSED) { @@ -555,7 +555,7 @@ TestCaseManualNotMergeEntry ( // It looks like the chioce is not bad, but sometime, we need to keep so= me small entry // PageTableBufferSize =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, NULL, &Pag= eTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, NULL, &Pag= eTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapMask, NUL= L); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); TestStatus =3D IsPageTableValid (PageTable, PagingMode); if (TestStatus !=3D UNIT_TEST_PASSED) { @@ -564,7 +564,7 @@ TestCaseManualNotMergeEntry ( =20 MapAttribute.Bits.Accessed =3D 1; PageTableBufferSize =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, NUL= L, &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_2MB, &MapAttribute, &MapMa= sk); + Status =3D PageTableMap (&PageTable, PagingMode, NUL= L, &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_2MB, &MapAttribute, &MapMa= sk, NULL); // // If it didn't use a big 1G entry to cover whole range, only change [0,= 2M] for some attribute won't need extra memory // @@ -619,10 +619,10 @@ TestCaseManualChangeNx ( // // Create Page table to cover [0,2G], with Nx =3D 0 // - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_1GB * 2, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_1GB * 2, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_1GB * 2, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, (UINT64)0, (UINT64)SIZE_1GB * 2, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); TestStatus =3D IsPageTableValid (PageTable, PagingMode); if (TestStatus !=3D UNIT_TEST_PASSED) { @@ -666,7 +666,7 @@ TestCaseManualChangeNx ( // // Call library to change Nx to 0 for [0,1G] // - Status =3D PageTableMap (&PageTable, PagingMode, NULL, &PageTableBufferS= ize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, NULL, &PageTableBufferS= ize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); TestStatus =3D IsPageTableValid (PageTable, PagingMode); if (TestStatus !=3D UNIT_TEST_PASSED) { @@ -741,30 +741,30 @@ TestCaseToCheckMapMaskAndAttr ( // // Create Page table to cover [0, 2G]. All fields of MapMask should be s= et. // - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); MapMask.Uint64 =3D MAX_UINT64; - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTa= bleBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTa= bleBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); =20 // // Update Page table to set [2G - 8K, 2G] from present to non-present. A= ll fields of MapMask except present should be set. // PageTableBufferSize =3D 0; - MapAttribute.Uint64 =3D SIZE_2GB - SIZE_8KB; + MapAttribute.Uint64 =3D 0; MapMask.Uint64 =3D 0; MapMask.Bits.Present =3D 1; MapMask.Bits.ReadWrite =3D 1; - Status =3D PageTableMap (&PageTable, PagingMode, Buffer,= &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMa= sk); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer,= &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMa= sk, NULL); UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); MapMask.Bits.ReadWrite =3D 0; - Status =3D PageTableMap (&PageTable, PagingMode, Buffer,= &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMa= sk); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer,= &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMa= sk, NULL); UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, 0, SIZE_2GB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBuffe= rSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); =20 // @@ -774,11 +774,11 @@ TestCaseToCheckMapMaskAndAttr ( MapAttribute.Uint64 =3D 0; MapMask.Uint64 =3D 0; MapMask.Bits.Present =3D 1; - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &= PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMask= ); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &= PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMask= , NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); MapAttribute.Bits.ReadWrite =3D 1; MapMask.Bits.ReadWrite =3D 1; - Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &= MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &= MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); =20 // @@ -791,10 +791,10 @@ TestCaseToCheckMapMaskAndAttr ( MapMask.Uint64 =3D 0; MapMask.Bits.ReadWrite =3D 1; MapMask.Bits.Present =3D 1; - Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &= MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &= MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); MapMask.Uint64 =3D MAX_UINT64; - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTa= bleBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMask); + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &PageTa= bleBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, &MapMask, NULL= ); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); =20 MapCount =3D 0; diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c index eb621e6e59..5fbc43c9d1 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c @@ -695,7 +695,8 @@ SingleMapEntryTest ( MapEntrys->Maps[MapsIndex].LinearAddress, MapEntrys->Maps[MapsIndex].Length, &MapEntrys->Maps[MapsIndex].Attribute, - &MapEntrys->Maps[MapsIndex].Mask + &MapEntrys->Maps[MapsIndex].Mask, + NULL ); =20 Attribute =3D &MapEntrys->Maps[MapsIndex].Attribute; @@ -755,7 +756,8 @@ SingleMapEntryTest ( MapEntrys->Maps[MapsIndex].LinearAddress, MapEntrys->Maps[MapsIndex].Length, &MapEntrys->Maps[MapsIndex].Attribute, - &MapEntrys->Maps[MapsIndex].Mask + &MapEntrys->Maps[MapsIndex].Mask, + NULL ); } =20 diff --git a/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c b/UefiCpuPk= g/Library/MpInitLib/X64/CreatePageTable.c index 7cf91ed9c4..c10121ede5 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c +++ b/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c @@ -60,7 +60,8 @@ CreatePageTable ( Address, Length, &MapAttribute, - &MapMask + &MapMask, + NULL ); ASSERT (Status =3D=3D EFI_BUFFER_TOO_SMALL); DEBUG ((DEBUG_INFO, "AP Page Table Buffer Size =3D %x\n", PageTableBuffe= rSize)); @@ -75,7 +76,8 @@ CreatePageTable ( Address, Length, &MapAttribute, - &MapMask + &MapMask, + NULL ); ASSERT_EFI_ERROR (Status); return PageTable; --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101392): https://edk2.groups.io/g/devel/message/101392 Mute This Topic: https://groups.io/mt/97725710/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 26 15:40:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101393+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101393+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679290499; cv=none; d=zohomail.com; s=zohoarc; b=FS6Qb2YK3iTvo9RjkkZQJmlYWS2HW4R1eq8LNwnTmHL0VAtERUat7XWPms9BlZYpTeFiqrM9fzFxPDa6EFZwZdcKJrZJ/Ia+uY2clud+DxBwNmpH8tCifwgfgO7+4bo5iC2EWg1GBcaCS39MtbqCNFShi8jOBue/Tc5f3c/ORAc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679290499; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=/hHcKvQqpWwzQS/J/SC4owJbBrjyV1XXEu6Uah0SJ3c=; b=fb/P2j6IBe7SC1BzV7FLs89el6SVaF/78UihCL26zP4xL0YEAQBmW27ncnerz2sCrYjWtTXVhfL2+Pu6gJvXeWS4hqrtS4IB+6wBaGOdqtmD4EMbJU5rBavoXEtoESU6OxRkcPbh+pwVM46Px4gmZg1GurAp8RY8n4Tt3cVRb7Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101393+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679290498962536.6470272411985; Sun, 19 Mar 2023 22:34:58 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id cwwFYY1788612xoo1BiVrDN6; Sun, 19 Mar 2023 22:34:58 -0700 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web11.7471.1679290475232002420 for ; Sun, 19 Mar 2023 22:34:58 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="401155694" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="401155694" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:34:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="770059590" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="770059590" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:34:55 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann , Zhiguang Liu Subject: [edk2-devel] [Patch V3 13/18] UefiCpuPkg/CpuPageTableLib: Modify RandomTest to check IsModified Date: Mon, 20 Mar 2023 13:33:24 +0800 Message-Id: <20230320053329.410-14-dun.tan@intel.com> In-Reply-To: <20230320053329.410-1-dun.tan@intel.com> References: <20230320053329.410-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: RT1N6RJjgh8QCQ7pPOXOleE6x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679290498; bh=mynn9i4EO621GQVFGGdS2HfGnEUcB1EVrG7yJd7mQS0=; h=Cc:Date:From:Reply-To:Subject:To; b=u2udnObzlFu3L5yR4kjVYG4oWExNcmsKnxa60XRmE29HoKYkVDBNJ0q1D9kWpaxDGet Xvonr7paLCSX/zHex+/iF726MgLXnky7BdeZvhVk/OtFhLwpGgvoSsm09Of3pAtGREL2p zRQ+MrnOusSPP0+zE4j7nBEjPesTwWcyjaY= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679290500558100013 Content-Type: text/plain; charset="utf-8" Modify RandomTest to check if parameter IsModified of PageTableMap() correctlly indicates whether input page table is modified or not. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Zhiguang Liu --- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c | 45 ++++++++++++= +++++++++++++++++++++------------ 1 file changed, 33 insertions(+), 12 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c index 5fbc43c9d1..81dd9e5836 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c @@ -636,6 +636,8 @@ SingleMapEntryTest ( VOID *Buffer; IA32_MAP_ENTRY *Map; UINTN MapCount; + IA32_MAP_ENTRY *Map2; + UINTN MapCount2; UINTN Index; UINTN KeyPointCount; UINTN NewKeyPointCount; @@ -648,11 +650,13 @@ SingleMapEntryTest ( UINT64 PreviousAddress; UINT64 RangeLimit; BOOLEAN IsNotPresent; + BOOLEAN IsModified; =20 MapsIndex =3D MapEntrys->Count; MapCount =3D 0; PreviousAddress =3D 0; IsNotPresent =3D FALSE; + IsModified =3D FALSE; =20 GenerateSingleRandomMapEntry (MaxAddress, MapEntrys); RangeLimit =3D MapEntrys->Maps[MapsIndex].LinearAddress + MapEntrys->Map= s[MapsIndex].Length; @@ -696,7 +700,7 @@ SingleMapEntryTest ( MapEntrys->Maps[MapsIndex].Length, &MapEntrys->Maps[MapsIndex].Attribute, &MapEntrys->Maps[MapsIndex].Mask, - NULL + &IsModified ); =20 Attribute =3D &MapEntrys->Maps[MapsIndex].Attribute; @@ -757,7 +761,7 @@ SingleMapEntryTest ( MapEntrys->Maps[MapsIndex].Length, &MapEntrys->Maps[MapsIndex].Attribute, &MapEntrys->Maps[MapsIndex].Mask, - NULL + &IsModified ); } =20 @@ -771,18 +775,31 @@ SingleMapEntryTest ( return TestStatus; } =20 - MapCount =3D 0; - Status =3D PageTableParse (*PageTable, PagingMode, NULL, &MapCount); - if (MapCount !=3D 0) { + MapCount2 =3D 0; + Status =3D PageTableParse (*PageTable, PagingMode, NULL, &MapCount2); + if (MapCount2 !=3D 0) { UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); =20 // - // Allocate memory for Maps + // Allocate memory for Map2 // Note the memory is only used in this one Single MapEntry Test // - Map =3D AllocatePages (EFI_SIZE_TO_PAGES (MapCount * sizeof (IA32_MAP_= ENTRY))); - ASSERT (Map !=3D NULL); - Status =3D PageTableParse (*PageTable, PagingMode, Map, &MapCount); + Map2 =3D AllocatePages (EFI_SIZE_TO_PAGES (MapCount2 * sizeof (IA32_MA= P_ENTRY))); + ASSERT (Map2 !=3D NULL); + Status =3D PageTableParse (*PageTable, PagingMode, Map2, &MapCount2); + } + + // + // Check if PageTable has been modified. + // + if (MapCount2 !=3D MapCount) { + UT_ASSERT_EQUAL (IsModified, TRUE); + } else { + if (CompareMem (Map, Map2, MapCount2 * sizeof (IA32_MAP_ENTRY)) !=3D 0= ) { + UT_ASSERT_EQUAL (IsModified, TRUE); + } else { + UT_ASSERT_EQUAL (IsModified, FALSE); + } } =20 UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); @@ -792,17 +809,17 @@ SingleMapEntryTest ( // Note the memory is only used in this one Single MapEntry Test // KeyPointCount =3D 0; - GetKeyPointList (MapEntrys, Map, MapCount, NULL, &KeyPointCount); + GetKeyPointList (MapEntrys, Map2, MapCount2, NULL, &KeyPointCount); KeyPointBuffer =3D AllocatePages (EFI_SIZE_TO_PAGES (KeyPointCount * siz= eof (UINT64))); ASSERT (KeyPointBuffer !=3D NULL); NewKeyPointCount =3D 0; - GetKeyPointList (MapEntrys, Map, MapCount, KeyPointBuffer, &NewKeyPointC= ount); + GetKeyPointList (MapEntrys, Map2, MapCount2, KeyPointBuffer, &NewKeyPoin= tCount); =20 // // Compare all key point's attribute // for (Index =3D 0; Index < NewKeyPointCount; Index++) { - if (!CompareEntrysforOnePoint (KeyPointBuffer[Index], MapEntrys, Map, = MapCount, InitMap, InitMapCount)) { + if (!CompareEntrysforOnePoint (KeyPointBuffer[Index], MapEntrys, Map2,= MapCount2, InitMap, InitMapCount)) { DEBUG ((DEBUG_INFO, "Error happens at below key point\n")); DEBUG ((DEBUG_INFO, "Index =3D %d KeyPointBuffer[Index] =3D 0x%lx\n"= , Index, KeyPointBuffer[Index])); Value =3D GetEntryFromPageTable (*PageTable, PagingMode, KeyPointBuf= fer[Index], &Level); @@ -816,6 +833,10 @@ SingleMapEntryTest ( FreePages (Map, EFI_SIZE_TO_PAGES (MapCount * sizeof (IA32_MAP_ENTRY))= ); } =20 + if (MapCount2 !=3D 0) { + FreePages (Map2, EFI_SIZE_TO_PAGES (MapCount2 * sizeof (IA32_MAP_ENTRY= ))); + } + return UNIT_TEST_PASSED; } =20 --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101393): https://edk2.groups.io/g/devel/message/101393 Mute This Topic: https://groups.io/mt/97725711/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 26 15:40:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101394+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101394+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679290501; cv=none; d=zohomail.com; s=zohoarc; b=IMT1bhwyndrte/hZXhXdBlrdIIb8dNbBZkUH6nxiRJLU2loxJJUbnIqyjQC0tJMc9KAHbPKgySEGihD3p7Mg9QmEKv3ptgkdHn0nTL3s5M1oA7BcPfM9fdwepDCfMzpM7eLl0TnQEKD3amshQJt8kS2gSbEZXR+VR0QN62vW7dg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679290501; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=TuF65m7mDoxzqjBSDKdCY53qGXnpRgmVqfEWcRNRqcU=; b=GnMpZiEDnx8P4u9etRHqSxrEoDzUjWF62fYhcsF5VDgb6kTVc+z+CFq/hM6/LRdg5YbQyCBvOOXiG7/xRazk2LJNCR5QKF17R8aEHvb2V76Cz1HFsvFjQF9ExA3a+p+P4eJ2PuN9uZT+trQIzp+uVW4FGoP8SrIATK7DVThSCnY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101394+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 16792905011442.425812643487234; Sun, 19 Mar 2023 22:35:01 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id oMdMYY1788612xb7jTq7lVez; Sun, 19 Mar 2023 22:35:00 -0700 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web11.7471.1679290475232002420 for ; Sun, 19 Mar 2023 22:35:00 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="401155717" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="401155717" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:34:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="770059597" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="770059597" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:34:58 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar Subject: [edk2-devel] [Patch V3 14/18] UefiCpuPkg: Fix IA32 build failure in CpuPageTableLib.inf Date: Mon, 20 Mar 2023 13:33:25 +0800 Message-Id: <20230320053329.410-15-dun.tan@intel.com> In-Reply-To: <20230320053329.410-1-dun.tan@intel.com> References: <20230320053329.410-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: utqCGPalbWNq1IrDm8SLeDKyx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679290500; bh=sAOS3Ln3Lz97HgRRHgo0scCBvYS208rxnS6ICaJAaUk=; h=Cc:Date:From:Reply-To:Subject:To; b=TOk/TvBz+l9gfxgsXps2doEv1XXtxpopsYQeJkfRU8Q7uEIICDeiNhWqxGXROofSRi2 kH4+CPna+j545R3QXeLf6LkEXoyhcknFmd1NqyeIeFGxCY6PUHeaniYra+wrIzX3+M6Cb g5q379ARKY9CiRblevqRT+HTyomDbQr+bnM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679290502635100001 Content-Type: text/plain; charset="utf-8" From: Zhiguang Liu The definition of IA32_MAP_ATTRIBUTE has 64 bits, and one of the bit field PageTableBaseAddress is from bit 12 to bit 52. This means if the compiler treats the 64bits value as two UINT32 value, the field PageTableBaseAddress spans two UINT32 value. That's why when building in NOOPT mode in IA32, the below issue is noticed: unresolved external symbol __allshl This patch fix the build failure by seperate field PageTableBaseAddress into two fields, make sure no field spans two UINT32 value. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Signed-off-by: Zhiguang Liu Signed-off-by: Ray Ni --- UefiCpuPkg/Include/Library/CpuPageTableLib.h | 32 +++++++++++++++= +---------------- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h | 125 +++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++---------------------------= ----------------------------------- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 22 +++++++++++----= ------- UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c | 6 +++--- 4 files changed, 93 insertions(+), 92 deletions(-) diff --git a/UefiCpuPkg/Include/Library/CpuPageTableLib.h b/UefiCpuPkg/Incl= ude/Library/CpuPageTableLib.h index c94d82ea65..5e545a35f6 100644 --- a/UefiCpuPkg/Include/Library/CpuPageTableLib.h +++ b/UefiCpuPkg/Include/Library/CpuPageTableLib.h @@ -11,22 +11,22 @@ =20 typedef union { struct { - UINT64 Present : 1; // 0 =3D Not present in memory, 1 = =3D Present in memory - UINT64 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Write - UINT64 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser - UINT64 WriteThrough : 1; // 0 =3D Write-Back caching, 1=3DW= rite-Through caching - UINT64 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cached - UINT64 Accessed : 1; // 0 =3D Not accessed, 1 =3D Acces= sed (set by CPU) - UINT64 Dirty : 1; // 0 =3D Not dirty, 1 =3D Dirty (s= et by CPU) - UINT64 Pat : 1; // PAT - - UINT64 Global : 1; // 0 =3D Not global, 1 =3D Global = (if CR4.PGE =3D 1) - UINT64 Reserved1 : 3; // Ignored - - UINT64 PageTableBaseAddress : 40; // Page Table Base Address - UINT64 Reserved2 : 7; // Ignored - UINT64 ProtectionKey : 4; // Protection key - UINT64 Nx : 1; // No Execute bit + UINT32 Present : 1; // 0 =3D Not present in memor= y, 1 =3D Present in memory + UINT32 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read= /Write + UINT32 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser + UINT32 WriteThrough : 1; // 0 =3D Write-Back caching, = 1=3DWrite-Through caching + UINT32 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cach= ed + UINT32 Accessed : 1; // 0 =3D Not accessed, 1 =3D = Accessed (set by CPU) + UINT32 Dirty : 1; // 0 =3D Not dirty, 1 =3D Dir= ty (set by CPU) + UINT32 Pat : 1; // PAT + UINT32 Global : 1; // 0 =3D Not global, 1 =3D Gl= obal (if CR4.PGE =3D 1) + UINT32 Reserved1 : 3; // Ignored + UINT32 PageTableBaseAddressLow : 20; // Page Table Base Address Low + + UINT32 PageTableBaseAddressHigh : 20; // Page Table Base Address Hi= gh + UINT32 Reserved2 : 7; // Ignored + UINT32 ProtectionKey : 4; // Protection key + UINT32 Nx : 1; // No Execute bit } Bits; UINT64 Uint64; } IA32_MAP_ATTRIBUTE; diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h b/UefiCpuPkg= /Library/CpuPageTableLib/CpuPageTable.h index 8d856d7c7e..2c67ecb469 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h @@ -29,11 +29,12 @@ typedef enum { } IA32_PAGE_LEVEL; =20 typedef struct { - UINT64 Present : 1; // 0 =3D Not present in memory, 1 = =3D Present in memory - UINT64 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Write - UINT64 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser - UINT64 Reserved : 58; - UINT64 Nx : 1; // No Execute bit + UINT32 Present : 1; // 0 =3D Not present in memory, 1 = =3D Present in memory + UINT32 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Write + UINT32 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser + UINT32 Reserved0 : 29; + UINT32 Reserved1 : 31; + UINT32 Nx : 1; // No Execute bit } IA32_PAGE_COMMON_ENTRY; =20 /// @@ -41,20 +42,20 @@ typedef struct { /// typedef union { struct { - UINT64 Present : 1; // 0 =3D Not present in memory, 1 = =3D Present in memory - UINT64 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Write - UINT64 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser - UINT64 WriteThrough : 1; // 0 =3D Write-Back caching, 1=3DW= rite-Through caching - UINT64 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cached - UINT64 Accessed : 1; // 0 =3D Not accessed, 1 =3D Acces= sed (set by CPU) - UINT64 Available0 : 1; // Ignored - UINT64 MustBeZero : 1; // Must Be Zero - - UINT64 Available2 : 4; // Ignored - - UINT64 PageTableBaseAddress : 40; // Page Table Base Address - UINT64 Available3 : 11; // Ignored - UINT64 Nx : 1; // No Execute bit + UINT32 Present : 1; // 0 =3D Not present in memor= y, 1 =3D Present in memory + UINT32 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read= /Write + UINT32 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser + UINT32 WriteThrough : 1; // 0 =3D Write-Back caching, = 1=3DWrite-Through caching + UINT32 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cach= ed + UINT32 Accessed : 1; // 0 =3D Not accessed, 1 =3D = Accessed (set by CPU) + UINT32 Available0 : 1; // Ignored + UINT32 MustBeZero : 1; // Must Be Zero + UINT32 Available2 : 4; // Ignored + UINT32 PageTableBaseAddressLow : 20; // Page Table Base Address Low + + UINT32 PageTableBaseAddressHigh : 20; // Page Table Base Address Hi= gh + UINT32 Available3 : 11; // Ignored + UINT32 Nx : 1; // No Execute bit } Bits; UINT64 Uint64; } IA32_PAGE_NON_LEAF_ENTRY; @@ -86,23 +87,23 @@ typedef IA32_PAGE_NON_LEAF_ENTRY IA32_PDE; /// typedef union { struct { - UINT64 Present : 1; // 0 =3D Not present in memory, 1 = =3D Present in memory - UINT64 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Write - UINT64 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser - UINT64 WriteThrough : 1; // 0 =3D Write-Back caching, 1=3DW= rite-Through caching - UINT64 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cached - UINT64 Accessed : 1; // 0 =3D Not accessed, 1 =3D Acces= sed (set by CPU) - UINT64 Dirty : 1; // 0 =3D Not dirty, 1 =3D Dirty (s= et by CPU) - UINT64 MustBeOne : 1; // Page Size. Must Be One - - UINT64 Global : 1; // 0 =3D Not global, 1 =3D Global = (if CR4.PGE =3D 1) - UINT64 Available1 : 3; // Ignored - UINT64 Pat : 1; // PAT - - UINT64 PageTableBaseAddress : 39; // Page Table Base Address - UINT64 Available3 : 7; // Ignored - UINT64 ProtectionKey : 4; // Protection key - UINT64 Nx : 1; // No Execute bit + UINT32 Present : 1; // 0 =3D Not present in memor= y, 1 =3D Present in memory + UINT32 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read= /Write + UINT32 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser + UINT32 WriteThrough : 1; // 0 =3D Write-Back caching, = 1=3DWrite-Through caching + UINT32 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cach= ed + UINT32 Accessed : 1; // 0 =3D Not accessed, 1 =3D = Accessed (set by CPU) + UINT32 Dirty : 1; // 0 =3D Not dirty, 1 =3D Dir= ty (set by CPU) + UINT32 MustBeOne : 1; // Page Size. Must Be One + UINT32 Global : 1; // 0 =3D Not global, 1 =3D Gl= obal (if CR4.PGE =3D 1) + UINT32 Available1 : 3; // Ignored + UINT32 Pat : 1; // PAT + UINT32 PageTableBaseAddressLow : 19; // Page Table Base Address Low + + UINT32 PageTableBaseAddressHigh : 20; // Page Table Base Address Hi= gh + UINT32 Available3 : 7; // Ignored + UINT32 ProtectionKey : 4; // Protection key + UINT32 Nx : 1; // No Execute bit } Bits; UINT64 Uint64; } IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE; @@ -123,22 +124,22 @@ typedef IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE IA32_PDPTE_= 1G; /// typedef union { struct { - UINT64 Present : 1; // 0 =3D Not present in memory, 1 = =3D Present in memory - UINT64 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Write - UINT64 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser - UINT64 WriteThrough : 1; // 0 =3D Write-Back caching, 1=3DW= rite-Through caching - UINT64 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cached - UINT64 Accessed : 1; // 0 =3D Not accessed, 1 =3D Acces= sed (set by CPU) - UINT64 Dirty : 1; // 0 =3D Not dirty, 1 =3D Dirty (s= et by CPU) - UINT64 Pat : 1; // PAT - - UINT64 Global : 1; // 0 =3D Not global, 1 =3D Global = (if CR4.PGE =3D 1) - UINT64 Available1 : 3; // Ignored - - UINT64 PageTableBaseAddress : 40; // Page Table Base Address - UINT64 Available3 : 7; // Ignored - UINT64 ProtectionKey : 4; // Protection key - UINT64 Nx : 1; // No Execute bit + UINT32 Present : 1; // 0 =3D Not present in memor= y, 1 =3D Present in memory + UINT32 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read= /Write + UINT32 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser + UINT32 WriteThrough : 1; // 0 =3D Write-Back caching, = 1=3DWrite-Through caching + UINT32 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cach= ed + UINT32 Accessed : 1; // 0 =3D Not accessed, 1 =3D = Accessed (set by CPU) + UINT32 Dirty : 1; // 0 =3D Not dirty, 1 =3D Dir= ty (set by CPU) + UINT32 Pat : 1; // PAT + UINT32 Global : 1; // 0 =3D Not global, 1 =3D Gl= obal (if CR4.PGE =3D 1) + UINT32 Available1 : 3; // Ignored + UINT32 PageTableBaseAddressLow : 20; // Page Table Base Address Low + + UINT32 PageTableBaseAddressHigh : 20; // Page Table Base Address Hi= gh + UINT32 Available3 : 7; // Ignored + UINT32 ProtectionKey : 4; // Protection key + UINT32 Nx : 1; // No Execute bit } Bits; UINT64 Uint64; } IA32_PTE_4K; @@ -149,16 +150,16 @@ typedef union { /// typedef union { struct { - UINT64 Present : 1; // 0 =3D Not present in memory, 1 = =3D Present in memory - UINT64 MustBeZero : 2; // Must Be Zero - UINT64 WriteThrough : 1; // 0 =3D Write-Back caching, 1=3DW= rite-Through caching - UINT64 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cached - UINT64 MustBeZero2 : 4; // Must Be Zero - - UINT64 Available : 3; // Ignored - - UINT64 PageTableBaseAddress : 40; // Page Table Base Address - UINT64 MustBeZero3 : 12; // Must Be Zero + UINT32 Present : 1; // 0 =3D Not present in memor= y, 1 =3D Present in memory + UINT32 MustBeZero : 2; // Must Be Zero + UINT32 WriteThrough : 1; // 0 =3D Write-Back caching, = 1=3DWrite-Through caching + UINT32 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cach= ed + UINT32 MustBeZero2 : 4; // Must Be Zero + UINT32 Available : 3; // Ignored + UINT32 PageTableBaseAddressLow : 20; // Page Table Base Address Low + + UINT32 PageTableBaseAddressHigh : 20; // Page Table Base Address Hi= gh + UINT32 MustBeZero3 : 12; // Must Be Zero } Bits; UINT64 Uint64; } IA32_PDPTE_PAE; diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 9dda308b00..fbfd6389dc 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -26,7 +26,7 @@ PageTableLibSetPte4K ( IN IA32_MAP_ATTRIBUTE *Mask ) { - if (Mask->Bits.PageTableBaseAddress) { + if (Mask->Bits.PageTableBaseAddressLow || Mask->Bits.PageTableBaseAddres= sHigh) { Pte4K->Uint64 =3D (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribu= te) + Offset) | (Pte4K->Uint64 & ~IA32_PE_BASE_ADDRESS_MASK_40); } =20 @@ -93,7 +93,7 @@ PageTableLibSetPleB ( IN IA32_MAP_ATTRIBUTE *Mask ) { - if (Mask->Bits.PageTableBaseAddress) { + if (Mask->Bits.PageTableBaseAddressLow || Mask->Bits.PageTableBaseAddres= sHigh) { PleB->Uint64 =3D (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribut= e) + Offset) | (PleB->Uint64 & ~IA32_PE_BASE_ADDRESS_MASK_39); } =20 @@ -238,7 +238,7 @@ IsAttributesAndMaskValidForNonPresentEntry ( // if ((Mask->Bits.ReadWrite =3D=3D 0) || (Mask->Bits.UserSupervisor =3D= =3D 0) || (Mask->Bits.WriteThrough =3D=3D 0) || (Mask->Bits.CacheDisabled = =3D=3D 0) || (Mask->Bits.Accessed =3D=3D 0) || (Mask->Bits.Dirty =3D=3D 0) || (= Mask->Bits.Pat =3D=3D 0) || (Mask->Bits.Global =3D=3D 0) || - (Mask->Bits.PageTableBaseAddress =3D=3D 0) || (Mask->Bits.Protecti= onKey =3D=3D 0) || (Mask->Bits.Nx =3D=3D 0)) + ((Mask->Bits.PageTableBaseAddressLow =3D=3D 0) && (Mask->Bits.Page= TableBaseAddressHigh =3D=3D 0)) || (Mask->Bits.ProtectionKey =3D=3D 0) || (= Mask->Bits.Nx =3D=3D 0)) { return RETURN_INVALID_PARAMETER; } @@ -388,7 +388,7 @@ PageTableLibMapInLevel ( PleBAttribute.Uint64 =3D PageTableLibGetPleBMapAttribute (&ParentPagin= gEntry->PleB, ParentAttribute); if ((((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRI= BUTE_ATTRIBUTES (Mask)) =3D=3D (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATT= RIBUTE_ATTRIBUTES (Mask)))) && - ( (Mask->Bits.PageTableBaseAddress =3D=3D 0) + ( ((Mask->Bits.PageTableBaseAddressLow =3D=3D 0) && (Mask->Bits.P= ageTableBaseAddressHigh =3D=3D 0)) || ((IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&PleBAttribute) += PagingEntryIndex * RegionLength) =3D=3D (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute)= + Offset)))) { @@ -690,7 +690,7 @@ PageTableMap ( return RETURN_INVALID_PARAMETER; } =20 - if ((LinearAddress % SIZE_4KB !=3D 0) || (Length % SIZE_4KB !=3D 0)) { + if (((UINTN)LinearAddress % SIZE_4KB !=3D 0) || ((UINTN)Length % SIZE_4K= B !=3D 0)) { // // LinearAddress and Length should be multiple of 4K. // @@ -732,12 +732,12 @@ PageTableMap ( *IsModified =3D FALSE; } =20 - ParentAttribute.Uint64 =3D 0; - ParentAttribute.Bits.PageTableBaseAddress =3D 1; - ParentAttribute.Bits.Present =3D 1; - ParentAttribute.Bits.ReadWrite =3D 1; - ParentAttribute.Bits.UserSupervisor =3D 1; - ParentAttribute.Bits.Nx =3D 0; + ParentAttribute.Uint64 =3D 0; + ParentAttribute.Bits.PageTableBaseAddressLow =3D 1; + ParentAttribute.Bits.Present =3D 1; + ParentAttribute.Bits.ReadWrite =3D 1; + ParentAttribute.Bits.UserSupervisor =3D 1; + ParentAttribute.Bits.Nx =3D 0; =20 // // Query the required buffer size without modifying the page table. diff --git a/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c b/UefiCpuPk= g/Library/MpInitLib/X64/CreatePageTable.c index c10121ede5..05a40bb225 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c +++ b/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c @@ -37,9 +37,9 @@ CreatePageTable ( MapAttribute.Bits.Present =3D 1; MapAttribute.Bits.ReadWrite =3D 1; =20 - MapMask.Bits.PageTableBaseAddress =3D 1; - MapMask.Bits.Present =3D 1; - MapMask.Bits.ReadWrite =3D 1; + MapMask.Bits.PageTableBaseAddressLow =3D 1; + MapMask.Bits.Present =3D 1; + MapMask.Bits.ReadWrite =3D 1; =20 PageTable =3D 0; PageTableBufferSize =3D 0; --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101394): https://edk2.groups.io/g/devel/message/101394 Mute This Topic: https://groups.io/mt/97725712/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 26 15:40:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101395+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101395+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679290504; cv=none; d=zohomail.com; s=zohoarc; b=TCMsF8QFM7A6PW0MUsjgAKr3BvwmAIobqKnpPA5O9P2GaP0G1/u7ZxkD7ykWBJv5KLfjGGKL9vjhgkYMQrE5kDoKiLsOhSuf01IecqCg9PXN85jrVWlEPO06ZQvrmw/Stfed7UatBvDRmM8F8AxBdhtDCJxvc0IHBDFwx6LXETo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679290504; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=SAZjgQCj3/MU3HV/3WxNX/F4fq+QSKUplhZ2+DUMjSo=; b=HRUJFjuPkbQYuWNK2wdN5uF4pZ18PrkzyjPwfy33om5as1rlDQQDc2xTnNn4FxCrOcYtCjZ5V+LBr49B5H89bE5GtHcip3wAVkLhSAIRiw6SY9BwOpM50VE8Xzw5WFYhAvYEJ1KTTA5WBl9nEXxdHsQntInNmK4rpAd3zMCiSMI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101395+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679290504399469.5512156076376; Sun, 19 Mar 2023 22:35:04 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 7KkoYY1788612xMYKJsrtMHY; Sun, 19 Mar 2023 22:35:04 -0700 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web11.7471.1679290475232002420 for ; Sun, 19 Mar 2023 22:35:03 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="401155741" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="401155741" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:35:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="770059630" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="770059630" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:35:00 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V3 15/18] UefiCpuPkg/MpInitLib: Add code to initialize MapMask to 0 Date: Mon, 20 Mar 2023 13:33:26 +0800 Message-Id: <20230320053329.410-16-dun.tan@intel.com> In-Reply-To: <20230320053329.410-1-dun.tan@intel.com> References: <20230320053329.410-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: g7rtvOW2vchnXaH6pnDmRdROx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679290504; bh=Kbmm2CvbmotagQh7Jk4d9tWb8U1TFKl3qhWQs5fXOS4=; h=Cc:Date:From:Reply-To:Subject:To; b=n/wY2Z2bsO8Mkd3wxwsJ81YUOidYvXf3rXoUwe3q1MVlFR2w0l9cmmXBMJtTUYIjS4I hlIrKNZdqVD8MBwp9d989UXGhN6Qx6ZnbgNY+EeWiK7rJR8iKjZGvjz/GLDY3P0eWFRgx ah0rQNERe3hzSscVJOMdCDV3H5HZiHJV2AE= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679290506551100001 Content-Type: text/plain; charset="utf-8" In function CreatePageTable(), Add code to initialize MapMask to 0. Missing the initialization doesn't cause functionality issue but looks confusing. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c | 1 + 1 file changed, 1 insertion(+) diff --git a/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c b/UefiCpuPk= g/Library/MpInitLib/X64/CreatePageTable.c index 05a40bb225..b631e82836 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c +++ b/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c @@ -37,6 +37,7 @@ CreatePageTable ( MapAttribute.Bits.Present =3D 1; MapAttribute.Bits.ReadWrite =3D 1; =20 + MapMask.Uint64 =3D 0; MapMask.Bits.PageTableBaseAddressLow =3D 1; MapMask.Bits.Present =3D 1; MapMask.Bits.ReadWrite =3D 1; --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101395): https://edk2.groups.io/g/devel/message/101395 Mute This Topic: https://groups.io/mt/97725713/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 26 15:40:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101396+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101396+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679290505; cv=none; d=zohomail.com; s=zohoarc; b=lDPdqyXkIZdatVy6Y2B+WzIdyBHX2xS9NtaiitmRGeA6dQ0hA9iNq/MaaWfDCMx99VoiBcokIovWp+cxq9hQv+bEOAW5joLJIf0opiO4cg+jzaqDxHA0/dIqgHWpOEzuNmHRUos+GjspKCVIXHhO1HIEJCvyynbNyFXoGOYw9u8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679290505; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=amcLlz86X03zWEdPYJ4tfvNmKCH/Vp3ycLDQjI05eCM=; b=OePkVQsD+bHI3+XA5w7x9eKg9WyKi0uUi1/x3aHthx9F+nxwogQABceX+ZDUPF/RkKci4ULIRFg8c82a8AZjM0kN8IFM6AfWtpmzVg8LERGo9BHxO1CIfbmIaRia+Xw/KCsggp/jrSG6IvFdDZILH64L58U2F7hKl7D6GMWQrTY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101396+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679290505571314.72184189136385; Sun, 19 Mar 2023 22:35:05 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id A5ZuYY1788612xlN6URZ7MAV; Sun, 19 Mar 2023 22:35:05 -0700 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web11.7471.1679290475232002420 for ; Sun, 19 Mar 2023 22:35:04 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="401155747" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="401155747" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:35:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="770059661" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="770059661" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:35:02 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar Subject: [edk2-devel] [Patch V3 16/18] UefiCpuPkg: Modify UnitTest code since tested API is changed Date: Mon, 20 Mar 2023 13:33:27 +0800 Message-Id: <20230320053329.410-17-dun.tan@intel.com> In-Reply-To: <20230320053329.410-1-dun.tan@intel.com> References: <20230320053329.410-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: bP10hosa1EmY2OVeqxCU30lxx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679290505; bh=2Gl6eVXyFdPb08H/i9PnRG7tt6DuDiZEyQuqtMsoouU=; h=Cc:Date:From:Reply-To:Subject:To; b=Fee7dJSbwqK8UfNtdxBSkgBZyqzuSQdfzg3qN+XDQOiXdLl3pZShx1QLj7JsNAObZGP vMGPvm1M9KXMq3uDO8N8EWpZh1xvKY4N0WGdBwmZP6hbS4hlIbGwt7CSpVV7Ne6wg6c/J JYDTfDpAiQ/xI3tXx2ZC1kxM5YZYP70KTqU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679290506641100005 Content-Type: text/plain; charset="utf-8" From: Zhiguang Liu Last commit changed the CpuPageTableLib API PageTableMap, unit test code should also be modified. Cc: Eric Dong Reviewed-by: Ray Ni Cc: Rahul Kumar Signed-off-by: Zhiguang Liu --- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c = | 38 ++++++++++++++++++-------------------- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c = | 84 +++++++++++++++++++++++++++++++++++++++++++++++-----------------------= -------------- UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c = | 4 ++-- 3 files changed, 67 insertions(+), 59 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUni= tTestHost.c b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUn= itTestHost.c index 6343b56c2f..e1efc84c82 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo= st.c @@ -422,15 +422,14 @@ TestCaseManualSizeNotMatch ( UINTN MapCount; IA32_PAGING_ENTRY *PagingEntry; =20 - PagingMode =3D Paging4Level; - PageTableBufferSize =3D 0; - PageTable =3D 0; - Buffer =3D NULL; - MapAttribute.Uint64 =3D 0; - MapMask.Uint64 =3D MAX_UINT64; - MapAttribute.Bits.Present =3D 1; - MapAttribute.Bits.ReadWrite =3D 1; - MapAttribute.Bits.PageTableBaseAddress =3D (SIZE_2MB - SIZE_4KB) >> 12; + PagingMode =3D Paging4Level; + PageTableBufferSize =3D 0; + PageTable =3D 0; + Buffer =3D NULL; + MapMask.Uint64 =3D MAX_UINT64; + MapAttribute.Uint64 =3D (SIZE_2MB - SIZE_4KB); + MapAttribute.Bits.Present =3D 1; + MapAttribute.Bits.ReadWrite =3D 1; // // Create Page table to cover [2M-4K, 4M], with ReadWrite =3D 1 // @@ -460,9 +459,9 @@ TestCaseManualSizeNotMatch ( // [2M-4K,2M], R/W =3D 0 // [2M ,4M], R/W =3D 1 // - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)PageTable; = // Get 4 level entry - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(PagingEntry->Pnle.B= its.PageTableBaseAddress << 12); // Get 3 level entry - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(PagingEntry->Pnle.B= its.PageTableBaseAddress << 12); // Get 2 level entry + PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)PageTable; = // Get 4 level entry + PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE= _BASE_ADDRESS (PagingEntry); // Get 3 level entry + PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE= _BASE_ADDRESS (PagingEntry); // Get 2 level entry PagingEntry->Uint64 =3D PagingEntry->Uint64 & (~(UINT64)0x2); MapCount =3D 0; Status =3D PageTableParse (PageTable, PagingMode, NULL, &Ma= pCount); @@ -480,20 +479,19 @@ TestCaseManualSizeNotMatch ( =20 UT_ASSERT_EQUAL (Map[1].LinearAddress, SIZE_2MB); UT_ASSERT_EQUAL (Map[1].Length, SIZE_2MB); - ExpectedMapAttribute.Uint64 =3D MapAttribute.Uint64; - ExpectedMapAttribute.Bits.ReadWrite =3D 1; - ExpectedMapAttribute.Bits.PageTableBaseAddress =3D SIZE_2MB >> 12; + ExpectedMapAttribute.Uint64 =3D MapAttribute.Uint64 + SIZE_4KB; + ExpectedMapAttribute.Bits.ReadWrite =3D 1; UT_ASSERT_EQUAL (Map[1].Attribute.Uint64, ExpectedMapAttribute.Uint64); =20 // // Set Page table [2M-4K, 2M+4K]'s ReadWrite =3D 1, [2M,2M+4K]'s ReadWri= te is already 1 // Just need to set [2M-4K,2M], won't need extra size, so the status sho= uld be success // - MapAttribute.Bits.Present =3D 1; - MapAttribute.Bits.ReadWrite =3D 1; - PageTableBufferSize =3D 0; - MapAttribute.Bits.PageTableBaseAddress =3D (SIZE_2MB - SIZE_4KB) >> 12; - Status =3D PageTableMap (&PageTable, Pag= ingMode, Buffer, &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB * 2, &= MapAttribute, &MapMask, NULL); + MapAttribute.Uint64 =3D SIZE_2MB - SIZE_4KB; + MapAttribute.Bits.Present =3D 1; + MapAttribute.Bits.ReadWrite =3D 1; + PageTableBufferSize =3D 0; + Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB * 2, &MapAttribut= e, &MapMask, NULL); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); return UNIT_TEST_PASSED; } diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c index 81dd9e5836..6b0f36dc1a 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c @@ -157,7 +157,8 @@ ValidateAndRandomeModifyPageTablePageTableEntry ( ) { UINT64 Index; - UINT64 TempPhysicalBase; + UINT32 PageTableBaseAddressLow; + UINT32 PageTableBaseAddressHigh; IA32_PAGING_ENTRY *ChildPageEntry; UNIT_TEST_STATUS Status; =20 @@ -180,17 +181,21 @@ ValidateAndRandomeModifyPageTablePageTableEntry ( if ((RandomNumber < 100) && RandomBoolean (50)) { RandomNumber++; if (Level =3D=3D 1) { - TempPhysicalBase =3D PagingEntry->Pte4K.Bits.PageTableBaseAddress; + PageTableBaseAddressLow =3D PagingEntry->Pte4K.Bits.PageTableBase= AddressLow; + PageTableBaseAddressHigh =3D PagingEntry->Pte4K.Bits.PageTableBase= AddressHigh; } else { - TempPhysicalBase =3D PagingEntry->PleB.Bits.PageTableBaseAddress; + PageTableBaseAddressLow =3D PagingEntry->PleB.Bits.PageTableBaseA= ddressLow; + PageTableBaseAddressHigh =3D PagingEntry->PleB.Bits.PageTableBaseA= ddressHigh; } =20 PagingEntry->Uint64 =3D (Random64 (0, MAX_UINT64) & mVal= idMaskLeaf[Level].Uint64) | mValidMaskLeafFlag[Level].Uint64; PagingEntry->Pte4K.Bits.Present =3D 1; if (Level =3D=3D 1) { - PagingEntry->Pte4K.Bits.PageTableBaseAddress =3D TempPhysicalBase; + PagingEntry->Pte4K.Bits.PageTableBaseAddressLow =3D PageTableBase= AddressLow; + PagingEntry->Pte4K.Bits.PageTableBaseAddressHigh =3D PageTableBase= AddressHigh; } else { - PagingEntry->PleB.Bits.PageTableBaseAddress =3D TempPhysicalBase; + PagingEntry->PleB.Bits.PageTableBaseAddressLow =3D PageTableBaseA= ddressLow; + PagingEntry->PleB.Bits.PageTableBaseAddressHigh =3D PageTableBaseA= ddressHigh; } =20 if ((PagingEntry->Uint64 & mValidMaskLeaf[Level].Uint64) !=3D Paging= Entry->Uint64) { @@ -212,15 +217,17 @@ ValidateAndRandomeModifyPageTablePageTableEntry ( =20 if ((RandomNumber < 100) && RandomBoolean (50)) { RandomNumber++; - TempPhysicalBase =3D PagingEntry->Pnle.Bits.PageTableBaseAddress; + PageTableBaseAddressLow =3D PagingEntry->PleB.Bits.PageTableBaseAddre= ssLow; + PageTableBaseAddressHigh =3D PagingEntry->PleB.Bits.PageTableBaseAddre= ssHigh; =20 - PagingEntry->Uint64 =3D Random64 (0, MAX_UINT6= 4) & mValidMaskNoLeaf[Level].Uint64; - PagingEntry->Pnle.Bits.Present =3D 1; - PagingEntry->Pnle.Bits.PageTableBaseAddress =3D TempPhysicalBase; + PagingEntry->Uint64 =3D Random64 (0, MAX_U= INT64) & mValidMaskNoLeaf[Level].Uint64; + PagingEntry->Pnle.Bits.Present =3D 1; + PagingEntry->PleB.Bits.PageTableBaseAddressLow =3D PageTableBaseAddre= ssLow; + PagingEntry->PleB.Bits.PageTableBaseAddressHigh =3D PageTableBaseAddre= ssHigh; ASSERT ((PagingEntry->Uint64 & mValidMaskLeafFlag[Level].Uint64) !=3D = mValidMaskLeafFlag[Level].Uint64); } =20 - ChildPageEntry =3D (IA32_PAGING_ENTRY *)(UINTN)((PagingEntry->Pnle.Bits= .PageTableBaseAddress) << 12); + ChildPageEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(IA32_PNLE_PAGE_TABLE_BA= SE_ADDRESS (&PagingEntry->Pnle)); for (Index =3D 0; Index < 512; Index++) { Status =3D ValidateAndRandomeModifyPageTablePageTableEntry (&ChildPage= Entry[Index], Level-1, MaxLeafLevel, Address + (Index<<(9*(Level-1) + 3))); if (Status !=3D UNIT_TEST_PASSED) { @@ -364,10 +371,12 @@ GenerateSingleRandomMapEntry ( } =20 if (mRandomOption & ONLY_ONE_ONE_MAPPING) { - MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress =3D Map= Entrys->Maps[MapsIndex].LinearAddress >> 12; - MapEntrys->Maps[MapsIndex].Mask.Bits.PageTableBaseAddress =3D 0xF= FFFFFFFFF; + MapEntrys->Maps[MapsIndex].Attribute.Uint64 &=3D (~IA32_MAP_ATTRIBUTE_= PAGE_TABLE_BASE_ADDRESS_MASK); + MapEntrys->Maps[MapsIndex].Attribute.Uint64 |=3D MapEntrys->Maps[MapsI= ndex].LinearAddress; + MapEntrys->Maps[MapsIndex].Mask.Uint64 |=3D IA32_MAP_ATTRIBUTE_PA= GE_TABLE_BASE_ADDRESS_MASK; } else { - MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress =3D (Ra= ndom64 (0, (((UINT64)1)<<52) - 1) & AlignedTable[Random32 (0, ARRAY_SIZE (A= lignedTable) -1)])>> 12; + MapEntrys->Maps[MapsIndex].Attribute.Uint64 &=3D (~IA32_MAP_ATTRIBUTE_= PAGE_TABLE_BASE_ADDRESS_MASK); + MapEntrys->Maps[MapsIndex].Attribute.Uint64 |=3D (Random64 (0, (((UINT= 64)1)<<52) - 1) & AlignedTable[Random32 (0, ARRAY_SIZE (AlignedTable) -1)]); } =20 MapEntrys->Count +=3D 1; @@ -414,8 +423,9 @@ CompareEntrysforOnePoint ( // for (Index =3D 0; Index < MapCount; Index++) { if ((Address >=3D Map[Index].LinearAddress) && (Address < (Map[Index].= LinearAddress + Map[Index].Length))) { - AttributeInMap.Uint64 =3D (Map[Index].Attribute.U= int64 & mSupportedBit.Uint64); - AttributeInMap.Bits.PageTableBaseAddress =3D ((Address - Map[Index].= LinearAddress) >> 12) + Map[Index].Attribute.Bits.PageTableBaseAddress; + AttributeInMap.Uint64 =3D (Map[Index].Attribute.Uint64 & mSupported= Bit.Uint64); + AttributeInMap.Uint64 &=3D (~IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDR= ESS_MASK); + AttributeInMap.Uint64 |=3D (Address - Map[Index].LinearAddress + IA3= 2_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&Map[Index].Attribute)) & IA32_MAP= _ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK; break; } } @@ -425,8 +435,10 @@ CompareEntrysforOnePoint ( // for (Index =3D 0; Index < InitMapCount; Index++) { if ((Address >=3D InitMap[Index].LinearAddress) && (Address < (InitMap= [Index].LinearAddress + InitMap[Index].Length))) { - AttributeInInitMap.Uint64 =3D (InitMap[Index].Att= ribute.Uint64 & mSupportedBit.Uint64); - AttributeInInitMap.Bits.PageTableBaseAddress =3D ((Address - InitMap= [Index].LinearAddress) >> 12) + InitMap[Index].Attribute.Bits.PageTableBase= Address; + AttributeInInitMap.Uint64 =3D (InitMap[Index].Attribute.Uint64 & mS= upportedBit.Uint64); + AttributeInInitMap.Uint64 &=3D (~IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_= ADDRESS_MASK); + AttributeInInitMap.Uint64 |=3D (Address - InitMap[Index].LinearAddre= ss + IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&InitMap[Index].Attribute)= ) & IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK; + break; } } @@ -443,8 +455,9 @@ CompareEntrysforOnePoint ( MaskInMapEntrys.Uint64 |=3D MapEntrys->Maps[Index].Mask.Uint64; AttributeInMapEntrys.Uint64 &=3D (~MapEntrys->Maps[Index].Mask.Uint6= 4); AttributeInMapEntrys.Uint64 |=3D (MapEntrys->Maps[Index].Attribute.= Uint64 & MapEntrys->Maps[Index].Mask.Uint64); - if (MapEntrys->Maps[Index].Mask.Bits.PageTableBaseAddress !=3D 0) { - AttributeInMapEntrys.Bits.PageTableBaseAddress =3D ((Address - Map= Entrys->Maps[Index].LinearAddress) >> 12) + MapEntrys->Maps[Index].Attribut= e.Bits.PageTableBaseAddress; + if (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&MapEntrys->Maps[Ind= ex].Mask) !=3D 0) { + AttributeInMapEntrys.Uint64 &=3D (~IA32_MAP_ATTRIBUTE_PAGE_TABLE_B= ASE_ADDRESS_MASK); + AttributeInMapEntrys.Uint64 |=3D (Address - MapEntrys->Maps[Index]= .LinearAddress + IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&MapEntrys->Ma= ps[Index].Attribute)) & IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK; } } } @@ -458,8 +471,8 @@ CompareEntrysforOnePoint ( if ((AttributeInMap.Uint64 & MaskInMapEntrys.Uint64) !=3D (AttributeInMa= pEntrys.Uint64 & MaskInMapEntrys.Uint64)) { DEBUG ((DEBUG_INFO, "=3D=3D=3D=3D=3D=3Ddetailed information begin=3D= =3D=3D=3D=3D\n")); DEBUG ((DEBUG_INFO, "\nError: Detect different attribute on a point wi= th linear address: 0x%lx\n", Address)); - DEBUG ((DEBUG_INFO, "By parsing page table, the point has Attribute 0x= %lx, and map to physical address 0x%lx\n", IA32_MAP_ATTRIBUTE_ATTRIBUTES (&= AttributeInMap) & MaskInMapEntrys.Uint64, AttributeInMap.Bits.PageTableBase= Address)); - DEBUG ((DEBUG_INFO, "While according to inputs, the point should Attri= bute 0x%lx, and should map to physical address 0x%lx\n", IA32_MAP_ATTRIBUTE= _ATTRIBUTES (&AttributeInMapEntrys) & MaskInMapEntrys.Uint64, AttributeInMa= pEntrys.Bits.PageTableBaseAddress)); + DEBUG ((DEBUG_INFO, "By parsing page table, the point has Attribute 0x= %lx, and map to physical address 0x%lx\n", IA32_MAP_ATTRIBUTE_ATTRIBUTES (&= AttributeInMap) & MaskInMapEntrys.Uint64, IA32_MAP_ATTRIBUTE_PAGE_TABLE_BAS= E_ADDRESS (&AttributeInMap))); + DEBUG ((DEBUG_INFO, "While according to inputs, the point should Attri= bute 0x%lx, and should map to physical address 0x%lx\n", IA32_MAP_ATTRIBUTE= _ATTRIBUTES (&AttributeInMapEntrys) & MaskInMapEntrys.Uint64, IA32_MAP_ATTR= IBUTE_PAGE_TABLE_BASE_ADDRESS (&AttributeInMapEntrys))); DEBUG ((DEBUG_INFO, "The total Mask is 0x%lx\n", MaskInMapEntrys.Uint6= 4)); =20 if (MapEntrys->InitCount !=3D 0) { @@ -727,7 +740,7 @@ SingleMapEntryTest ( // if ((Mask->Bits.ReadWrite =3D=3D 0) || (Mask->Bits.UserSupervisor = =3D=3D 0) || (Mask->Bits.WriteThrough =3D=3D 0) || (Mask->Bits.CacheDisable= d =3D=3D 0) || (Mask->Bits.Accessed =3D=3D 0) || (Mask->Bits.Dirty =3D=3D 0) ||= (Mask->Bits.Pat =3D=3D 0) || (Mask->Bits.Global =3D=3D 0) || - (Mask->Bits.PageTableBaseAddress =3D=3D 0) || (Mask->Bits.Protec= tionKey =3D=3D 0) || (Mask->Bits.Nx =3D=3D 0)) + ((Mask->Bits.PageTableBaseAddressLow =3D=3D 0) && (Mask->Bits.Pa= geTableBaseAddressHigh =3D=3D 0)) || (Mask->Bits.ProtectionKey =3D=3D 0) ||= (Mask->Bits.Nx =3D=3D 0)) { RemoveLastMapEntry (MapEntrys); UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); @@ -1012,21 +1025,18 @@ TestCaseforRandomTest ( UT_ASSERT_EQUAL (Random64 (100, 100), 100); UT_ASSERT_TRUE ((Random32 (9, 10) >=3D 9) & (Random32 (9, 10) <=3D 10)); UT_ASSERT_TRUE ((Random64 (9, 10) >=3D 9) & (Random64 (9, 10) <=3D 10)); - - mSupportedBit.Bits.Present =3D 1; - mSupportedBit.Bits.ReadWrite =3D 1; - mSupportedBit.Bits.UserSupervisor =3D 1; - mSupportedBit.Bits.WriteThrough =3D 1; - mSupportedBit.Bits.CacheDisabled =3D 1; - mSupportedBit.Bits.Accessed =3D 1; - mSupportedBit.Bits.Dirty =3D 1; - mSupportedBit.Bits.Pat =3D 1; - mSupportedBit.Bits.Global =3D 1; - mSupportedBit.Bits.Reserved1 =3D 0; - mSupportedBit.Bits.PageTableBaseAddress =3D 0; - mSupportedBit.Bits.Reserved2 =3D 0; - mSupportedBit.Bits.ProtectionKey =3D 0xF; - mSupportedBit.Bits.Nx =3D 1; + mSupportedBit.Uint64 =3D 0; + mSupportedBit.Bits.Present =3D 1; + mSupportedBit.Bits.ReadWrite =3D 1; + mSupportedBit.Bits.UserSupervisor =3D 1; + mSupportedBit.Bits.WriteThrough =3D 1; + mSupportedBit.Bits.CacheDisabled =3D 1; + mSupportedBit.Bits.Accessed =3D 1; + mSupportedBit.Bits.Dirty =3D 1; + mSupportedBit.Bits.Pat =3D 1; + mSupportedBit.Bits.Global =3D 1; + mSupportedBit.Bits.ProtectionKey =3D 0xF; + mSupportedBit.Bits.Nx =3D 1; =20 mRandomOption =3D ((CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT *)Context)->R= andomOption; mNumberIndex =3D 0; diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c b/Uef= iCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c index 10fdee2f94..22f179c21f 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c @@ -140,7 +140,7 @@ IsPageTableEntryValid ( UT_ASSERT_EQUAL ((PagingEntry->Uint64 & mValidMaskNoLeaf[Level].Uint64= ), PagingEntry->Uint64); } =20 - ChildPageEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(((UINTN)(PagingEntry->P= nle.Bits.PageTableBaseAddress)) << 12); + ChildPageEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(IA32_PNLE_PAGE_TABLE_BA= SE_ADDRESS (&PagingEntry->Pnle)); for (Index =3D 0; Index < 512; Index++) { Status =3D IsPageTableEntryValid (&ChildPageEntry[Index], Level-1, Max= LeafLevel, Address + (Index<<(9*(Level-1) + 3))); if (Status !=3D UNIT_TEST_PASSED) { @@ -233,7 +233,7 @@ GetEntryFromSubPageTable ( // // Not a leaf // - ChildPageEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(((UINTN)(PagingEntry->P= nle.Bits.PageTableBaseAddress)) << 12); + ChildPageEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(IA32_PNLE_PAGE_TABLE_BA= SE_ADDRESS (&PagingEntry->Pnle)); *Level =3D *Level -1; Index =3D Address >> (*Level * 9 + 3); ASSERT (Index =3D=3D (Index & ((1<< 9) - 1))); --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101396): https://edk2.groups.io/g/devel/message/101396 Mute This Topic: https://groups.io/mt/97725714/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 26 15:40:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101397+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101397+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679290507; cv=none; d=zohomail.com; s=zohoarc; b=VZG/0M++fq4qtNAEP7k4n70RVLNVnfM0pqxiArcR24rxYz7QnqTcJ39TCTsYATHccYnhhKb5gT+JyYITx2E7LGPIDWWq/1kCcovAl3OTKA5aJmQ1UekOctSAYhHW+5NsekqYfLxHqFFF81T7gt9jslM0aBlzxYuCtQPhLlh8GHs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679290507; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=rjR2+XKSz0eFE84oRsvgzTzyfK6fMXQ8yipwr7oO5YQ=; b=SKSylPZ1gOucevzgWH8sRWkJuBo8Z8hscKqhQ3/55NPJm9j8/d+kCrvdLKXk4XruXN7SjFPEn8e+EHg8PlQbHDn5vYLRcpxHbsS1gkNQwgaQ/g7My3Wae4wPNxwM3vZ3PZCF6ch+DPAqH7oX3XUzvoPF3BraEA/CSHM6bqaVa+U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101397+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679290507776361.52987054986636; Sun, 19 Mar 2023 22:35:07 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 3mdiYY1788612xsbVZIBquqh; Sun, 19 Mar 2023 22:35:07 -0700 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web11.7471.1679290475232002420 for ; Sun, 19 Mar 2023 22:35:06 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="401155770" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="401155770" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:35:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="770059676" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="770059676" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:35:04 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V3 17/18] UefiCpuPkg/CpuPageTableLib: Add check for page table creation Date: Mon, 20 Mar 2023 13:33:28 +0800 Message-Id: <20230320053329.410-18-dun.tan@intel.com> In-Reply-To: <20230320053329.410-1-dun.tan@intel.com> References: <20230320053329.410-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: cjuG77vpWmYeVb9BTLx8Frzox1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679290507; bh=I4TTdKpxWdxqEJxscWGl6J9N5qE0DWIOKEUKneXwrXo=; h=Cc:Date:From:Reply-To:Subject:To; b=jUPKc13+mpGHpSXUJ1bUxX+AVgV84N7Lunu6KiWr+2gaPc6pvvW2UsgSbqNIeQmsAJ5 grscV1+wPsfDR9ruG0KPL893X5tPuvMXpproByOFzeqtg2FFlWgMN+3MiUK+0UPyo76RN s9vRtyOL4y7SSTg9AvZN5SrbK6XyaUYSb3g= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679290508630100009 Content-Type: text/plain; charset="utf-8" Add code to compare ParentPagingEntry Attribute&Mask and input Attribute&Mask to decide if new next level page table is needed in non-present ParentPagingEntry condition. This can help avoid unneccessary page table creation. For example, there is a page table in which [0, 1G] is mapped(Lv4[0] ,Lv3[0,0], a non-leaf level4 entry and a leaf level3 entry).And we only want to map [1G, 1G+2M] linear address still as non-present. The expected behaviour should be nothing happens in the process. However, previous code logic doesn't check if ParentPagingEntry Attribute&Mask and input Attribute&Mask are the same in non-present ParentPagingEntry condition. Then a new 4K memory is allocated for Lv2 since 1G+2M is not 1G-aligned. So when ParentPagingEntry is non-present, before allocate 4K memory for next level paging, we also check if ParentPagingEntry Attribute& Mask and input Attribute&Mask are the same. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 18 ++++++++++++++++= ++ 1 file changed, 18 insertions(+) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index fbfd6389dc..29191d26b5 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -355,6 +355,24 @@ PageTableLibMapInLevel ( return Status; } =20 + // + // Use NOP attributes as the attribute of grand-parents because CPU wi= ll consider + // the actual attributes of grand-parents when determing the memory ty= pe. + // + PleBAttribute.Uint64 =3D PageTableLibGetPleBMapAttribute (&ParentPagin= gEntry->PleB, ParentAttribute); + if ((((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRI= BUTE_ATTRIBUTES (Mask)) + =3D=3D (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATT= RIBUTE_ATTRIBUTES (Mask)))) && + ( ((Mask->Bits.PageTableBaseAddressLow =3D=3D 0) && (Mask->Bits.P= ageTableBaseAddressHigh =3D=3D 0)) + || ((IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&PleBAttribute) += PagingEntryIndex * RegionLength) + =3D=3D (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute)= + Offset)))) + { + // + // This function is called when the memory length is less than the r= egion length of the parent level. + // No need to split the page when the attributes equal. + // + return RETURN_SUCCESS; + } + // // The parent entry is CR3 or PML5E/PML4E/PDPTE/PDE. // It does NOT point to an existing page directory. --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101397): https://edk2.groups.io/g/devel/message/101397 Mute This Topic: https://groups.io/mt/97725715/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 26 15:40:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101398+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101398+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1679290509; cv=none; d=zohomail.com; s=zohoarc; b=VKLqN5FM1K/PmpFZaM//zKQw9S3ICyqsPosgxQegPVwK4WrQH3RGCvEMxGISr1cLZPSUyVZSJgH5P+WuboXNJSLfTCbyE9jgkyz9EHLJ7bMl3hDEH3Z9d7hxiXjPTVSgzR8AbxSrEq2mYhoDKbXMhFFXJhA1owNgumR02Dc+BLY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679290509; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=5W8mg/jX5LQf6xZZiRK5GXMtt/YBUbkIA/OvCTYusjU=; b=GB57l74CmvFb2FhQoZBDC+lVjEEMdB1q4hXRnDFGkbyHjAv+DPlo7/DvufIxRxYG5YKYNenKXTFF6+picZiUzG5Fg82ecw+D4/61Xq/wBll6JvI2weExUslf64HdvPg4/JUgQHPyMI8QjC9d/cO5Tdvi90l+NQZobD4j913F7to= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101398+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1679290509835375.5240425043462; Sun, 19 Mar 2023 22:35:09 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 5bAIYY1788612xrPzjZfPLSK; Sun, 19 Mar 2023 22:35:09 -0700 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web11.7471.1679290475232002420 for ; Sun, 19 Mar 2023 22:35:09 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="401155796" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="401155796" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:35:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10654"; a="770059695" X-IronPort-AV: E=Sophos;i="5.98,274,1673942400"; d="scan'208";a="770059695" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2023 22:35:07 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V3 18/18] UefiCpuPkg: Combine branch for non-present and leaf ParentEntry Date: Mon, 20 Mar 2023 13:33:29 +0800 Message-Id: <20230320053329.410-19-dun.tan@intel.com> In-Reply-To: <20230320053329.410-1-dun.tan@intel.com> References: <20230320053329.410-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: NtcYigj31hYwOezfOdyVdBc4x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1679290509; bh=yR1vvWDO3om9A0+pytyYqN6xrJFk/IUqU5KeOyagfGQ=; h=Cc:Date:From:Reply-To:Subject:To; b=E+HXYbmUSmBxNLbEl9Maykp8nXIpV6tXn+z2ellA+CD+VDBbapYpNH8M84qFEePIlPa JR8A7Tc/Vi+Ye8W/XIt5TXP5ItFlwMKmoNSOjHd9hSTumCFi7TFxbai673qz9anpLq41g sSLgBmddUQjvID2appa3Dsd8sfvC25LZkyw= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1679290510632100013 Content-Type: text/plain; charset="utf-8" Combine the 'if' condition branch for non-present and leaf Parent Entry in PageTableLibMapInLevel. Most steps of these two condition are the same. This commit doesn't change any functionality. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 76 ++++++++++++++++= ++++++------------------------------------------------------ 1 file changed, 22 insertions(+), 54 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index 29191d26b5..3e7cc2839f 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -345,65 +345,32 @@ PageTableLibMapInLevel ( // ParentPagingEntry ONLY is deferenced for checking Present and MustBeO= ne bits // when Modify is FALSE. // - - if (ParentPagingEntry->Pce.Present =3D=3D 0) { - // - // [LinearAddress, LinearAddress + Length] contains non-present range. - // - Status =3D IsAttributesAndMaskValidForNonPresentEntry (Attribute, Mask= ); - if (RETURN_ERROR (Status)) { - return Status; - } - - // - // Use NOP attributes as the attribute of grand-parents because CPU wi= ll consider - // the actual attributes of grand-parents when determing the memory ty= pe. - // - PleBAttribute.Uint64 =3D PageTableLibGetPleBMapAttribute (&ParentPagin= gEntry->PleB, ParentAttribute); - if ((((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRI= BUTE_ATTRIBUTES (Mask)) - =3D=3D (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATT= RIBUTE_ATTRIBUTES (Mask)))) && - ( ((Mask->Bits.PageTableBaseAddressLow =3D=3D 0) && (Mask->Bits.P= ageTableBaseAddressHigh =3D=3D 0)) - || ((IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&PleBAttribute) += PagingEntryIndex * RegionLength) - =3D=3D (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute)= + Offset)))) - { - // - // This function is called when the memory length is less than the r= egion length of the parent level. - // No need to split the page when the attributes equal. - // - return RETURN_SUCCESS; - } - + if ((ParentPagingEntry->Pce.Present =3D=3D 0) || IsPle (ParentPagingEntr= y, Level + 1)) { // - // The parent entry is CR3 or PML5E/PML4E/PDPTE/PDE. + // When ParentPagingEntry is non-present, parent entry is CR3 or PML5E= /PML4E/PDPTE/PDE. // It does NOT point to an existing page directory. + // When ParentPagingEntry is present, parent entry is leaf PDPTE_1G or= PDE_2M. Split to 2M or 4K pages. + // Note: it's impossible the parent entry is a PTE_4K. // - ASSERT (Buffer =3D=3D NULL || *BufferSize >=3D SIZE_4KB); - CreateNew =3D TRUE; - *BufferSize -=3D SIZE_4KB; + OneOfPagingEntry.Pnle.Uint64 =3D 0; + PleBAttribute.Uint64 =3D PageTableLibGetPleBMapAttribute (&Par= entPagingEntry->PleB, ParentAttribute); =20 - if (Modify) { - ParentPagingEntry->Uintn =3D (UINTN)Buffer + *BufferSize; - ZeroMem ((VOID *)ParentPagingEntry->Uintn, SIZE_4KB); + if (ParentPagingEntry->Pce.Present =3D=3D 0) { // - // Set default attribute bits for PML5E/PML4E/PDPTE/PDE. + // [LinearAddress, LinearAddress + Length] contains non-present rang= e. // - PageTableLibSetPnle (&ParentPagingEntry->Pnle, &NopAttribute, &AllOn= eMask); + Status =3D IsAttributesAndMaskValidForNonPresentEntry (Attribute, Ma= sk); + if (RETURN_ERROR (Status)) { + return Status; + } } else { - // - // Just make sure Present and MustBeZero (PageSize) bits are accurat= e. - // - OneOfPagingEntry.Pnle.Uint64 =3D 0; + PageTableLibSetPle (Level, &OneOfPagingEntry, 0, &PleBAttribute, &Al= lOneMask); } - } else if (IsPle (ParentPagingEntry, Level + 1)) { - // - // The parent entry is a PDPTE_1G or PDE_2M. Split to 2M or 4K pages. - // Note: it's impossible the parent entry is a PTE_4K. - // + // // Use NOP attributes as the attribute of grand-parents because CPU wi= ll consider // the actual attributes of grand-parents when determing the memory ty= pe. // - PleBAttribute.Uint64 =3D PageTableLibGetPleBMapAttribute (&ParentPagin= gEntry->PleB, ParentAttribute); if ((((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRI= BUTE_ATTRIBUTES (Mask)) =3D=3D (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATT= RIBUTE_ATTRIBUTES (Mask)))) && ( ((Mask->Bits.PageTableBaseAddressLow =3D=3D 0) && (Mask->Bits.P= ageTableBaseAddressHigh =3D=3D 0)) @@ -420,17 +387,18 @@ PageTableLibMapInLevel ( ASSERT (Buffer =3D=3D NULL || *BufferSize >=3D SIZE_4KB); CreateNew =3D TRUE; *BufferSize -=3D SIZE_4KB; - PageTableLibSetPle (Level, &OneOfPagingEntry, 0, &PleBAttribute, &AllO= neMask); if (Modify) { - // - // Create 512 child-level entries that map to 2M/4K. - // PagingEntry =3D (IA32_PAGING_ENTRY *)((UINTN)Buffer + *BufferSize); ZeroMem (PagingEntry, SIZE_4KB); =20 - for (SubOffset =3D 0, Index =3D 0; Index < 512; Index++) { - PagingEntry[Index].Uint64 =3D OneOfPagingEntry.Uint64 + SubOffset; - SubOffset +=3D RegionLength; + if (ParentPagingEntry->Pce.Present) { + // + // Create 512 child-level entries that map to 2M/4K. + // + for (SubOffset =3D 0, Index =3D 0; Index < 512; Index++) { + PagingEntry[Index].Uint64 =3D OneOfPagingEntry.Uint64 + SubOffse= t; + SubOffset +=3D RegionLength; + } } =20 // --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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