From nobody Fri Oct 25 15:40:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101108+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101108+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1678727865; cv=none; d=zohomail.com; s=zohoarc; b=H4gkH9vx/bW+bX1X3NPPy/K8TYfeNE4nGH9+57mhHVQqtR786idAPYdRwVQAtTN6M7Ir9Ih4M4558B5o26XoiLIzHLFK8tV0tS0z1DhP8g9og9mqCiMC581daI72aiBsNKu4w2ibnOzJVZIwYttEAn1n1whPZ6Q1kDAD/TcAhAc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678727865; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=c/RIZ9RHZyJHjGN0RTdg6CWhY2hHQbhrKrv3okSovyI=; b=jftz1hmwtpbELvwh1C5EfnjNg7l7I7eL8CmSZFkYSh0G2jPY8Urg+A4bLzKNVGSSQA9oBmU3M52kcO5d6aUc0yujRsHdnNcjlQEa5EM7ZkPT6ZrWfYM46Cq0u7gqJNCAdpNUUBkiL2OzVIvZciOb8KgwA58PtSP9kdj33QKCZxc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101108+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1678727865945749.3697101941933; Mon, 13 Mar 2023 10:17:45 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 8DTJYY1788612xQqDjuZif6q; Mon, 13 Mar 2023 10:17:45 -0700 X-Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by mx.groups.io with SMTP id smtpd.web10.25782.1678727864999019556 for ; Mon, 13 Mar 2023 10:17:45 -0700 X-Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 74A066145C; Mon, 13 Mar 2023 17:17:44 +0000 (UTC) X-Received: by smtp.kernel.org (Postfix) with ESMTPSA id E172AC433EF; Mon, 13 Mar 2023 17:17:41 +0000 (UTC) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Michael Kinney , Liming Gao , Jiewen Yao , Michael Kubacki , Sean Brogan , Rebecca Cran , Leif Lindholm , Sami Mujawar , Taylor Beebe Subject: [edk2-devel] [PATCH v5 04/38] ArmPkg/ArmMmuLib ARM: Isolate the access flag from AP mask Date: Mon, 13 Mar 2023 18:16:40 +0100 Message-Id: <20230313171714.3866151-5-ardb@kernel.org> In-Reply-To: <20230313171714.3866151-1-ardb@kernel.org> References: <20230313171714.3866151-1-ardb@kernel.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ardb@kernel.org X-Gm-Message-State: IY5kvSsmhDRfoNdaEhDvtRTpx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1678727865; bh=i8kXR25bs1dvy6KOkgSzRy8e+aC/PrMn9UBAuBzGtpY=; h=Cc:Date:From:Reply-To:Subject:To; b=YkEUxw+DFAU2f5AE2FBcfsSpWMhQn5YfN0Jpsvt2IQQf304HUffCTQHv4tu//WYzJkA QfWCJNkD6bZpA0zSPJTknWvaa5qOl8zGgH28BZjuGmMJTZc/1bp+DSPyL/xS9TsMwVfCg 1MjfMgc5uFzOl6TLSJ+ua2SfNY2Nr0xC0YQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1678727867926100001 Content-Type: text/plain; charset="utf-8" Split the ARM permission fields in the short descriptors into an access flag and AP[2:1] as per the recommendation in the ARM ARM. This makes the access flag available separately, which allows us to implement EFI_MEMORY_RP memory analogous to how it will be implemented for AArch64. Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Drivers/CpuDxe/Arm/Mmu.c | 47 ++++++++++---------- ArmPkg/Include/Chipset/ArmV7Mmu.h | 40 +++++++++++------ ArmPkg/Library/ArmLib/Arm/ArmV7Support.S | 2 + ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c | 1 + ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c | 12 ++++- 5 files changed, 63 insertions(+), 39 deletions(-) diff --git a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c b/ArmPkg/Drivers/CpuDxe/Arm/Mm= u.c index 8eb1f71395f5..07faab8216ec 100644 --- a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c @@ -50,30 +50,27 @@ SectionToGcdAttributes ( =20 // determine protection attributes switch (SectionAttributes & TT_DESCRIPTOR_SECTION_AP_MASK) { - case TT_DESCRIPTOR_SECTION_AP_NO_NO: // no read, no write - // *GcdAttributes |=3D EFI_MEMORY_RO | EFI_MEMORY_RP; - break; - - case TT_DESCRIPTOR_SECTION_AP_RW_NO: + case TT_DESCRIPTOR_SECTION_AP_NO_RW: case TT_DESCRIPTOR_SECTION_AP_RW_RW: // normal read/write access, do not add additional attributes break; =20 // read only cases map to write-protect - case TT_DESCRIPTOR_SECTION_AP_RO_NO: + case TT_DESCRIPTOR_SECTION_AP_NO_RO: case TT_DESCRIPTOR_SECTION_AP_RO_RO: *GcdAttributes |=3D EFI_MEMORY_RO; break; - - default: - return EFI_UNSUPPORTED; } =20 // now process eXectue Never attribute - if ((SectionAttributes & TT_DESCRIPTOR_SECTION_XN_MASK) !=3D 0 ) { + if ((SectionAttributes & TT_DESCRIPTOR_SECTION_XN_MASK) !=3D 0) { *GcdAttributes |=3D EFI_MEMORY_XP; } =20 + if ((SectionAttributes & TT_DESCRIPTOR_SECTION_AF) =3D=3D 0) { + *GcdAttributes |=3D EFI_MEMORY_RP; + } + return EFI_SUCCESS; } =20 @@ -114,30 +111,27 @@ PageToGcdAttributes ( =20 // determine protection attributes switch (PageAttributes & TT_DESCRIPTOR_PAGE_AP_MASK) { - case TT_DESCRIPTOR_PAGE_AP_NO_NO: // no read, no write - // *GcdAttributes |=3D EFI_MEMORY_RO | EFI_MEMORY_RP; - break; - - case TT_DESCRIPTOR_PAGE_AP_RW_NO: + case TT_DESCRIPTOR_PAGE_AP_NO_RW: case TT_DESCRIPTOR_PAGE_AP_RW_RW: // normal read/write access, do not add additional attributes break; =20 // read only cases map to write-protect - case TT_DESCRIPTOR_PAGE_AP_RO_NO: + case TT_DESCRIPTOR_PAGE_AP_NO_RO: case TT_DESCRIPTOR_PAGE_AP_RO_RO: *GcdAttributes |=3D EFI_MEMORY_RO; break; - - default: - return EFI_UNSUPPORTED; } =20 // now process eXectue Never attribute - if ((PageAttributes & TT_DESCRIPTOR_PAGE_XN_MASK) !=3D 0 ) { + if ((PageAttributes & TT_DESCRIPTOR_PAGE_XN_MASK) !=3D 0) { *GcdAttributes |=3D EFI_MEMORY_XP; } =20 + if ((PageAttributes & TT_DESCRIPTOR_PAGE_AF) =3D=3D 0) { + *GcdAttributes |=3D EFI_MEMORY_RP; + } + return EFI_SUCCESS; } =20 @@ -166,6 +160,7 @@ SyncCacheConfigPage ( // Convert SectionAttributes into PageAttributes NextPageAttributes =3D TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (*NextSectionAttributes) | + TT_DESCRIPTOR_CONVERT_TO_PAGE_AF (*NextSectionAttributes) | TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (*NextSectionAttributes); =20 // obtain page table base @@ -174,7 +169,7 @@ SyncCacheConfigPage ( for (i =3D 0; i < TRANSLATION_TABLE_PAGE_COUNT; i++) { if ((SecondLevelTable[i] & TT_DESCRIPTOR_PAGE_TYPE_MASK) =3D=3D TT_DES= CRIPTOR_PAGE_TYPE_PAGE) { // extract attributes (cacheability and permissions) - PageAttributes =3D SecondLevelTable[i] & (TT_DESCRIPTOR_PAGE_CACHE_P= OLICY_MASK | TT_DESCRIPTOR_PAGE_AP_MASK); + PageAttributes =3D SecondLevelTable[i] & (TT_DESCRIPTOR_PAGE_CACHE_P= OLICY_MASK | TT_DESCRIPTOR_PAGE_AP_MASK | TT_DESCRIPTOR_PAGE_AF); =20 if (NextPageAttributes =3D=3D 0) { // start on a new region @@ -213,6 +208,7 @@ SyncCacheConfigPage ( // Convert back PageAttributes into SectionAttributes *NextSectionAttributes =3D TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY (NextPageAttributes) | + TT_DESCRIPTOR_CONVERT_TO_SECTION_AF (NextPageAttributes) | TT_DESCRIPTOR_CONVERT_TO_SECTION_AP (NextPageAttributes); =20 return EFI_SUCCESS; @@ -256,14 +252,14 @@ SyncCacheConfig ( FirstLevelTable =3D (ARM_FIRST_LEVEL_DESCRIPTOR *)(ArmGetTTBR0BaseAddres= s ()); =20 // Get the first region - NextSectionAttributes =3D FirstLevelTable[0] & (TT_DESCRIPTOR_SECTION_CA= CHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK); + NextSectionAttributes =3D FirstLevelTable[0] & (TT_DESCRIPTOR_SECTION_CA= CHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK | TT_DESCRIPTOR_SECTION_AF); =20 // iterate through each 1MB descriptor NextRegionBase =3D NextRegionLength =3D 0; for (i =3D 0; i < TRANSLATION_TABLE_SECTION_COUNT; i++) { if ((FirstLevelTable[i] & TT_DESCRIPTOR_SECTION_TYPE_MASK) =3D=3D TT_D= ESCRIPTOR_SECTION_TYPE_SECTION) { // extract attributes (cacheability and permissions) - SectionAttributes =3D FirstLevelTable[i] & (TT_DESCRIPTOR_SECTION_CA= CHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK); + SectionAttributes =3D FirstLevelTable[i] & (TT_DESCRIPTOR_SECTION_CA= CHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK | TT_DESCRIPTOR_SECTION_AF); =20 if (NextSectionAttributes =3D=3D 0) { // start on a new region @@ -383,6 +379,10 @@ EfiAttributeToArmAttribute ( ArmAttributes |=3D TT_DESCRIPTOR_SECTION_XN_MASK; } =20 + if ((EfiAttributes & EFI_MEMORY_RP) =3D=3D 0) { + ArmAttributes |=3D TT_DESCRIPTOR_SECTION_AF; + } + return ArmAttributes; } =20 @@ -482,6 +482,7 @@ GetMemoryRegion ( *RegionAttributes =3D TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY (P= ageAttributes) | TT_DESCRIPTOR_CONVERT_TO_SECTION_S (PageAttributes= ) | TT_DESCRIPTOR_CONVERT_TO_SECTION_XN (PageAttribute= s) | + TT_DESCRIPTOR_CONVERT_TO_SECTION_AF (PageAttribute= s) | TT_DESCRIPTOR_CONVERT_TO_SECTION_AP (PageAttribute= s); } =20 diff --git a/ArmPkg/Include/Chipset/ArmV7Mmu.h b/ArmPkg/Include/Chipset/Arm= V7Mmu.h index e0219747df86..da4f3160f8ff 100644 --- a/ArmPkg/Include/Chipset/ArmV7Mmu.h +++ b/ArmPkg/Include/Chipset/ArmV7Mmu.h @@ -80,21 +80,21 @@ #define TT_DESCRIPTOR_PAGE_S_NOT_SHARED (0UL << 10) #define TT_DESCRIPTOR_PAGE_S_SHARED (1UL << 10) =20 -#define TT_DESCRIPTOR_SECTION_AP_MASK ((1UL << 15) | (3UL << 10)) -#define TT_DESCRIPTOR_SECTION_AP_NO_NO ((0UL << 15) | (0UL << 10)) -#define TT_DESCRIPTOR_SECTION_AP_RW_NO ((0UL << 15) | (1UL << 10)) -#define TT_DESCRIPTOR_SECTION_AP_RW_RO ((0UL << 15) | (2UL << 10)) -#define TT_DESCRIPTOR_SECTION_AP_RW_RW ((0UL << 15) | (3UL << 10)) -#define TT_DESCRIPTOR_SECTION_AP_RO_NO ((1UL << 15) | (1UL << 10)) -#define TT_DESCRIPTOR_SECTION_AP_RO_RO ((1UL << 15) | (3UL << 10)) +#define TT_DESCRIPTOR_SECTION_AP_MASK ((1UL << 15) | (1UL << 11)) +#define TT_DESCRIPTOR_SECTION_AP_NO_RW ((0UL << 15) | (0UL << 11)) +#define TT_DESCRIPTOR_SECTION_AP_RW_RW ((0UL << 15) | (1UL << 11)) +#define TT_DESCRIPTOR_SECTION_AP_NO_RO ((1UL << 15) | (0UL << 11)) +#define TT_DESCRIPTOR_SECTION_AP_RO_RO ((1UL << 15) | (1UL << 11)) =20 -#define TT_DESCRIPTOR_PAGE_AP_MASK ((1UL << 9) | (3UL << 4)) -#define TT_DESCRIPTOR_PAGE_AP_NO_NO ((0UL << 9) | (0UL << 4)) -#define TT_DESCRIPTOR_PAGE_AP_RW_NO ((0UL << 9) | (1UL << 4)) -#define TT_DESCRIPTOR_PAGE_AP_RW_RO ((0UL << 9) | (2UL << 4)) -#define TT_DESCRIPTOR_PAGE_AP_RW_RW ((0UL << 9) | (3UL << 4)) -#define TT_DESCRIPTOR_PAGE_AP_RO_NO ((1UL << 9) | (1UL << 4)) -#define TT_DESCRIPTOR_PAGE_AP_RO_RO ((1UL << 9) | (3UL << 4)) +#define TT_DESCRIPTOR_SECTION_AF (1UL << 10) + +#define TT_DESCRIPTOR_PAGE_AP_MASK ((1UL << 9) | (1UL << 5)) +#define TT_DESCRIPTOR_PAGE_AP_NO_RW ((0UL << 9) | (0UL << 5)) +#define TT_DESCRIPTOR_PAGE_AP_RW_RW ((0UL << 9) | (1UL << 5)) +#define TT_DESCRIPTOR_PAGE_AP_NO_RO ((1UL << 9) | (0UL << 5)) +#define TT_DESCRIPTOR_PAGE_AP_RO_RO ((1UL << 9) | (1UL << 5)) + +#define TT_DESCRIPTOR_PAGE_AF (1UL << 4) =20 #define TT_DESCRIPTOR_SECTION_XN_MASK (0x1UL << 4) #define TT_DESCRIPTOR_PAGE_XN_MASK (0x1UL << 0) @@ -124,20 +124,24 @@ #define TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(Desc) ((((Desc) & TT_D= ESCRIPTOR_SECTION_AP_MASK) >> 6) & TT_DESCRIPTOR_PAGE_AP_MASK) #define TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(Desc) ((((Desc) & TT_D= ESCRIPTOR_SECTION_NG_MASK) >> 6) & TT_DESCRIPTOR_PAGE_NG_MASK) #define TT_DESCRIPTOR_CONVERT_TO_PAGE_S(Desc) ((((Desc) & TT_D= ESCRIPTOR_SECTION_S_MASK) >> 6) & TT_DESCRIPTOR_PAGE_S_MASK) +#define TT_DESCRIPTOR_CONVERT_TO_PAGE_AF(Desc) ((((Desc) & TT_D= ESCRIPTOR_SECTION_AF) >> 6) & TT_DESCRIPTOR_PAGE_AF) #define TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(Desc) ((((Desc) & TT_D= ESCRIPTOR_SECTION_XN_MASK) >> 4) & TT_DESCRIPTOR_PAGE_XN_MASK) #define TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(Desc) ((((Desc) & (0x3= << 12)) >> 6) | (Desc & (0x3 << 2))) =20 #define TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(Desc) ((((Desc) & T= T_DESCRIPTOR_PAGE_AP_MASK) << 6) & TT_DESCRIPTOR_SECTION_AP_MASK) #define TT_DESCRIPTOR_CONVERT_TO_SECTION_S(Desc) ((((Desc) & T= T_DESCRIPTOR_PAGE_S_MASK) << 6) & TT_DESCRIPTOR_SECTION_S_MASK) +#define TT_DESCRIPTOR_CONVERT_TO_SECTION_AF(Desc) ((((Desc) & T= T_DESCRIPTOR_PAGE_AF) << 6) & TT_DESCRIPTOR_SECTION_AF) #define TT_DESCRIPTOR_CONVERT_TO_SECTION_XN(Desc) ((((Desc) & T= T_DESCRIPTOR_PAGE_XN_MASK) << 4) & TT_DESCRIPTOR_SECTION_XN_MASK) #define TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(Desc) ((((Desc) & (= 0x3 << 6)) << 6) | (Desc & (0x3 << 2))) =20 #define TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK (TT_DESCRIPTOR_SECTION_NS_MA= SK | TT_DESCRIPTOR_SECTION_NG_MASK | \ TT_DESCRIPTOR= _SECTION_S_MASK | TT_DESCRIPTOR_SECTION_AP_MASK | \ + TT_DESCRIPTOR= _SECTION_AF | \ TT_DESCRIPTOR= _SECTION_XN_MASK | TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) =20 #define TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK (TT_DESCRIPTOR_PAGE_NG_MASK | T= T_DESCRIPTOR_PAGE_S_MASK | \ TT_DESCRIPTOR= _PAGE_AP_MASK | TT_DESCRIPTOR_PAGE_XN_MASK | \ + TT_DESCRIPTOR= _PAGE_AF | \ TT_DESCRIPTOR= _PAGE_CACHE_POLICY_MASK) =20 #define TT_DESCRIPTOR_SECTION_DOMAIN_MASK (0x0FUL << 5) @@ -159,6 +163,7 @@ TT_DESCRIPTOR_= SECTION_S_SHARED | \ TT_DESCRIPTOR_= SECTION_DOMAIN(0) | \ TT_DESCRIPTOR_= SECTION_AP_RW_RW | \ + TT_DESCRIPTOR_= SECTION_AF | \ TT_DESCRIPTOR_= SECTION_CACHE_POLICY_WRITE_BACK_ALLOC) #define TT_DESCRIPTOR_SECTION_WRITE_THROUGH(NonSecure) (TT_DESCRIPTOR_SEC= TION_TYPE_SECTION = | \ ((NonSecure) ?= TT_DESCRIPTOR_SECTION_NS : 0) | \ @@ -166,6 +171,7 @@ TT_DESCRIPTOR_= SECTION_S_SHARED | \ TT_DESCRIPTOR_= SECTION_DOMAIN(0) | \ TT_DESCRIPTOR_= SECTION_AP_RW_RW | \ + TT_DESCRIPTOR_= SECTION_AF | \ TT_DESCRIPTOR_= SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC) #define TT_DESCRIPTOR_SECTION_DEVICE(NonSecure) (TT_DESCRIPTOR_SEC= TION_TYPE_SECTION = | \ ((NonSecure) ?= TT_DESCRIPTOR_SECTION_NS : 0) | \ @@ -174,6 +180,7 @@ TT_DESCRIPTOR_= SECTION_DOMAIN(0) | \ TT_DESCRIPTOR_= SECTION_AP_RW_RW | \ TT_DESCRIPTOR_= SECTION_XN_MASK | \ + TT_DESCRIPTOR_= SECTION_AF | \ TT_DESCRIPTOR_= SECTION_CACHE_POLICY_SHAREABLE_DEVICE) #define TT_DESCRIPTOR_SECTION_UNCACHED(NonSecure) (TT_DESCRIPTOR_SEC= TION_TYPE_SECTION = | \ ((NonSecure) ? = TT_DESCRIPTOR_SECTION_NS : 0) | \ @@ -181,28 +188,33 @@ TT_DESCRIPTOR_S= ECTION_S_NOT_SHARED | \ TT_DESCRIPTOR_S= ECTION_DOMAIN(0) | \ TT_DESCRIPTOR_S= ECTION_AP_RW_RW | \ + TT_DESCRIPTOR_= SECTION_AF | \ TT_DESCRIPTOR_S= ECTION_CACHE_POLICY_NON_CACHEABLE) =20 #define TT_DESCRIPTOR_PAGE_WRITE_BACK (TT_DESCRIPTOR_PAGE_TYPE_PAGE = | \ TT_DESCRIPTOR_PAGE= _NG_GLOBAL | \ TT_DESCRIPTOR_PAGE= _S_SHARED | \ TT_DESCRIPTOR_PAGE= _AP_RW_RW | \ + TT_DESCRIPTOR_PAGE= _AF | \ TT_DESCRIPTOR_PAGE= _CACHE_POLICY_WRITE_BACK_ALLOC) #define TT_DESCRIPTOR_PAGE_WRITE_THROUGH (TT_DESCRIPTOR_PAGE_TYPE_PAGE = | \ TT_DESCRIPTOR_PAGE= _NG_GLOBAL | \ TT_DESCRIPTOR_PAGE= _S_SHARED | \ TT_DESCRIPTOR_PAGE= _AP_RW_RW | \ + TT_DESCRIPTOR_PAGE= _AF | \ TT_DESCRIPTOR_PAGE= _CACHE_POLICY_WRITE_THROUGH_NO_ALLOC) #define TT_DESCRIPTOR_PAGE_DEVICE (TT_DESCRIPTOR_PAGE_TYPE_PAGE = | \ TT_DESCRIPTOR_PAGE= _NG_GLOBAL | \ TT_DESCRIPTOR_PAGE= _S_NOT_SHARED | \ TT_DESCRIPTOR_PAGE= _AP_RW_RW | \ + TT_DESCRIPTOR_PAGE= _AF | \ TT_DESCRIPTOR_PAGE= _XN_MASK | \ TT_DESCRIPTOR_PAGE= _CACHE_POLICY_SHAREABLE_DEVICE) #define TT_DESCRIPTOR_PAGE_UNCACHED (TT_DESCRIPTOR_PAGE_TYPE_PAGE = | \ TT_DESCRIPTOR_PAGE= _NG_GLOBAL | \ TT_DESCRIPTOR_PAGE= _S_NOT_SHARED | \ TT_DESCRIPTOR_PAGE= _AP_RW_RW | \ + TT_DESCRIPTOR_PAGE= _AF | \ TT_DESCRIPTOR_PAGE= _CACHE_POLICY_NON_CACHEABLE) =20 // First Level Descriptors diff --git a/ArmPkg/Library/ArmLib/Arm/ArmV7Support.S b/ArmPkg/Library/ArmL= ib/Arm/ArmV7Support.S index 4925f6628e1e..1f396adffc11 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmV7Support.S +++ b/ArmPkg/Library/ArmLib/Arm/ArmV7Support.S @@ -16,6 +16,7 @@ .set CTRL_C_BIT, (1 << 2) .set CTRL_B_BIT, (1 << 7) .set CTRL_I_BIT, (1 << 12) +.set CTRL_AFE_BIT,(1 << 29) =20 =20 ASM_FUNC(ArmInvalidateDataCacheEntryByMVA) @@ -64,6 +65,7 @@ ASM_FUNC(ArmInvalidateInstructionCache) ASM_FUNC(ArmEnableMmu) mrc p15,0,R0,c1,c0,0 orr R0,R0,#1 + orr R0,R0,#CTRL_AFE_BIT mcr p15,0,R0,c1,c0,0 dsb isb diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c b/ArmPkg/Libra= ry/ArmMmuLib/Arm/ArmMmuLibConvert.c index 6e2f08a7ce15..52dbfd714029 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c @@ -23,6 +23,7 @@ ConvertSectionAttributesToPageAttributes ( PageAttributes =3D 0; PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (SectionA= ttributes); PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (SectionAttributes); + PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_AF (SectionAttributes); PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_XN (SectionAttributes); PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_NG (SectionAttributes); PageAttributes |=3D TT_DESCRIPTOR_CONVERT_TO_PAGE_S (SectionAttributes); diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c b/ArmPkg/Librar= y/ArmMmuLib/Arm/ArmMmuLibUpdate.c index 12d0f4c30f8e..484c67476619 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c @@ -104,7 +104,7 @@ UpdatePageEntries ( =20 // EntryMask: bitmask of values to change (1 =3D change this value, 0 = =3D leave alone) // EntryValue: values at bit positions specified by EntryMask - EntryMask =3D TT_DESCRIPTOR_PAGE_TYPE_MASK | TT_DESCRIPTOR_PAGE_AP_MASK = | TT_DESCRIPTOR_PAGE_XN_MASK; + EntryMask =3D TT_DESCRIPTOR_PAGE_TYPE_MASK | TT_DESCRIPTOR_PAGE_AP_MASK = | TT_DESCRIPTOR_PAGE_XN_MASK | TT_DESCRIPTOR_PAGE_AF; EntryValue =3D TT_DESCRIPTOR_PAGE_TYPE_PAGE; =20 // Although the PI spec is unclear on this, the GCD guarantees that only @@ -138,6 +138,10 @@ UpdatePageEntries ( return EFI_UNSUPPORTED; } =20 + if ((Attributes & EFI_MEMORY_RP) =3D=3D 0) { + EntryValue |=3D TT_DESCRIPTOR_PAGE_AF; + } + if ((Attributes & EFI_MEMORY_RO) !=3D 0) { EntryValue |=3D TT_DESCRIPTOR_PAGE_AP_RO_RO; } else { @@ -237,7 +241,7 @@ UpdateSectionEntries ( =20 // Make sure we handle a section range that is unmapped EntryMask =3D TT_DESCRIPTOR_SECTION_TYPE_MASK | TT_DESCRIPTOR_SECTION_XN= _MASK | - TT_DESCRIPTOR_SECTION_AP_MASK; + TT_DESCRIPTOR_SECTION_AP_MASK | TT_DESCRIPTOR_SECTION_AF; EntryValue =3D TT_DESCRIPTOR_SECTION_TYPE_SECTION; =20 // Although the PI spec is unclear on this, the GCD guarantees that only @@ -281,6 +285,10 @@ UpdateSectionEntries ( EntryValue |=3D TT_DESCRIPTOR_SECTION_XN_MASK; } =20 + if ((Attributes & EFI_MEMORY_RP) =3D=3D 0) { + EntryValue |=3D TT_DESCRIPTOR_SECTION_AF; + } + // obtain page table base FirstLevelTable =3D (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress= (); =20 --=20 2.39.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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