From nobody Fri Oct 25 15:40:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+101119+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101119+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1678727895; cv=none; d=zohomail.com; s=zohoarc; b=JQlFup6YSQrUwJJXwyBizPwkpfgBd7euF48wBPNiGQHr8jYDVyBowYDE0CQQqmDrmc9QggDWVCKgdLwQv7cBG3Gno8T8a7rDFo6ZX8R9WwuQON1zuATm9Uljdsowzt5X8Tq4btvZX+lF+QqVED97bjdGpnaDTzSB9t708taj0SE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678727895; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=YzPkuPSUQnFPu+uIbW8vYi+Fw0IV3PMBk6cs3A0tLwI=; b=F3ku+ySTGn1sLVx1wuVWKqDnySshZ8f1vw5/k9bj0lnZS1YipLXjTSah5ZVJODMqGrBo1KzdFUIiX/Io9xfp0K/uvXo68LV4hPuMWfCXcLmVGkqLLkteb6ES2QhPpQ21x9cEPSkcsZcTMgNE7nql37nZnslOkE/gTemLM8LnRyw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+101119+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1678727895258495.90132068903256; Mon, 13 Mar 2023 10:18:15 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id sHqoYY1788612xJX1v5Beu7Y; Mon, 13 Mar 2023 10:18:14 -0700 X-Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by mx.groups.io with SMTP id smtpd.web11.26489.1678727894322214383 for ; Mon, 13 Mar 2023 10:18:14 -0700 X-Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id D65CE61368; Mon, 13 Mar 2023 17:18:13 +0000 (UTC) X-Received: by smtp.kernel.org (Postfix) with ESMTPSA id 175EEC433A7; Mon, 13 Mar 2023 17:18:10 +0000 (UTC) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Michael Kinney , Liming Gao , Jiewen Yao , Michael Kubacki , Sean Brogan , Rebecca Cran , Leif Lindholm , Sami Mujawar , Taylor Beebe Subject: [edk2-devel] [PATCH v5 15/38] ArmPkg/ArmMmuLib: Introduce region types for RO/XP WB cached memory Date: Mon, 13 Mar 2023 18:16:51 +0100 Message-Id: <20230313171714.3866151-16-ardb@kernel.org> In-Reply-To: <20230313171714.3866151-1-ardb@kernel.org> References: <20230313171714.3866151-1-ardb@kernel.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ardb@kernel.org X-Gm-Message-State: uOftCBaLjNtNoMGAnXJZXrBAx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1678727894; bh=FGrVH2MTpJgEpaR3NIZvxSEYk30zrFbi9EylXwemCVI=; h=Cc:Date:From:Reply-To:Subject:To; b=gJb/XVGHMULhVs/XacRkYaTxfK6K4PEqeMkeGyRVeepbuW1rY2wYBBbEdt6IVPQ+yoi FA2YOC13ng7RbXnCve9j+/x6IPz8nN8x1X2CpUVuKMhhbFqzhank4CLpLbxprB62qu0EK 9XtEbzgi4uz56v1h4syuvGQADtP+drdxHx4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1678727896124100005 Content-Type: text/plain; charset="utf-8" To prepare for the enablement of booting EFI with the SCTLR.WXN control enabled, which makes all writeable memory regions non-executable by default, introduce a memory type that we will use to describe the flash region that carries the SEC and PEIM modules that execute in place. Even if these are implicitly read-only due to the ROM nature, they need to be mapped with read-only attributes in the page tables to be able to execute from them. Also add the XP counterpart which will be used for all normal DRAM right at the outset. Signed-off-by: Ard Biesheuvel --- ArmPkg/Include/Library/ArmLib.h | 6 ++++ ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 30 ++++++++++++++++---- ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c | 16 +++++++++++ 3 files changed, 46 insertions(+), 6 deletions(-) diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLi= b.h index a53f60d98852..fb1ae57b3522 100644 --- a/ArmPkg/Include/Library/ArmLib.h +++ b/ArmPkg/Include/Library/ArmLib.h @@ -35,6 +35,12 @@ typedef enum { // Do NOT use below two attributes if you are not sure. ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE, =20 + // Special region types for memory that must be mapped with read-only or + // non-execute permissions from the very start, e.g., to support the use + // of the WXN virtual memory control. + ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_RO, + ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_XP, + ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH, ARM_MEMORY_REGION_ATTRIBUTE_DEVICE, } ARM_MEMORY_REGION_ATTRIBUTES; diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Libr= ary/ArmMmuLib/AArch64/ArmMmuLibCore.c index ee4c5c995ce8..419b3b028201 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -37,12 +37,34 @@ ArmMemoryAttributeToPageAttribute ( IN ARM_MEMORY_REGION_ATTRIBUTES Attributes ) { + UINT64 Permissions; + + switch (Attributes) { + case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_RO: + Permissions =3D TT_AP_NO_RO; + break; + + case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_XP: + case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE: + if (ArmReadCurrentEL () =3D=3D AARCH64_EL2) { + Permissions =3D TT_XN_MASK; + } else { + Permissions =3D TT_UXN_MASK | TT_PXN_MASK; + } + break; + default: + Permissions =3D 0; + break; + } + switch (Attributes) { case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE: return TT_ATTR_INDX_MEMORY_WRITE_BACK; =20 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK: - return TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE; + case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_RO: + case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_XP: + return TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE | Perm= issions; =20 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH: return TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE; @@ -54,11 +76,7 @@ ArmMemoryAttributeToPageAttribute ( default: ASSERT (0); case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE: - if (ArmReadCurrentEL () =3D=3D AARCH64_EL2) { - return TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK; - } else { - return TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK; - } + return TT_ATTR_INDX_DEVICE_MEMORY | Permissions; } } =20 diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c b/ArmPkg/Library/= ArmMmuLib/Arm/ArmMmuLibCore.c index 154298357460..00c5f42cd91a 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c @@ -106,6 +106,14 @@ PopulateLevel2PageTable ( PageAttributes =3D TT_DESCRIPTOR_PAGE_WRITE_BACK; PageAttributes &=3D ~TT_DESCRIPTOR_PAGE_S_SHARED; break; + case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_RO: + PageAttributes =3D TT_DESCRIPTOR_PAGE_WRITE_BACK; + PageAttributes |=3D TT_DESCRIPTOR_PAGE_AP_NO_RO; + break; + case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_XP: + PageAttributes =3D TT_DESCRIPTOR_PAGE_WRITE_BACK; + PageAttributes |=3D TT_DESCRIPTOR_PAGE_XN_MASK; + break; case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH: PageAttributes =3D TT_DESCRIPTOR_PAGE_WRITE_THROUGH; break; @@ -240,6 +248,14 @@ FillTranslationTable ( Attributes =3D TT_DESCRIPTOR_SECTION_WRITE_BACK; Attributes &=3D ~TT_DESCRIPTOR_SECTION_S_SHARED; break; + case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_RO: + Attributes =3D TT_DESCRIPTOR_SECTION_WRITE_BACK; + Attributes |=3D TT_DESCRIPTOR_SECTION_AP_NO_RO; + break; + case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_XP: + Attributes =3D TT_DESCRIPTOR_SECTION_WRITE_BACK; + Attributes |=3D TT_DESCRIPTOR_SECTION_XN_MASK; + break; case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH: Attributes =3D TT_DESCRIPTOR_SECTION_WRITE_THROUGH; break; --=20 2.39.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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