Split the ARM permission fields in the short descriptors into an access
flag and AP[2:1] as per the recommendation in the ARM ARM. This makes
the access flag available separately, which allows us to implement
EFI_MEMORY_RP memory analogous to how it will be implemented for
AArch64.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
---
ArmPkg/Drivers/CpuDxe/Arm/Mmu.c | 47 ++++++++++----------
ArmPkg/Include/Chipset/ArmV7Mmu.h | 40 +++++++++++------
ArmPkg/Library/ArmLib/Arm/ArmV7Support.S | 2 +
ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c | 1 +
ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c | 12 ++++-
5 files changed, 63 insertions(+), 39 deletions(-)
diff --git a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c
index 8eb1f71395f5..07faab8216ec 100644
--- a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c
+++ b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c
@@ -50,30 +50,27 @@ SectionToGcdAttributes (
// determine protection attributes
switch (SectionAttributes & TT_DESCRIPTOR_SECTION_AP_MASK) {
- case TT_DESCRIPTOR_SECTION_AP_NO_NO: // no read, no write
- // *GcdAttributes |= EFI_MEMORY_RO | EFI_MEMORY_RP;
- break;
-
- case TT_DESCRIPTOR_SECTION_AP_RW_NO:
+ case TT_DESCRIPTOR_SECTION_AP_NO_RW:
case TT_DESCRIPTOR_SECTION_AP_RW_RW:
// normal read/write access, do not add additional attributes
break;
// read only cases map to write-protect
- case TT_DESCRIPTOR_SECTION_AP_RO_NO:
+ case TT_DESCRIPTOR_SECTION_AP_NO_RO:
case TT_DESCRIPTOR_SECTION_AP_RO_RO:
*GcdAttributes |= EFI_MEMORY_RO;
break;
-
- default:
- return EFI_UNSUPPORTED;
}
// now process eXectue Never attribute
- if ((SectionAttributes & TT_DESCRIPTOR_SECTION_XN_MASK) != 0 ) {
+ if ((SectionAttributes & TT_DESCRIPTOR_SECTION_XN_MASK) != 0) {
*GcdAttributes |= EFI_MEMORY_XP;
}
+ if ((SectionAttributes & TT_DESCRIPTOR_SECTION_AF) == 0) {
+ *GcdAttributes |= EFI_MEMORY_RP;
+ }
+
return EFI_SUCCESS;
}
@@ -114,30 +111,27 @@ PageToGcdAttributes (
// determine protection attributes
switch (PageAttributes & TT_DESCRIPTOR_PAGE_AP_MASK) {
- case TT_DESCRIPTOR_PAGE_AP_NO_NO: // no read, no write
- // *GcdAttributes |= EFI_MEMORY_RO | EFI_MEMORY_RP;
- break;
-
- case TT_DESCRIPTOR_PAGE_AP_RW_NO:
+ case TT_DESCRIPTOR_PAGE_AP_NO_RW:
case TT_DESCRIPTOR_PAGE_AP_RW_RW:
// normal read/write access, do not add additional attributes
break;
// read only cases map to write-protect
- case TT_DESCRIPTOR_PAGE_AP_RO_NO:
+ case TT_DESCRIPTOR_PAGE_AP_NO_RO:
case TT_DESCRIPTOR_PAGE_AP_RO_RO:
*GcdAttributes |= EFI_MEMORY_RO;
break;
-
- default:
- return EFI_UNSUPPORTED;
}
// now process eXectue Never attribute
- if ((PageAttributes & TT_DESCRIPTOR_PAGE_XN_MASK) != 0 ) {
+ if ((PageAttributes & TT_DESCRIPTOR_PAGE_XN_MASK) != 0) {
*GcdAttributes |= EFI_MEMORY_XP;
}
+ if ((PageAttributes & TT_DESCRIPTOR_PAGE_AF) == 0) {
+ *GcdAttributes |= EFI_MEMORY_RP;
+ }
+
return EFI_SUCCESS;
}
@@ -166,6 +160,7 @@ SyncCacheConfigPage (
// Convert SectionAttributes into PageAttributes
NextPageAttributes =
TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (*NextSectionAttributes) |
+ TT_DESCRIPTOR_CONVERT_TO_PAGE_AF (*NextSectionAttributes) |
TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (*NextSectionAttributes);
// obtain page table base
@@ -174,7 +169,7 @@ SyncCacheConfigPage (
for (i = 0; i < TRANSLATION_TABLE_PAGE_COUNT; i++) {
if ((SecondLevelTable[i] & TT_DESCRIPTOR_PAGE_TYPE_MASK) == TT_DESCRIPTOR_PAGE_TYPE_PAGE) {
// extract attributes (cacheability and permissions)
- PageAttributes = SecondLevelTable[i] & (TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK | TT_DESCRIPTOR_PAGE_AP_MASK);
+ PageAttributes = SecondLevelTable[i] & (TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK | TT_DESCRIPTOR_PAGE_AP_MASK | TT_DESCRIPTOR_PAGE_AF);
if (NextPageAttributes == 0) {
// start on a new region
@@ -213,6 +208,7 @@ SyncCacheConfigPage (
// Convert back PageAttributes into SectionAttributes
*NextSectionAttributes =
TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY (NextPageAttributes) |
+ TT_DESCRIPTOR_CONVERT_TO_SECTION_AF (NextPageAttributes) |
TT_DESCRIPTOR_CONVERT_TO_SECTION_AP (NextPageAttributes);
return EFI_SUCCESS;
@@ -256,14 +252,14 @@ SyncCacheConfig (
FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)(ArmGetTTBR0BaseAddress ());
// Get the first region
- NextSectionAttributes = FirstLevelTable[0] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK);
+ NextSectionAttributes = FirstLevelTable[0] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK | TT_DESCRIPTOR_SECTION_AF);
// iterate through each 1MB descriptor
NextRegionBase = NextRegionLength = 0;
for (i = 0; i < TRANSLATION_TABLE_SECTION_COUNT; i++) {
if ((FirstLevelTable[i] & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) {
// extract attributes (cacheability and permissions)
- SectionAttributes = FirstLevelTable[i] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK);
+ SectionAttributes = FirstLevelTable[i] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK | TT_DESCRIPTOR_SECTION_AF);
if (NextSectionAttributes == 0) {
// start on a new region
@@ -383,6 +379,10 @@ EfiAttributeToArmAttribute (
ArmAttributes |= TT_DESCRIPTOR_SECTION_XN_MASK;
}
+ if ((EfiAttributes & EFI_MEMORY_RP) == 0) {
+ ArmAttributes |= TT_DESCRIPTOR_SECTION_AF;
+ }
+
return ArmAttributes;
}
@@ -482,6 +482,7 @@ GetMemoryRegion (
*RegionAttributes = TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY (PageAttributes) |
TT_DESCRIPTOR_CONVERT_TO_SECTION_S (PageAttributes) |
TT_DESCRIPTOR_CONVERT_TO_SECTION_XN (PageAttributes) |
+ TT_DESCRIPTOR_CONVERT_TO_SECTION_AF (PageAttributes) |
TT_DESCRIPTOR_CONVERT_TO_SECTION_AP (PageAttributes);
}
diff --git a/ArmPkg/Include/Chipset/ArmV7Mmu.h b/ArmPkg/Include/Chipset/ArmV7Mmu.h
index e0219747df86..da4f3160f8ff 100644
--- a/ArmPkg/Include/Chipset/ArmV7Mmu.h
+++ b/ArmPkg/Include/Chipset/ArmV7Mmu.h
@@ -80,21 +80,21 @@
#define TT_DESCRIPTOR_PAGE_S_NOT_SHARED (0UL << 10)
#define TT_DESCRIPTOR_PAGE_S_SHARED (1UL << 10)
-#define TT_DESCRIPTOR_SECTION_AP_MASK ((1UL << 15) | (3UL << 10))
-#define TT_DESCRIPTOR_SECTION_AP_NO_NO ((0UL << 15) | (0UL << 10))
-#define TT_DESCRIPTOR_SECTION_AP_RW_NO ((0UL << 15) | (1UL << 10))
-#define TT_DESCRIPTOR_SECTION_AP_RW_RO ((0UL << 15) | (2UL << 10))
-#define TT_DESCRIPTOR_SECTION_AP_RW_RW ((0UL << 15) | (3UL << 10))
-#define TT_DESCRIPTOR_SECTION_AP_RO_NO ((1UL << 15) | (1UL << 10))
-#define TT_DESCRIPTOR_SECTION_AP_RO_RO ((1UL << 15) | (3UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_MASK ((1UL << 15) | (1UL << 11))
+#define TT_DESCRIPTOR_SECTION_AP_NO_RW ((0UL << 15) | (0UL << 11))
+#define TT_DESCRIPTOR_SECTION_AP_RW_RW ((0UL << 15) | (1UL << 11))
+#define TT_DESCRIPTOR_SECTION_AP_NO_RO ((1UL << 15) | (0UL << 11))
+#define TT_DESCRIPTOR_SECTION_AP_RO_RO ((1UL << 15) | (1UL << 11))
-#define TT_DESCRIPTOR_PAGE_AP_MASK ((1UL << 9) | (3UL << 4))
-#define TT_DESCRIPTOR_PAGE_AP_NO_NO ((0UL << 9) | (0UL << 4))
-#define TT_DESCRIPTOR_PAGE_AP_RW_NO ((0UL << 9) | (1UL << 4))
-#define TT_DESCRIPTOR_PAGE_AP_RW_RO ((0UL << 9) | (2UL << 4))
-#define TT_DESCRIPTOR_PAGE_AP_RW_RW ((0UL << 9) | (3UL << 4))
-#define TT_DESCRIPTOR_PAGE_AP_RO_NO ((1UL << 9) | (1UL << 4))
-#define TT_DESCRIPTOR_PAGE_AP_RO_RO ((1UL << 9) | (3UL << 4))
+#define TT_DESCRIPTOR_SECTION_AF (1UL << 10)
+
+#define TT_DESCRIPTOR_PAGE_AP_MASK ((1UL << 9) | (1UL << 5))
+#define TT_DESCRIPTOR_PAGE_AP_NO_RW ((0UL << 9) | (0UL << 5))
+#define TT_DESCRIPTOR_PAGE_AP_RW_RW ((0UL << 9) | (1UL << 5))
+#define TT_DESCRIPTOR_PAGE_AP_NO_RO ((1UL << 9) | (0UL << 5))
+#define TT_DESCRIPTOR_PAGE_AP_RO_RO ((1UL << 9) | (1UL << 5))
+
+#define TT_DESCRIPTOR_PAGE_AF (1UL << 4)
#define TT_DESCRIPTOR_SECTION_XN_MASK (0x1UL << 4)
#define TT_DESCRIPTOR_PAGE_XN_MASK (0x1UL << 0)
@@ -124,20 +124,24 @@
#define TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_AP_MASK) >> 6) & TT_DESCRIPTOR_PAGE_AP_MASK)
#define TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_NG_MASK) >> 6) & TT_DESCRIPTOR_PAGE_NG_MASK)
#define TT_DESCRIPTOR_CONVERT_TO_PAGE_S(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_S_MASK) >> 6) & TT_DESCRIPTOR_PAGE_S_MASK)
+#define TT_DESCRIPTOR_CONVERT_TO_PAGE_AF(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_AF) >> 6) & TT_DESCRIPTOR_PAGE_AF)
#define TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_XN_MASK) >> 4) & TT_DESCRIPTOR_PAGE_XN_MASK)
#define TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(Desc) ((((Desc) & (0x3 << 12)) >> 6) | (Desc & (0x3 << 2)))
#define TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(Desc) ((((Desc) & TT_DESCRIPTOR_PAGE_AP_MASK) << 6) & TT_DESCRIPTOR_SECTION_AP_MASK)
#define TT_DESCRIPTOR_CONVERT_TO_SECTION_S(Desc) ((((Desc) & TT_DESCRIPTOR_PAGE_S_MASK) << 6) & TT_DESCRIPTOR_SECTION_S_MASK)
+#define TT_DESCRIPTOR_CONVERT_TO_SECTION_AF(Desc) ((((Desc) & TT_DESCRIPTOR_PAGE_AF) << 6) & TT_DESCRIPTOR_SECTION_AF)
#define TT_DESCRIPTOR_CONVERT_TO_SECTION_XN(Desc) ((((Desc) & TT_DESCRIPTOR_PAGE_XN_MASK) << 4) & TT_DESCRIPTOR_SECTION_XN_MASK)
#define TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(Desc) ((((Desc) & (0x3 << 6)) << 6) | (Desc & (0x3 << 2)))
#define TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK (TT_DESCRIPTOR_SECTION_NS_MASK | TT_DESCRIPTOR_SECTION_NG_MASK | \
TT_DESCRIPTOR_SECTION_S_MASK | TT_DESCRIPTOR_SECTION_AP_MASK | \
+ TT_DESCRIPTOR_SECTION_AF | \
TT_DESCRIPTOR_SECTION_XN_MASK | TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK)
#define TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK (TT_DESCRIPTOR_PAGE_NG_MASK | TT_DESCRIPTOR_PAGE_S_MASK | \
TT_DESCRIPTOR_PAGE_AP_MASK | TT_DESCRIPTOR_PAGE_XN_MASK | \
+ TT_DESCRIPTOR_PAGE_AF | \
TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK)
#define TT_DESCRIPTOR_SECTION_DOMAIN_MASK (0x0FUL << 5)
@@ -159,6 +163,7 @@
TT_DESCRIPTOR_SECTION_S_SHARED | \
TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
TT_DESCRIPTOR_SECTION_AP_RW_RW | \
+ TT_DESCRIPTOR_SECTION_AF | \
TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC)
#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \
@@ -166,6 +171,7 @@
TT_DESCRIPTOR_SECTION_S_SHARED | \
TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
TT_DESCRIPTOR_SECTION_AP_RW_RW | \
+ TT_DESCRIPTOR_SECTION_AF | \
TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)
#define TT_DESCRIPTOR_SECTION_DEVICE(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \
@@ -174,6 +180,7 @@
TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
TT_DESCRIPTOR_SECTION_AP_RW_RW | \
TT_DESCRIPTOR_SECTION_XN_MASK | \
+ TT_DESCRIPTOR_SECTION_AF | \
TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE)
#define TT_DESCRIPTOR_SECTION_UNCACHED(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \
@@ -181,28 +188,33 @@
TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
TT_DESCRIPTOR_SECTION_AP_RW_RW | \
+ TT_DESCRIPTOR_SECTION_AF | \
TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE)
#define TT_DESCRIPTOR_PAGE_WRITE_BACK (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
TT_DESCRIPTOR_PAGE_S_SHARED | \
TT_DESCRIPTOR_PAGE_AP_RW_RW | \
+ TT_DESCRIPTOR_PAGE_AF | \
TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC)
#define TT_DESCRIPTOR_PAGE_WRITE_THROUGH (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
TT_DESCRIPTOR_PAGE_S_SHARED | \
TT_DESCRIPTOR_PAGE_AP_RW_RW | \
+ TT_DESCRIPTOR_PAGE_AF | \
TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)
#define TT_DESCRIPTOR_PAGE_DEVICE (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \
TT_DESCRIPTOR_PAGE_AP_RW_RW | \
+ TT_DESCRIPTOR_PAGE_AF | \
TT_DESCRIPTOR_PAGE_XN_MASK | \
TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE)
#define TT_DESCRIPTOR_PAGE_UNCACHED (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \
TT_DESCRIPTOR_PAGE_AP_RW_RW | \
+ TT_DESCRIPTOR_PAGE_AF | \
TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE)
// First Level Descriptors
diff --git a/ArmPkg/Library/ArmLib/Arm/ArmV7Support.S b/ArmPkg/Library/ArmLib/Arm/ArmV7Support.S
index 4925f6628e1e..1f396adffc11 100644
--- a/ArmPkg/Library/ArmLib/Arm/ArmV7Support.S
+++ b/ArmPkg/Library/ArmLib/Arm/ArmV7Support.S
@@ -16,6 +16,7 @@
.set CTRL_C_BIT, (1 << 2)
.set CTRL_B_BIT, (1 << 7)
.set CTRL_I_BIT, (1 << 12)
+.set CTRL_AFE_BIT,(1 << 29)
ASM_FUNC(ArmInvalidateDataCacheEntryByMVA)
@@ -64,6 +65,7 @@ ASM_FUNC(ArmInvalidateInstructionCache)
ASM_FUNC(ArmEnableMmu)
mrc p15,0,R0,c1,c0,0
orr R0,R0,#1
+ orr R0,R0,#CTRL_AFE_BIT
mcr p15,0,R0,c1,c0,0
dsb
isb
diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c
index 6e2f08a7ce15..52dbfd714029 100644
--- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c
+++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c
@@ -23,6 +23,7 @@ ConvertSectionAttributesToPageAttributes (
PageAttributes = 0;
PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (SectionAttributes);
PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (SectionAttributes);
+ PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_AF (SectionAttributes);
PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_XN (SectionAttributes);
PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_NG (SectionAttributes);
PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_S (SectionAttributes);
diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c
index 12d0f4c30f8e..484c67476619 100644
--- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c
+++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c
@@ -104,7 +104,7 @@ UpdatePageEntries (
// EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
// EntryValue: values at bit positions specified by EntryMask
- EntryMask = TT_DESCRIPTOR_PAGE_TYPE_MASK | TT_DESCRIPTOR_PAGE_AP_MASK | TT_DESCRIPTOR_PAGE_XN_MASK;
+ EntryMask = TT_DESCRIPTOR_PAGE_TYPE_MASK | TT_DESCRIPTOR_PAGE_AP_MASK | TT_DESCRIPTOR_PAGE_XN_MASK | TT_DESCRIPTOR_PAGE_AF;
EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE;
// Although the PI spec is unclear on this, the GCD guarantees that only
@@ -138,6 +138,10 @@ UpdatePageEntries (
return EFI_UNSUPPORTED;
}
+ if ((Attributes & EFI_MEMORY_RP) == 0) {
+ EntryValue |= TT_DESCRIPTOR_PAGE_AF;
+ }
+
if ((Attributes & EFI_MEMORY_RO) != 0) {
EntryValue |= TT_DESCRIPTOR_PAGE_AP_RO_RO;
} else {
@@ -237,7 +241,7 @@ UpdateSectionEntries (
// Make sure we handle a section range that is unmapped
EntryMask = TT_DESCRIPTOR_SECTION_TYPE_MASK | TT_DESCRIPTOR_SECTION_XN_MASK |
- TT_DESCRIPTOR_SECTION_AP_MASK;
+ TT_DESCRIPTOR_SECTION_AP_MASK | TT_DESCRIPTOR_SECTION_AF;
EntryValue = TT_DESCRIPTOR_SECTION_TYPE_SECTION;
// Although the PI spec is unclear on this, the GCD guarantees that only
@@ -281,6 +285,10 @@ UpdateSectionEntries (
EntryValue |= TT_DESCRIPTOR_SECTION_XN_MASK;
}
+ if ((Attributes & EFI_MEMORY_RP) == 0) {
+ EntryValue |= TT_DESCRIPTOR_SECTION_AF;
+ }
+
// obtain page table base
FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
--
2.39.2
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-=-=-=-=-=-=-=-=-=-=-=-On Mon, Mar 13, 2023 at 18:16:40 +0100, Ard Biesheuvel wrote:
> Split the ARM permission fields in the short descriptors into an access
> flag and AP[2:1] as per the recommendation in the ARM ARM. This makes
> the access flag available separately, which allows us to implement
> EFI_MEMORY_RP memory analogous to how it will be implemented for
> AArch64.
>
> Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
Comment: it seems your setup has lost the diff.orderFile setting, so
we end up with the new definitions after their first use.
> ---
> ArmPkg/Drivers/CpuDxe/Arm/Mmu.c | 47 ++++++++++----------
> ArmPkg/Include/Chipset/ArmV7Mmu.h | 40 +++++++++++------
> ArmPkg/Library/ArmLib/Arm/ArmV7Support.S | 2 +
> ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c | 1 +
> ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c | 12 ++++-
> 5 files changed, 63 insertions(+), 39 deletions(-)
>
> diff --git a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c
> index 8eb1f71395f5..07faab8216ec 100644
> --- a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c
> +++ b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c
> @@ -50,30 +50,27 @@ SectionToGcdAttributes (
>
> // determine protection attributes
> switch (SectionAttributes & TT_DESCRIPTOR_SECTION_AP_MASK) {
> - case TT_DESCRIPTOR_SECTION_AP_NO_NO: // no read, no write
> - // *GcdAttributes |= EFI_MEMORY_RO | EFI_MEMORY_RP;
> - break;
> -
> - case TT_DESCRIPTOR_SECTION_AP_RW_NO:
> + case TT_DESCRIPTOR_SECTION_AP_NO_RW:
> case TT_DESCRIPTOR_SECTION_AP_RW_RW:
> // normal read/write access, do not add additional attributes
> break;
>
> // read only cases map to write-protect
> - case TT_DESCRIPTOR_SECTION_AP_RO_NO:
> + case TT_DESCRIPTOR_SECTION_AP_NO_RO:
> case TT_DESCRIPTOR_SECTION_AP_RO_RO:
> *GcdAttributes |= EFI_MEMORY_RO;
> break;
> -
> - default:
> - return EFI_UNSUPPORTED;
> }
>
> // now process eXectue Never attribute
> - if ((SectionAttributes & TT_DESCRIPTOR_SECTION_XN_MASK) != 0 ) {
> + if ((SectionAttributes & TT_DESCRIPTOR_SECTION_XN_MASK) != 0) {
> *GcdAttributes |= EFI_MEMORY_XP;
> }
>
> + if ((SectionAttributes & TT_DESCRIPTOR_SECTION_AF) == 0) {
> + *GcdAttributes |= EFI_MEMORY_RP;
> + }
> +
> return EFI_SUCCESS;
> }
>
> @@ -114,30 +111,27 @@ PageToGcdAttributes (
>
> // determine protection attributes
> switch (PageAttributes & TT_DESCRIPTOR_PAGE_AP_MASK) {
> - case TT_DESCRIPTOR_PAGE_AP_NO_NO: // no read, no write
> - // *GcdAttributes |= EFI_MEMORY_RO | EFI_MEMORY_RP;
> - break;
> -
> - case TT_DESCRIPTOR_PAGE_AP_RW_NO:
> + case TT_DESCRIPTOR_PAGE_AP_NO_RW:
> case TT_DESCRIPTOR_PAGE_AP_RW_RW:
> // normal read/write access, do not add additional attributes
> break;
>
> // read only cases map to write-protect
> - case TT_DESCRIPTOR_PAGE_AP_RO_NO:
> + case TT_DESCRIPTOR_PAGE_AP_NO_RO:
> case TT_DESCRIPTOR_PAGE_AP_RO_RO:
> *GcdAttributes |= EFI_MEMORY_RO;
> break;
> -
> - default:
> - return EFI_UNSUPPORTED;
> }
>
> // now process eXectue Never attribute
> - if ((PageAttributes & TT_DESCRIPTOR_PAGE_XN_MASK) != 0 ) {
> + if ((PageAttributes & TT_DESCRIPTOR_PAGE_XN_MASK) != 0) {
> *GcdAttributes |= EFI_MEMORY_XP;
> }
>
> + if ((PageAttributes & TT_DESCRIPTOR_PAGE_AF) == 0) {
> + *GcdAttributes |= EFI_MEMORY_RP;
> + }
> +
> return EFI_SUCCESS;
> }
>
> @@ -166,6 +160,7 @@ SyncCacheConfigPage (
> // Convert SectionAttributes into PageAttributes
> NextPageAttributes =
> TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (*NextSectionAttributes) |
> + TT_DESCRIPTOR_CONVERT_TO_PAGE_AF (*NextSectionAttributes) |
> TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (*NextSectionAttributes);
>
> // obtain page table base
> @@ -174,7 +169,7 @@ SyncCacheConfigPage (
> for (i = 0; i < TRANSLATION_TABLE_PAGE_COUNT; i++) {
> if ((SecondLevelTable[i] & TT_DESCRIPTOR_PAGE_TYPE_MASK) == TT_DESCRIPTOR_PAGE_TYPE_PAGE) {
> // extract attributes (cacheability and permissions)
> - PageAttributes = SecondLevelTable[i] & (TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK | TT_DESCRIPTOR_PAGE_AP_MASK);
> + PageAttributes = SecondLevelTable[i] & (TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK | TT_DESCRIPTOR_PAGE_AP_MASK | TT_DESCRIPTOR_PAGE_AF);
>
> if (NextPageAttributes == 0) {
> // start on a new region
> @@ -213,6 +208,7 @@ SyncCacheConfigPage (
> // Convert back PageAttributes into SectionAttributes
> *NextSectionAttributes =
> TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY (NextPageAttributes) |
> + TT_DESCRIPTOR_CONVERT_TO_SECTION_AF (NextPageAttributes) |
> TT_DESCRIPTOR_CONVERT_TO_SECTION_AP (NextPageAttributes);
>
> return EFI_SUCCESS;
> @@ -256,14 +252,14 @@ SyncCacheConfig (
> FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)(ArmGetTTBR0BaseAddress ());
>
> // Get the first region
> - NextSectionAttributes = FirstLevelTable[0] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK);
> + NextSectionAttributes = FirstLevelTable[0] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK | TT_DESCRIPTOR_SECTION_AF);
>
> // iterate through each 1MB descriptor
> NextRegionBase = NextRegionLength = 0;
> for (i = 0; i < TRANSLATION_TABLE_SECTION_COUNT; i++) {
> if ((FirstLevelTable[i] & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) {
> // extract attributes (cacheability and permissions)
> - SectionAttributes = FirstLevelTable[i] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK);
> + SectionAttributes = FirstLevelTable[i] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK | TT_DESCRIPTOR_SECTION_AF);
>
> if (NextSectionAttributes == 0) {
> // start on a new region
> @@ -383,6 +379,10 @@ EfiAttributeToArmAttribute (
> ArmAttributes |= TT_DESCRIPTOR_SECTION_XN_MASK;
> }
>
> + if ((EfiAttributes & EFI_MEMORY_RP) == 0) {
> + ArmAttributes |= TT_DESCRIPTOR_SECTION_AF;
> + }
> +
> return ArmAttributes;
> }
>
> @@ -482,6 +482,7 @@ GetMemoryRegion (
> *RegionAttributes = TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY (PageAttributes) |
> TT_DESCRIPTOR_CONVERT_TO_SECTION_S (PageAttributes) |
> TT_DESCRIPTOR_CONVERT_TO_SECTION_XN (PageAttributes) |
> + TT_DESCRIPTOR_CONVERT_TO_SECTION_AF (PageAttributes) |
> TT_DESCRIPTOR_CONVERT_TO_SECTION_AP (PageAttributes);
> }
>
> diff --git a/ArmPkg/Include/Chipset/ArmV7Mmu.h b/ArmPkg/Include/Chipset/ArmV7Mmu.h
> index e0219747df86..da4f3160f8ff 100644
> --- a/ArmPkg/Include/Chipset/ArmV7Mmu.h
> +++ b/ArmPkg/Include/Chipset/ArmV7Mmu.h
> @@ -80,21 +80,21 @@
> #define TT_DESCRIPTOR_PAGE_S_NOT_SHARED (0UL << 10)
> #define TT_DESCRIPTOR_PAGE_S_SHARED (1UL << 10)
>
> -#define TT_DESCRIPTOR_SECTION_AP_MASK ((1UL << 15) | (3UL << 10))
> -#define TT_DESCRIPTOR_SECTION_AP_NO_NO ((0UL << 15) | (0UL << 10))
> -#define TT_DESCRIPTOR_SECTION_AP_RW_NO ((0UL << 15) | (1UL << 10))
> -#define TT_DESCRIPTOR_SECTION_AP_RW_RO ((0UL << 15) | (2UL << 10))
> -#define TT_DESCRIPTOR_SECTION_AP_RW_RW ((0UL << 15) | (3UL << 10))
> -#define TT_DESCRIPTOR_SECTION_AP_RO_NO ((1UL << 15) | (1UL << 10))
> -#define TT_DESCRIPTOR_SECTION_AP_RO_RO ((1UL << 15) | (3UL << 10))
> +#define TT_DESCRIPTOR_SECTION_AP_MASK ((1UL << 15) | (1UL << 11))
> +#define TT_DESCRIPTOR_SECTION_AP_NO_RW ((0UL << 15) | (0UL << 11))
> +#define TT_DESCRIPTOR_SECTION_AP_RW_RW ((0UL << 15) | (1UL << 11))
> +#define TT_DESCRIPTOR_SECTION_AP_NO_RO ((1UL << 15) | (0UL << 11))
> +#define TT_DESCRIPTOR_SECTION_AP_RO_RO ((1UL << 15) | (1UL << 11))
>
> -#define TT_DESCRIPTOR_PAGE_AP_MASK ((1UL << 9) | (3UL << 4))
> -#define TT_DESCRIPTOR_PAGE_AP_NO_NO ((0UL << 9) | (0UL << 4))
> -#define TT_DESCRIPTOR_PAGE_AP_RW_NO ((0UL << 9) | (1UL << 4))
> -#define TT_DESCRIPTOR_PAGE_AP_RW_RO ((0UL << 9) | (2UL << 4))
> -#define TT_DESCRIPTOR_PAGE_AP_RW_RW ((0UL << 9) | (3UL << 4))
> -#define TT_DESCRIPTOR_PAGE_AP_RO_NO ((1UL << 9) | (1UL << 4))
> -#define TT_DESCRIPTOR_PAGE_AP_RO_RO ((1UL << 9) | (3UL << 4))
> +#define TT_DESCRIPTOR_SECTION_AF (1UL << 10)
> +
> +#define TT_DESCRIPTOR_PAGE_AP_MASK ((1UL << 9) | (1UL << 5))
> +#define TT_DESCRIPTOR_PAGE_AP_NO_RW ((0UL << 9) | (0UL << 5))
> +#define TT_DESCRIPTOR_PAGE_AP_RW_RW ((0UL << 9) | (1UL << 5))
> +#define TT_DESCRIPTOR_PAGE_AP_NO_RO ((1UL << 9) | (0UL << 5))
> +#define TT_DESCRIPTOR_PAGE_AP_RO_RO ((1UL << 9) | (1UL << 5))
> +
> +#define TT_DESCRIPTOR_PAGE_AF (1UL << 4)
>
> #define TT_DESCRIPTOR_SECTION_XN_MASK (0x1UL << 4)
> #define TT_DESCRIPTOR_PAGE_XN_MASK (0x1UL << 0)
> @@ -124,20 +124,24 @@
> #define TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_AP_MASK) >> 6) & TT_DESCRIPTOR_PAGE_AP_MASK)
> #define TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_NG_MASK) >> 6) & TT_DESCRIPTOR_PAGE_NG_MASK)
> #define TT_DESCRIPTOR_CONVERT_TO_PAGE_S(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_S_MASK) >> 6) & TT_DESCRIPTOR_PAGE_S_MASK)
> +#define TT_DESCRIPTOR_CONVERT_TO_PAGE_AF(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_AF) >> 6) & TT_DESCRIPTOR_PAGE_AF)
> #define TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_XN_MASK) >> 4) & TT_DESCRIPTOR_PAGE_XN_MASK)
> #define TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(Desc) ((((Desc) & (0x3 << 12)) >> 6) | (Desc & (0x3 << 2)))
>
> #define TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(Desc) ((((Desc) & TT_DESCRIPTOR_PAGE_AP_MASK) << 6) & TT_DESCRIPTOR_SECTION_AP_MASK)
> #define TT_DESCRIPTOR_CONVERT_TO_SECTION_S(Desc) ((((Desc) & TT_DESCRIPTOR_PAGE_S_MASK) << 6) & TT_DESCRIPTOR_SECTION_S_MASK)
> +#define TT_DESCRIPTOR_CONVERT_TO_SECTION_AF(Desc) ((((Desc) & TT_DESCRIPTOR_PAGE_AF) << 6) & TT_DESCRIPTOR_SECTION_AF)
> #define TT_DESCRIPTOR_CONVERT_TO_SECTION_XN(Desc) ((((Desc) & TT_DESCRIPTOR_PAGE_XN_MASK) << 4) & TT_DESCRIPTOR_SECTION_XN_MASK)
> #define TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(Desc) ((((Desc) & (0x3 << 6)) << 6) | (Desc & (0x3 << 2)))
>
> #define TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK (TT_DESCRIPTOR_SECTION_NS_MASK | TT_DESCRIPTOR_SECTION_NG_MASK | \
> TT_DESCRIPTOR_SECTION_S_MASK | TT_DESCRIPTOR_SECTION_AP_MASK | \
> + TT_DESCRIPTOR_SECTION_AF | \
> TT_DESCRIPTOR_SECTION_XN_MASK | TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK)
>
> #define TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK (TT_DESCRIPTOR_PAGE_NG_MASK | TT_DESCRIPTOR_PAGE_S_MASK | \
> TT_DESCRIPTOR_PAGE_AP_MASK | TT_DESCRIPTOR_PAGE_XN_MASK | \
> + TT_DESCRIPTOR_PAGE_AF | \
> TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK)
>
> #define TT_DESCRIPTOR_SECTION_DOMAIN_MASK (0x0FUL << 5)
> @@ -159,6 +163,7 @@
> TT_DESCRIPTOR_SECTION_S_SHARED | \
> TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
> TT_DESCRIPTOR_SECTION_AP_RW_RW | \
> + TT_DESCRIPTOR_SECTION_AF | \
> TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC)
> #define TT_DESCRIPTOR_SECTION_WRITE_THROUGH(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
> ((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \
> @@ -166,6 +171,7 @@
> TT_DESCRIPTOR_SECTION_S_SHARED | \
> TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
> TT_DESCRIPTOR_SECTION_AP_RW_RW | \
> + TT_DESCRIPTOR_SECTION_AF | \
> TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)
> #define TT_DESCRIPTOR_SECTION_DEVICE(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
> ((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \
> @@ -174,6 +180,7 @@
> TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
> TT_DESCRIPTOR_SECTION_AP_RW_RW | \
> TT_DESCRIPTOR_SECTION_XN_MASK | \
> + TT_DESCRIPTOR_SECTION_AF | \
> TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE)
> #define TT_DESCRIPTOR_SECTION_UNCACHED(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
> ((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \
> @@ -181,28 +188,33 @@
> TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
> TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
> TT_DESCRIPTOR_SECTION_AP_RW_RW | \
> + TT_DESCRIPTOR_SECTION_AF | \
> TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE)
>
> #define TT_DESCRIPTOR_PAGE_WRITE_BACK (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
> TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
> TT_DESCRIPTOR_PAGE_S_SHARED | \
> TT_DESCRIPTOR_PAGE_AP_RW_RW | \
> + TT_DESCRIPTOR_PAGE_AF | \
> TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC)
> #define TT_DESCRIPTOR_PAGE_WRITE_THROUGH (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
> TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
> TT_DESCRIPTOR_PAGE_S_SHARED | \
> TT_DESCRIPTOR_PAGE_AP_RW_RW | \
> + TT_DESCRIPTOR_PAGE_AF | \
> TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)
> #define TT_DESCRIPTOR_PAGE_DEVICE (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
> TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
> TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \
> TT_DESCRIPTOR_PAGE_AP_RW_RW | \
> + TT_DESCRIPTOR_PAGE_AF | \
> TT_DESCRIPTOR_PAGE_XN_MASK | \
> TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE)
> #define TT_DESCRIPTOR_PAGE_UNCACHED (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
> TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
> TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \
> TT_DESCRIPTOR_PAGE_AP_RW_RW | \
> + TT_DESCRIPTOR_PAGE_AF | \
> TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE)
>
> // First Level Descriptors
> diff --git a/ArmPkg/Library/ArmLib/Arm/ArmV7Support.S b/ArmPkg/Library/ArmLib/Arm/ArmV7Support.S
> index 4925f6628e1e..1f396adffc11 100644
> --- a/ArmPkg/Library/ArmLib/Arm/ArmV7Support.S
> +++ b/ArmPkg/Library/ArmLib/Arm/ArmV7Support.S
> @@ -16,6 +16,7 @@
> .set CTRL_C_BIT, (1 << 2)
> .set CTRL_B_BIT, (1 << 7)
> .set CTRL_I_BIT, (1 << 12)
> +.set CTRL_AFE_BIT,(1 << 29)
>
>
> ASM_FUNC(ArmInvalidateDataCacheEntryByMVA)
> @@ -64,6 +65,7 @@ ASM_FUNC(ArmInvalidateInstructionCache)
> ASM_FUNC(ArmEnableMmu)
> mrc p15,0,R0,c1,c0,0
> orr R0,R0,#1
> + orr R0,R0,#CTRL_AFE_BIT
> mcr p15,0,R0,c1,c0,0
> dsb
> isb
> diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c
> index 6e2f08a7ce15..52dbfd714029 100644
> --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c
> +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c
> @@ -23,6 +23,7 @@ ConvertSectionAttributesToPageAttributes (
> PageAttributes = 0;
> PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (SectionAttributes);
> PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (SectionAttributes);
> + PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_AF (SectionAttributes);
> PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_XN (SectionAttributes);
> PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_NG (SectionAttributes);
> PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_S (SectionAttributes);
> diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c
> index 12d0f4c30f8e..484c67476619 100644
> --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c
> +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c
> @@ -104,7 +104,7 @@ UpdatePageEntries (
>
> // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
> // EntryValue: values at bit positions specified by EntryMask
> - EntryMask = TT_DESCRIPTOR_PAGE_TYPE_MASK | TT_DESCRIPTOR_PAGE_AP_MASK | TT_DESCRIPTOR_PAGE_XN_MASK;
> + EntryMask = TT_DESCRIPTOR_PAGE_TYPE_MASK | TT_DESCRIPTOR_PAGE_AP_MASK | TT_DESCRIPTOR_PAGE_XN_MASK | TT_DESCRIPTOR_PAGE_AF;
> EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE;
>
> // Although the PI spec is unclear on this, the GCD guarantees that only
> @@ -138,6 +138,10 @@ UpdatePageEntries (
> return EFI_UNSUPPORTED;
> }
>
> + if ((Attributes & EFI_MEMORY_RP) == 0) {
> + EntryValue |= TT_DESCRIPTOR_PAGE_AF;
> + }
> +
> if ((Attributes & EFI_MEMORY_RO) != 0) {
> EntryValue |= TT_DESCRIPTOR_PAGE_AP_RO_RO;
> } else {
> @@ -237,7 +241,7 @@ UpdateSectionEntries (
>
> // Make sure we handle a section range that is unmapped
> EntryMask = TT_DESCRIPTOR_SECTION_TYPE_MASK | TT_DESCRIPTOR_SECTION_XN_MASK |
> - TT_DESCRIPTOR_SECTION_AP_MASK;
> + TT_DESCRIPTOR_SECTION_AP_MASK | TT_DESCRIPTOR_SECTION_AF;
> EntryValue = TT_DESCRIPTOR_SECTION_TYPE_SECTION;
>
> // Although the PI spec is unclear on this, the GCD guarantees that only
> @@ -281,6 +285,10 @@ UpdateSectionEntries (
> EntryValue |= TT_DESCRIPTOR_SECTION_XN_MASK;
> }
>
> + if ((Attributes & EFI_MEMORY_RP) == 0) {
> + EntryValue |= TT_DESCRIPTOR_SECTION_AF;
> + }
> +
> // obtain page table base
> FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
>
> --
> 2.39.2
>
>
>
>
>
>
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